Tri-state bus transmission method and circuit

Abstract

The invention relates to a three-state bus transmission method and circuit. The present application relates to a method and a corresponding circuit for generating a bus transmission signal transitioning between a dominant state, a suppressed state and an implicit state. The method includes receiving a transmission control signal that transitions between a dominant state and an implicit state; detecting a first state transition of the transmission control signal, the first state transition being one of a dominant-to-implicit state transition and an implicit-to-dominant state transition; and continuously generating a plurality of transmitter control signals based on the transmission control signal, the first state transition, and the plurality of delays, and controlling the transmitter to transmit the bus transmission signal based on the plurality of transmitter control signals. The plurality of delays has a sequence tuple including a dominant-to-implicit sequence and an implicit-dominant sequence and only a suppression delay included in the dominant-to-implicit sequence, maintaining the bus transmission signal in a suppression state.

Description

Technical Field

[0001] The present invention generally relates to providing signaling on a bus using a transmission circuit, and more particularly, to a transmission method and related transmission circuit. Background Art

[0002] Transmissions on buses in general, and on automotive buses in particular, need to comply with strict signaling requirements regarding various aspects, including but not limited to timing requirements and electromagnetic noise emissions. For this purpose, transmission circuits with multiple segments can be used, which can be arranged, for example, in an H-bridge configuration. Based on these multiple segments, the transmission can be fine-tuned to comply with various signaling requirements. However, while multiple segments enable fine-tuned transmissions, they also increase the complexity of the control methods and circuit arrangements of the transmission circuits, increase the risk of violating timing requirements, and if clock control circuits are used, also increase the risk of violating electromagnetic noise requirements.

[0003] Therefore, an object of the present disclosure is to control a multi-segment transmission circuit in a timely and stable manner. Summary of the invention

[0004] To achieve this purpose, the present disclosure provides a method for generating a bus transmission signal to be transmitted by a transmitter on a bus, the transmitter including an H-bridge formed by four sets of switches. The bus transmission signal is configured to transition between a dominant state, an inhibited state, and a recessive state. The method includes receiving a transmission control signal, the transmission control signal is configured to transition between a dominant state and a recessive state; detecting a first state transition of the transmission control signal, the first state transition being one of a dominant to recessive state transition and a recessive to dominant state transition; and continuously generating a plurality of transmitter control signals based on the transmission control signal, the first state transition, and a plurality of delays. The plurality of delays have a sequence tuple, the sequence tuple including a dominant to recessive sequence corresponding to a dominant to recessive state transition and a recessive to dominant sequence corresponding to a recessive to dominant state transition. In addition, the plurality of delays include an inhibited delay that is only included in the dominant to recessive sequence, the inhibited delay causing the bus transmission signal to remain in an inhibited state during the inhibited delay. Therefore, continuously generating a plurality of transmitter control signals includes applying a plurality of delays to the transmission control signal based on the sequence tuple and the first state transition. Finally, the method includes controlling four sets of switches to transmit the bus transmission signal based on the plurality of transmitter control signals.

[0005] The present disclosure further provides a bus transmission circuit. The bus transmission circuit includes a transmitter and a transmission control circuit, the transmitter includes an H-bridge formed by four sets of switches and is configured to provide a bus transmission signal on a bus, the transmission control circuit is coupled to the transmitter and is configured to receive a transmission control signal, the transmission control signal is configured to transition between a dominant state and a recessive state. The transmission control circuit includes a transition detection logic and a delay logic, the transition detection logic is configured to detect a first state transition of the transmission control signal, the first state transition is one of a dominant to recessive state transition and a recessive to dominant state transition, the delay logic includes a plurality of delay elements and is configured to continuously generate a plurality of transmitter control signals based on the transmission control signal, the first state transition and a plurality of delay elements. The plurality of delay elements have a sequence tuple, the sequence tuple includes a dominant to recessive sequence corresponding to a dominant to recessive state transition and a recessive to dominant sequence corresponding to a recessive to dominant state transition. The plurality of delay elements include an inhibition delay element that is only included in the dominant to recessive sequence, the inhibition delay element keeps the bus transmission signal in an inhibition state while applying the inhibition delay element. Therefore, in order to continuously generate multiple transmitter control signals, the delay logic is configured to apply multiple delay elements to the transmission control signals in a sequence corresponding to the first state transition. In addition, the transmission control circuit is further configured to control four sets of switches to transmit bus transmission signals based on the multiple transmitter control signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Examples of the present disclosure will be described with reference to the following drawings, wherein like reference numerals refer to like elements.

[0007] Figure 1 A flow chart of a method for generating a bus transmission signal according to an example of the present disclosure is shown.

[0008] Figure 2 A block diagram of a bus transmission circuit according to an example of the present disclosure is shown.

[0009] Figure 3 A transmitter according to an example of the present disclosure is shown.

[0010] Figure 4A and Figure 4B A control signal conversion circuit according to an example of the present disclosure is shown.

[0011] FIG. 5A to FIG. 5E A transmission control circuit and its elements according to an example of the present disclosure are shown.

[0012] Fig. 6A and Figure 6B The bus transmission signal from the recessive state to the dominant state and the FIG. 5A to FIG. 5EThe corresponding control signal generated by the transmission control circuit.

[0013] Fig. 7A and Figure 7B The bus transmission signal of the example according to the present disclosure is changed from the dominant state to the recessive state and the FIG. 5A to FIG. 5E The corresponding control signal generated by the transmission control circuit.

[0014] Fig. 8A and Figure 8B Bus transmission signals, control signals contributing to the bus transmission signals, and corresponding transmission control signals are shown according to examples of the present disclosure.

[0015] It should be understood that the above-mentioned drawings are by no means intended to limit the present disclosure. On the contrary, these drawings are provided to help understand the present disclosure. It will be readily understood by those skilled in the art that the various aspects of the present invention shown in one drawing may be combined with the various aspects in another drawing or may be omitted without departing from the scope of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure generally provides a method for generating a bus transmission signal based on a transmission control signal and a corresponding bus transmission circuit.

[0017] In the context of the present disclosure, a bus transmission signal is considered to have three states: a recessive state, a suppressed state, and a dominant state. The recessive state and the suppressed state each correspond to a voltage level of a bus transmission signal corresponding to a logic 0. That is, in terms of logic levels, the recessive state and the suppressed state are indistinguishable from each other. However, in the suppressed state, the transmitter exhibits a higher conductivity, i.e., a lower impedance. The suppressed state can be used, for example, during the data phase of the bus, i.e., during the phase of the bus during which a device coupled to the bus transmits data through the bus. Based on the higher conductivity, i.e., the lower impedance compared to the recessive state, the transmitter causes less oscillation in the data phase, thereby being able to meet the signal integrity requirements of the bus. The dominant state corresponds to a voltage level of a bus transmission signal corresponding to a logic 1. Therefore, a plurality of transmitter control signals control the segments of the transmitter to transition between these three states, i.e., transition between a logic 0, a logic 0 with a higher conductivity, and a logic 1.

[0018] The transmission control signal indicates whether the bus transmission signal is to be in a recessive state or in a dominant state. Therefore, in the context of the present disclosure, the transmission control signal has at least two states: a recessive state (i.e., logic 0) and a dominant state (i.e., logic 1). In other words, the transmission control signal is configured to indicate at least two of the three states of the bus transmission signal, and therefore shares at least two of the three states of the bus transmission signal. For this reason, the transmission control signal can be transformed between a recessive state and a dominant state. Such a transformation can therefore be referred to as a recessive to dominant transformation, a dominant to recessive transformation, and more generally referred to as a state transition.

[0019] In order to generate the bus transmission signal based on the transmission control signal, a transmitter having a plurality of segments is used. The transmitter can be implemented, for example, by four sets of parallel switches arranged as an H-bridge. When a first state transition of the transmission control signal is detected, a plurality of transmitter control signals are generated by applying a plurality of delays to the transmission control signal to control the plurality of segments of the transmitter. In other words, the method uses the transmission control signal and generates the plurality of transmitter control signals as a plurality of delayed copies of the transmission control signal, for example, Figure 6B and Figure 7B Based on multiple transmitter control signals, the segments of the transmitter are individually switched on and off, thereby causing the bus transmission signal to transition between three states, such as Fig. 6A and Fig. 7A shown.

[0020] In order to ensure that the transitions between these three states meet the timing requirements set by the specification of the bus for state transitions, multiple delays define the time intervals between the control of the individual sections of the transmitter, and thereby define the transition times between these three states. In order to transition from the recessive state to the dominant state, and vice versa, the multiple delays include sequence tuples, that is, the multiple delays are applied to the transmission control signal to generate two sequences of the multiple control signals: a dominant to recessive sequence and a recessive to dominant sequence. However, although the multiple delays specifically include an inhibition delay, that is, a delay that keeps the bus transmission signal in the inhibition state for the duration of the inhibition delay, the inhibition delay is only included in the dominant to recessive sequence. In other words, when transitioning from the dominant state to the recessive state, the multiple delays pause the transition from the dominant state to the recessive state in the inhibition state. If a second state transition of the transmission control signal occurs (which can instruct the transmitter to return the bus transmission signal to the dominant state), this can enable the transmitter to return to the dominant state in a more timely manner. In terms of the logic value of the transmission, pausing in the inhibition state has no effect on the logic value of the transmission, because the inhibition state also corresponds to a logic 0. In other words, when transitioning from the dominant state to the recessive state, if the transmission control signal indicates to do so, multiple delays keep the bus transmission signal in the inhibited state so as to be able to return to the dominant state more quickly. Only when the inhibit delay has expired and no second state transition has occurred during the inhibit delay, the bus transmission signal begins to transition from the inhibit state to the recessive state. Therefore, in addition to the above-mentioned deployment of the inhibit state during the data phase, the inhibit state in the context of the present disclosure is also used to achieve a faster transition between logic 0 and logic 1.

[0021] In order to further improve the timing when transitioning from the recessive state or the inhibited state to the dominant state, the method may also generate a plurality of auxiliary transmitter control signals upon detecting a transition of the transmission control signal from the recessive state to the dominant state. The plurality of auxiliary transmitter control signals may be generated in the same manner as the transmitter control signal, i.e., they may be generated by delaying the transmission control signal. In the case of the plurality of auxiliary transmitter control signals, the transmission control signal is delayed by a plurality of auxiliary delays. The plurality of auxiliary delays may correspond to delays in the plurality of delays defining a transition of the bus transmission signal from the recessive state to the inhibited state. Thus, the plurality of auxiliary delays may likewise have a recessive to dominant sequence and a dominant to recessive sequence, although the latter may not be used, as will be seen from the discussion of the generation of the plurality of auxiliary transmitter control signals.

[0022] Assuming that the plurality of auxiliary delays corresponds to a portion of the plurality of delays defining a transition between a recessive state and an inhibit state, the plurality of auxiliary transmitter control signals may correspond to a transmitter control signal among the plurality of transmitter control signals that causes the transmitter to transition the bus transmission signal from the recessive state to the inhibit state. However, the plurality of auxiliary transmission control signals are not used to control a section of the transmitter, but are used for comparison with the plurality of transmission control signals.

[0023] More specifically, upon the transition of the transmission control signal from the recessive state to the dominant state, the generation of the plurality of auxiliary transmitter control signals may be initiated by applying the plurality of auxiliary delays in a recessive-to-dominant sequence. Simultaneously, the generation of the plurality of transmitter control signals based on the previous transition of the transmission control signal from the dominant state to the recessive state may continue by applying the plurality of delays in a dominant-to-recessive sequence. While the plurality of auxiliary transmitter control signals and the plurality of transmitter control signals are generated, the generated auxiliary transmitter control signals and the generated transmitter control signals are compared. Once the auxiliary transmitter control signals are generated based on delays in the plurality of auxiliary delays corresponding to delays in the plurality of delays concurrently used to generate the transmitter control signals, the recessive-to-dominant sequence of the plurality of auxiliary delays and the dominant-to-recessive sequence of the plurality of delays are considered to intersect. Upon determining such an intersection, the generation of the plurality of transmitter control signals will reverse the sequence in which the plurality of delays are applied to the transmission control signals from a dominant-to-recessive sequence to a recessive-to-dominant sequence. Thus, based on the generation of the plurality of auxiliary transmitter control signals and their comparison with the concurrently generated transmitter control signals, the generation of the plurality of transmitter control signals may be inverted before reaching the recessive state (eg, Figure 8B In the figure, the solid line indicates the transmitter control signal, and the dotted line indicates the auxiliary transmitter control signal.) In addition to the above-mentioned transition pause regarding the inhibit state, this can further increase the speed at which the bus transmission signal returns to the dominant state.

[0024] In addition to the above advantages regarding the speed when transitioning from the recessive state to the dominant state, the above method can also additionally reduce electromagnetic noise by relying only on signal delays, signal comparisons and transition detection (which does not require a clock.) Assuming that the multiple sections of the transmitter can switch in a time range between 1ns and 100ns, clock speeds in the GHz range may otherwise be required, which may introduce electromagnetic noise, which may violate the specifications of the bus.

[0025] This general concept will be explained with reference to the accompanying drawings, Figure 1 A flow chart of a method for generating a bus transfer signal is provided. Figures 2 to 5E An example implementation of a bus transfer circuit is shown, and FIG. 6A to FIG. 8B Signals associated with a method for generating a bus transfer signal and an implementation of a bus transfer circuit are shown.

[0026] Figure 1 shows the method for generating the bus transfer signal V BUS Flow chart of method 100. The bus transmission signal V BUS will be transmitted by the transmitter on the bus. The bus may be, for example, a controller area network (CAN) bus. However, it should be understood that the bus may be any type of bus that defines a logic 0 state, a logic 0 state with higher conductivity, and a logic 1 state. The transmitter may be a transmitter having multiple segments, such as Figure 3 An example transmitter 200 is shown.

[0027] Simply go to Figure 3 , the transmitter 200 may include an H-bridge formed by four sets of switches T1 to T4, which may be controlled to output a bus transmission signal V BUS Each set of switches T1 to T4 includes a plurality of transistors coupled in parallel. Figure 3 In the example of , each switch group T1 to T4 includes eight transistors coupled in parallel. However, it should be understood that the switch group may include any number of transistors coupled in parallel, such as 40 or 100. In addition, the switch groups T1 to T4 may include different numbers of transistors coupled in parallel. For example, the switch group T2 and the switch group T3 may include 10 transistors coupled in parallel, while the switch group T1 and the switch group T4 may include 100 transistors coupled in parallel. The switch groups T1 to T4 may receive control signals S1 to S4 at their respective control terminals, which are based on the plurality of transmitter control signals S CTRL1 To S CTRL8 , for example, Figure 4A Therefore, the switch groups T1 to T4 can be controlled by the control signals S1 to S4 based on the plurality of transmitter control signals S CTRL1 To S CTRL8 To control the output by the transmission control signal S TX Indicates the bus transfer signal V BUS , and can therefore transition between the dominant state, the inhibited state and the recessive state. The bus transmission signal V BUS An example of transitioning between states is Fig. 6A , Fig. 7A , Fig. 8A and Figure 8B As shown. Fig. 6A In the bus, the signal V BUS From the recessive state to the dominant state. Fig. 7A In the bus, the signal V BUS From the dominant state to the recessive state via the inhibitory state. Fig. 8A and Figure 8B Both transitions are shown.

[0028] In step 101, the method 100 receives a transmission control signal S TX , the transmission control signal is configured to transition between a dominant state and a recessive state, and thereby instructs the transmitter 200 to output the bus transmission signal V in the corresponding state BUS and transitions between dominant and recessive states, as described above. Transmission control signal S TX Examples of Figure 6B , Figure 7B and FIG. 8A to FIG. 8B As shown. Transmission control signal S TX It may be provided by a microcontroller or some other type of logic device configured to communicate with other devices over a bus.

[0029] In step 102, the method 100 detects a transmission control signal S TX The first state transition is one of an explicit to implicit state transition and an implicit to explicit state transition.

[0030] Based on the transmission control signal S received in step 101 TX and the first state transition detected in step 102, the method 100 performs the following steps in step 103 by transmitting the control signal S TX A plurality of delays are applied to continuously generate a plurality of transmitter control signals.

[0031] As described above, the plurality of delays define the time intervals between the control of individual sections of the transmitter (such as individual transistors of one of the switch groups T1 to T4 of the transmitter 200), and thus define the bus transmission signal V BUS More precisely, multiple delays can be defined as shown in equation (1):

[0032] TD={td1,…,tsup,…,tdn} (1)

[0033] In equation (1), T D Indicates multiple delays. Multiple delays T D Including n delays t d1 to dn and the suppression delay t sup , inhibition delay t sup The bus transmits the signal V BUS Inhibit delay t sup Based on a plurality of delays T including n delays D , the continuous generation of multiple transmitter control signals can generate n transmitter control signals.

[0034] To illustrate the principle of including n delays and suppressing delay t supMultiple delays T D Conceptually generate n transmitter control signals, respectively in Fig. 6A and Figure 6B as well as Fig. 7A and Figure 7B Examples with n=8 are provided for implicit to explicit transitions and explicit to implicit transitions.

[0035] exist Fig. 6A In the bus, the signal V BUS From a latent state to an explicit state, such as Fig. 6A The voltage diagram and the conductivity diagram are shown in both diagrams, and are shown at the upper end of the two diagrams. In the voltage diagram, V rec and V dom Respectively represent the bus transmission signal V in recessive state and dominant state BUS In the conductivity diagram, G rec , G sup and G dom represents the conductivity of the output of the transmitter 200 in the recessive state, the inhibited state, and the dominant state. In addition, the vertical dashed lines indicate 6A to 7B The start and end of eight of the exemplary multiple delays. The corresponding delay t d1 to d8 is also indicated at the lower end of both graphs.

[0036] Figure 6B shows the transmission control signal S TX lead to Fig. 6A The bus transmission signal V BUS The implicit to explicit transformation. Fig. 6A As shown, the transmission control signal S TX At the delay t d1 Initially, it shows a transition from recessive to dominant. d1 When it expires, a transmitter control signal S is generated CTRL1 , which corresponds to being delayed by a delay t d1 The transmission control signal S TX . At delay t d2 When it expires, a transmitter control signal S is generated CTRL2 , which corresponds to being delayed by a delay t d1 and t d2 The transmission control signal S TX . At delay t d3 When it expires, a transmitter control signal S is generated CTRL2 , which corresponds to being delayed by a delay t d1 ,t d2 and t d3 The transmission control signal S TX This process continues until the transmitter control signal S is generated.CTRL8 , which corresponds to the transmission control signal S delayed by the sum of all delays in the exemplary plurality of delays including eight delays. TX The plurality of control signals S are continuously generated based on an exemplary plurality of delays including eight delays. CTRL1 To S CTRL8 cause Fig. 6A The bus transmission signal V BUS , as shown by the eight latencies at the lower end of both graphs.

[0037] and Fig. 6A and Figure 6B similar, Fig. 7A and Figure 7B The same concept of explicit to implicit transition is shown. That is, Figure 7B Shows the cause Fig. 7A The bus transmission signal V BUS The dominant to recessive transition of the transmission control signal S TX .like Fig. 7A and Figure 7B As shown, when the bus changes from the dominant state to the recessive state, the bus transmission signal V BUS The suppression state is maintained during at least a portion of the suppression delay tsup, such as from the transmission signal V BUS The conductivity of the transmission control signal is shown in Figure 1, which remains at the suppressed conductivity Gsup during the duration of the suppression delay tsup. Figure 6B In other words, the transmitter control signal S CTRL8 Corresponding to being delayed by a delay t d8 The transmission control signal S TX , transmitter control information S CTRL7 Corresponding to the delayed t d8 and t d7 Transmission control information S TX ,etc. Fig. 7A The bus transmission signal V BUS The fact that the suppression state is maintained during at least a portion of the suppression delay tsup is Figure 7B This is illustrated by the fact that the transmission control signal S CTRL3 Relative to the transmission control signal S CTRL4 is delayed by delay td3 and suppressed by delay tsup.

[0038] like Fig. 6A and Figure 6B as well as Fig. 7A and Figure 7B As shown in the example, multiple transmitter control signals S CTRL1 To S CTRL8The continuous generation of the transmission control signal S refers to the fact that the transmission control signal S is generated one after another, and the transmission control signal S is applied to the transmission control signal S. TX The fact that the delay of S is accumulated with each successively generated transmitter control signal. In other words, the transmitter control signal S CTRLM Corresponding to being delayed by a delay t d1 To td M The sum of the transmission control signals S TX .

[0039] also, Fig. 6A and Figure 6B as well as Fig. 7A and Figure 7B The example shows that multiple delays have a sequence tuple, that is, multiple delays are applied to the transmission control signal S TX In order to continuously generate the order of multiple transmitter control signals. Assuming that the transmission control signal S TX There are two possible state transitions, and the sequence tuple includes an explicit to implicit sequence corresponding to the explicit to implicit state transition and an implicit to explicit sequence corresponding to the implicit to explicit state transition. The explicit to implicit sequence can be defined as shown in equation (2):

[0040] seqD2R=tdn,…,tsup,…,td1 (2)

[0041] Similarly, the implicit to explicit sequence can be defined as shown in equation (3):

[0042] seqR2D=td1,…,tdn ( 3 )

[0043] It can be seen from equations (2) and (3) that the plurality of delays includes the suppression delay tsup only in the dominant to recessive sequence. As described above, the purpose of keeping the bus transmission signal VBUS in the suppression state is to enable a faster return from logic 0 to the dominant state, i.e., logic 1. Therefore, the suppression delay tsup is not required in the recessive to dominant sequence (which corresponds to the transition from logic 0 to logic 1).

[0044] It should be understood that the plurality of delays includes a number of delays corresponding to the number of sections of the transmitter so as to continuously generate a number of transmitter control signals corresponding to the number of sections. Since each set of switches T1 to T4 of the example transmitter 200 includes eight transistors in parallel, the examples throughout the figures are based on a plurality of delays including eight delays.

[0045] From the above discussion of multiple delays and 6A to 7B It can be seen that multiple delays ultimately define the bus transmission signal V BUSThe transition time between the three states. Therefore, the minimum multiple delay T D,min It can be expressed based on equation (1), as shown in equation (4):

[0046] TD,min={tR2S,tsup,tS2D} (4)

[0047] In other words, the plurality of delays may include at least one implicit delay defining a time period corresponding to a transition time between the inhibited state and the recessive state, and at least one explicit delay defining a time period corresponding to a transition time between the explicit state and the inhibited state. D,min Indicates bus transmission signal V BUS As described above, the number of delays included in the plurality of delays may correspond to the number of sectors of the transmitter 200 and may be distributed as needed during the transitions from the recessive state to the dominant state and from the dominant state to the recessive state via the inhibited state. That is, the sum of all delays in the plurality of delays in the recessive-to-dominant sequence defines the recessive-to-dominant transition time, and the sum of all delays in the plurality of delays in the dominant-to-implicit sequence defines the dominant-to-implicit transition time, and the sum of all delays in the plurality of delays in the dominant-to-implicit sequence from the start of the dominant-to-implicit sequence to the inhibited delay defines the dominant-to-inhibited transition time.

[0048] Although the delay t d1 to d8 exist 6A to 7B , but it should be understood that the delays in the plurality of delays may define variable delay times, i.e., the delays in the plurality of delays may be different relative to each other and may have any length required to define the transition times from the recessive state to the dominant state and from the dominant state via the inhibited state to the recessive state according to the specification of the bus to which the transmitter is coupled. For example, a delay in the plurality of delays may be defined to shorten the transition from the inhibited state to the recessive state, or may be defined to increase the bus transmission signal V BUS The slope of is maintained within the range that complies with the electromagnetic interference requirements and the timing requirements of the specification of the bus to which the transmitter is coupled.

[0049] In step 104, method 100 performs a control operation based on a plurality of transmitter control signals S CTRL1 To S CTRL8 To control four sets of switches to transmit bus transmission signals. In other words, multiple transmitter control signals S CTRL1 To S CTRL8 is provided to various sections of the transmitter, such as control terminals of transistors forming the transmitter 200, so as to control the transmission control signal S received in step 101. TXCauses the bus to transmit signal V BUS The four switches can be controlled by multiple transmitter control signals S CTRL1 To S CTRL8 directly controlled, or may be converted into control signals, such as control signals S1 to S4, as will be described with respect to Figure 4A and Figure 4B discussed.

[0050] The method 100 may include step 105, wherein the method 100 detects that the transmission control signal S TX The second state transition may also be one of an explicit to implicit state transition and an implicit to explicit state transition.

[0051] After detecting the second state transition in step 105, method 100 may proceed to step 106, where method 100 determines whether the second state transition is a recessive to dominant state transition and whether the plurality of transmitter control signals generated successively in step 103 have reached at least the suppression delay t sup In other words, the method 100 may determine the transmission control signal S in step 106. TX Whether it indicates that the bus transmission signal V BUS will be in the dominant state so that the bus transmits the signal V BUS The determination may also include determining which delay is currently being applied to generate the plurality of transmission control signals in step 103, so as to determine whether the continuous generation of the plurality of transmission control signals has reached or exceeded the suppression delay t sup , that is, whether the continuous generation of multiple transmission control signals in step 103 and the corresponding control in step 104 have reached the bus transmission signal V BUS from suppression to recessive transformation.

[0052] If the corresponding control in step 103 and step 104 has not reached the bus transmission signal V BUS If the suppressed to recessive transition of the control signal S is detected, the method 100 may proceed to step 110, where the method 100 may be performed by transmitting the control signal S in a recessive to dominant sequence starting from the last delay applied in the dominant to recessive sequence. TX The plurality of delays are applied to continuously generate the plurality of transmitter control signals. In other words, step 110 corresponds to step 103, wherein the application of the plurality of delays is immediately changed from a dominant to recessive sequence to a recessive to dominant sequence. Thus, method 100 may continue to perform step 104 based on the continuous generation of the plurality of transmitter control signals of step 110, such as Figure 1 As shown by the arrow pointing from step 110 to step 104.

[0053] It should be understood that if step 103 has applied the last delay of the plurality of delays, that is, if the bus transmission signal is transmitted before the transmission control signal S TX After the first transition of has reached the recessive state, the method 100 may start transmitting the control signal S by a first delay in a plurality of delays in a sequence from recessive to dominant. TX The plurality of delays is applied to perform step 110. In other words, if step 103 has applied the last delay of the plurality of delays, step 110 may be performed like step 103 and may be considered to correspond to step 103 in this case.

[0054] If the corresponding control in step 103 and step 104 has reached the bus transmission signal V BUS If the suppression is to be implicitly changed, the method 100 may proceed to steps 107 to 109.

[0055] In step 107, the method 100 may transmit the control signal S TX A plurality of auxiliary delays are applied to successively generate the plurality of auxiliary transmitter control signals. As described above, the plurality of auxiliary delays correspond to delays defining a transition from a recessive state to an inhibited state in the plurality of delays, the delays being applied in an auxiliary recessive-to-dominant sequence. Return FIG. 6A to FIG. 7B , where the plurality of delays includes eight delays, the plurality of auxiliary delays in this example includes three delays, ie, all delays before the suppression delay in the plurality of delays. Thus, in this example, the plurality of auxiliary transmitter control signals generated in step 107 corresponds to the transmitter control signal S CTRL1 To S CTRL3 More generally, the plurality of auxiliary transmitter control signals may correspond to transmitter control signals that cause the transmitter 200 to transition from the recessive state to the inhibited state. However, unlike the transmitter control signals used to control the transmitter 200, the plurality of auxiliary transmitter control signals may be used only for subsequent monitoring in step 108 and not for controlling the transmitter.

[0056] In step 108, method 100 may monitor the continuous generation of the plurality of transmitter control signals and the continuous generation of the plurality of auxiliary transmitter control signals to determine the intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence. To this end, as part of step 108, method 100 may continuously compare the transmission control signals S TXThe method 100 may generate a plurality of delays and corresponding ones of the plurality of auxiliary delays for the plurality of transmit controller signals and the plurality of auxiliary transmitter control signals, and determine an intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence if the generating of the plurality of transmitter control signals and the generating of the plurality of auxiliary transmitter control signals apply corresponding ones of the plurality of delays and corresponding ones of the auxiliary delays to the transmitter control signals. In other words, the method 100 may compare the generating of the plurality of transmitter control signals of step 103 and the generating of the plurality of auxiliary transmitter control signals of step 107 in step 108 to determine when the corresponding ones of the plurality of delays and corresponding ones of the plurality of auxiliary delays are applied by steps 103 and 107. This comparison may be performed at step 108. Figure 1 In the example, this is indicated by arrows pointing from step 108 to step 103 and step 107, and vice versa.

[0057] Fig. 8A and Figure 8B The concept of step 110 and steps 107 and 108 is shown. To this end, both figures show an exemplary transmission control signal S TX , which exhibits a first state transition from a dominant state to a recessive state and a second state transition from a recessive state to a dominant state. Fig. 8A In the exemplary transmission control signal S TX The second state transition occurs faster than Figure 8B The two figures also show the bus transmission signal V BUS The voltage level and conductivity level of , and a dominant state counter, which indicates the number of transmitter control signals in the dominant state with a solid line and the number of auxiliary transmitter control signals in the dominant state with a dotted line. Assume Fig. 8A and Figure 8B The examples are all transmitting signals V from the bus BUS and an exemplary transmission control signal S TX All transmitter control signals S CTRL1 To S CTRL8 Initially, all are in the dominant state and transition to the recessive state based on the plurality of delays and generation of the transmitter control signals in step 103. Thus, the dominant state counters of the plurality of transmitter control signals decrease as the transmitter control signals successively transition to the recessive state.

[0058] exist Fig. 8A Indicates the bus transmission signal V BUS An exemplary transmission control signal S returning to the dominant state TX The second state transition occurs at the last transmission control signal S CTRL1Therefore, the method 100 proceeds from step 105 to step 110 via step 106 to generate a plurality of transmitter control signals starting from the first delay of the plurality of delays in the recessive to dominant sequence in order to transmit the bus transmission signal V BUS Transition to dominant state. Since step 107 is never triggered, the master state counter for multiple auxiliary delays remains at zero.

[0059] exist Figure 8B Indicates the bus transmission signal V BUS An exemplary transmission control signal S returning to the dominant state TX The second state transition occurs at the inhibition delay t sup During this period, this can be seen, for example, in the conductivity diagram, and the dominant state counter of the plurality of transmitter control signals remains at the transmitter control signal S in the dominant state. CTRL1 To S CTRL3 Thus, method 100 proceeds from step 105 to step 107 via step 106 and begins continuously generating the auxiliary control signal, as indicated by the dashed line, while still continuously generating the transmitter control signal as part of step 103. As indicated by the incrementing main state counter of the auxiliary transmitter control signal and the decrementing main state counter of the transmitter control signal, steps 103 and 107 continue to generate the transmitter control signal based on the first transition and the second transition, respectively, until step 107 determines that both steps 103 and 107 apply the delay t d2 To generate S in the hidden state CTRL2 and the corresponding auxiliary transmitter control signal in a dominant state. This is represented in the main state counter diagram by the intersecting solid and dashed lines. Thus, at this point in time, step 107 determines the intersection of the delay application by steps 103 and 107 and therefore proceeds to step 109.

[0060] In step 109, the method 100 may transmit the control signal S in a recessive-to-dominant sequence starting from a delay corresponding to the intersection among the plurality of delays after the intersection is determined. TX Multiple delays are applied to continuously generate multiple transmitter control signals. Figure 8B As shown, the master state counters of the plurality of transmitter control signals start to increase again after the intersection. Based on the continuous generation of the plurality of transmitter control signals in step 109, the method 100 controls the bus transmission signal V in step 104. BUS Return to the explicit state, such as Figure 1 The arrow from step 109 to step 104 and Figure 8B The bus transfer signal returning to the dominant state is shown in FIG.

[0061] In summary, the method 100 controls the signal STX After the first transition, multiple transmission control signals are generated to generate a bus transmission signal V BUS , the plurality of transmission control signals corresponding to the transmitter control signals S successively delayed by a plurality of delays as discussed with respect to steps 101 to 104 TX If the first transition is a dominant to recessive transition and a second transition back to the dominant state occurs, steps 107 and 108 or step 110 may be performed to return to the dominant state in a timely manner.

[0062] It should be understood that the voltage levels used to indicate the recessive and dominant states of signals in the figures are provided as examples only. Depending on the implementation of the examples of the present disclosure, the dominant state may be represented by a logical 0 and the recessive state may be represented by a logical 1, or vice versa.

[0063] The method 100 may be implemented by a bus transmission circuit, such as Figures 2 to 5E Examples of the present disclosure are shown.

[0064] Figure 2 An example bus transmission circuit according to the present disclosure is shown, which includes a transmitter having multiple sections (such as the transmitter 200 discussed above), a transmission control circuit 400, and may also include control signal conversion logic 300.

[0065] The transmission control circuit is configured to implement Figure 1 To this end, the transmission control circuit includes a delay logic 410 and may further include an auxiliary delay logic 420 and a delay comparison logic 430.

[0066] The delay logic 410 is configured to transmit the control signal S TX Multiple delays are applied. Therefore, the delay logic 410 is configured to perform steps 103, 109, and 110 of the method 100. To this end, the delay logic 410 may include multiple delay elements corresponding to the multiple delays described above. Since the example in the figure is based on an exemplary multiple delay with eight delays, Figure 5B The example of the delay logic 410 in EMBODIMENT 4 includes eight delay elements 440 and an inhibitory delay element 411 .

[0067] like Figure 5B As shown, the plurality of delay elements 440 may be arranged as a delay element chain coupled to each other. More specifically, in order to implement the plurality of transmission control signals S in a recessive to dominant sequence or a dominant to recessive sequence CTRL1 To S CTRL8 Each delay element 440 may be coupled to an adjacent delay element 440 via two connections. More specifically, each delay element 440 may be coupled to an adjacent delay element 440 after having applied its delay to the transmission control signal S TXThen a transmission control signal S is provided in one of the two directions. TX , so as to realize the continuous generation of multiple transmission control signals S in the currently applicable sequence CTRL1 To S CTRL8 Therefore, the transmission control signal S TX and (after application of the first delay in the currently applicable sequence) the currently generated transmission control signal may be in the transmission control signal S TX The recessive-to-dominant transition propagates from left to right and can transmit control signals on the bus S TX The two propagation directions are as follows: Figure 5B In addition, each delay element 440 is configured to receive a transmission control signal S TX , in order to configure the direction of propagation, i.e., which sequence of the plurality of delayed sequence tuples is used. Before being provided to each delay element 440, if a second transition is detected as discussed with respect to steps 105 and 106, i.e., if the second transition is detected while the delay logic 410 is still transmitting the control signal S based on the first transition TX Applying multiple delays, the transmission control signal S can be transmitted through AND gate 412 TX With dominant to recessive transition signal S D2R The comparison is performed to change the propagation direction of the plurality of delay elements 440. If the control signal S is transmitted based on the output of the AND gate 412 TX is provided to each delay element 440, then the signal provided to each delay element 330 may be referred to as S TX,INT .

[0068] In order to achieve the suppression delay t sup , the delay suppression element 411 may be coupled to Figure 5B The third delay element 440 and the fourth delay element 440 in the embodiment of the present invention are used to transmit the transmitter control signal S CTRL3 To S CTRL1 Delay suppression delay t sup ,like Figure 7B To this end, the suppression delay element 411 can be implemented, for example, by a resistor and a capacitor. If the suppression delay t sup To achieve this in a controllable manner, both the resistor and the capacitor can also provide controllable resistance values ​​and controllable capacitance values. sup is only applied in a dominant to recessive sequence, thus bypassing the suppressor delay element 411 in the right-to-left propagation direction in the delay logic 410. More generally, the suppressor delay element 411 can thus be coupled to the bus transmission signal V BUSThe last delay element 440 corresponds to the transition from the dominant state to the inhibited state and is coupled to the bus transfer signal V BUS The transition from the inhibited state to the recessive state corresponds to the first delay element 440 but only in the direction corresponding to the dominant to recessive sequence.

[0069] The delay logic 410 can convert the plurality of transmitter control signals S CTRL1 To S CTRL8 directly to the transmitter 200, or for example Figure 2 As shown, multiple transmitter control signals S CTRL1 To S CTRL8 The conversion logic 300 may be configured to convert the plurality of transmitter control signals S CTRL1 To S CTRL8 In addition, the delay logic 410 can convert the bus transmission signal V BUS The transmitter control signal corresponding to the transition from the inhibited state to the recessive state (i.e., Figure 5B In the example, the transmitter control signal S CTRL1 To S CTRL3 ) is provided to the delay comparison logic 430 as the bus signal S CTRL(3:1) , in order to implement steps 105 to 109 (if to be implemented).

[0070] The conversion logic 300 may be as follows Figure 4A and Figure 4B As shown in Figure 4A As shown, the conversion logic 300 may include eight paired conversion units 3101 to 3108. Each paired conversion unit 310 i The two transmitter control signals S CTRL,i and S CTRL,n-i+1 Converted into four control signals S 1,i To S 4,i That is, each pair conversion unit 310 i A control signal may be generated for each of the four sets of switches of the transmitter 200. For example, the pair conversion unit 3101 may convert the transmitter control signal S CTRL1 and S CTRL8 Converted into control signal S 1,1 To S 4,1 , and the paired conversion unit 3108 can convert the transmitter control signal S CTRL8 and S CTRL1 Converted into control signal S 1,8 To S 4,8 Each pair conversion unit 310 i The conversion of two transmitter control signals into four control signals can be performed as Figure 4B shown.

[0071] Each pair conversion unit 310 i It may include two inverting amplifiers 311, two non-inverting amplifiers 312, and an XOR gate 313. Based on these elements, each pair conversion unit 310 i The transmitter control signal S can be inverted and amplified CTRL(i) To generate the control signal S 1,i , by amplifying the transmitter control signal S CTRL(i) To generate the control signal S 4,i , by amplifying and inverting the output of the XOR gate 313 to generate the control signal S 2,i , and generates a control signal S by amplifying the output of the XOR gate 313 3,i The XOR gate 313 can receive S CTRL(i) and S CTRL,n-i+1 .

[0072] The auxiliary delay logic 420 may include an inverter 421, an AND gate 422, a multiplexer 423, and a plurality of auxiliary delay elements, which may be implemented by a delay element 440, as previously discussed with respect to the delay logic 410. The auxiliary delay logic 420 may implement step 107, i.e., continuously generate a plurality of auxiliary transmitter control signals. To this end, the plurality of auxiliary delay elements may be arranged as an auxiliary delay element chain.

[0073] The auxiliary delay element chain includes a number of delay elements 440 corresponding to the number of delay elements 440 included in the delay logic 410, and these delay elements are configured to generate a signal V BUS The transmitter control signal changes from the inhibited state to the dominant state, i.e., Figure 5B and Figure 5C In the example, three delay elements transmit the control signal S TX Application delay t d1 to d3 In addition, the plurality of auxiliary delay elements includes an additional delay element 440 at the end of the delay element chain. The additional delay element may receive the final auxiliary transmitter control signal S AUX3 , delaying the final auxiliary transmitter control signal S AUX3 , and provides a delayed final auxiliary transmitter control signal S AUX3 As the selection signal of the multiplexer 423. Therefore, the auxiliary delay element 440 chain of the auxiliary delay logic may include one more delay element than the delay element 440 included in the delay logic 410 to generate the bus transition signal V BUS Transmitter control signal to transition from inhibited state to recessive state.

[0074] Instead of transmitting the control signal S TX Each auxiliary delay element 440 can receive an auxiliary delay element input signal S AUX,IN The auxiliary delay element input signal S can be generated AUX,IN , so that when the transmission control signal S is detected TX The second transition from the recessive state to the dominant state causes the auxiliary delay logic 420 to start generating a plurality of auxiliary transmitter control signals S AUX1 To S AUX3 , while the delay logic 410 is based on the transmission control signal S TX In the process of generating a plurality of transmitter control signals by a first state transition from a dominant state to a recessive state, the first state transition causes the bus transmission signal V BUS From the repressed state to the recessive state. Figure 5B In the example, the bus transmission signal V BUS The transmitter control signal transitioning from the inhibit state to the recessive state corresponds to the transmitter control signal S CTRL1 To S CTRL3 .

[0075] To generate the auxiliary delay element input signal S AUX,IN , the auxiliary delay logic 420 may receive the internal transmission control signal S TX,INT , left output signal S OUT,L4 and the left output signal S OUT,L1 . Left output signal S OUT,L4 and S OUT,L1 corresponds to the output of the fourth delay element and the first delay element in the left direction (ie, in the dominant to recessive direction). In addition, the left output signal S OUT,L4 Corresponding to the transmitter control signal S CTRL4 , the delay logic 410 applies a first delay to the signal that inhibits the transition to recessive, namely, the delay t d3 (See Figure 7B ), and the left output signal S OUT,L1 Corresponding to the transmitter control signal S CTRL1 , that is, the delay logic 410 applies the bus transmission signal V BUS The last delayed signal of the inhibition to the recessive transition, i.e. the delay t d1 (See Figure 7B ). Therefore, the left output signal S OUT,L4 and S OUT,L1 Indicates bus transmission signal V BUS Based on these signals, the auxiliary delay 420 can be controlled by converting the left output signal S OUT,L4 Invert and use AND gate 422 to invert the left output signal S OUT,L4With signal left output S OUT,L1 The comparison is used to generate the auxiliary delay element input signal S AUX,IN The output of AND gate 422 and the internal transmission control signal S of delay logic 410 TX,INT It is then provided to a multiplexer 423 which may be controlled based on the output of the fourth delay element of the delay element chain, as described above.

[0076] The auxiliary delay logic 420 may also be configured to output an auxiliary transmitter control signal S AUX1 and bus signal S AUX(3:1) , the bus signal can combine all auxiliary transmitter control signals in the plurality of auxiliary transmitter control signals as the bus signal.

[0077] Figure 5D An example of an implementation of a delay element 440 according to an example of the present disclosure is provided, which delay element can be used in the delay logic 410 and the auxiliary delay logic 420. As shown, if the delay element 440 is to be used in the delay logic 410, the delay element 440 can be configured to receive the left input signal S IN,L , right input signal S IN,R and the internal transmission control signal S TX,INT If the auxiliary logic 420 and the delay comparison logic 430 are not implemented, the control signal may be a transmission control signal S TX , or if the delay element 440 is to be used in the auxiliary delay logic 420, the control signal may be the auxiliary delay element input signal S AUX,IN In addition, the delay element 440 can be configured to output the left output signal S OUT,L , right output signal S OUT,R and the transmitter control signal S CTRL . Right input signal S IN,R corresponds to the signal provided to the delay element 440 in the right propagation direction, i.e., when multiple delay elements apply corresponding delays in a dominant to recessive sequence. IN,L corresponds to the signal provided to the delay element 440 in the left propagation direction, that is, when the plurality of delay elements apply the corresponding delays in a recessive to dominant sequence. Thus, when the delay element 440 transmits the control signal S in a dominant to recessive sequence TX When its delay is applied, that is, when the delay element 440 is applied to the right input signal S IN,R When its delay is applied, the left output signal S OUT,L Corresponding to the output of the delay element. When the delay element 440 transmits the control signal S in a recessive to dominant sequence TX When its delay is applied, that is, when the delay element 440 delays the left input signal S IN,LWhen its delay is applied, the right output signal S OUT,R Corresponds to the output of the delay element.

[0078] In order to IN,L , right input signal S IN,R and the internal transmission control signal S TX,INT Generate left output signal S OUT,L , right output signal S OUT,R and the transmitter control signal S CTRL The delay element 440 may include a multiplexer 441, a delay unit 442, an AND gate 443, and an OR gate 444. The multiplexer 443 receives the right input signal S IN,R and the left input signal S IN,L Both, and one of the two signals is provided to the delay unit 442. The transmission control signal S TX , internal transmission control signal S TX,INT Or auxiliary delay element input signal S AUX,IN can be provided to the multiplexer 441 as a selection signal of the multiplexer 441. Therefore, if the transmission control signal S TX , internal transmission control signal S TX,INT or delay element input signal S AUX,IN In the recessive state, the multiplexer 441 converts the right input signal S IN,R Provided to the delay unit 442. In addition, if the transmission control signal S TX , internal transmission control signal S TX,INT Or auxiliary delay element input signal S AUX,IN In the dominant state, the multiplexer 441 converts the left input signal S IN,L Provided to delay unit 442.

[0079] The delay element 442 may be implemented, for example, by a resistor and a capacitor. If the suppression delay of the suppression delay element 440 is to be realized in a controllable manner, both the resistor and the capacitor may also provide a controllable resistance value and a controllable capacitance value.

[0080] The output of the delay element 442 is provided as the transmitter control signal S of the delay element 440. CTRL In addition, the output of the delay element 442 is provided to an AND gate 443 and an OR gate 444, which also receive the transmission control signal S TX , internal transmission control signal S TX,INT Or auxiliary delay element input signal S AUX,IN, depending on whether the delay element 440 is used in the delay logic 410 and whether the auxiliary logic 420 is implemented or whether the delay element 440 is to be used in the auxiliary logic 420. The output of the AND gate 443 is provided as the right output S OUT,R The output of OR gate 444 is provided as the left output S OUT,L AND gate 443 and OR gate 444 thereby ensure that only signals having a dominant state are propagated to the right and only signals having a recessive state are propagated to the left.

[0081] Figure 5E An example of delay comparison logic 430 is provided. Delay comparison logic 430 may be configured to implement step 108 of method 100, namely, monitoring the generation of a plurality of transmitter control signals and a plurality of auxiliary transmitter control signals to determine an intersection of a sequence of applying a plurality of delays and a sequence of applying a plurality of auxiliary delays. To this end, delay comparison logic 430 may receive an auxiliary delay element input signal S AUX,IN , auxiliary transmitter control signal S AUX1 , bus signal S AUX(3:1) and bus signal S CTRL(3:1) If the auxiliary delay element input signal S AUX,IN In the dominant state, the auxiliary delay element input signal S AUX,IN The auxiliary logic 420 may be indicated to have started generating a plurality of auxiliary transmitter control signals. AUX,IN , auxiliary transmitter control signal S AUX1 , bus signal S AUX(3:1) and bus signal S CTRL(3:1) , the delay logic 430 may generate a dominant to recessive transition signal S D2R , which can indicate the transmission signal S TX However, based on the detection of the intersection by the delay comparison logic 430, the dominant to recessive transition signal S D2R The transmission signal S TX In other words, the delay comparison logic 430 only generates the dominant to recessive transition signal S D2R , to indicate that the explicit to implicit transition has occurred once the intersection of the sequence of applying multiple delays and applying multiple auxiliary delays is determined.

[0082] In order to generate the dominant to recessive transition signal S as described above D2R The delay comparison logic may include a comparison unit 431, an AND gate 432, and a trigger 433. The comparison unit 431 may be configured to compare the bus signal S AUX(3:1) and bus signal S CTRL(3:1) . Bus signal SCTRL(3:1) The transmitter control signal included in the dominant state is greater than the bus signal S AUX(3:1) The comparison unit 431 outputs a logic 1 if the auxiliary transmitter control signal S CTRL1 and S CTRL2 In the dominant state, and only the auxiliary transmitter control signal S AUX1 is in a dominant state, the comparison unit 431 outputs a logic 1. As another example, if only the transmitter control signal S CTRL1 is in the dominant state, and the auxiliary transmitter control signal S AUX1 and S AUX2 is in a dominant state, then the comparison unit 431 outputs a logic 0. Based on the comparison, the unit 431 can determine that the sequence of applying multiple delays intersects the sequence of applying multiple auxiliary delays. The output of the comparison unit 431 is provided to the inverting reset input of the flip-flop 433. The set input of the flip-flop 433 can receive the auxiliary transmitter control signal S through the AND gate 432. AUX1 The auxiliary delay element compares the input signal S AUX,IN The flip-flop 433 may use the set input and the inverted reset input to output the dominant to recessive transition signal S as defined above. D2R .

[0083] It should be understood that Figures 2 to 5E The implementation of the method 100 shown is provided only as an example. The method 100 can be implemented in any manner based on the following principles, that is, based on the transmission control signal S TX The state change will transmit the control signal S TX Multiple delays are continuously delayed to generate the bus transfer signal V BUS The corresponding change is achieved by using the bus transmission signal V BUS The inhibit state shortens the bus transmission signal V BUS The delay time of the state transition.

[0084] The present invention can be further illustrated by the following examples.

[0085] In one example, a method for generating a bus transmission signal for transmission on a bus by a transmitter, the transmitter including an H-bridge formed by four sets of switches, wherein the bus transmission signal is configured to transition between a dominant state, an inhibit state, and a recessive state, the method including: receiving a transmission control signal, the transmission control signal being configured to transition between a dominant state and a recessive state; detecting a first state transition of the transmission control signal, the first state transition being one of a dominant to recessive state transition and a recessive to dominant state transition; continuously generating a plurality of transmitter control signals based on the transmission control signal, the first state transition, and a plurality of delays, wherein: the plurality of delays have a sequence tuple, the sequence tuple including a dominant to recessive sequence corresponding to a dominant to recessive state transition and a recessive to dominant sequence corresponding to a recessive to dominant state transition, and the plurality of delays including an inhibit delay included only in the dominant to recessive sequence, the inhibit delay causing the bus transmission signal to remain in an inhibit state during the inhibit delay, and continuously generating the plurality of transmitter control signals includes applying the plurality of delays to the transmission control signal based on the sequence tuple and the first state transition, and controlling the four sets of switches based on the plurality of transmitter control signals to transmit the bus transmission signal.

[0086] The example method may also include: detecting a second state transition of the transmitter control signal after the first state transition, the second state transition being one of a dominant to recessive state transition and a recessive to dominant state transition; and if the second state transition is a recessive to dominant state transition and if the consecutive generation of the plurality of transmitter control signals has reached at least the inhibit delay, consecutively generating the plurality of auxiliary transmitter control signals by applying a plurality of auxiliary delays to the transmission control signal, the plurality of auxiliary delays corresponding to delays in the plurality of delays defining a transition from a recessive state to an inhibit state and having an auxiliary recessive to dominant sequence; monitoring the consecutive generation of the plurality of transmitter control signals and the consecutive generation of the plurality of auxiliary transmitter control signals to determine an intersection of the auxiliary recessive to dominant sequence and the dominant to recessive sequence; and consecutively generating the plurality of transmitter control signals by applying a plurality of delays to the transmission control signal in a recessive to dominant sequence starting from a delay in the plurality of delays corresponding to the intersection after the determination of the intersection.

[0087] In the example method, the continuous generation of the plurality of transmitter control signals and the monitoring of the continuous generation of the plurality of auxiliary transmitter control signals may include: continuously comparing corresponding delays in a plurality of delays and a plurality of auxiliary delays applied to the transmission control signals to generate the plurality of transmitter control signals and the plurality of auxiliary transmitter control signals; and determining an intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence if the generating of the plurality of transmitter control signals and the generating of the plurality of auxiliary transmitter control signals apply corresponding delays in the plurality of delays and a plurality of auxiliary delays to the transmission control signals.

[0088] The example method may also include, if the second state transition is a recessive-to-dominant state transition and if the consecutive generation of the plurality of transmitter control signals has not reached at least the inhibit delay, consecutively generating the plurality of transmitter control signals by applying a plurality of delays to the transmission control signals in a recessive-to-dominant sequence starting from a last delay applied in the dominant-to-recessive sequence.

[0089] In the example method, the plurality of delays may further include at least one explicit delay defining a time period corresponding to a transition time between an explicit state and an inhibited state, and at least one implicit delay defining a time period corresponding to a transition time between an inhibited state and an implicit state.

[0090] In the example method, each delay of the plurality of delays may define a variable delay time.

[0091] In this example method, the sum of all delays in a plurality of delays in a recessive to dominant sequence may define a recessive to dominant transition time, the sum of all delays in a plurality of delays in a dominant to recessive sequence may define a dominant to recessive transition time, and the sum of all delays in a plurality of delays in a dominant to recessive sequence from the start of the dominant to recessive sequence to the inhibit delay may define a dominant to inhibit transition time.

[0092] In this example method, the hold-down delay may be less than a bit transfer time of the bus.

[0093] In this example method, the bus may be a controller area network (CAN) bus.

[0094] An example bus transmission circuit includes: a transmitter and a transmission control circuit, the transmitter includes an H-bridge formed by four sets of switches and is configured to provide a bus transmission signal on a bus, the bus transmission signal is configured to transition between a dominant state, an inhibited state, and a recessive state, the transmission control circuit is coupled to the transmitter and is configured to: receive the transmission control signal, the transmission control signal is configured to transition between a dominant state and a recessive state; and detect a first state transition of the transmission control signal, the first state transition being one of a dominant-to-recessive state transition and a recessive-to-dominant state transition, wherein the transmission control logic includes a delay logic, the delay logic includes a plurality of delay elements and is configured to receive the transmission control signal based on the transmission control signal, the first state transition, and the first state transition. The invention relates to a transmission control circuit for continuously generating a plurality of transmitter control signals by using a plurality of delay elements, wherein the plurality of delay elements have a sequence tuple, the sequence tuple includes a dominant-to-recessive sequence corresponding to a dominant-to-recessive state transition and a recessive-to-dominant sequence corresponding to a recessive-to-dominant state transition, the plurality of delay elements include an inhibition delay element included only in the dominant-to-recessive sequence, the inhibition delay keeps the bus transmission signal in an inhibition state during the inhibition delay, and continuously generates a plurality of transmitter control signals, the delay logic is configured to apply the plurality of delay elements to the transmission control signal in a sequence corresponding to a first state transition, wherein the transmission control circuit is further configured to control the four sets of switches based on the plurality of transmitter control signals to transmit the bus transmission signal.

[0095] In the example bus transmission circuit, the transmission control circuit may be further configured to detect a second state transition of the transmitter control signal after the first state transition, the second state transition being one of a dominant-to-recessive state transition and a recessive-to-dominant state transition, the transmission control circuit may further include an auxiliary delay logic, the auxiliary delay logic including a plurality of auxiliary delay elements, the plurality of auxiliary delay elements corresponding to delay elements defining a transition from a recessive state to an inhibited state in the plurality of delay elements and having an auxiliary recessive-to-dominant sequence, the auxiliary delay logic may be configured to: if the second state transition is a recessive-to-dominant state transition and if a plurality of transmitter control signals are generated consecutively If the suppression signal has reached at least the suppression delay, the plurality of auxiliary transmitter control signals are continuously generated by applying the plurality of auxiliary delay elements to the transmission control signal. The transmission control circuit may further include delay comparison logic, the delay comparison logic being configured to monitor the continuous generation of the plurality of transmitter control signals and the continuous generation of the plurality of auxiliary transmitter control signals to determine an intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence. The delay logic may also be configured to continuously generate the plurality of transmitter control signals by applying the plurality of delay elements to the transmission control signal in a recessive-to-dominant sequence starting from a delay of the plurality of delay elements corresponding to the intersection after the determination of the intersection.

[0096] In the example bus transmission circuit, in order to monitor the continuous generation of the plurality of transmitter control signals and the continuous generation of the plurality of auxiliary transmitter control signals, the delay comparison logic may be further configured to: continuously compare corresponding delay elements among the plurality of delay elements and the plurality of auxiliary delay elements applied to the transmission control signals to generate the plurality of transmitter control signals and the plurality of auxiliary transmitter control signals; and determine an intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence if the generation of the plurality of transmitter control signals and the generation of the plurality of auxiliary transmitter control signals apply corresponding delay elements among the plurality of delay elements and the plurality of auxiliary delay elements to the transmission control signals.

[0097] In the example bus transmission circuit, the delay logic may be configured to, if the second state transition is a recessive-to-dominant state transition and if the consecutive generation of the plurality of transmitter control signals has not reached at least the inhibit delay, consecutively generate the plurality of transmitter control signals by applying a plurality of delay elements to the transmission control signal in a recessive-to-dominant sequence starting from a last delay applied in a dominant-to-recessive sequence after the second transition.

[0098] The above description is provided to illustrate the method and corresponding bus transmission circuit for generating bus transmission signals. It should be understood that this specification is by no means intended to limit the scope of the present disclosure to the precise embodiments discussed throughout the specification. On the contrary, those skilled in the art will appreciate that the examples of the present disclosure may be combined, modified or condensed without departing from the scope of the present disclosure as defined by the following claims.

Claims

1. A method (100) for generating a bus transmission signal (V BUS ) can be transmitted on a bus by a transmitter, the transmitter comprising an H-bridge formed by four sets of switches (T1-T4), wherein the bus transmission signal (V BUS ) is configured to transition between a dominant state, an inhibited state, and a recessive state, the method comprising: Receive (101) a transmission control signal (S TX ), the transmission control signal (S TX ) is configured to transition between the dominant state and the recessive state; Detecting (102) the transmission control signal (S TX ), wherein the first state transition is one of an explicit to implicit state transition and an implicit to explicit state transition; Based on the transmission control signal (S TX ), the first state transition and a plurality of delays (t d1 -t d8 ) to continuously generate (103) a plurality of transmitter control signals (S CTRL1 -S CTRL8 ),in: The multiple delays (t d1 -t d8 ) has a sequence tuple, the sequence tuple comprising a dominant-to-recessive sequence corresponding to the dominant-to-recessive state transition and a recessive-to-dominant sequence corresponding to the recessive-to-dominant state transition, and The multiple delays (t d1 -t d8 ) includes only the inhibition delay (t sup ), the inhibition delay (t sup ) enables the bus to transmit signals (V BUS ) remains in the inhibited state during the inhibit delay, and Continuously generate (104) the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) includes transferring the plurality of delays (t d1 -t d8 ) is applied to the transmission control signal application, and Based on the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) to control (104) the four sets of switches (T1-T4) to transmit the bus transmission signal (V BUS ).

2. The method (100) according to claim 1, further comprising: Detect (105) the transmission control signal (S TX ) after the first state transition, the second state transition being one of the dominant-to-recessive state transition and the recessive-to-dominant state transition; and If (106) the second state transition is the recessive to dominant state transition and if the continuous generation (103) of the plurality of transmitter control signals has reached at least the suppression delay (t sup ),but: By controlling the transmission control signal (S TX ) applying a plurality of auxiliary delays to successively generate (107) a plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ), the plurality of auxiliary delays corresponding to the plurality of delays (t d1 -t d8 ) wherein a transition from said recessive state to said inhibited state is defined and has a delay that assists a recessive to dominant sequence; monitoring (108) the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ) to determine the intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence; as well as The plurality of transmitter control signals are continuously generated (109) by applying the plurality of delays to the transmission control signals in the implicit-to-dominant sequence starting from a delay of the plurality of delays corresponding to the intersection after the determination of the intersection.

3. The method (100) of claim 2, wherein the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ) said continuous generation (107) comprises: Continuous comparison is applied to the transmission control signal (S TX ) to generate the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and the plurality of delays (t d1 -t d8 ) and corresponding delays among the plurality of auxiliary delays; as well as If the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and generating (107) the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ) to transmit a control signal (S TX ) applies the multiple delays (t d1 -t d8 ) and the corresponding delays in the plurality of auxiliary delays, then determining the intersection of the auxiliary implicit-to-dominant sequence and the dominant-to-implicit sequence.

4. The method (100) according to any one of claims 2 and 3, further comprising: If (106) the second state transition is the recessive to dominant state transition and if the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) has not yet reached the inhibition delay (t sup ), then by applying the plurality of delays (t d1 -t d8 ) to continuously generate the multiple transmitter control signals.

5. The method (100) according to any one of the preceding claims, wherein the plurality of delays (t d1 -t d8 ) also includes: at least one dominant delay defining a time period corresponding to a transition time between the dominant state and the inhibited state; as well as At least one implicit delay defines a time period corresponding to a transition time between the inhibited state and the recessive state.

6. The method (100) according to any one of the preceding claims, wherein the plurality of delays (t d1 -t d8 ) defines a variable delay time.

7. The method (100) according to any one of the preceding claims, wherein: The plurality of delays (t d1 -t d8 ) defines the implicit to explicit transition time, The plurality of delays (t d1 -t d8 ) defines the dominant to recessive transition time, and From the start of the dominant to recessive sequence to the inhibition delay (t sup ) of the plurality of delays (t d1 -t d8 ) defines the dominant to inhibited transition time.

8. The method (100) according to any one of the preceding claims, wherein the suppression delay (t sup ) is less than the bit transmission time of the bus.

9. The method (100) of claim 6, wherein the bus is a Controller Area Network (CAN) bus.

10. A bus transmission circuit, comprising: The transmitter (200) includes an H-bridge formed by four sets of switches (T1-T4) and is configured to provide a bus transmission signal (V BUS ), the bus transmission signal (V BUS ) is configured to transition between a dominant state, an inhibited state, and a recessive state; as well as A transmission control circuit (400) is coupled to the transmitter (200) and is configured to: Receive transmission control signal (S TX ), the transmission control signal (S TX ) is configured to transition between the dominant state and the recessive state, and Detecting the transmission control signal (S TX ), the first state transition being one of a dominant-to-recessive state transition and a recessive-to-dominant state transition, wherein the transmission control logic (400) comprises a delay logic (410), the delay logic comprising a plurality of delay elements (440) and configured to transmit the transmission control signal (S TX ), the first state transition and the plurality of delay elements (440) to continuously generate a plurality of transmitter control signals (S CTRL1 To S CTRL8 ),in: The plurality of delay elements (440) have a sequence tuple including a dominant-to-implicit sequence corresponding to the dominant-to-implicit state transition and a recessive-to-dominant sequence corresponding to the recessive-to-dominant state transition, The plurality of delay elements (440) include an inhibiting delay element (411) included only in the dominant-to-recessive sequence, the inhibiting delay element (411) causing the bus transmission signal (V BUS ) remains in the inhibited state while applying the inhibit delay element (411), and In order to continuously generate the plurality of transmitter control signals (S CTRL1 To S CTRL8 ), the delay logic (410) is configured to delay the transmission control signal (S TX ) applies the plurality of delay elements (440), wherein the transmission control circuit (410) is further configured to transmit the plurality of transmitter control signals (S CTRL1 To S CTRL8 ) to control the four sets of switches (T1-T4) to transmit the bus transmission signal (V BUS ).

11. The bus transmission circuit according to claim 10, wherein: The transmission control circuit (400) is further configured to detect the transmission control signal (S TX ), the second state transition being one of the explicit-to-implicit state transition and the implicit-to-explicit state transition, The transmission control circuit (400) further includes auxiliary delay logic (420), the auxiliary delay logic including a plurality of auxiliary delay elements (440), the plurality of auxiliary delay elements corresponding to delay elements of the plurality of delay elements (440) defining a transition from the recessive state to the inhibited state and having an auxiliary recessive to dominant sequence, The auxiliary delay logic (410) is configured to: if the second state transition is the recessive to dominant state transition and if the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) has at least reached the suppression delay element (411), then by controlling the transmission control signal (S TX ) applying the plurality of auxiliary delay elements (440) to continuously generate a plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ), The transmission control circuit (400) further comprises a delay comparison logic (430) configured to: monitor the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ) to determine the intersection of the auxiliary recessive-to-dominant sequence and the dominant-to-recessive sequence, and The delay logic (410) is further configured to: after the determination of the intersection, the transmission control signal (S) is transmitted in the implicit to dominant sequence starting from the delay of the plurality of delay elements (440) corresponding to the intersection. TX ) applies the plurality of delay elements (440) to continuously generate the plurality of transmitter control signals (S CTRL1 -S CTRL8 ).

12. The bus transmission circuit according to claim 11, wherein in order to monitor the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ), the delay comparison logic (430) is further configured to: Continuous comparison is applied to the transmission control signal (S TX ) to generate the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ) of the plurality of delay elements (440) and a corresponding delay element of the plurality of auxiliary delay elements (440); and If the plurality of transmitter control signals (S CTRL1 -S CTRL8 ) and generating the plurality of auxiliary transmitter control signals (S AUX1 -S AUX3 ) to transmit a control signal (S TX ) applies a corresponding delay element (440) among the plurality of delay elements (440) and a corresponding delay element (440) among the plurality of auxiliary delay elements (440), then determines the intersection of the auxiliary implicit-to-dominant sequence and the dominant-to-implicit sequence.

13. The bus transmission circuit according to any one of claims 11 and 12, wherein the delay logic (410) is configured to: If the second state transition is the recessive-to-dominant state transition and if the continuously generated plurality of transmitter control signals have not yet reached at least the inhibit delay element (411), the transmit control signals (S) are inhibited by inhibiting the transmission control signals (S) in the recessive-to-dominant sequence starting from the last delay applied in the dominant-to-recessive sequence after the second transition. TX ) applying the plurality of delay elements (440) to continuously generate the plurality of transmitter control signals (S CTRL1 -S CTRL8 ).

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