A method for implementing a SPAD array-based pulse camera

Abstract

A kind of SPAD array-based pulse camera implementation method, comprising the following steps: step one: the pulse signal representing photon output by SPAD array pixel is converted into an n-photon pulse signal representing that n photons are detected within a certain time by digital logic system;Wherein n is the integer greater than or equal to 1;Step two: according to the preset readout timing, the n-photon pulse signal of each pixel in a row of pixels is sequentially read out in a cycle, and the n-photon pulse signal sequence of each pixel is obtained;Step three: the relationship between n-photon pulse signals in the n-photon pulse sequence output by each pixel is used to derive the light intensity, and the pulse camera detection function is completed.The present application can solve the problem of SPAD pulse camera adapting to different scenes and low signal-to-noise ratio, so that it can be widely popularized and applied.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of pulse cameras, in particular to a pulse camera implementation method based on a SPAD array. BACKGROUND

[0002] Pulse cameras based on pulse imaging theory have great potential in high-speed imaging, target tracking, and intelligent imaging based on pulse neural networks. Pulse cameras capture photons through photosensitive devices, generate pulses when the cumulative number of photons reaches a set threshold, and accordingly reconstruct the light intensity at any time to achieve high-speed imaging in continuous time. Existing pulse cameras based on CIS imaging chips use comparators for threshold judgment, consume a large number of chips, and have limited detection sensitivity. Single-photon avalanche diodes (SPADs) are a kind of photoelectric detection devices with fast response, high gain, etc. When a SPAD detects a photon input, it outputs a pulse signal under the joint action of a quenching circuit. Based on SPAD devices, a pulse stream for pulse imaging can be directly output to complete the function of a pulse camera. However, due to the different photon response capabilities of different background light intensities and the low signal-to-noise ratio of single-photon response, a pulse camera implementation method suitable for SPADs is needed to solve the problem of low signal-to-noise ratio and adapt to different scenarios. SUMMARY

[0003] The application provides a pulse camera implementation method based on a SPAD array to solve the defects in the prior art.

[0004] The application is implemented by the following technical solutions:

[0005] A pulse camera implementation method based on a SPAD array, comprising the following steps:

[0006] Step 1: converting the pulse signals representing photons output by the SPAD array pixels into an n-photon pulse signal representing n photons detected in a certain time through a digital logic system; wherein n is an integer greater than or equal to 1;

[0007] Step 2: sequentially reading out the n-photon pulse signals of each pixel in a row of pixels in a cycle according to a preset readout timing to obtain a sequence of n-photon pulse signals of each pixel;

[0008] Step 3: the relationship between the n-photon pulse signals in the n-photon pulse sequence output by each pixel realizes the deduction of the light intensity and completes the pulse camera detection function.

[0009] The pulse camera implementation method based on a SPAD array as described above, wherein the digital logic system comprises a photon counting module, a counting comparison module, and a counting reset module.

[0010] The photon counting module is configured to accumulate and count the photon signals output by the SPAD photon detector pixels.

[0011] The counting comparison module is configured to compare the photon counting value output by the photon counting module with a set threshold n, and output an n-photon pulse signal when the accumulated counting value of the photon counting module reaches the set threshold n.

[0012] The counting reset module is configured to reset the photon counting module according to the n-photon pulse signal output by the counting comparison module.

[0013] The readout timing in step two is configured to output the n-photon pulse signals output by the digital logic system in each pixel of the pixel array in a time sequence.

[0014] The gray-scale image expressing the light intensity is reconstructed by the cumulative counting method or the pulse interval method in step three.

[0015] The cumulative counting method is configured to count the number of pulse signals output in a period of time, and obtain the gray-scale value of the pixel representing the light intensity information in the period of time.

[0016] The pulse interval method is configured to count the readout period between two pulses output by the pixel, and obtain the time required for accumulating n photons, and the reciprocal of the accumulated light intensity time is the gray-scale value corresponding to the time.

[0017] The SPAD array is composed of M columns and N rows of pixel units arranged, and each row of M pixels is connected in sequence based on the readout timing, and the output of each pixel data in the row is completed at the end of each row. Each of the M pixels in each row includes a readout shift register connected in sequence, and under the control of a unified readout signal and a readout clock, the readout of the pixel data in the row is realized. The pixel unit includes a SPAD device, a quenching circuit, a photon counting circuit, a comparison and latching circuit, a counting reset circuit, a latching reset circuit, and a readout shift register.

[0018] The pulse camera implementation method based on the SPAD array as described above, the photon counting circuit is composed of n-bit D flip-flop, and the output n-bit binary value represents the number of recorded SPAD array output digital pulses; The reset of the counter is controlled by the counting reset circuit.

[0019] The pulse camera implementation method based on the SPAD array as described above, the comparison latch circuit is composed of a digital comparator and a D flip-flop; The comparison latch circuit is inputted with an external m-bit binary code value to determine the photon threshold; When the counting value outputted by the photon counting circuit is equal to the set photon threshold, a high level "1" is outputted and latched by the latch; When the counting value outputted by the photon counting circuit does not reach the set photon threshold, a low level "0" is outputted and the latch does not respond.

[0020] The pulse camera implementation method based on the SPAD array as described above, the latch reset circuit is used to reset the D flip-flop in the comparison latch circuit according to the trigger of the readout signal; The reset method ensures that the counting function and the comparison function of the circuit are not affected by the subsequent readout timing and work normally.

[0021] The pulse camera implementation method based on the SPAD array as described above, the counting reset circuit is used to reset the counter in the photon counting circuit according to the output of the comparison latch circuit.

[0022] The pulse camera implementation method based on the SPAD array as described above, the readout shift register includes a D flip-flop and a two-way selector; The two-way selector is controlled by the readout signal to control the data in the current pixel or the data of the previous pixel to enter the D flip-flop; The output end of the D flip-flop is connected to the two-way selector of the next pixel; The D flip-flop completes the transfer and readout of the data between pixels under the control of the readout clock.

[0023] The advantage of the present application is that the present application can solve the problem of SPAD pulse camera adapting to different scenes and low signal-to-noise ratio, so that it can be widely promoted and applied. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 It is a schematic diagram of the SPAD array structure of the present application;

[0026] Figure 2 are the cumulative counting method (Fig. a) and the pulse interval method (Fig. b) of the pixel output pulse sequence in the present application to reconstruct the gray scale image representing the light intensity;

[0027] Figure 3 is a schematic diagram of the circuit structure in a single pixel of the present application. DETAILED DESCRIPTION

[0028] To make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0029] A pulse camera implementation method based on a SPAD array, comprising the following steps:

[0030] Step one: converting the pulse signal representing photons output by the SPAD array pixel into an n-photon pulse signal representing n photons detected in a certain time through a digital logic system; wherein n is an integer greater than or equal to 1;

[0031] Step two: sequentially performing cyclic readout on the n-photon pulse signals of each pixel in a row of pixels according to a preset readout timing to obtain the n-photon pulse signal sequence of each pixel;

[0032] Step three: the relationship between the n-photon pulse signals in the n-photon pulse sequence output by each pixel realizes the deduction of the light intensity and completes the pulse camera detection function.

[0033] Preferably, the digital logic system described in the embodiment comprises a photon counting module, a counting comparison module and a counting reset module.

[0034] Preferably, the photon counting module described in the embodiment is used for accumulating counting the photon signals output by the SPAD photon detector pixel.

[0035] Preferably, the counting comparison module described in the embodiment is used for comparing the photon counting value output by the photon counting module with the set threshold value n, and when the counting value of the photon counting module accumulates to the set threshold value n, an n-photon pulse signal is output; the generation of the n-photon pulse signal is determined by the set threshold value n and occurs when n photons are detected by the SPAD array; the set threshold value n is a positive integer and can be selected according to the scene light intensity and the array readout rate.

[0036] Preferably, the count reset module in the embodiment is used to reset the photon counting module according to the n-photon pulse signal output by the count comparison module.

[0037] Preferably, the readout timing in the second step in the embodiment is used to output the n-photon pulse signal output by the digital logic system in each pixel of the pixel array in sequence.

[0038] Preferably, each row of the pixel array in the embodiment is composed of M pixels, each pixel is connected in sequence, and the last pixel realizes external data output.

[0039] Preferably, as shown in the embodiment, the digital logic system generates the n-photon pulse signal of each pixel in a row of M pixels based on the readout clock during the readout signal trigger period. Figure 1

[0040] Preferably, the readout clock in the embodiment is connected to each pixel to control the signal in each pixel to be read out in sequence, and the readout of the data of one pixel is completed in each clock cycle, that is, M clock cycles are needed to read out the data of the row.

[0041] Preferably, the readout signal in the embodiment is used to complete the synchronous storage of the data in each pixel during the non-trigger period, and the data of the row of pixels is read out in sequence during the readout signal trigger period.

[0042] Preferably, the readout signal in the embodiment is triggered for M clock cycles each time, and the non-trigger event lasts for one clock cycle each time.

[0043] Preferably, the SPAD array in the embodiment needs M+1 clock cycles for one readout.

[0044] Preferably, the data read out by each row of pixels in the embodiment is an M data sequence composed of M "0"s and "1"s, and a plurality of M data sequences are formed after the same row of pixels is read out in multiple cycles, and the data combination at the same position of each M data sequence forms the n-photon pulse signal sequence of the pixel corresponding to the position.

[0045] ​The threshold value is 4 in the embodiment, the first row represents the photon stream, due to the randomness of the photon behavior and the change of the light intensity, the photon pulse shows a non-equidistant pulse sequence; the second row represents the SPAD detector pixel output photon signal, under the action of the SPAD and the quenching circuit, one pulse signal is output for each detected photon; the third row represents the cumulative counting of the photon counting module to the photon signal, when the photon counting value reaches 4, the digital logic resets the photon counting module and starts a new photon counting; the fourth row represents the n-photon pulse, when the photon counting value reaches 4, the n-photon pulse signal is pulled up to high level; when the rising edge of the readout signal comes, the n-photon pulse signal is reset to low level; the fifth row represents the readout signal, the readout signal high level lasts for M readout clock periods, and the readout signal low level lasts for 1 readout clock period; during the high level period, the n-photon pulse of each pixel in the row is sequentially transferred to the readout, and during the low level period, the next readout period is prepared. The sixth row represents the pixel readout pulse signal, under the control of the readout signal, the n-photon pulse signal is read out and converted into a “01” signal sequence according to the readout signal frequency; when the rising edge of the readout signal comes, if the n-photon pulse signal is high level, “1” is output, and if the n-photon pulse signal is low level, “0” is output.

[0046] Preferably, as shown in the step three of the embodiment, the gray scale image representing the light intensity is reconstructed by the cumulative counting method or the pulse interval method. Figure 2

[0047] Preferably, the specific operation of the cumulative counting method of the embodiment is as follows: the number of pulse signals output in a period of time is cumulatively counted to obtain the gray scale value of the pixel in the period of time, which represents the light intensity information; in the embodiment, the cumulative period is 4, that is, the gray scale value of the time period (4*readout period) is output after every four signals are cumulatively counted, and the pulse signal sequence is converted into a 4-value gray scale sequence.

[0048] Preferably, the specific operation of the pulse interval method of the embodiment is as follows: the readout period between two pulses output by the pixel is counted to obtain the time required for accumulating n photons, and the inverse of the light intensity accumulation time is the gray scale value corresponding to the time; that is, the interval between each “1” and the previous “1”; the light intensity at the time is inversely proportional to the pulse interval, and the pulse interval can obtain the gray scale value between the two pulses.

[0049] Preferably, the SPAD array of the embodiment is composed of M column N row pixel units arranged, based on the readout timing, each row of M pixels is connected in sequence, and the data output of each pixel in the row is completed at the end of each row; the readout shift register in each row of M pixels is connected in sequence, and under the control of the unified readout signal and the readout clock, the readout of the pixel data in the row is realized; the pixel unit (the circuit structure diagram is as shown in​Figure 3 The SPAD device, quenching circuit, photon counting circuit, comparison latch circuit, counting reset circuit, latch reset circuit, and readout shift register are shown in FIG. 1.

[0050] Preferably, the photon counting circuit is composed of n-bit D flip-flop, and outputs n-bit binary value to represent the number of recorded SPAD array output digital pulses; the reset of the counter is controlled by the counting reset circuit.

[0051] Preferably, the comparison latch circuit is composed of digital comparator and D flip-flop; the comparison latch circuit is inputted with m-bit binary code from outside to determine the photon threshold value; when the output count value of the photon counting circuit is equal to the set photon threshold value, the comparison latch circuit outputs high level "1", and the output is latched by the latch; when the output count value of the photon counting circuit is not equal to the set photon threshold value, the comparison latch circuit outputs low level "0", and the latch does not respond.

[0052] Preferably, the latch reset circuit is used to reset the D flip-flop in the comparison latch circuit according to the trigger of the readout signal; the reset method ensures that the counting function and comparison function of the circuit are not affected by the subsequent readout timing and work normally.

[0053] Preferably, the counting reset circuit is used to reset the counter in the photon counting circuit according to the output of the comparison latch circuit.

[0054] Preferably, the readout shift register includes D flip-flop and two-way selector; the two-way selector is controlled by the readout signal to control the data in the current pixel or the data in the previous pixel to enter the D flip-flop; the output end of the D flip-flop is connected to the two-way selector of the next pixel; the D flip-flop completes the transfer and readout of the data between pixels under the control of the readout clock.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing a SPAD array based pulsed camera, the method comprising: It comprises the following steps: Step one: converting the pulse signal representing photons output by the SPAD array pixel into an n-photon pulse signal representing n photons detected in a certain time through a digital logic system; wherein n is an integer greater than or equal to 1; Step two: sequentially performing cyclic readout on the n-photon pulse signal of each pixel in a row of pixels according to a preset readout timing to obtain the n-photon pulse signal sequence of each pixel; Step three: the relationship between the n-photon pulse signals in the n-photon pulse sequence output by each pixel realizes the deduction of light intensity and completes the pulse camera detection function; The digital logic system comprises a photon counting module, a counting comparison module, and a counting reset module; The photon counting module is used to accumulate and count the photon signals output by the SPAD photon detector pixel; The counting comparison module is used to compare the photon counting value output by the photon counting module with the set threshold value n, and when the counting value of the photon counting module accumulates to the set threshold value n, an n-photon pulse signal is output; The counting reset module is used to reset the photon counting module according to the n-photon pulse signal output by the counting comparison module; In step three, the gray-scale image expressing light intensity is reconstructed by the cumulative counting method or the pulse interval method; The specific operation of the cumulative counting method is to accumulate and count the number of pulse signals output in a period of time to obtain the gray-scale value of the pixel representing the light intensity information in that period of time; The specific operation of the pulse interval method is to count the readout period between two pulses output by the pixel to obtain the time required for accumulating n photons, and the reciprocal of the light intensity accumulation time is the gray-scale value corresponding to that moment.

2. The method of claim 1, wherein: The readout timing in step two outputs the n-photon pulse signal output by the digital logic system inside each pixel of the pixel array in sequence.

3. The method of claim 1, wherein: The SPAD array is composed of M columns and N rows of pixel units, and each row of M pixels is connected in sequence based on the readout timing, and the data of each pixel in the row is output at the end of each row; the readout shift register inside each row of M pixels is connected in sequence, and under the control of the unified readout signal and the readout clock, the readout of the data of the entire row of pixels is realized; the pixel unit comprises a SPAD device, a quenching circuit, a photon counting circuit, a comparison and latching circuit, a counting reset circuit, a latching reset circuit, and a readout shift register.

4. The method of claim 3, wherein: The photon counting circuit is composed of an n-bit D flip-flop, which outputs an n-bit binary number representing the number of recorded digital pulses output by the SPAD array; the reset of the counter is controlled by the counting reset circuit.

5. The method of claim 3, wherein: The comparison and latching circuit is composed of a digital comparator and a D flip-flop; the comparison and latching circuit is externally inputted with an m-bit binary code value to determine the photon threshold value; when the counting value output by the photon counting circuit is equal to the set photon threshold value, a high level "1" is output, and the latch is latched; when the counting value output by the photon counting circuit does not reach the set photon threshold value, a low level "0" is output, and the latch does not respond.

6. The method of claim 5, wherein: The latch reset circuit is used for resetting the D flip-flop in the comparison latch circuit according to the trigger of the readout signal; and the reset method ensures that the circuit counting function and the comparison function are not affected by the subsequent readout timing and can be normally completed.

7. The method of claim 3, wherein the SPAD array-based pulse camera is implemented by: The counting reset circuit is used for resetting the counter in the photon counting circuit according to the output of the comparison latch circuit.

8. The method of claim 3, wherein the SPAD array-based pulse camera is implemented by: The readout shift register comprises a D flip-flop and a two-way selector; the two-way selector is controlled by the readout signal to control the data in the current pixel or the data in the previous pixel to enter the D flip-flop; and the output end of the D flip-flop is connected to the two-way selector of the next pixel. The D flip-flop is used for completing the transfer and readout of the data between pixels under the control of the readout clock.

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