Storage unit, storage structure and preparation method thereof

Abstract

The present disclosure relates to a memory cell, a memory structure, and a method for preparing the same. The memory cell includes: a shared bit line extending along a first direction; a shared word line extending along a third direction, and the shared word line includes a write word line portion and a read word line portion; a first filling structure located on the sidewalls of the write word line portion; a write channel structure including a write gate dielectric layer and a write channel layer, the write gate dielectric layer extending along the sidewalls of the write word line portion and each sidewall of the first filling structure, and the write channel layer located on the surface of the write gate dielectric layer; an isolation layer including a first isolation portion, the first isolation portion located on a side of the write channel layer away from the shared word line; a read channel structure including a read gate dielectric layer and a read channel layer, the read gate dielectric layer extending along the sidewalls of the first isolation portion and the sidewalls of the write channel layer, and the read channel layer extending along the sidewalls of the shared bit line, the surface of the read gate dielectric layer, and the sidewalls of the read word line portion. In the embodiments of the present disclosure, the storage density can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a memory cell, a memory structure, and a preparation method thereof. Background Art

[0002] With the development of storage technology, people have increasingly higher demands on the integration and density of storage devices.

[0003] Traditionally, storage density has been increased through fabrication methods such as the 6F2 layout and buried word lines. However, further scaling at smaller sizes using these methods can significantly degrade device electrical performance. This makes further scaling very difficult, limiting further increases in storage density.

[0004] A 2TOC memory cell consists of two transistors (a read transistor and a write transistor) without a capacitor, effectively reducing the area occupied by the memory cell and thereby increasing storage density. However, the storage density of existing 2TOC memory cells still cannot meet the growing demand. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a storage unit, a storage structure and a preparation method thereof that can further improve storage density.

[0006] A storage unit comprising:

[0007] a shared bit line extending along a first direction;

[0008] a shared word line arranged along a second direction with the shared bit line, the shared word line extending along a third direction, the shared word line including a write word line portion and a read word line portion connected to each other in the first direction, the first direction intersecting with the second direction, a plane defined by the first direction and the second direction being a first plane, and the third direction intersecting with the first plane;

[0009] a first filling structure located on a sidewall of the write word line portion away from the shared bit line;

[0010] a write channel structure, comprising a write gate dielectric layer and a write channel layer, wherein the write gate dielectric layer extends along a sidewall of the write word line portion facing the shared bit line, a sidewall of the write word line portion away from the read word line portion, and each sidewall of the first filling structure, and the write channel layer is located on a surface of the write gate dielectric layer away from the write word line portion and surrounds the write word line portion and the first filling structure;

[0011] an isolation layer, comprising a first isolation portion, wherein the first isolation portion is located on a side of the write channel layer away from the shared word line along the first direction;

[0012] A read channel structure includes a read gate dielectric layer and a read channel layer, wherein the read gate dielectric layer extends along the sidewall of the first isolation portion away from the shared word line, the sidewall of the first isolation portion away from the shared bit line, and the sidewall of the write channel layer away from the write gate dielectric layer, and the read channel layer extends along the sidewall in the second direction of the shared bit line, the surface of the read gate dielectric layer away from the side of the write channel layer, and the sidewall in the second direction of the read word line portion.

[0013] In one embodiment, compared to the sidewall of the first filling structure away from the shared bit line along the second direction, the sidewall of the first isolation portion away from the shared bit line along the second direction is closer to the shared bit line.

[0014] In one embodiment, the isolation layer further includes a second isolation portion, and the second isolation portion is located between the read word line portion and the shared bit line.

[0015] In one embodiment, the memory cell further includes a second filling structure, the second filling structure including a first filling portion and a second filling portion, the second filling portion and the first filling portion are respectively located on opposite sides of the read word line portion in the second direction, and the first filling portion is located between the second isolation portion and the write channel layer, and the second filling portion is located between the write gate dielectric layer and the read gate dielectric layer.

[0016] In one embodiment, the second filling structure further includes a third filling portion, and the third filling portion is located between the read word line portion and the second isolation portion.

[0017] In one embodiment, the read word line portion includes a first sub-word line portion, a second sub-word line portion and a third sub-word line portion, the first sub-word line portion is connected to the write word line portion in a first direction, the second sub-word line portion and the third sub-word line portion are both connected to the first sub-word line portion in a second direction, and the second sub-word line portion is connected to the read channel layer in the second direction, and the third sub-word line portion and the second sub-word line portion are respectively located on both sides of the second filling portion in the first direction.

[0018] In one embodiment, the shared bit line includes a write bit line portion and a read bit line portion connected in the second direction, the write bit line portion extends along the first direction, the read bit line portion is located between the write bit line portion and the read channel layer, and the read channel layer is located on the side wall of the read bit line portion.

[0019] In one embodiment, the method includes:

[0020] substrate;

[0021] A plurality of memory cell layers are stacked along a third direction on the substrate, each of the memory cell layers comprising a plurality of the aforementioned memory cells, wherein the shared word line passes through each of the memory cell layers and is shared by the related memory cells of each of the memory cell layers.

[0022] A method for preparing a storage structure, comprising:

[0023] A substrate is provided, wherein a first region and a second region are provided on the substrate, the first region including a first sub-region and a second sub-region, the first sub-region is located between the first region and the second sub-region, the second direction intersects the first direction, and a plane defined by the first direction and the second direction is a first plane;

[0024] forming a comb-tooth-shaped stacked structure on the substrate, the stacked structure comprising alternating sacrificial material layers and isolation material layers, and the stacked structure having a comb-tooth stem and comb-tooth bars, the comb-tooth stem extending along a first direction and located in the first region, the comb-tooth bars located in the second region, and a plurality of the comb-tooth bars arranged along the first direction on the comb-tooth stem, with isolation initial structures between the comb-tooth bars;

[0025] A first through-hole extending along a third direction is formed on a side of the comb-tooth bar close to the first region, and the remaining comb-tooth bars form an annular rack. A write channel material layer and a write gate dielectric material layer are sequentially formed on the sidewall of the first through-hole, and a write word line portion and a first filling material layer are formed on the surface of the write gate dielectric material layer. The write word line portion fills the first through-hole of the first sub-region, and the first filling material layer fills the first through-hole of the second sub-region. The third direction intersects the first plane.

[0026] Removing the initial isolation structure located in the second sub-region and the initial isolation structure located on the side of the write word line portion in the first sub-region, and removing the annular rack located in the second sub-region, so that the remaining initial isolation structure forms an isolation structure, and the remaining annular rack forms a first sub-tooth and a second sub-tooth, wherein the second sub-tooth is located between the isolation structure and the first through-hole, and the isolation material layer in the first sub-tooth forms a first isolation portion;

[0027] forming a read gate dielectric material layer and a read channel material layer in sequence along the sidewalls of the comb teeth in the second direction, the sidewalls of the first sub-tooth, the sidewalls of the write channel material layer, and the sidewalls of the second sub-tooth;

[0028] removing the write gate dielectric material layer, the write channel material layer, and a portion of the second sub-tooth located between the write word line portion and the isolation structure to form a second through hole extending along the third direction;

[0029] forming a read word line portion in the second through hole, the read word line portion being spaced apart from the write channel material layer and connected to the read channel material layer, wherein the read word line portion is connected to the write word line portion to form a shared word line;

[0030] removing the isolation material layer located in the first region to form a hollow cavity, and forming a shared bit line filling the hollow cavity and connecting the read channel material layer;

[0031] The sacrificial material layer is removed, and the write channel material layer, the write gate dielectric material layer, the read gate dielectric material layer, the read channel material layer, and the first filling material layer are side-etched opposite to the sacrificial material layer to form a write channel layer, a write gate dielectric layer, a read gate dielectric layer, a read channel layer, and a first filling structure, respectively, wherein the write channel layer and the write gate dielectric layer form a write channel structure, and the read gate dielectric layer and the read channel layer form a read channel structure.

[0032] In one embodiment, removing the write gate dielectric material layer, the write channel material layer, and a portion of the second sub-tooth located between the write word line portion and the isolation structure to form a second through hole includes:

[0033] The write gate dielectric material layer, the write channel material layer and the portion of the second sub-tooth opposite to the write word line portion are removed to form an initial opening, and the remaining second sub-tooth forms a third sub-tooth, and the isolation material layer in the third sub-tooth forms a second isolation portion, and the second isolation portion and the first isolation portion form an isolation layer.

[0034] In one embodiment, while removing the write gate dielectric material layer, the write channel material layer, and a portion of the second sub-tooth opposite to the write word line portion to form the initial opening, portions of the write channel material layer located on both sides of the initial opening in the second direction are also removed to form a first opening and a second opening, wherein the first opening connects to the first region, and the first opening, the second opening, and the initial opening form an initial through hole;

[0035] removing the read gate dielectric material layer, the read channel material layer, and a portion of the second sub-tooth located between the write word line portion and the isolation structure to form a second through hole, further comprising:

[0036] A second filling material layer is filled in a portion of the initial through hole, wherein the second filling material layer includes a first filling material and a second filling material respectively filled in the first opening and the second opening, and the remaining initial through hole forms an intermediate through hole.

[0037] The read gate dielectric material layer and the write gate dielectric material layer located on the sidewall of the middle through hole in the second direction are removed to form a third opening and a fourth opening. The third opening, the fourth opening and the middle through hole form the second through hole.

[0038] In one embodiment, the second filling material layer further includes a third filling material, and the third filling material is filled on the side wall of the third sub-tooth.

[0039] In one embodiment, while removing the sacrificial material layer and side-etching the write channel material layer, the write gate dielectric material layer, the read gate dielectric material layer, the read channel material layer, and the portion of the first filling material layer opposite to the sacrificial material layer, the portion of the second filling material layer opposite to the sacrificial material layer is also side-etched, and the remaining second filling material layer forms a second filling structure.

[0040] In one embodiment, removing the isolation material layer in the first region to form a hollow cavity, and forming a shared bit line filling the hollow cavity and connecting the read channel layer includes:

[0041] removing the read gate dielectric material layer located on the sidewall of the comb teeth to form a fifth opening;

[0042] removing the isolation material layer located in the first area to form the hollow cavity;

[0043] A shared bit line is formed in the hollow cavity and the fifth opening, and the shared bit line is located between adjacent sacrificial material layers in the third direction.

[0044] In one embodiment, the step of sequentially forming a read gate dielectric material layer and a read channel material layer on the sidewalls of the comb teeth in the second direction, the sidewalls of the first sub-tooth, the sidewalls of the write channel material layer, and the sidewalls of the second sub-tooth includes:

[0045] forming the read gate dielectric material layer along the sidewalls of the comb teeth in the second direction, the sidewalls of the first sub-tooth, the sidewalls of the write channel material layer, the sidewalls of the second sub-tooth, and the sidewalls of the isolation structure, and forming a read channel material layer on a surface of the read gate dielectric material layer away from the write channel material layer;

[0046] The read gate dielectric material layer and the read channel material layer located on the sidewalls of the isolation structure are removed.

[0047] The above-mentioned memory cell, memory structure, and preparation method thereof include a shared word line and a shared bit line. The shared word line includes a write word line portion and a read word line portion connected to each other. The write word line portion can serve as the write word line of the write transistor, and the read word line portion can serve as the read word line of the read transistor. Furthermore, the shared bit line can simultaneously serve as the write bit line of the write transistor and the read bit line RBL of the read transistor. This effectively saves the wiring area of ​​the memory cell, thereby effectively improving the memory cell density. At the same time, this can simplify the wiring process. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 is a flow chart of a method for preparing a storage structure provided in one embodiment;

[0050] Figures 2 to 17 Schematic diagram of the structure obtained during the preparation of the storage structure provided in one embodiment, wherein: Figures 5 to 17 A schematic diagram illustrating a structure obtained during the preparation of a storage unit in a storage structure;

[0051] Figure 18 A schematic diagram of a local structure of a storage structure provided in one embodiment;

[0052] Figure 19 A schematic structural diagram of a storage unit provided in one embodiment;

[0053] Figure 20 A circuit diagram of a memory cell provided in accordance with an embodiment.

[0054] Description of reference numerals:

[0055] 100-substrate, 200-stacked structure, 2101-sacrificial material layer, 2201-isolation material layer, 200a-comb tooth stem, 200b-comb tooth bar, 200c-annular rack, 200d-first sub-tooth, 200e-second sub-tooth, 200f-third sub-tooth, 300-isolation structure, 3001-isolation initial structure, 400-write channel structure, 410-write channel layer, 411 first channel portion, 412-second channel portion, 413-third channel portion, 420-write gate dielectric layer, 4101-write channel material layer, 4201-write gate dielectric material layer, 500-shared word line, 510-write word line portion, 520-read word line portion, 600-first filling structure, 6001-first filling material layer, 700-read channel structure, 71 0-read gate dielectric layer, 720-read channel layer, 721-fourth channel portion, 722-fifth channel portion, 723-sixth channel portion, 7101-read gate dielectric material layer, 7201-read channel material layer, 800-shared bit line, 810-write bit line portion, 820-read bit line portion, 900-second filling structure, 910-first filling portion, 920-second filling portion, 930-third filling portion, 9001-second filling material layer, 9101-first filling portion material, 9201-second filling portion material, 9301-third filling portion material, 10-first through hole, 20-second through hole, 21-initial through hole, 21a-first opening, 21b-second opening, 22-middle through hole, 23-third opening, 24-fourth opening, 30-hollow cavity. DETAILED DESCRIPTION

[0056] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0058] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0059] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0060] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] In one embodiment, see Figure 1 , provides a method for preparing a storage structure, comprising the following steps:

[0062] Step S10, providing a substrate 100, wherein the substrate 100 is provided with a first area A1 and a second area A2 extending along a first direction and arranged along a second direction, the second area A2 including a first sub-area A21 and a second sub-area A22, the first sub-area A21 being located between the first area A1 and the second sub-area A22, the second direction intersecting the first direction, and a plane defined by the first and second directions being a first plane;

[0063] Step S20, see Figures 2 to 4 A comb-tooth-shaped stacked structure 200 is formed on a substrate 100. The stacked structure 200 includes alternating sacrificial material layers 2101 and isolation material layers 2201. The stacked structure 200 has a comb-tooth stem 200a and comb-tooth bars 200b. The comb-tooth stem 200a extends along a first direction and is located in a first area A1. The comb-tooth bars 200b are located in a second area A2. A plurality of comb-tooth bars 200b are arranged along the first direction on the comb-tooth stem 200a. Isolation initial structures 3001 are formed between the comb-tooth bars 200b.

[0064] Step S30, see Figures 5 to 8 A first through hole 10 extending along a third direction is formed on a side of the comb-tooth bar 200b close to the first area A1, and the remaining comb-tooth bars 200b form an annular rack 200c. A write channel material layer 4101 and a write gate dielectric material layer 4201 are sequentially formed on the sidewalls of the first through hole 10. A write word line portion 510 and a first filling material layer 6001 are formed on the surface of the write gate dielectric material layer 4201. The write word line portion 510 fills the first through hole 10 in the first sub-area A21, and the first filling material layer 6001 fills the first through hole 10 in the second sub-area A12. The third direction intersects the first plane.

[0065] Step S40, see Figure 9 , removing the isolation initial structure 3001 located in the second sub-area A22 and the isolation initial structure 3001 located on the side of the write word line portion 510 in the first sub-area A21, and removing the annular rack 200c located in the second sub-area A22. The remaining isolation initial structure 3001 forms the isolation structure 300. The remaining annular rack 200c forms a first sub-tooth 200d and a second sub-tooth 200e. The second sub-tooth 200e is located between the isolation structure 300 and the first through-hole 10. The isolation material layer 2201 in the first sub-tooth 200d forms a first isolation portion 221.

[0066] Step S50, see Figures 10 and 11 A read gate dielectric material layer 7101 and a read channel material layer 7201 are sequentially formed along the sidewalls of the comb tooth stem 200a in the second direction, the sidewalls of the first sub-tooth 200d, the sidewalls of the write channel material layer 4101, and the sidewalls of the second sub-tooth 200e;

[0067] Step S60, see Figures 12 to 13 , removing the write gate dielectric material layer 4201 , the write channel material layer 4101 , and a portion of the second sub-tooth 200 e located between the write word line portion 510 and the isolation structure 300 to form a second through hole 20 extending along the third direction;

[0068] Step S70, see Figure 14 A read word line portion 520 is formed in the second through hole 20 , the read word line portion 520 being spaced apart from the write channel material layer 4101 and connected to the read channel material layer 7201 . The read word line portion 520 is connected to the write word line portion 510 to form a shared word line 500 .

[0069] Step S80, please refer to Figures 15 and 16 , removing the isolation material layer 2201 located in the first area A1 to form a hollow cavity 30 , and forming a shared bit line 800 filling the hollow cavity 30 and connected to the read channel material layer 7201 ;

[0070] Step S90, see Figure 17 , remove the sacrificial material layer 2101, and side-etch the write channel material layer 4101, the write gate dielectric material layer 4201, the read gate dielectric material layer 7101, the read channel material layer 7201, and the first filling material layer 6001 opposite to the sacrificial material layer 2101 to form a write channel layer 410, a write gate dielectric layer 420, a read gate dielectric layer 710, a read channel layer 720, and a first filling structure 600, respectively, wherein the write channel layer 410 and the write gate dielectric layer 420 form a write channel structure 400, and the read gate dielectric material layer 7101 and the read channel layer 720 form a read channel structure 700.

[0071] In step S10, refer to Figure 2 The base 100 may include a substrate. The substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator substrates. The type of substrate should not limit the scope of protection of the present disclosure.

[0072] As an example, the base 100 may further include other functional film layers formed on the substrate. Of course, the base 100 may also include only the substrate, and its specific form may be set according to requirements.

[0073] The substrate 100 may be provided with a plurality of groups of first areas A1 and second areas A2 arranged along the second direction. Each group of first areas A1 and second areas A2 extends along the first direction and is arranged along the second direction. In this manner, multiple groups of memory cells arranged along the second direction may be formed. Each group of first areas A1 and second areas A2 may form a group of memory cells. Memory cells in the same group and in the same layer may share a common shared bit line 800 extending along the first direction.

[0074] In step S20, when forming the stacked structure 200 on the substrate 100, refer to Figure 2 First, sacrificial material layers 2101 and isolation material layers 2201 made of different materials may be alternately formed on the substrate 100 by a deposition process or the like.

[0075] The isolation material layer 2201 may be made of a different material than the sacrificial layer 112, so that they can serve as etch stop layers for each other. The material of the sacrificial material layer 2101 may include, but is not limited to, silicon oxide. The material of the isolation material layer 2201 may include, but is not limited to, silicon nitride.

[0076] Furthermore, as an example, at least one isolation material layer 2201 may be formed. When the number of isolation material layers 2201 is greater than or equal to two, multiple stacked memory cell layers may be formed, thereby increasing storage density.

[0077] Then, see Figure 3 The sacrificial material layer 2101 and the isolation material layer 2201 in the second area A2 can be etched using a photolithography process, thereby forming a plurality of isolation trenches in the second area A2 that penetrate the sacrificial material layer 2101 and the isolation material layer 2201. The plurality of isolation trenches are spaced apart along the first direction. The sacrificial material layer 2101 and the isolation material layer 2201 between adjacent isolation trenches form comb teeth 200b. Simultaneously, the sacrificial material layer 2101 and the isolation material layer 2201 in the first area A1 form comb teeth 200a.

[0078] Afterwards, see Figure 4 , the isolation trench may be filled with an initial isolation structure 3001. The material of the initial isolation structure 3001 may be different from that of the sacrificial material layer 2101 and the isolation material layer 2201. In this case, when the sacrificial material layer 2101 or the isolation material layer 2201 is removed in the relevant steps, the initial isolation structure 3001 may not be removed.

[0079] As an example, the material of the isolation initial structure 3001 may include, but is not limited to, a low dielectric constant material.

[0080] In step S30, refer to Figure 5A first through hole 10 extending along the third direction can be formed by photolithography, etching, etc. The first through hole 10 is located on a side of the comb bar 200b close to the first area A1, thereby exposing the comb bar 200a of the first area A1.

[0081] At this time, after the first through hole 10 is formed, the ring-shaped rack 200 c formed by the remaining comb teeth 200 b has an open side, and the comb teeth stem 200 a is connected to the open side.

[0082] Then, see Figure 6 A write channel material layer 4101, a write gate dielectric material layer 4201, and a first filling material layer 6001 extending along the third direction can be sequentially formed on the sidewall of the first through hole 10 by processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first filling material layer 6001 can initially fill the first through hole 10.

[0083] Afterwards, see Figure 7 , the first filling material layer 6001 in the first through hole 10 in the first sub-area A21 can be removed. Then, refer to Figure 8 , and then forming a write word line portion 510 in the second through hole 20 of the first sub-area A21.

[0084] At this time, the write word line portion 510 may extend along the third direction. Meanwhile, a write gate dielectric material layer 4201 is provided between the write word line portion 510 and the write channel material layer 4101 , thereby serving as the write word line WWL of the write transistor T1 .

[0085] The material of the write channel material layer 4101 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, thereby improving transistor performance. Furthermore, IGZO material cost is relatively low and the manufacturing process is relatively simple, thereby effectively reducing process costs.

[0086] The material for writing the gate dielectric material layer 4201 may include, but is not limited to, high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0087] The material of the first filling material layer 6001 may include, but is not limited to, silicon nitride. For example, the material of the first filling material layer 6001 may also include silicon oxide or silicon oxynitride.

[0088] The material of the write word line portion 510 may include, but is not limited to, metal tungsten (W). For example, the material of the write word line 510 may also include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al).

[0089] In step S40, refer to Figure 8 , the isolation initial structure 3001 that needs to be removed can be removed by photolithography, etching and other processes, thereby forming the isolation structure 300. Then, refer to Figure 9 The annular rack 200c in the second sub-area A22 can be removed by photolithography, etching, or other processes to form the first sub-tooth 200d and the second sub-tooth 200e. The first sub-tooth 200d and the second sub-tooth 200e are located in the first sub-area A21 and connected to the comb tooth stem 200a.

[0090] In step S50 , the read gate dielectric material layer 7101 and the read channel material layer 7201 may be sequentially formed through a deposition process and may extend along the third direction.

[0091] As an example, step S50 may include:

[0092] Step S51, see Figure 10 A read gate dielectric material layer 7101 is formed along the sidewalls of the comb-tooth stem 200a in the second direction, the sidewalls of the first sub-tooth 200d, the sidewalls of the write channel material layer 4101, the sidewalls of the second sub-tooth 200e, and the sidewalls of the isolation structure 300, and a read channel material layer 7201 is formed on the surface of the read gate dielectric material layer 7101 away from the write channel material layer 4101;

[0093] Step S52, see Figure 11 , the read gate dielectric material layer 7101 and the read channel material layer 7201 located on the sidewalls of the isolation structure 300 are removed.

[0094] At this time, in step S51 , a read gate dielectric material layer 7101 and a read channel material layer 7201 may be formed on both the horizontal surface and the vertical surface (sidewall) of the structure formed in the previous step by chemical vapor deposition or the like.

[0095] Then, the read gate dielectric material layer 7101 and the read channel material layer 7201 located on the horizontal surface can be removed by anisotropic etching methods such as dry etching, thereby forming a read gate dielectric material layer 7101 and a read channel material layer 7201 located on the side wall of the comb tooth stem 200a in the second direction, the side wall of the first sub-tooth 200d, the side wall of the write channel material layer 4101, the side wall of the second sub-tooth 200e and the side wall of the isolation structure 300.

[0096] In step S52 , the read gate dielectric material layer 7101 and the read channel material layer 7201 located on the sidewalls of the isolation structure 300 may be removed by photolithography, etching, or other processes.

[0097] Of course, in other examples, step S50 can also be implemented in other ways. For example, a mask layer covering the isolation structure 300 can also be formed first. Then, a read gate dielectric material layer 7101 and a read channel material layer 7201 can be formed on the horizontal surface and vertical surface (sidewall) of the structure after the mask layer is formed by chemical vapor deposition or the like. Afterwards, the read gate dielectric material layer 7101 and the read channel material layer 7201 located on the horizontal surface are removed, and the read gate dielectric material layer 7101 and the read channel material layer 7201 located on the sidewall of the comb stem 200a in the second direction, the sidewall of the first sub-tooth 200d, the sidewall of the write channel material layer 4101, and the sidewall of the second sub-tooth 200e are retained. The mask layer is then removed.

[0098] The material of the read gate dielectric material layer 7101 may include, but is not limited to, a high-k dielectric material such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the read gate dielectric material layer 7101 may be the same as or different from the material of the write gate dielectric material layer 4201.

[0099] The material of the read channel material layer 7201 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, thereby improving transistor performance. Furthermore, IGZO material cost is relatively low and the manufacturing process is relatively simple, thereby effectively reducing process costs.

[0100] In step S60, refer to Figure 12 as well as Figure 13 The write gate dielectric material layer 4201 located between the write word line portion 510 and the isolation structure 300, the write channel material layer 4101 located between the write word line portion 510 and the isolation structure 300, and the second sub-tooth 200e located between the write word line portion 510 and the isolation structure 300 can be removed simultaneously by dry etching or the like, thereby forming a second through hole 20 exposing the write word line portion 510.

[0101] In step S70, refer to Figure 14 The second through hole 20 extends along the third direction. Therefore, the read word line portion 520 formed in the second through hole 20 can extend along the third direction. The read word line portion 520 connects to the write word line portion 510, thereby forming a shared word line 500 extending along the third direction.

[0102] The material of the read word line portion 520 may include, but is not limited to, tungsten (W). For example, the material of the read word line portion 520 may also include cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al). The read word line portion 520 and the write word line portion 510 may be made of the same material or different materials.

[0103] The read word line portion 520 is connected to the read channel material layer 7201 , thereby serving as the read word line RWL of the read transistor T2 . The read word line portion 520 is spaced apart from the write channel material layer 4101 , thereby preventing leakage from occurring between the read word line portion 520 and the write channel material layer 4101 .

[0104] In step S80, refer to Figure 15 After removing the isolation material layer 2201 in the first area A1, the space between adjacent sacrificial material layers 2101 on both sides of the isolation material layer 2201 along the third direction in the first area A1 is hollowed out, thereby forming a hollow cavity 30 extending along the first direction between adjacent sacrificial material layers 2101 in the first area A1. The shared bit line 800 fills the hollow cavity 30 and thus also extends along the first direction.

[0105] At the same time, before forming the writing channel material layer 4101, the first through hole 10 is formed to expose the comb stem 200a of the first area A1, that is, to expose the isolation material layer 2201 and the sacrificial material layer 2101 of the first area A1. Figure 16 After removing the isolation material layer 2201 located in the first area A1, a shared bit line 800 is formed in the hollow cavity 30 to connect to the write channel material layer 4101 located on the sidewall of the first through hole 10, thereby serving as the write bit line WBL of the write transistor T1.

[0106] Furthermore, the shared bit line 800 is connected to the read channel material layer 7201 , and thus can serve as the read bit line RBL of the read transistor T2 .

[0107] In step S90, refer to Figure 17 as well as Figure 18After removing the sacrificial material layer 2101, the shared word line 500 formed by the read word line portion 520 and the write word line portion 510 can be used as an etch stop layer to etch the write channel material layer 4101, the write gate dielectric material layer 4201, the read gate dielectric material layer 7101, the read channel material layer 7201, and the first filling material layer 6001 extending along the third direction. The portions of the layers opposite the sacrificial material layer 2101 are removed, thereby forming the write channel layer 410, the write gate dielectric layer 420, the read gate dielectric layer 710, the read channel layer 720, and the first filling structure 600 located between adjacent sacrificial material layers 2101 along the third direction. The write channel layer 410 and the write gate dielectric layer 420 form the write channel structure 400. The read gate dielectric material layer 7101 and the read channel layer 720 form the read channel structure 700.

[0108] See also Figure 19 In this case, the write channel layer 410 may include a first channel portion 411, a second channel portion 412, and a third channel portion 413 connected in sequence. The first channel portion 411 and the second channel portion 412 are both located in the first sub-area A21. The first channel portion 411 is located between the write word line portion 510 and the shared bit line 800. The third channel portion 413 is located in the second sub-area A22.

[0109] The write word line portion 510 of the shared word line 500 serves as the write word line WWL of the write transistor T1 and can form the write transistor T1 together with the write channel structure 400. The second channel portion 412 between the first channel portion 411 and the third channel portion 413 can serve as the channel region of the write transistor T1. The first channel portion 411 and the third channel portion 413 can serve as the source region and the drain region of the write transistor T1, respectively. The first channel portion 411 is connected to the shared bit line 800, so that one of the source region and the drain region of the write transistor T1 can be connected to the write bit line WBL. The sidewall of the third channel portion 413 is provided with a read channel structure 700. Therefore, the third channel portion 413 can serve as the gate of the read transistor T2, thereby forming the read transistor T2 together with the read channel structure 700.

[0110] Also, see Figure 19The read channel layer 720 may include a fourth channel portion 721, a fifth channel portion 722, and a sixth channel portion 723 connected in sequence. The fifth channel portion 722 surrounds the third channel portion 413 and can serve as the channel region of the read transistor T2. The fourth channel portion 721 and the sixth channel portion 723 are located on either side of the third channel portion 413, respectively, thereby serving as the source and drain regions of the read transistor T2. At the same time, the fourth channel portion 721 is connected to the shared bit line 800, thereby allowing one of the source and drain regions of the read transistor T2 to be connected to the read bit line RBL. The sixth channel portion 723 is connected to the read word line portion 520 of the shared word line 500, thereby allowing the other of the source and drain regions of the read transistor T2 to be connected to the read word line RWL.

[0111] In this embodiment, a memory cell with a 2T0C architecture can be formed, and the memory cell includes a shared word line 500 and a shared bit line 800. The shared word line 500 includes a write word line portion 510 and a read word line portion 520 connected to each other. The write word line portion 510 can serve as the write word line WWL of the write transistor T1, and the read word line portion 520 can serve as the read word line RWL of the read transistor T2. Furthermore, the shared bit line 800 can simultaneously serve as the write bit line WBL of the write transistor T1 and the read bit line RBL of the read transistor T2. In this manner, the wiring area of ​​the memory cell can be effectively reduced, thereby effectively improving the memory cell density. Furthermore, the wiring process can be simplified.

[0112] In one embodiment, step S60 includes:

[0113] Step S61, see Figure 12 , the write gate dielectric material layer 4201, the write channel material layer 4101 and the portion of the second sub-tooth 200e opposite to the write word line portion 510 are removed to form an initial opening 21c, and the remaining second sub-tooth 200e forms a third sub-tooth 200f. Figure 17 The isolation material layer 2201 in the third sub-tooth 200 f forms a second isolation portion 222 , and the second isolation portion 222 and the first isolation portion 221 form an isolation layer 220 .

[0114] The second sub-tooth 200 e , the write channel material layer 4101 , and the write gate dielectric material layer 4201 may be selectively etched by dry etching or the like.

[0115] At this time, the second isolation portion 222 is located between the read word line portion 520 and the shared bit line 800 , thereby effectively insulating and isolating the two.

[0116] In one embodiment, in step S61, see Figure 12, while removing the write gate dielectric material layer 4201, the write channel material layer 4101 and the portion of the second sub-tooth 200e opposite to the write word line portion 510 to form an initial opening 21c, the portion of the write channel material layer 4101 located on both sides of the initial opening 21c in the second direction is also removed to form a first opening 21a and a second opening 21b. The first opening 21a is connected to the first area A1, and the first opening 21a, the second opening 21b and the initial opening 21c form an initial through hole 21.

[0117] And step S60 further includes:

[0118] Step S62, see Figure 13 A second filling material layer 9001 is filled in a portion of the initial through hole 21. The second filling material layer 9001 includes a first filling material 9101 and a second filling material 9201 that are filled in the first opening 21a and the second opening 21b, respectively. The remaining initial through hole 21 forms an intermediate through hole 22.

[0119] Step S63, see Figure 13 , remove the reading gate dielectric material layer 7101 and the writing gate dielectric material layer 4201 located on the side wall of the middle through hole 22 in the second direction, thereby forming a third opening 23 and a fourth opening 24, and the third opening 23, the fourth opening 24 and the middle through hole 22 form a second through hole 20.

[0120] At this time, in step S61, after removing the write gate dielectric material layer 4201, the write channel material layer 4101 and the portion of the second sub-tooth 200e opposite to the write word line portion 510, part of the write channel material layer 4101 located on both sides of the write word line portion 510 is also removed, thereby forming a first opening 21a and a second opening 21b.

[0121] In step S62, the material of the second filling material layer 9001 may include but is not limited to silicon nitride. For example, the material of the second filling material layer 9001 may also include silicon oxide or silicon oxynitride.

[0122] The first opening 21 a may be filled with the first filler material 9101 , and the second opening 21 b may be filled with the second filler material 9201 .

[0123] The first filling material 9101 and the second filling material 9201 can effectively isolate the write channel material layer 4101 from the subsequently formed read word line portion 520, thereby effectively isolating the write channel material layer 4101 from the read word line portion 520 and the write word line portion 510, thereby effectively isolating the gate of the write transistor T1 from the channel region.

[0124] In step S63 , the read gate dielectric material layer 7101 and the write gate dielectric material layer 4201 located on the sidewall of the middle through hole 22 in the second direction can be simultaneously etched away, which can effectively reduce the etching difficulty.

[0125] After removing the read gate dielectric material layer 7101 formed on the sidewall of the second sub-tooth 200e, the third opening 23 can be formed. Simultaneously, after etching away the write gate dielectric material layer 4201 opposite to the read gate dielectric material layer 7101, the fourth opening 24 can be formed.

[0126] After forming the read word line portion 520 in the second through-hole 20 in a subsequent step, the read word line portion 520 may include a first sub-word line portion 521 located in the middle through-hole 22, a second sub-word line portion 522 located in the third opening 23, and a third sub-word line portion 523 located in the fourth opening 24. The first sub-word line portion 521 connects to the write word line portion 510 in the first direction. The second sub-word line portion 522 and the third sub-word line portion 523 both connect to the first sub-word line portion 521 in the second direction. The second sub-word line portion 522 and the third sub-word line portion 523 are located on both sides of the second filler material 9201 in the first direction.

[0127] At this time, the read word line portion 520 can be effectively connected to the read channel material layer 7201 through the second sub-word line portion 522 .

[0128] In other embodiments, the fourth opening 24 may not be formed when the second through hole 20 is formed. In this case, the read word line portion 520 may not include the third sub-word line portion 523 .

[0129] Furthermore, in other embodiments, the write channel material layer 4101 may be isolated from the subsequently formed read word line portion 520 by other means.

[0130] For example, the initial through hole 21 formed in step S61 may not include the first opening 21a and the second opening 21b formed on both sides of the initial opening 21c, but only include the initial opening 21c. In this case, after step S61, an insulating material layer may be formed on the inner wall of the initial opening 21c. Afterwards, the read gate dielectric material layer 7101 formed on the side wall of the second sub-tooth 200e in the previous step is removed and part of the insulating material layer connected thereto is removed, thereby forming the second through hole 20. At this time, the read word line portion 520 formed in the second through hole 20 can also be effectively isolated from the write channel material layer 4101. Moreover, the read word line portion 520 can also be effectively contacted and connected with the read channel material layer 7201.

[0131] In one embodiment, see Figure 13The second filling material layer 9001 further includes a third filling material 9301 , and the third filling material 9301 is filled on the side wall of the third sub-tooth 200 f .

[0132] At this time, in step S62 , a filling material for filling the initial through hole 21 may be first formed, and then a portion of the filling material may be removed by etching, thereby simultaneously forming a first filling material 9101 , a second filling material 9201 , and a third filling material 9301 .

[0133] At this point, the read word line portion 520 is formed on the side of the third filler material 9301 away from the first area A1. Therefore, in addition to the second isolation portion 222, the third filler material 9301 is present between the read word line portion 520 and the shared bit line 800 formed in subsequent steps. This effectively reduces the parasitic capacitance between the read word line portion 520 and the shared bit line 800.

[0134] Of course, in other embodiments, the third filling material 9301 may not be formed, and this is not limited here.

[0135] In one embodiment, in step S90, see Figure 17 as well as Figure 18 , remove the sacrificial material layer 2101, and while side-etching the write channel material layer 4101, the write gate dielectric material layer 4201, the read gate dielectric material layer 7101, the read channel material layer 7201, and the first filling material layer 6001 that are opposite to the sacrificial material layer 2101, the side-etching is also performed on the second filling material layer 9001 that is opposite to the sacrificial material layer 2101. The remaining second filling material layer 9001 forms a second filling structure 900.

[0136] After the side etching, the remaining first filler material 9101 forms the first filler 910 . The second filler material 9201 forms the second filler 920 . When the second filler material layer 9001 further includes the third filler material 9301 , the remaining second filler material layer 9001 forms the third filler 930 .

[0137] In one embodiment, step S80 includes:

[0138] Step S81, please refer to Figure 15 , removing the read gate dielectric material layer 7101 located on the sidewall of the comb stem 200 a to form a fifth opening 40;

[0139] Step S82, please refer to Figure 15 , removing the isolation material layer 2201 located in the first area A1 to form a hollow cavity 30;

[0140] Step S83, please refer to Figures 16 to 18 A shared bit line 800 is formed in the hollow cavity 30 and the fifth opening 40 , and the shared bit line 800 is located between adjacent sacrificial material layers 2101 in the third direction.

[0141] In step S81, the read gate dielectric material layer 7101 located on the sidewall of the comb-teeth stem 200a can be removed by dry etching or the like. The fifth opening 40 formed after etching can extend along the third direction, for example.

[0142] In step S82, the isolation material layer 2201 located in the first area A1 may be removed by wet etching or the like, thereby forming a hollow cavity 30 between adjacent sacrificial material layers 2101. The hollow cavity 30 may extend along the first direction.

[0143] In step S83, refer to Figure 16 First, a shared bit line material layer 8001 can be formed in the hollow cavity 30 and the fifth opening 40 by electroplating or chemical vapor deposition.

[0144] The material of the shared bit line material layer 8001 may include, but is not limited to, metal tungsten (W). For example, the material of the shared bit line material layer 8001 may also include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al).

[0145] Then, in step S90, the sacrificial material layer 2101 is removed, and while the portions of the write channel material layer 4101, the write gate dielectric material layer 4201, the read gate dielectric material layer 7101, the read channel material layer 7201 and the first filling material layer 6001 opposite to the sacrificial material layer 2101 are side etched, the shared bit line material layer 8001 opposite to the sacrificial material layer 2101 can also be side etched, and the remaining shared bit line material layer 8001 forms a shared bit line 800.

[0146] At this time, after the side etching, the shared bit line material layer 8001 formed in the hollow cavity 30 can remain unchanged, thereby forming a write bit line portion 810 extending along the first direction. At the same time, after the side etching, the shared bit line material layer 8001 formed in the fifth opening 40 can be isolated, thereby forming a read bit line portion 820. The write bit line portion 810 and the read bit line portion 820 together form the shared bit line 800. Furthermore, the write bit line portion 810 of the shared bit line 800 extends along the first direction.

[0147] In one embodiment, see Figure 18 , also provides a storage structure, which can be but is not limited to being prepared by the above-mentioned storage structure preparation method.

[0148] Please also see Figure 2 and Figure 18 The memory structure includes a substrate 100 and multiple memory cell layers located on the substrate 100, wherein the multiple memory cell layers are stacked along a third direction. Each memory cell layer includes multiple memory cells. The memory cells also include a shared word line 500 and a shared bit line 800. The shared word line 500 runs through each memory cell layer and is shared by the associated memory cells in each memory cell layer.

[0149] and in the same storage unit, see Figure 19 and Figure 20 The shared word line 500 can serve as the write word line WWL of the write transistor T1 and can also serve as the read word line RWL of the read transistor T2, so that the write word line WWL is connected to the read word line RWL; and the shared bit line 800 can simultaneously serve as the write bit line WBL of the write transistor T1 and the read bit line RBL of the read transistor T2, so that the write bit line WBL is connected to the read bit line RBL.

[0150] In one embodiment, see Figure 17 as well as Figure 19 , also provides a memory cell, which includes a shared bit line 800, a shared word line 500, a first filling structure 600, a write channel structure 400, an isolation layer 220, and a read channel structure 700.

[0151] The shared bit line 800 extends along a first direction.

[0152] The material of the shared bit line 800 may include, but is not limited to, metal tungsten (W). For example, the material of the shared bit line 800 may also include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al).

[0153] The shared word line 500 and the shared bit line 800 are arranged along the second direction. Meanwhile, the shared word line 500 extends along the third direction. The first direction intersects the second direction, a plane defined by the first and second directions is a first plane, and the third direction intersects the first plane.

[0154] Also, the shared word line 500 includes a write word line portion 510 and a read word line portion 520 connected to each other in a first direction.

[0155] The material of the write word line portion 510 and / or the read word line portion 520 may include, but is not limited to, tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al). Furthermore, the materials of the write word line portion 510 and the read word line portion 520 may be the same or different.

[0156] The first filling structure 600 is connected to the write word line portion 510 in the second direction and is located on a sidewall of the write word line portion 510 away from the shared bit line 800 .

[0157] The material of the first filling structure 600 may include, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

[0158] The write channel structure 400 includes a write gate dielectric layer 420 and a write channel layer 410 .

[0159] The material of the write gate dielectric layer 420 may include but is not limited to high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0160] The material of the write channel layer 410 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, thereby improving transistor performance. Furthermore, IGZO material cost is relatively low and the manufacturing process is relatively simple, thereby effectively reducing process costs.

[0161] The write gate dielectric layer 420 extends along the sidewalls of the write word line portion 510 facing the shared bit line 800, the sidewalls of the write word line portion 510 away from the read word line portion 520, and the sidewalls of the first filling structure 600. The write channel layer 410 is located on the surface of the write gate dielectric layer 420 away from the write word line portion 510 and surrounds the write word line portion 510 and the first filling structure 600.

[0162] The isolation layer 220 includes a first isolation portion 221. The first isolation portion 221 is connected to the shared bit line 800 in the second direction and is located on a side of the write channel layer 410 away from the shared word line 500 in the first direction.

[0163] The material of the isolation layer 220 may include, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

[0164] The read channel structure 700 includes a read gate dielectric layer 710 and a read channel layer 720 .

[0165] The material of the read gate dielectric layer 710 may include, but is not limited to, high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0166] The material of the read channel layer 720 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, thereby improving transistor performance. Furthermore, IGZO material cost is relatively low and the manufacturing process is relatively simple, thereby effectively reducing process costs.

[0167] The read gate dielectric layer 710 extends along the sidewalls of the first isolation portion 221 away from the shared word line 500 , the sidewalls of the first isolation portion 221 away from the shared bit line 800 , and the sidewalls of the write channel layer 410 away from the write gate dielectric layer 420 .

[0168] The read channel layer 720 extends along the second direction sidewall of the shared bit line 800 , the surface of the read gate dielectric layer 710 away from the write channel layer 410 , and the second direction sidewall of the read word line portion 520 .

[0169] See also Figure 19 The write channel layer 410 may include a first channel portion 411, a second channel portion 412, and a third channel portion 413 connected in sequence. The first channel portion 411 is located between the write word line portion 510 and the shared bit line 800. The third channel portion 413 surrounds the first filling structure 600. The second channel portion 412 is located between the first channel portion 411 and the third channel portion 413.

[0170] The write word line portion 510 of the shared word line 500 serves as the write word line WWL of the write transistor T1 and can form the write transistor T1 together with the write channel structure 400. The second channel portion 412 between the first channel portion 411 and the third channel portion 413 can serve as the channel region of the write transistor T1. The first channel portion 411 and the third channel portion 413 can serve as the source region and the drain region of the write transistor T1, respectively. The first channel portion 411 is connected to the shared bit line 800, so that one of the source region and the drain region of the write transistor T1 can be connected to the write bit line WBL. The sidewall of the third channel portion 413 is provided with a read channel structure 700. Therefore, the third channel portion 413 can serve as the gate of the read transistor T2, thereby forming the read transistor T2 together with the read channel structure 700.

[0171] Meanwhile, the read channel layer 720 may include a fourth channel portion 721 , a fifth channel portion 722 , and a sixth channel portion 723 that are sequentially connected.

[0172] The fifth channel portion 722 surrounds the third channel portion 413 and serves as the channel region of the read transistor T2. The fourth channel portion 721 and the sixth channel portion 723 are located on either side of the third channel portion 413, serving as the source and drain regions of the read transistor T2, respectively. Furthermore, the fourth channel portion 721 is connected to the shared bit line 800, allowing one of the source and drain regions of the read transistor T2 to be connected to the read bit line RBL. The sixth channel portion 723 is connected to the read word line portion 520 of the shared word line 500, allowing the other of the source and drain regions of the read transistor T2 to be connected to the read word line RWL.

[0173] In this embodiment, the memory cell is a 2T0C memory cell, and the memory cell includes a shared word line 500 and a shared bit line 800. The shared word line 500 includes a write word line portion 510 and a read word line portion 520 connected to each other. The write word line portion 510 can serve as the write word line WWL of the write transistor T1, and the read word line portion 520 can serve as the read word line RWL of the read transistor T2. Furthermore, the shared bit line 800 can simultaneously serve as the write bit line WBL of the write transistor T1 and the read bit line RBL of the read transistor T2. In this manner, the wiring area of ​​the memory cell can be effectively reduced, thereby effectively improving the memory cell density. Furthermore, the wiring process can be simplified.

[0174] In one embodiment, see Figure 17 Compared to the sidewall of the first filling structure 600 away from the shared bit line 800 along the second direction, the sidewall of the first isolation portion 221 away from the shared bit line 800 along the second direction is closer to the shared bit line 800 .

[0175] The distance between the shared bit line 800 and the sidewall of the first filling structure 600 away from the shared bit line 800 is set to d1, and the distance between the shared bit line 800 and the sidewall of the first isolation portion 221 away from the shared bit line 800 is set to d2.

[0176] At this time, d1 is greater than d2, so that the length of the third channel portion 413 of the write channel layer 410 can be effectively increased, thereby effectively increasing the gate width of the read transistor T2 and effectively increasing the gate control capability of the read transistor T2.

[0177] Of course, in other embodiments, d1 may also be set to be less than or equal to d2, and this is not limited here.

[0178] In one embodiment, see Figure 17 The isolation layer 220 further includes a second isolation portion 222 . That is, the second isolation portion 222 and the first isolation portion 221 are provided in the same layer, and both are located in the isolation layer 220 .

[0179] The second isolation portion 222 is located between the read word line portion 520 and the shared bit line 800 , thereby effectively insulating and isolating the read word line portion 520 and the shared bit line 800 .

[0180] In other embodiments, the second isolation portion 222 and the first isolation portion 221 may be located in different film layers.

[0181] In one embodiment, see Figure 17 , the storage unit further includes a second filling structure 900 .

[0182] The material of the second filling structure 900 may include but is not limited to silicon nitride. For example, the material of the second filling material layer 9001 may also include silicon oxide or silicon oxynitride.

[0183] The second filling structure 900 includes a first filling portion 910 and a second filling portion 920. The second filling portion 920 and the first filling portion 910 are located on opposite sides of the read word line portion 520 in the second direction. The first filling portion 910 is located between the second isolation portion 222 and the write channel layer 410, and the second filling portion 920 is located between the write gate dielectric layer 420 and the read gate dielectric layer 710.

[0184] At this time, the first filling portion 910 and the second filling portion 920 can effectively insulate and isolate the read word line portion 520 from the write channel layer 410 , thereby effectively insulating and isolating the write word line portion 510 from the write channel layer 410 .

[0185] In one embodiment, see Figure 17 In addition to the first filling part 910 and the second filling part 920, the second filling structure 900 also includes a third filling part 930. The first filling part 910, the second filling part 920 and the third filling part 930 can be provided in the same layer and formed at the same time.

[0186] The third filling portion 930 is located between the read word line portion 520 and the second isolation portion 222 , thereby effectively reducing the parasitic capacitance between the read word line portion 520 and the shared bit line 800 .

[0187] In one embodiment, see Figure 17 The read word line portion 520 includes a first sub-word line portion 521, a second sub-word line portion 522, and a third sub-word line portion 523. The first sub-word line portion 521 is connected to the write word line portion 510 in the first direction. The second sub-word line portion 522 and the third sub-word line portion 523 are both connected to the first sub-word line portion 521 in the second direction.

[0188] The second sub-word line portion 522 is connected to the read channel layer 720 in the second direction. The third sub-word line portion 523 and the second sub-word line portion 522 are respectively located on both sides of the second filling portion 920 in the first direction.

[0189] At this time, the read word line portion 520 can be effectively connected to the read channel layer 720 through the second sub-word line portion 522. The third sub-word line portion 523 and the second sub-word line portion 522 are respectively located on both sides of the second filling portion 920, which can reduce the difficulty of manufacturing the read word line portion 520 and reduce the resistance of the read word line portion 520, thereby reducing the resistance of the shared word line 500.

[0190] In other embodiments, the read word line portion 520 may also include only the first sub-word line portion 521 and the second sub-word line portion 522 , but not the third sub-word line portion 523 .

[0191] In one embodiment, the shared bit line 800 includes a write bit line portion 810 and a read bit line portion 820 connected in the second direction. The write bit line portion 810 extends along the first direction, and the read bit line portion 820 is located between the write bit line portion 820 and the read channel layer 720. The read channel layer 720 is located on the sidewall of the read bit line portion 820.

[0192] At this time, the materials of the write bit line portion 810 and the read bit line portion 820 can be the same or different. Multiple read bit line portions 820 can be arranged along the first direction on the same write bit line portion 810, so that the same write bit line portion 810 can be shared by multiple memory cells arranged in the first direction.

[0193] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A storage unit, characterized in that: include: a shared bit line extending along a first direction; a shared word line arranged along a second direction with the shared bit line, the shared word line extending along a third direction, the shared word line including a write word line portion and a read word line portion connected to each other in the first direction, the first direction intersecting with the second direction, a plane defined by the first direction and the second direction being a first plane, and the third direction intersecting with the first plane; a first filling structure located on a sidewall of the write word line portion away from the shared bit line; a write channel structure, comprising a write gate dielectric layer and a write channel layer, wherein the write gate dielectric layer extends along a sidewall of the write word line portion facing the shared bit line, a sidewall of the write word line portion away from the read word line portion, and each sidewall of the first filling structure, and the write channel layer is located on a surface of the write gate dielectric layer away from the write word line portion and surrounds the write word line portion and the first filling structure; an isolation layer, comprising a first isolation portion, wherein the first isolation portion is located on a side of the write channel layer away from the shared word line along the first direction; A read channel structure includes a read gate dielectric layer and a read channel layer, wherein the read gate dielectric layer extends along the sidewall of the first isolation portion away from the shared word line, the sidewall of the first isolation portion away from the shared bit line, and the sidewall of the write channel layer away from the write gate dielectric layer, and the read channel layer extends along the sidewall in the second direction of the shared bit line, the surface of the read gate dielectric layer away from the side of the write channel layer, and the sidewall in the second direction of the read word line portion.

2. The storage unit according to claim 1, wherein Compared to the sidewall of the first filling structure farther away from the shared bit line along the second direction, the sidewall of the first isolation portion farther away from the shared bit line along the second direction is closer to the shared bit line.

3. The storage unit according to claim 1, wherein The isolation layer further includes a second isolation portion located between the read word line portion and the shared bit line.

4. The storage unit according to claim 3, wherein: The storage unit also includes a second filling structure, which includes a first filling portion and a second filling portion. The second filling portion and the first filling portion are respectively located on opposite sides of the read word line portion in the second direction, and the first filling portion is located between the second isolation portion and the write channel layer, and the second filling portion is located between the write gate dielectric layer and the read gate dielectric layer.

5. The storage unit according to claim 4, wherein: The second filling structure further includes a third filling portion located between the read word line portion and the second isolation portion. The storage unit according to claim 4 , wherein: The read word line portion includes a first sub-word line portion, a second sub-word line portion and a third sub-word line portion, the first sub-word line portion is connected to the write word line portion in a first direction, the second sub-word line portion and the third sub-word line portion are both connected to the first sub-word line portion in a second direction, and the second sub-word line portion is connected to the read channel layer in the second direction, and the third sub-word line portion and the second sub-word line portion are respectively located on both sides of the second filling portion in the first direction.

7. The storage unit according to claim 1, wherein: The shared bit line includes a write bit line portion and a read bit line portion connected in the second direction, the write bit line portion extends along the first direction, the read bit line portion is located between the write bit line portion and the read channel layer, and the read channel layer is located on a sidewall of the read bit line portion.

8. A storage structure, characterized in that: include: substrate; A plurality of memory cell layers are stacked along a third direction on the substrate, each of the memory cell layers comprising a plurality of memory cells according to any one of claims 1 to 7, wherein the shared word line passes through each of the memory cell layers and is shared by the related memory cells of each of the memory cell layers.

9. A method for preparing a storage structure, characterized in that: include: A substrate is provided, wherein a first region and a second region are provided on the substrate, the first region including a first sub-region and a second sub-region, the first sub-region is located between the first region and the second sub-region, the second direction intersects the first direction, and a plane defined by the first direction and the second direction is a first plane; forming a comb-tooth-shaped stacked structure on the substrate, the stacked structure comprising alternating sacrificial material layers and isolation material layers, and the stacked structure having a comb-tooth stem and comb-tooth bars, the comb-tooth stem extending along a first direction and located in the first region, the comb-tooth bars located in the second region, and a plurality of the comb-tooth bars arranged along the first direction on the comb-tooth stem, with isolation initial structures between the comb-tooth bars; A first through-hole extending along a third direction is formed on a side of the comb-tooth bar close to the first region, and the remaining comb-tooth bars form an annular rack. A write channel material layer and a write gate dielectric material layer are sequentially formed on the sidewall of the first through-hole, and a write word line portion and a first filling material layer are formed on the surface of the write gate dielectric material layer. The write word line portion fills the first through-hole of the first sub-region, and the first filling material layer fills the first through-hole of the second sub-region. The third direction intersects the first plane. Removing the initial isolation structure located in the second sub-region and the initial isolation structure located on the side of the write word line portion in the first sub-region, and removing the annular rack located in the second sub-region, so that the remaining initial isolation structure forms an isolation structure, and the remaining annular rack forms a first sub-tooth and a second sub-tooth, wherein the second sub-tooth is located between the isolation structure and the first through-hole, and the isolation material layer in the first sub-tooth forms a first isolation portion; forming a read gate dielectric material layer and a read channel material layer in sequence along the sidewalls of the comb teeth in the second direction, the sidewalls of the first sub-tooth, the sidewalls of the write channel material layer, and the sidewalls of the second sub-tooth; removing the write gate dielectric material layer, the write channel material layer, and a portion of the second sub-tooth located between the write word line portion and the isolation structure to form a second through hole extending along the third direction; forming a read word line portion in the second through hole, the read word line portion being spaced apart from the write channel material layer and connected to the read channel material layer, wherein the read word line portion is connected to the write word line portion to form a shared word line; removing the isolation material layer located in the first region to form a hollow cavity, and forming a shared bit line filling the hollow cavity and connecting the read channel material layer; The sacrificial material layer is removed, and the write channel material layer, the write gate dielectric material layer, the read gate dielectric material layer, the read channel material layer, and the first filling material layer are side-etched opposite to the sacrificial material layer to form a write channel layer, a write gate dielectric layer, a read gate dielectric layer, a read channel layer, and a first filling structure, respectively, wherein the write channel layer and the write gate dielectric layer form a write channel structure, and the read gate dielectric layer and the read channel layer form a read channel structure.

10. The method for preparing the storage structure according to claim 9, characterized in that: Removing the write gate dielectric material layer, the write channel material layer, and a portion of the second sub-tooth located between the write word line portion and the isolation structure to form a second through hole, comprising: The write gate dielectric material layer, the write channel material layer and the portion of the second sub-tooth opposite to the write word line portion are removed to form an initial opening, and the remaining second sub-tooth forms a third sub-tooth, and the isolation material layer in the third sub-tooth forms a second isolation portion, and the second isolation portion and the first isolation portion form an isolation layer.

11. The method for preparing the storage structure according to claim 10, characterized in that: removing the write gate dielectric material layer, the write channel material layer, and a portion of the second sub-tooth opposite to the write word line portion to form an initial opening, and also removing portions of the write channel material layer located on both sides of the initial opening in the second direction to form a first opening and a second opening, wherein the first opening connects to the first region, and the first opening, the second opening, and the initial opening form an initial through hole; removing the read gate dielectric material layer, the read channel material layer, and a portion of the second sub-tooth located between the write word line portion and the isolation structure to form a second through hole, further comprising: A second filling material layer is filled in a portion of the initial through hole, wherein the second filling material layer includes a first filling material and a second filling material respectively filled in the first opening and the second opening, and the remaining initial through hole forms an intermediate through hole. The read gate dielectric material layer and the write gate dielectric material layer located on the sidewall of the middle through hole in the second direction are removed to form a third opening and a fourth opening. The third opening, the fourth opening and the middle through hole form the second through hole.

12. The method for preparing the storage structure according to claim 11, characterized in that: The second filling material layer further includes a third filling material, and the third filling material is filled on the side wall of the third sub-tooth.

13. The method for preparing the storage structure according to claim 11 or 12, characterized in that: While removing the sacrificial material layer and side-etching the write channel material layer, the write gate dielectric material layer, the read gate dielectric material layer, the read channel material layer and the portion of the first filling material layer opposite to the sacrificial material layer, the portion of the second filling material layer opposite to the sacrificial material layer is also side-etched, and the remaining second filling material layer forms a second filling structure.

14. The method for preparing the storage structure according to claim 9, characterized in that: Removing the isolation material layer located in the first region to form a hollow cavity, and forming a shared bit line filling the hollow cavity and connected to the read channel layer, comprising: removing the read gate dielectric material layer located on the sidewall of the comb teeth to form a fifth opening; removing the isolation material layer located in the first area to form the hollow cavity; A shared bit line is formed in the hollow cavity and the fifth opening, and the shared bit line is located between adjacent sacrificial material layers in the third direction.

15. The method for preparing the storage structure according to claim 9, characterized in that: The step of sequentially forming a read gate dielectric material layer and a read channel material layer along the sidewalls of the comb teeth in the second direction, the sidewalls of the first sub-tooth, the sidewalls of the write channel material layer, and the sidewalls of the second sub-tooth comprises: forming the read gate dielectric material layer along the sidewalls of the comb teeth in the second direction, the sidewalls of the first sub-tooth, the sidewalls of the write channel material layer, the sidewalls of the second sub-tooth, and the sidewalls of the isolation structure, and forming a read channel material layer on a surface of the read gate dielectric material layer away from the write channel material layer; The read gate dielectric material layer and the read channel material layer located on the sidewalls of the isolation structure are removed.

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