Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method of the memory device. A memory device may include: a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked in a first direction, the stacked structure including a cell region and a contact region, the contact region extending from the cell region and having a step structure; a plurality of contact plugs in contact with the plurality of conductive layers, respectively, in the contact region, the plurality of contact plugs extending in a first direction; and a plurality of lower pillars in contact with the contact plugs, respectively, the plurality of lower pillars being located on the bottoms of the contact plugs in the stacked structure. Each lower pillar of the plurality of lower pillars may include a liner layer in contact with the stacked structure and a pillar structure surrounded by the liner layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0086321 filed on July 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a memory block having a three-dimensional structure and a method of manufacturing the memory device. Background Art

[0004] The memory device may include a nonvolatile memory device in which data stored remains intact even when power is interrupted. The nonvolatile memory device may be divided into a two-dimensional structure and a three-dimensional structure according to a structure in which memory cells are arranged. The memory cells of the nonvolatile memory device having a two-dimensional structure may be arranged in a single layer above a substrate, and the memory cells of the nonvolatile memory device having a three-dimensional structure may be stacked above the substrate in a vertical direction. Since the integration level of the nonvolatile memory device having a three-dimensional structure is higher than that of the nonvolatile memory device having a two-dimensional structure, electronic devices using the nonvolatile memory device having a three-dimensional structure have recently been increasingly used. Summary of the invention

[0005] According to one aspect of the present disclosure, a memory device is provided, which includes: a stacking structure, which includes a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked along a first direction, the stacking structure includes a cell region and a contact region, the contact region extends from the cell region and has a step structure; a plurality of contact plugs respectively contacting the plurality of conductive layers in the contact region, the plurality of contact plugs extending in the first direction; and a plurality of lower pillars respectively contacting the contact plugs, the plurality of lower pillars being located on the bottom of the contact plugs in the stacking structure, wherein each of the plurality of lower pillars includes: a liner layer contacting the stacking structure; and a pillar structure surrounded by the liner layer.

[0006] According to another aspect of the present disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a preliminary stacking structure by alternately stacking a plurality of first material layers and a plurality of second material layers in a first direction, the preliminary stacking structure comprising a cell region and a contact region, the contact region extending from the cell region and having a step structure; forming a plurality of openings penetrating the preliminary stacking structure in the contact region; forming a stacking structure by replacing a plurality of first material layers with a plurality of third material layers; forming a plurality of lower pillars, each of the lower pillars comprising a liner layer and a pillar structure, the liner layer being in contact with the stacking structure, the pillar structure being surrounded by the liner layer, so that steps formed with the plurality of third material layers are exposed in the step structure; and forming a plurality of contact plugs on the plurality of lower pillars in the plurality of openings, the plurality of contact plugs respectively being in contact with the steps of the plurality of third material layers.

[0007] According to another aspect of the present disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a preliminary stacking structure in which a plurality of first material layers and a plurality of second material layers are stacked in a step structure; forming a plurality of pairs, each pair comprising a first material layer among a plurality of first material layers and a second material layer among a plurality of second material layers; forming an upper insulating layer above the preliminary stacking structure; forming a plurality of openings penetrating the upper insulating layer and the preliminary stacking structure; forming a stacking structure by replacing the plurality of first material layers with a plurality of third material layers; forming a plurality of lower pillars in a first region of the plurality of openings, each lower pillar comprising a liner layer and a pillar structure; and forming a plurality of contact plugs in a second region of the plurality of openings above the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0009] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0010] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0011] Figure 2 is a view schematically illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 3A and Figure 3Bis a view illustrating a cell region and a contact region of a memory device according to an embodiment of the present disclosure.

[0013] FIG. 4A to FIG. 4D is a view illustrating a contact plug and a lower pillar according to an embodiment of the present disclosure.

[0014] FIG. 5A to FIG. 12A , FIG. 5B to FIG. 12B and FIG. 5C to FIG. 12C is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0015] Fig.13 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0016] Fig.14 is a diagram illustrating a solid-state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0017] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily realize the technical spirit of the present disclosure.

[0019] Embodiments provide a memory device and a method of manufacturing the memory device, which can enhance the stability of a manufacturing process and improve the operational reliability of the memory device.

[0020] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0021] refer to Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0022] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0023] The first to i-th memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked in a vertical direction over a substrate.

[0024] Depending on the programming method, the memory cell can store one bit or two bits or more of data. For example, a method of storing one bit of data in one memory cell can be called a single-level cell (SLC) method, and a method of storing two bits of data in one memory cell can be called a multi-level cell (MLC) method. A method of storing three bits of data in one memory cell is called a three-level cell (TLC) method, and a method of storing four bits of data in one memory cell can be called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0025] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0026] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0027] The programming voltage may be a voltage applied to a selected word line among word lines WL in a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. The turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. The turn-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the turn-off voltage may be set to 0V. The precharge voltage may be a voltage higher than 0V, and may be applied to a bit line in a read operation. The verification voltage may be used in a verification operation to determine whether the threshold voltage of a selected memory cell has increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0028] The read voltage may be applied to the selected word line in a read operation of the selected memory cell. For example, the read voltage may be set to various levels according to the programming mode of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among the word lines WL in a programming or read operation, and may be used to turn on the memory cells connected to the unselected word lines. The erase voltage may be used to erase the memory cells included in the selected memory block in an erase operation, and may be applied to the source line SL.

[0029] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the i-th memory block BLKi through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0030] The page buffer group 140 may include a page buffer (not shown) connected to each of the first to i-th memory blocks BLK1 to BLKi. The page buffer (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi, respectively, through the bit lines BL. In a read operation, in response to a page buffer control signal PBSIG, the page buffer (not shown) may sense a current or voltage of the bit line BL that varies according to a threshold voltage of a selected memory cell, and temporarily store the sensed data.

[0031] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and may transmit an enable signal through the column line. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0032] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and may transmit data received from an external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0033] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation of the selected memory block, and may output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation of the selected memory block.

[0034] Figure 2 is a view schematically illustrating a memory device according to an embodiment of the present disclosure.

[0035] refer to Figure 2 , the memory device may include a peripheral circuit structure PC and memory blocks BLK1 to BLKi disposed on a substrate SUB. The memory blocks BLK1 to BLKi may overlap with the peripheral circuit structure PC.

[0036] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0037] The peripheral circuit structure PC may include a row decoder ( Figure 1 130 shown in), column decoder ( Figure 1 150 shown in FIG), a page buffer group ( Figure 1 140 shown in), control circuit ( Figure 1 180) etc., which constitute a circuit for controlling the operation of the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include: NMOS transistors, PMOS transistors, resistors, capacitors, etc. electrically connected to the memory blocks BLK1 to BLKi. The peripheral circuit structure PC may be disposed between the substrate SUB and the memory blocks BLK1 to BLKi.

[0038] Each memory block in the memory blocks BLK1 to BLKi may include: a source structure, a bit line, a cell string electrically connected to the source structure and the bit line, a word line electrically connected to the cell string, and a selection line electrically connected to the cell string. Each cell string in the cell string may include a memory cell and a selection transistor connected in series through a cell plug. Each selection line in the selection line may be used as a gate electrode of a selection transistor corresponding thereto, and each word line in the word line may be used as a gate electrode of a memory cell corresponding thereto.

[0039] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKi may be connected in a manner similar to Figure 2 For example, the peripheral circuit structure PC may be disposed on the memory blocks BLK1 to BLKi.

[0040] In another embodiment, Figure 2 Unlike shown, the peripheral circuit structure PC may be disposed on a partial region of the substrate SUB that does not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be disposed on regions of the substrate SUB that do not overlap with each other.

[0041] Figure 3A and Figure 3B is a view illustrating a cell region and a contact region of a memory device according to an embodiment of the present disclosure. Figure 3A is a perspective view illustrating a cell region CR and a contact region CTR of the memory device 100 . Figure 3B is a plan view illustrating the layout of the cell region CR and the contact region CTR of the memory device 100 .

[0042] refer to Figure 3A and Figure 3B, the memory device 100 may include a stacked structure STK in which the conductive layers CD and the interlayer insulating layers IL are alternately stacked in the Z direction. The stacked structure STK may extend in the X direction and the Y direction. The stacked structure STK may include a cell region CR and a contact region CTR extending from the cell region CR in the X direction. The contact region CTR may have a step structure having a plurality of steps. Each of the plurality of steps may include a conductive layer CD and an interlayer insulating layer IL. Each step may expose the conductive layer CD corresponding thereto. For example, the top surface of each step may include a portion of the top surface of the conductive layer CD.

[0043] The cell plug CP may extend in the Z direction in the cell region CR of the stacked structure STK. The cell plug CP may penetrate the cell region CR of the stacked structure STK in the Z direction. Each of the cell plugs CP may include a memory layer having a columnar shape. The memory layer may include a barrier layer BX, a charge trapping layer CTL formed along the inner wall of the barrier layer BX, a tunnel insulating layer TX formed along the inner wall of the charge trapping layer, or a combination of at least two thereof. Each of the cell plugs CP may include a channel layer CH formed along the inner wall of the tunnel insulating layer TX and a core column CO formed inside the channel layer CH. The barrier layer BX and the tunnel insulating layer TX may be formed of an oxide layer (e.g., a silicon oxide layer), an oxynitride layer (e.g., a silicon oxynitride layer), or any combination thereof. The charge trapping layer CTL may be a charge storage layer and may include a nitride layer or a variable resistance material. The channel layer CH may be formed of a conductive layer, such as a doped silicon layer. In another example, the channel layer CH may be replaced by an electrode structure. The core column CO may be formed of an insulating layer or a conductive layer. The blocking layer BX, the charge trapping layer CTL, the tunnel insulating layer TX, the channel layer CH, and the pillar CO formed in the cell plug CP may extend in the Z direction. A capping layer for improving electrical characteristics of a selection transistor included in each cell string may be further formed on top of the pillar CO.

[0044] A contact plug CT may be formed in the contact region CTR of the stacked structure STK. The contact plugs CT may correspond to the plurality of steps included in the step structure in the contact region CTR, respectively. For example, each of the contact plugs CT may be connected to a conductive layer CD included in any one of the plurality of steps. The contact plugs CT may be in contact with the conductive layers CD, respectively, and may extend in the Z direction.

[0045] The number of cell plugs CP and contact plugs CT is not limited to Figure 3A and Figure 3BThe number shown in FIG. 1 and may vary according to the area of ​​the stacked structure STK or the number of stacks of the conductive layer CD and the interlayer insulating layer IL. In addition, the positions of the cell plugs CP and the contact plugs CT are not limited to Figure 3A and Figure 3B The cell plug CP and the contact plug CT may be formed at various positions as long as they include FIG. 4A to FIG. 4D Features described in .

[0046] FIG. 4A to FIG. 4D is a view illustrating a contact plug and a lower pillar according to an embodiment of the present disclosure. Figure 4A is a cross-sectional view of the first embodiment according to the present disclosure, which corresponds to the Figure 3B The cross section taken along the line AA' is shown in FIG. Figure 4B is a cross-sectional view of a second embodiment according to the present disclosure, corresponding to the Figure 3B The cross section taken along the line AA' is shown in FIG. Figure 4C is corresponding to along Figure 4A and Figure 4B A cross-sectional view of a cross section taken along line BB' is shown in FIG.

[0047] Figure 4D is corresponding to along Figure 4A and Figure 4B A cross-sectional view of a cross section taken along line CC' is shown.

[0048] refer to Figure 4A The stacked structure STK may include conductive layers CD and interlayer insulating layers IL alternately stacked along the Z direction. The conductive layer CD may include a first conductive layer CD1 and a second conductive layer CD2 located below the first conductive layer CD1. The stacked structure STK may include a cell region CR and a contact region CTR, such as Figure 3A and Figure 3B shown, and in Figure 4A 1 and 2. A portion of the contact region CTR is shown in FIG. The conductive layer CD and the interlayer insulating layer IL may have a step structure in the contact region CTR, and the steps formed with the corresponding conductive layers CD may be exposed through the step structure. For example, a portion of the first conductive layer CD1 and a portion of the second conductive layer CD2 may be exposed in each step. The second conductive layer CD2 may extend longer in the X direction than the first conductive layer CD1.

[0049] An upper insulating layer UIL covering the stack structure STK may be disposed over the stack structure STK. The upper insulating layer UIL may cover the step structure of the stack structure STK. The upper insulating layer UIL may have a substantially flat top surface.

[0050] The contact plugs CT may be in contact with the conductive layer CD, respectively. The contact plugs CT may be in contact with the steps of the conductive layer CD, respectively. The contact plugs CT may be electrically connected to the conductive layer CD, respectively. For example, the first contact plug CT1 may not be connected to the second conductive layer CD2. Each of the contact plugs CT may extend in the Z direction. For example, the contact plug CT may penetrate the upper insulating layer UIL. The upper insulating layer UIL may fill the space between the contact plugs CT. In one embodiment, the contact plugs CT may be arranged to be spaced apart from each other in the X direction. In another embodiment, as in Figure 4A Unlike the example shown in FIG. 1 , the contact plugs CT may be arranged to be spaced apart from each other in the Y direction. In yet another embodiment, the memory device 100 may further include a Figure 4A The contact plugs CT shown in FIG. 1 are contact plugs spaced apart from each other in the Y direction. In addition, the number of the contact plugs CT, the direction in which the contact plugs CT are arranged, or the positions in which the contact plugs CT are arranged may be variously changed.

[0051] The lower pillars DP may overlap with the contact plugs CT, respectively. The lower pillars DP may contact with the contact plugs CT, respectively. The bottom surfaces of the contact plugs CT may contact with the top surfaces of the lower pillars DP, respectively. For example, the first lower pillar DP1 may be located below the first contact plug CT1 in the stack structure STK, and the first lower pillar DP1 may penetrate at least a portion of the stack structure STK below the first contact plug CT1. The first lower pillar DP1 may overlap with the first contact plug CT1. The top surface of the first lower pillar DP1 may contact with the bottom surface of the first contact plug CT1. In the present disclosure, the lower pillar DP may be designated or understood as a dummy pillar.

[0052] The lower pillar DP may be located below the contact plug CT in the stacked structure STK. Each of the lower pillars DP may penetrate at least a portion of the stacked structure STK while being respectively below each of the contact plugs CT in the contact plugs CT. For example, the first lower pillar DP1 may penetrate the conductive layer CD and the interlayer insulating layer IL located below the first conductive layer CD1. The lower pillar DP may penetrate at least one conductive layer CD and at least one corresponding interlayer insulating layer IL included in the stacked structure STK. For example, the first lower pillar DP1 may penetrate the conductive layer CD and their corresponding interlayer insulating layer IL disposed below the first conductive layer CD1 among the conductive layers CD and the interlayer insulating layers IL included in the stacked structure STK. For example, the first lower pillar DP1 may penetrate the second conductive layer CD2. The first lower pillar DP1 may not completely penetrate the first conductive layer CD1, but the other lower pillars DP may fully penetrate the first conductive layer CD1. The second conductive layer CD2 may be penetrated by the first lower pillar DP1, and may be penetrated by the other lower pillars DP except the first lower pillar DP1. In addition, the interlayer insulating layer IL disposed between the first conductive layer CD1 and the second conductive layer CD2 corresponding to the first conductive layer CD1 may be penetrated by the first down pillar DP1 , and may be penetrated by the other down pillars DP except the first down pillar DP1 .

[0053] Each of the lower pillars DP may be formed of at least two different materials. Each of the lower pillars DP may include a pad layer LL in contact with the stacked structure STK and a column structure PS surrounded by the pad layer LL. The pad layer LL may surround the column structure PS. The column structure PS may be spaced apart from the stacked structure STK by the pad layer LL. For example, the pad layer LL may be formed of a material (e.g., an oxide layer, a nitride layer, an oxynitride layer, or an oxide layer doped with a metal) capable of insulating the conductive layers CD from each other. In addition, the column structure PS may be formed of polysilicon (e.g., undoped polysilicon) or an oxide layer.

[0054] The upper insulating layer UIL and the stack structure STK may be opened by the opening PH. The opening PH may penetrate the upper insulating layer UIL and the stack structure STK in the Z direction. The opening PH may be filled with the lower pillar DP and the contact plug CT, respectively. For example, each of the openings PH may include a first region PH1 in which the lower pillar DP is located and a second region PH2 in which the contact plug CT is located. The lower pillar DP may be located in the first region PH1 of the opening PH, and the contact plug CT may be located in the second region PH2 of the opening PH. The first region PH1 of the opening PH may be located in the stack structure STK. The second region PH2 of the opening PH may penetrate the upper insulating layer UIL and may extend into the conductive layer CD exposed at each step among the conductive layers CD included in the stack structure STK. The heights of the first regions PH1 in the corresponding openings PH may be different from each other, and the heights of the second regions PH2 in the corresponding openings PH may be different from each other. However, the total height of the openings PH may be substantially the same.

[0055] The width of the opening PH in the X direction or the Y direction can be changed depending on the position on the Z axis. Figure 4A The width in the X direction is illustrated in the figure, but the description of the width in the X direction can be applied to the width in the Y direction. The opening PH can penetrate the conductive layer CD with a first width W1, and can penetrate the interlayer insulating layer IL with a second width W2 greater than the first width W1. Moreover, the opening PH can penetrate the upper insulating layer UIL with a third width W3 greater than the second width W2. Due to the difference in etching speed between the upper insulating layer UIL and the interlayer insulating layer IL, the width of the opening PH penetrating the upper insulating layer UIL (e.g., the third width W3) can be greater than the width of the opening PH penetrating the interlayer insulating layer IL (e.g., the second width W2). In the present disclosure, the width of the opening PH penetrating the upper insulating layer UIL can vary according to the position on the Z axis, but the third width W3 can be a maximum value, a minimum value, an average value, a median value, a value at a specific position specified on the Z axis, or a value determined by a constant reference among the values ​​of the width of the opening PH penetrating the upper insulating layer UIL.

[0056] Since the width of the opening PH varies along the Z direction, the width of the lower pillar DP may vary along the Z direction. For example, the lower pillar DP may have a first width W1 at a level corresponding to the conductive layer CD. Also, the lower pillar DP may have a second width W2 greater than the first width W1 at a level corresponding to the interlayer insulating layer IL.

[0057] The liner layer LL may extend along the inner wall of the corresponding opening PH. The liner layer LL may be formed with a substantially constant width along the inner wall of each opening PH, and the opening PH has different widths along the Z direction. Each of the column structures PS may include a vertical portion P1 extending in the Z direction and a horizontal protrusion P2 protruding from the vertical portion P1 toward the interlayer insulating layer IL. The horizontal protrusion P2 of the column structure PS may have a columnar shape surrounding the vertical portion P1.

[0058] Since the width of the opening PH varies in the Z direction, one portion of each of the contact plugs CT may have a third width W3, and another portion of each of the contact plugs CT may have a first width W1. Each of the contact plugs CT may include an extension C1 extending in the Z direction and a protrusion C2 protruding from the extension C1 toward each of the lower pillars DP. The extension C1 may have a third width W3, and the extension C2 may have a first width W1.

[0059] The extension C1 of the contact plug CT may be formed inside the upper insulating layer UIL. For example, the extension C1 of the contact plug CT may penetrate the upper insulating layer UIL. The extension C1 of the contact plug CT may respectively contact the top surface of the conductive layer CD exposed by the step. For example, the extension C1 of the first contact plug CT1 may be electrically connected to the first conductive layer CD1 while contacting the first conductive layer CD1. The first conductive layer CD1 may be penetrated by the opening PH with a first width W1, but the extension C1 of the first contact plug CT1 may have a third width W3. Therefore, the extension C1 may contact the top surface of the first conductive layer CD1.

[0060] The protrusions C2 of the contact plugs CT may respectively contact the inner walls of the conductive layer CD exposed by the steps. For example, the protrusions C2 of the first contact plugs CT1 may contact the inner walls of the first conductive layer CD1 exposed by the openings PH. The protrusions C2 of the first contact plugs CT1 may fill a portion of the region where the first conductive layer CD1 is opened by the openings PH.

[0061] The protrusions C2 of the contact plugs CT may respectively contact the top surfaces of the lower pillars DP. For example, the protrusions C2 of the first contact plugs CT1 may protrude from the extensions C1 of the first contact plugs CT1 toward the first lower pillars DP1 to contact the top surfaces of the first lower pillars DP1. Figure 4A , the protrusions C2 of the contact plugs CT may make contact with top surfaces of the corresponding pillar structures PS of the lower pillars DP, respectively.

[0062] The boundary surface between the protrusion C2 of the first contact plug CT1 and the first lower pillar DP1 may be located between the top surface and the bottom surface of the first conductive layer CD1. The protrusion C2 of the first contact plug CT1 may be inserted into the space in which the first conductive layer CD1 is opened by the opening PH. The protrusion C2 of the first contact plug CT1 may fill at least a portion of the space in which the first conductive layer CD1 is opened by the opening PH. For example, in the space in which the first conductive layer CD1 is opened by the opening PH, the remaining portion of the space not filled by the first lower pillar DP1 may be filled with the first contact plug CT1. Therefore, in the space in which the first conductive layer CD1 is opened by the opening PH filled with the first contact plug CT1 and the first lower pillar DP1, the boundary surface between the first region PH1 and the second region PH2 may be located between the top surface and the bottom surface of the first conductive layer CD1.

[0063] Although Figure 4A An embodiment is illustrated in which a space in which the first conductive layer CD1 is opened by the opening PH is filled with a portion of the first lower pillar DP1 and a portion of the first contact plug CT1, but the present disclosure is not limited thereto. For example, the protrusion C2 of the first contact plug CT1 may penetrate the first conductive layer CD1, and a boundary surface between the first contact plug CT1 and the first lower pillar DP1 may be located at the same level as the bottom surface of the first conductive layer CD1.

[0064] refer to Figure 4B , each of the lower pillars DP' may include a liner layer LL in contact with the stack structure STK, a pillar structure PS' surrounded by the liner layer LL, and a covering pattern CV covering a top surface of the pillar structure PS'. Figure 4A and Figure 4B When compared with each other, Figure 4B The lower pillar DP' shown in FIG. 1 may further include a covering pattern CV. Figure 4A In the case shown in FIG. 1 , the top surface of the pillar structure PS may be in contact with the bottom surface of the contact plug CT. Figure 4B In the case shown in FIG. 2 , the top surface of the pillar structure PS′ may not be in contact with the bottom surface of the contact plug CT. Figure 4B The pillar structure PS' shown in FIG. 5 may be spaced apart from the contact plug CT by the capping pattern CV. For example, the capping pattern CV may be formed of an oxide layer (eg, a silicon oxide layer), a nitride layer, an oxynitride layer, an oxide layer doped with a metal, or any combination thereof.

[0065] Figure 4C Can correspond to along Figure 4A and Figure 4B The cross section is obtained along the line BB' shown in FIG. Figure 4D Can correspond to along Figure 4A and Figure 4B The cross section is obtained by the line CC' shown in FIG. Figure 4A and Figure 4B In the embodiment, except for the presence of the covering pattern CV, the other components are substantially identical to each other, and therefore, in Figure 4C and Figure 4D This paper mainly describes the Figure 4A The cross section and the Figure 4A The cross section is taken along the line CC' shown in FIG.

[0066] refer to Figure 4C , the first conductive layer CD1 may be in contact with the first contact plug CT1. The first contact plug CT1 may fill a portion of the space in which the first conductive layer CD1 is opened. On a cross section taken along line BB', the first contact plug CT1 may have a first width W1. Another portion of the space in which the first conductive layer CD1 is opened may be filled with a lower pillar DP. The lower pillar DP may include a liner layer LL in contact with the first conductive layer CD1 and a pillar structure PS surrounded by the liner layer LL. On a cross section taken along line BB', the lower pillar DP in contact with the first conductive layer CD1 may have a first width W1. The upper insulating layer UIL may be penetrated by the contact plug CT. On a cross section taken along line BB', the contact plug CT may have a third width W3.

[0067] refer to Figure 4D , the lower pillars DP may fill the space in which the interlayer insulating layer IL is opened. For example, the interlayer insulating layer IL may be penetrated by the lower pillars DP. The interlayer insulating layer IL may be penetrated by the first lower pillar DP1 and another lower pillar DP other than the first lower pillar DP1. Each of the lower pillars DP may include a liner layer LL and a pillar structure PS, the liner layer LL is in contact with the interlayer insulating layer IL, and the pillar structure PS is surrounded by the liner layer LL. On a cross section taken along line CC', each of the lower pillars DP may have a second width W2. The upper insulating layer UIL may be penetrated by the contact plug CT. On a cross section taken along line CC', the contact plug CT may have a third width W3.

[0068] refer to FIG. 4A to FIG. 4D, the openings PH penetrating the upper insulating layer UIL and the stacked structure STK have substantially the same length in the Z direction. However, each of the contact plugs CT filled in the openings PH may be in contact with the conductive layer CD that becomes the target, and may not be in contact with other conductive layers CD. For example, the first contact plug CT1 is in contact with the first conductive layer CD1, but may not be in contact with other conductive layers (e.g., the second conductive layer CD2). Since the lower portion of the opening PH is filled with the lower pillar DP, the contact plug CT may not be in contact with other conductive layers CD except for the conductive layer CD exposed at the corresponding step (e.g., the conductive layer CD that becomes the target). For example, since the first lower pillar DP1 is located below the first contact plug CT1, the first contact plug CT1 may not be in contact with other conductive layers CD except for the first conductive layer CD1. Therefore, the memory device may include lower pillars DP respectively overlapping with the contact plugs CT and formed in the stacked structure STK, and therefore, a breakdown phenomenon (for example, a phenomenon in which the contact plugs are connected to other conductive layers other than the targeted conductive layer) may not occur during the manufacturing process of the memory device, or the number of occurrences of the breakdown phenomenon may be reduced.

[0069] In addition, the contact plug CT may contact the top surface and the inner wall of the conductive layer CD exposed by the corresponding step. For example, the first contact plug CT1 may contact a portion of the top surface of the first conductive layer CD1 and a portion of the inner wall of the first conductive layer CD1. According to the present disclosure, the area in which the contact plug CT contacts the conductive layer CD may be increased compared to the existing contact plug and the existing conductive layer, and thus, the resistance between the contact plug CT and the conductive layer CD may be reduced.

[0070] FIG. 5A to FIG. 12A , FIG. 5B to FIG. 12B and FIG. 5C to FIG. 12C is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure. Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A and Fig. 12A Each of the Figure 3B A cross-sectional view of a cross section taken along line AA' is shown. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B and Fig. 12B Each of the Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A and Fig. 12A Each of the cross-sectional views shown is a cross-sectional view of a cross section taken along line BB'. Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C and Fig. 12C Each of the Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A and Fig. 12A Each of the cross-sectional views shown is a cross-sectional view of a cross section taken along line CC'.

[0071] refer to FIG. 5A to FIG. 5C , the first material layer SF and the second material layer IL may be alternately stacked. The first material layer SF may be formed of a material that can be selectively removed in a subsequent process. The second material layer IL may be formed of an insulating material. The first material layer SF may be formed of a material having an etching selectivity different from that of the second material layer IL. For example, the first material layer SF may be formed of a nitride layer. The second material layer IL may be formed of an oxide layer (e.g., a silicon oxide layer).

[0072] Portions of the alternately stacked first material layers SF and second material layers IL may be etched to form a preliminary stacked structure pSTK having a step structure. A preliminary stacked structure pSTK may be formed in which the first material layers SF and second material layers IL forming pairs are stacked in a step structure. For example, portions of the first material layers SF and second material layers IL may be etched so that each of the first material layers SF is exposed. Figure 5A The area shown in may correspond to a contact area as a part of the preliminary stacking structure pSTK.

[0073] An upper insulating layer UIL may be formed over the preliminary stack structure pSTK. The upper insulating layer UIL may cover the step structure of the preliminary stack structure pSTK. The upper insulating layer UIL may be an oxide layer.

[0074] refer to FIG. 6A to FIG. 6C, holes H1 may be formed inside the upper insulating layer UIL and the preliminary stacked structure pSTK. For example, holes H1 may be formed that penetrate the upper insulating layer UIL, the first material layer SF, and the second material layer IL. An anisotropic dry etching process may be performed to form the holes H1 at designated locations. Each of the holes H1 may have a first width W1.

[0075] Each of the holes H1 may penetrate the upper insulating layer UIL and the preliminary stacked structure pSTK. For example, the hole H1 may be formed to penetrate the entire structure including the upper insulating layer UIL and the preliminary stacked structure pSTK. Therefore, the hole H1 may be formed together with other openings included in the memory device 100. For example, Figure 3A and Figure 3B Reference together FIG. 6A to FIG. 6C , the opening for forming the cell plug CP and the hole H1 for forming the contact plug CT and the lower pillar DP can be formed at the same time. When the opening for forming the cell plug CP and the hole H1 for forming the lower pillar DP are formed at the same time, the cost and the required time can be reduced compared with when the opening and the hole H1 are separately formed by separate processes. In addition to the opening for forming the cell plug CP, various openings (for example, holes with a large aspect ratio) and Fig. 6A The hole H1 is shown in FIG.

[0076] refer to 7A to 7C , an opening PH may be formed that penetrates the upper insulating layer UIL and the preliminary stacked structure pSTK. For example, a portion of the second material layer IL exposed by the hole H1 may be etched to form a first extension portion EP1. In addition, a portion of the upper insulating layer UIL exposed by the hole H1 may be etched to form a second extension portion EP2. The process of forming the first extension portion EP1 and the second extension portion EP2 through the hole H1 may be a wet etching process to allow the first material layer SF to remain and selectively etch a portion of the second material layer IL and a portion of the upper insulating layer UIL. Each of the openings PH may include a hole H1, and a first extension portion EP1 and a second extension portion EP2 extending from the hole H1.

[0077] The opening PH may have different widths along the Z direction. Figure 7B , the opening PH may penetrate the first material layer SF with a first width W1. Since the upper insulating layer UIL and the second material layer IL are selectively etched after forming the hole H1, the opening PH on the cross section taken along the BB' line may have the same width as the hole H1 (eg, the first width W1). Figure 7C, the opening PH may penetrate the second material layer IL with a second width W2. Since a portion of the second material layer IL is etched after forming the hole H1 to form the first extension portion EP1, the opening PH on the cross section taken along the line CC' may have a second width W2 greater than the first width W1. Figure 7B and Figure 7C , the opening PH may penetrate the upper insulating layer UIL with a third width W3. Since a portion of the upper insulating layer UIL is etched after forming the hole H1 to form the second extension portion EP2, the opening PH on the cross section taken along line BB' and the opening PH on the cross section taken along line CC' may have a third width W3 greater than the first width W1.

[0078] refer to Fig. 7A and Figure 7C , the width of the second extension portion EP2 may be greater than the width of the first extension portion EP1. Although the upper insulating layer UIL and the second material layer IL are simultaneously etched through the hole H1, due to the difference in etching speed between the upper insulating layer UIL and the second material layer IL, the width of the first extension portion EP1 and the width of the second extension portion EP2 may be different from each other. For example, for an etchant used in the wet etching process through the hole H1, the upper insulating layer IL may be etched faster than the second material layer IL.

[0079] refer to FIG. 8A to FIG. 8C , the preliminary liner layer pLL may be formed along the inner wall of the opening PH. The preliminary liner layer pLL may be formed along the surface inside the opening PH. For example, the preliminary liner layer pLL may be formed on the inner wall of the opening PH with a substantially constant thickness.

[0080] Inside the opening PH having the preliminary liner layer pLL formed on the inner wall thereof, a sacrificial layer ML may be formed. The sacrificial layer ML may be formed to be surrounded by the preliminary liner layer pLL. The sacrificial layer ML may fill the opening PH. For example, the sacrificial layer ML may be formed of a metal layer such as tungsten.

[0081] refer to 9A to 9C , the first material layer SF may be replaced with the third material layer CD, thereby forming a stacked structure STK. In a state in which the opening PH is filled with the preliminary liner layer pLL and the sacrificial layer ML, the first material layer SF may be replaced with the third material layer CD. Fig.9A, but a trench may be formed that penetrates the preliminary stacked structure pSTK and extends in the X direction. The first material layer SF exposed by the trench may be removed. While the first material layer SF is removed, the opening PH may be filled with a preliminary liner layer pLL and a sacrificial layer ML, which may support the second material layer IL. The area where the first material layer SF is removed, i.e., between the second material layers IL, may be filled with a third material layer CD. The third material layer CD may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si). The third material layer CD may be used as a gate line, for example, a drain select line DSL, a word line WL, and a source select line SSL.

[0082] After forming the stack structure STK in which the second material layers IL and the third material layers CD are alternately stacked, the sacrificial layers ML respectively filled in the openings PH may be removed. For example, the sacrificial layers ML may be removed by a wet etching process to allow the preliminary liner layer pLL to remain and selectively etch the sacrificial layer ML. Since the sacrificial layers ML are removed, the preliminary liner layer pLL extending along the inner wall of the opening PH may be exposed.

[0083] A preliminary column layer pPS may be formed inside an opening PH having a preliminary liner layer pLL formed on its inner wall. The preliminary column layer pPS may be formed on a preliminary liner layer pLL extending along the inner wall of the corresponding opening PH. A portion of the opening PH may be filled with each of the preliminary column layers pPS, but each of the preliminary column layers pPS may not be filled in other portions of the opening PH. For example, the preliminary column layer pPS may include a first recess RC1. The preliminary column layer pPS may fill a lower portion of the opening pH having a relatively small width (e.g., a first width W1 and a second width W2). For example, the opening PH penetrating the stacked structure STK may be filled with a preliminary column layer pPS. An upper portion of the opening PH having a relatively large width (e.g., a third width W3) may not be completely filled with a preliminary column layer pPS. For example, inside the opening PH penetrating the upper insulating layer UIL, a first recess RC1 surrounded by a preliminary column layer pPS may be formed.

[0084] refer to Figures 10A to 10C , at least a portion of the preliminary column layer pPS formed on the inner wall of the opening PH may be removed. A portion of the preliminary column layer pPS may be removed by a first recess RC1 included in the preliminary column layer pPS. For example, a portion of the preliminary column layer pPS may be removed by a wet etching process to allow the preliminary liner layer pLL to remain and selectively etch the preliminary column layer pPS. The portion of the preliminary column layer pPS that is not removed but remains may become a column structure PS.

[0085] Since part of the preliminary column layer pPS is removed, part of the preliminary pad layer pLL may be exposed. Since part of the preliminary column layer pPS is removed, the first recess RC1 may be expanded into the second recess RC2. Part of the preliminary pad layer pLL and the top surface of the column structure PS may be exposed through the second recess RC2.

[0086] refer to FIG. 11A to FIG. 11C , a portion of the preliminary liner layer pLL formed along the inner wall of the opening PH may be removed. A portion of the preliminary liner layer pLL exposed by the second recess RC2 may be removed. For example, a portion of the preliminary liner layer pLL may be removed by a wet etching process to allow the upper insulating layer UIL, the third material layer CD, and the pillar structure PS to remain and selectively etch the preliminary liner layer pLL.

[0087] The portion of the preliminary liner layer pLL that is not removed but remains may become the liner layer LL. The lower pillars DP may include the liner layer LL and the pillar structure PS, respectively. The lower pillars DP may fill a portion of the corresponding opening PH. The lower pillars DP may be formed to have a height at which a step formed with the third material layer CD may be exposed. For example, the lower pillars DP may fill the first region PH1 of the opening PH. The first region PH1 of the opening PH may be formed in the stacked structure STK.

[0088] Since a portion of the preliminary liner layer pLL is removed, the upper insulating layer UIL may be exposed. Since a portion of the preliminary liner layer pLL is removed, the second recess RC2 may be expanded into a third recess RC3. The upper insulating layer UIL, the third material layer CD, and the lower pillar DP may be exposed through the third recess RC3. For example, the second region PH2 of the opening PH may correspond to the third recess RC3. The second region PH2 of the opening PH may penetrate the upper insulating layer UIL and may expose a portion of the lower pillar DP and a portion of the third material layer CD.

[0089] refer to FIG. 12A to FIG. 12C , contact plugs CT respectively contacting the steps of the third material layer CD may be formed in the openings PH. The contact plugs CT may be respectively filled in the openings PH to be formed on and in contact with the lower pillars DP. The contact plugs CT may fill the third recess RC3. For example, the lower pillars DP may be formed in the first region PH1 of the opening PH, and the contact plugs CT may be formed in the second region PH2 of the opening PH. The contact plugs CT may be formed of a material (e.g., a metal layer) that may be electrically connected to the third material layer CD.

[0090] refer to FIG. 10A to FIG. 12A , contact plugs CT may be formed on the lower pillars DP including the liner layer LL and the pillar structure PS, respectively. However, in order to form Figure 4B The lower column DP' shown in Fig. 10A and Fig.11A A surface treatment process is added on the pillar structure PS between the processes of Fig. 10A The oxidation process is performed on the column structure PS exposed by the second recess RC2 shown in FIG. When the oxidation process is performed on the column structure PS, since the surface of the column structure PS exposed by the second recess RC2 is oxidized, a layer of oxidized carbon may be formed on the top surface of the column structure PS. Figure 4B The other parts that are not changed into the covering pattern CV may become Figure 4B The column structure PS' shown in FIG. Fig.11A In the process described above, when a portion of the preliminary liner layer pLL is removed, a portion of the cover pattern CV may be etched. Therefore, a lower pillar DP' may be formed, which includes the liner layer LL, the pillar structure PS', and the cover pattern CV whose portion is etched. Since the pillar structure PS' is covered by the cover pattern CV, the pillar structure PS' may not be exposed through the third recess RC3. In addition, with respect to reference Fig. 12A According to the described process, a contact plug CT may be formed in the third recess RC3 exposing the upper insulating layer UIL, the third material layer CD, the liner layer LL, and the capping pattern CV.

[0091] Fig.13 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0092] refer to Fig.13 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0093] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control programming, reading, or erasing operations, or the controller 3100 may control background operations of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0094] The controller 3100 can communicate with an external device through a connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. Exemplarily, the controller 3100 can communicate with an external device through at least one communication protocol in various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced mini disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one communication protocol in the various communication protocols mentioned above.

[0095] The memory device 3200 may include a memory unit and may be connected to Figure 1 The memory device 100 shown in FIG. 1 is configured identically.

[0096] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, mini SD, micro SD, and SDHC), and a universal flash storage (UFS).

[0097] Fig.14 is a diagram illustrating a solid-state drive (SSD) system to which the memory device of the present disclosure is applied.

[0098] refer to Fig.14 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0099] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. Exemplarily, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0100] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be connected to Figure 1 The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0101] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100 and be charged with the power. When the supply of power from the host 4100 is not stable, the auxiliary power supply 4230 may provide power to the SSD 4200. Exemplarily, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard, and may provide auxiliary power to the SSD 4200.

[0102] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0103] According to the present disclosure, defects that may occur during the manufacturing process of the contact plug in the contact region can be reduced. Therefore, the stability of the manufacturing process of the memory device can be enhanced, and the operational reliability of the memory device can be improved.

[0104] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0105] In the above-described embodiments, all steps may be selectively performed, or some steps in the steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for the purpose of understanding the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0106] Meanwhile, exemplary embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, those specific terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments, and within the spirit and scope of the present disclosure, many variations are possible. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: A stacked structure comprising a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked along a first direction, the stacked structure comprising a cell region and a contact region, the contact region extending from the cell region and having a step structure; a plurality of contact plugs in the contact region respectively contacting the plurality of conductive layers, the plurality of contact plugs extending in the first direction; as well as a plurality of lower pillars respectively contacting the contact plugs, the plurality of lower pillars being located on bottoms of the contact plugs in the stacked structure; Each of the plurality of lower pillars comprises: a liner layer in contact with the stacked structure; as well as A column structure is surrounded by the liner layer.

2. The memory device according to claim 1 , wherein each of the plurality of lower pillars is located in a plurality of openings penetrating the stack structure, respectively, and Each of the plurality of openings penetrates the plurality of conductive layers with a first width, and penetrates the plurality of interlayer insulating layers with a second width greater than the first width. 3 . The memory device of claim 2 , wherein at least a portion of each of the plurality of contact plugs has a third width greater than the second width. 4 . The memory device of claim 2 , wherein the liner layer is formed along an inner wall of each of the plurality of openings.

5. The memory device of claim 1 , wherein the pillar structure comprises: a vertical portion extending in the first direction; as well as A horizontal protrusion protrudes from the vertical portion toward each of the plurality of interlayer insulating layers. The memory device of claim 1 , wherein the pillar structure is spaced apart from the stack structure by the liner layer. 7 . The memory device of claim 1 , wherein a top surface of the pillar structure contacts a bottom surface of a corresponding contact plug among the plurality of contact plugs.

8. The memory device of claim 1 , wherein each of the plurality of lower pillars further comprises a covering pattern covering a top surface of the pillar structure, and wherein the top surface of the pillar structure is spaced apart from a corresponding contact plug among the plurality of contact plugs by the capping pattern.

9. The memory device of claim 1 , wherein a first contact plug among the plurality of contact plugs: electrically connected to a first conductive layer among the plurality of conductive layers; and Contacting a first lower pillar among the plurality of lower pillars.

10. The memory device of claim 9, wherein the first contact plug comprises: an extension portion extending in the first direction; as well as A protrusion protrudes from the extending portion toward the first lower column. 11 . The memory device of claim 10 , wherein the extending portion of the first contact plug contacts a top surface of the first conductive layer. 12 . The memory device of claim 10 , wherein the protrusion of the first contact plug contacts an inner wall of the first conductive layer exposed by the opening and contacts a top surface of the first lower pillar. 13 . The memory device of claim 10 , wherein a boundary surface between the protrusion of the first contact plug and the first lower pillar is located between a top surface and a bottom surface of the first conductive layer.

14. The memory device according to claim 10, further comprising an upper insulating layer covering the stack structure, The extending portion of the first contact plug is located inside the upper insulating layer.

15. The memory device of claim 9, wherein the plurality of conductive layers further comprises a second conductive layer located below the first conductive layer, and The first lower pillar penetrates the second conductive layer.

16. A method of manufacturing a memory device, the method comprising: forming a preliminary stacking structure by alternately stacking a plurality of first material layers and a plurality of second material layers in a first direction, the preliminary stacking structure comprising a unit region and a contact region, the contact region extending from the unit region and having a step structure; forming a plurality of openings penetrating the preliminary stacked structure in the contact region; forming a stacked structure by replacing the plurality of first material layers with a plurality of third material layers; forming a plurality of lower pillars, each of the lower pillars comprising a liner layer and a pillar structure, the liner layer being in contact with the stacked structure, the pillar structure being surrounded by the liner layer, so that steps formed with the plurality of third material layers are exposed in the step structure; as well as A plurality of contact plugs are formed on the plurality of lower pillars in the plurality of openings, the plurality of contact plugs respectively contacting the steps of the plurality of third material layers.

17. The method of claim 16, wherein forming each of the plurality of openings comprises: forming an upper insulating layer covering the preliminary stacked structure; forming a hole penetrating the upper insulating layer and the preliminary stacked structure; forming a first extension portion by etching a portion of each of the plurality of second material layers exposed through the hole; as well as forming a second extension portion by etching a portion of the upper insulating layer exposed through the hole, and Each of the plurality of openings includes the hole and the first extension portion and the second extension portion extending from the hole. The method of claim 17 , wherein a width of the second extension is greater than a width of the first extension.

19. The method according to claim 16, further comprising: Before replacing the first material layer with the third material layer: forming a preliminary lining layer along an inner wall of each of the plurality of openings; as well as A sacrificial layer filling each of the plurality of openings is formed, the sacrificial layer being surrounded by the preliminary liner layer.

20. The method of claim 19, wherein forming the stacked structure comprises: replacing the plurality of first material layers with the plurality of third material layers in a state in which each of the plurality of openings is filled with the preliminary liner layer and the sacrificial layer; as well as The sacrificial layer filled in each of the openings is removed.

21. The method of claim 19, wherein forming each of the plurality of lower pillars comprises: forming a preliminary column layer on the preliminary liner layer extending along the inner wall of each of the plurality of openings; forming the column structure by removing at least a portion of the preliminary column layer; as well as The liner layer is formed by etching at least a portion of the preliminary liner layer through a space in which the preliminary column layer is removed.

22. A method of manufacturing a memory device, the method comprising: forming a preliminary stacking structure in which a plurality of first material layers and a plurality of second material layers are stacked in a stepped structure; forming a plurality of pairs, each pair comprising one of the plurality of first material layers and one of the plurality of second material layers; forming an upper insulating layer on the preliminary stacked structure; forming a plurality of openings penetrating the upper insulating layer and the preliminary stacked structure; forming a stacked structure by replacing the plurality of first material layers with a plurality of third material layers; forming a plurality of lower pillars in first regions of the plurality of openings, each lower pillar comprising a liner layer and a pillar structure; as well as A plurality of contact plugs are formed in a second region of the plurality of openings above the first region.

23. The method of claim 22, wherein forming the stacked structure comprises: forming a preliminary liner layer along an inner surface of each of the plurality of openings; forming a sacrificial layer inside each of the plurality of openings having the preliminary liner layer formed on the inner surface thereof; removing the plurality of first material layers; forming the plurality of third material layers in the regions where the plurality of first material layers are removed; as well as The sacrificial layer is removed.

24. The method of claim 22, wherein forming the plurality of lower pillars comprises: forming a preliminary column layer inside each of the plurality of openings having the preliminary liner layer formed on an inner surface thereof; as well as A portion of each preliminary column layer and a portion of each preliminary liner layer are removed so that a portion of the upper insulating layer and portions of the plurality of third material layers are exposed.

25. The method of claim 24, wherein removing the portion of each preliminary column layer and the portion of each preliminary liner layer comprises: exposing a portion of each preliminary liner layer by removing a portion of each preliminary column layer; as well as The exposed preliminary liner layer is removed.

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