Random access memory structure and method of manufacturing the same

Abstract

The application provides a random access memory structure and a manufacturing method thereof. The method comprises: a substrate, the substrate comprising an array region and a logic region arranged adjacently, the substrate having a step structure, the step structure having a first step surface corresponding to the array region and a second step surface corresponding to the logic region; a first conductive channel, the first conductive channel extending from the first step surface to a first metal wiring layer in the array region; a second conductive channel, the second conductive channel extending from the second step surface to a second metal wiring layer in the logic region; a random access memory cell, the random access memory cell being arranged on the first step surface and in contact with the first conductive channel; and a top metal layer, the top metal layer being arranged in contact with at least one side of the random access memory cell away from the first conductive channel. According to the application, the number of masks is reduced, the process flow is simplified, and thus the manufacturing cost of the random access memory structure is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a random access memory structure and its fabrication method. Background Technology

[0002] MRAM memory cells (MTJs) typically consist of three basic layers: a ferromagnetic layer, an insulating tunneling layer, and a fixed layer. When the magnetic moments of the ferromagnetic and fixed layers are in opposite directions, the memory device exhibits a high-resistivity state (Rap); when the magnetic moments are in the same direction, it exhibits a low-resistivity state (Rp). This distinction between high and low resistance states allows for the storage of information "1" and "0". As a novel type of memory, MRAM offers significant advantages over traditional Flash memory in terms of read / write speed and device reliability. However, the main drawbacks currently hindering the development of MRAM are low array density and high manufacturing costs.

[0003] Therefore, it is necessary to optimize the process integration scheme to reduce the number of process steps, thereby further reducing manufacturing costs. Summary of the Invention

[0004] The main objective of this invention is to provide a random access memory structure and its manufacturing method to solve the problem of high manufacturing cost in the prior art for forming random access memory structures.

[0005] To achieve the above objectives, according to one aspect of the present invention, a random access memory (RAM) structure is provided, comprising: a substrate including an array region and a logic region disposed adjacent to each other, the substrate having a stepped structure having a first stepped surface corresponding to the array region and a second stepped surface corresponding to the logic region; a first conductive channel extending from the first stepped surface to a first metal interconnect layer in the array region; a second conductive channel extending from the second stepped surface to a second metal interconnect layer in the logic region; a RAM cell disposed on the first stepped surface and in contact with the first conductive channel; and a top metal layer in contact with at least the side of the RAM cell away from the first conductive channel.

[0006] Furthermore, it also includes: the top metal layer is respectively configured to contact the side of the random access memory cell away from the first conductive channel and the second conductive channel.

[0007] Furthermore, it also includes a barrier layer, which is respectively connected in contact with the random access memory cell and the first conductive channel.

[0008] Furthermore, the random access memory unit includes any one of magnetic random access memory units, phase change random access memory units, and resistive random access memory units.

[0009] To achieve the above objectives, according to one aspect of the present invention, a method for fabricating a random access memory (RAM) structure is provided. The method includes: providing a substrate, the substrate including an array region and a logic region disposed adjacent to each other, wherein the array region has a first conductive channel and the logic region has a second conductive channel, and the first and second conductive channels are formed in the same etching step and the same filling step; etching at least a portion of the substrate corresponding to the array region to form a step structure in the substrate, the step structure having a first step surface corresponding to the array region and a second step surface corresponding to the logic region, wherein the first conductive channel extends from the first step surface to a first metal interconnect layer of the array region, and the second conductive channel extends from the second step surface to a second metal interconnect layer of the logic region; forming a RAM cell on the first step surface, the RAM cell being disposed in contact with the first conductive channel; and forming a first metal layer that is disposed in contact with at least the side of the RAM cell away from the first conductive channel.

[0010] Furthermore, the steps for forming the stepped structure include: setting a first mask plate on the above-mentioned substrate, the first mask plate having a cutout area, the cutout area being at least corresponding to the array area; etching the substrate corresponding to the cutout area to remove a portion of the substrate corresponding to the array area, thereby forming the stepped structure.

[0011] Furthermore, it also includes: forming a second metal layer that is respectively in contact with the side of the random access memory cell away from the first conductive channel and the second conductive channel.

[0012] Further, the step of forming a random access memory cell includes: forming a random access memory cell film layer at least on a first step surface; disposing a second mask on the random access memory cell film layer, the second mask having a preset pattern and exposing at least the remaining part of the random access memory cell film layer excluding the corresponding preset pattern; etching the random access memory cell film layer according to the preset pattern sequence to remove the exposed random access memory cell film layer and form a random access memory cell.

[0013] Furthermore, after the step of forming the stepped structure and before the step of forming the random access memory cell, the fabrication method further includes: forming a barrier material layer on the first step surface and the second step surface; in the step of forming the random access memory cell, a random access memory cell film layer is formed on the side of the barrier material layer away from the first conductive channel, and the random access memory cell film layer is sequentially etched to form the random access memory cell and the barrier layer.

[0014] Further, after the step of forming the barrier material layer and before the step of forming the random access memory cell and the barrier layer, the step of forming the random access memory cell film layer includes: forming a lower electrode material layer covering the barrier material layer; removing a portion of the lower electrode material layer by chemical mechanical polishing, so that the remaining lower electrode material layer located in the array region has a first thickness in a first direction; thinning the remaining lower electrode material layer located in the array region, so that the thinned lower electrode material layer has a second thickness in the first direction, the first thickness being greater than the second thickness; forming an intermediate material layer that at least covers the thinned lower electrode material layer and an upper electrode material layer that covers the intermediate material layer, wherein the thinned lower electrode material layer, the intermediate material layer, and the upper electrode material layer form the random access memory cell film layer.

[0015] The present invention provides a random access memory (RAM) structure. Since the substrate of this RAM structure includes an array region and a logic region disposed adjacently, and the substrate has a stepped structure, the stepped structure can have a first stepped surface corresponding to the array region and a second stepped surface corresponding to the logic region. Furthermore, since the substrate also has a first conductive channel and a second conductive channel, wherein the first conductive channel is located in the array region and the second conductive channel is located in the logic region, and the first and second conductive channels are formed in the same etching step and the same filling step, and the substrate also has a first metal interconnect layer located in the array region and a second metal interconnect layer located in the logic region, thus, when the array region and logic region correspond to the stepped structure, the first conductive channel extends from the first stepped surface to the first metal interconnect layer in the array region, and the second conductive channel extends from the second stepped surface to the second metal interconnect layer in the logic region. Therefore, a RAM cell that contacts the first conductive channel can be disposed on the first stepped surface, and at least a top metal layer that contacts the RAM cell can be disposed. In other words, this application can form the first conductive channel and the second conductive channel in the random access memory cell in the same step. Compared with the prior art, which requires different etching steps to form the bottom via corresponding to the first conductive channel and the top via corresponding to the second conductive channel, this application reduces the number of etching masks, thereby greatly reducing the manufacturing cost of the random access memory structure. Attached Figure Description

[0016] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0017] Figure 1 A cross-sectional schematic diagram of a random access memory structure according to an embodiment of this application is shown;

[0018] Figure 2 A schematic cross-sectional view of the substrate provided in a random access memory structure according to an embodiment of the present invention is shown.

[0019] Figure 3 It shows in Figure 2 A schematic cross-sectional view of the stepped structure formed in the substrate is shown.

[0020] Figure 4 It shows in Figure 3 The diagram shows a cross-sectional view of the structure in which a lower electrode material layer, a random access memory cell film layer, and an upper electrode material layer are formed.

[0021] Figure 5 Etching is shown Figure 4 The structure shown is a cross-sectional view of a random access memory cell and a protective layer.

[0022] Figure 6 It shows in Figure 5 The diagram shows a cross-sectional view of the structure in which the insulating dielectric layer is formed.

[0023] Figure 7 A schematic diagram of the cross-sectional structure forming the top metal layer is shown;

[0024] Figure 8 It shows in Figure 3 The diagram shows a cross-sectional view of the structure in which a barrier material layer and a lower electrode material layer are formed.

[0025] Figure 9 It shows the Figure 8 A schematic diagram of the cross-sectional structure of the lower electrode material layer after chemical mechanical polishing in the structure shown.

[0026] Figure 10 It shows in Figure 9 Based on the structure shown, a cross-sectional view of the electrode material layer after further etching is obtained.

[0027] Figure 11 It shows in Figure 10 A schematic cross-sectional view of the structure in which the random access memory cell film layer and the upper electrode material layer are formed;

[0028] Figure 12 Etching is shown Figure 11 The diagram shows a cross-sectional structure that forms a random access memory cell and a protective layer.

[0029] Figure 13 It shows in Figure 12 The diagram shows a cross-sectional view of the structure in which the insulating dielectric layer is formed.

[0030] The above figures include the following reference numerals:

[0031] 10. Substrate; 20. First metal interconnect layer; 30. Second metal interconnect layer; 40. First conductive channel; 50. Second conductive channel; 51. Random access memory cell film layer; 60. Lower electrode material layer; 70. Intermediate material layer; 80. Upper electrode material layer; 90. Random access memory cell; 100. Protective layer; 110. Insulating dielectric layer; 120. Top metal layer; 130. Barrier material layer. Detailed Implementation

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] As mentioned in the background section, the main drawbacks of existing technologies that restrict the development of MRAM are low array density and high manufacturing cost. In order to solve the above technical problems, the inventors of this application provide a random access memory structure and its manufacturing method.

[0036] In some optional embodiments, a random access memory (RAM) structure is provided, comprising: a substrate including an array region and a logic region disposed adjacently, the substrate having a stepped structure having a first stepped surface corresponding to the array region and a second stepped surface corresponding to the logic region; a first conductive channel extending from the first stepped surface to a first metal interconnect layer in the array region; a second conductive channel extending from the second stepped surface to a second metal interconnect layer in the logic region; a RAM cell disposed on the first stepped surface and contacted by the first conductive channel; and a top metal layer contacting at least the side of the RAM cell away from the first conductive channel.

[0037] Wherein, the first direction is perpendicular to the first step surface, the first conductive channel has a first height in the first direction, and the second conductive channel has a second height in the first direction, the first height being less than the second height. Optionally, the height difference between the first height and the second height can be 50 nm to 200 nm. Further, the materials of the first and second conductive channels can be any one or more selected independently from titanium (Ti), tungsten (W), tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).

[0038] It should be noted that the first and second conductive channels are formed in the same etching and filling steps, and then etched to form a stepped structure.

[0039] Furthermore, the aforementioned random access memory structure also includes a protective layer and an insulating dielectric layer. The protective layer is disposed on the outer periphery of the random access memory cell and on the first step surface, meaning that the magnetoresistive random access memory cell has an exposed surface on the side away from the first conductive channel. The dielectric insulating layer is disposed on the side of the protective layer away from the substrate. Thus, during the formation of the top metal layer on the side of the magnetoresistive random access memory cell away from the first conductive channel, the top metal layer can be electrically connected to the exposed surface of the magnetoresistive random access memory cell. By providing the insulating dielectric layer, the sum of the thicknesses of the protective layer and the insulating dielectric layer is consistent with the thickness of the magnetoresistive random access memory cell in the direction perpendicular to the first step surface, thereby enabling at least a top metal layer of uniform thickness to be formed in the array region corresponding to the first step surface.

[0040] Through this application, since the substrate of the random access memory structure includes an array region and a logic region disposed adjacently, and the substrate has a stepped structure, the stepped structure can have a first stepped surface corresponding to the array region and a second stepped surface corresponding to the logic region. Furthermore, since the substrate also has a first conductive channel and a second conductive channel, wherein the first conductive channel is located in the array region and the second conductive channel is located in the logic region, and the first and second conductive channels are formed in the same etching step and the same filling step, and the substrate also correspondingly has a first metal interconnect layer located in the array region and a second metal interconnect layer located in the logic region, thereby achieving [the desired effect]. When the column area and logic area correspond to the aforementioned stepped structure, the first conductive channel extends from the first stepped surface into the first metal interconnect layer in the array area, and the second conductive channel extends from the second stepped surface into the second metal interconnect layer in the logic area. Thus, in a first direction perpendicular to the first stepped surface, the first conductive channel has a first height in the first direction, and the second conductive channel has a second height in the first direction, where the first height is less than the second height. This allows for the provision of random access memory (RAM) cells that contact the first conductive channel on the first stepped surface, and at least a top metal layer that contacts the RAM cells. In other words, the RAM structure of this application allows for the formation of the first and second conductive channels within the RAM cells in the same step. Compared to the prior art, which requires different etching steps to form bottom vias corresponding to the first conductive channel and top vias corresponding to the second conductive channel, this application reduces the number of photomasks, thereby significantly reducing the manufacturing cost of the RAM structure.

[0041] In some optional embodiments, the above-described random access memory structure further includes: a top metal layer that is respectively in contact with the side of the random access memory cell away from the first conductive channel and the second conductive channel.

[0042] Specifically, in an optional embodiment, the above-mentioned random access memory structure includes a substrate with a stepped structure, a first conductive channel located in the array region of the substrate and a second conductive channel located in the logic region of the substrate, random access memory cells that are contacted and disposed in contact with the first conductive channel, and a top metal layer that is contacted and disposed in contact with the random access memory cells.

[0043] Specifically, in another optional embodiment, the top metal layer in the above-described random access memory structure is not only in contact with the random access memory cells, but also in contact with the second conductive channel located in the logic region. This embodiment enables an electrical connection between the array region and the logic region in the above-described random access memory structure.

[0044] In some optional embodiments, the above-described random access memory structure further includes a barrier layer, which is disposed in contact with the random access memory cell and the first conductive channel, respectively.

[0045] Specifically, in one optional embodiment, the above-described random access memory (RAM) structure includes a substrate with a stepped structure, a first conductive channel located in an array region of the substrate, a second conductive channel located in a logic region of the substrate, a barrier layer contacting the first conductive channel, a RAM cell contacting the barrier layer, and a top metal layer contacting at least the RAM cell. In this embodiment, by providing a barrier layer between the first conductive channel and the RAM cell, the quality of each film layer in the formed RAM cell is improved.

[0046] Specifically, in another optional embodiment, the aforementioned random access memory (RAM) structure not only has barrier layers that are respectively contacted with the first conductive channel and the RAM cell, but also has a top metal layer that is respectively contacted with the upper electrode of the RAM cell and the second conductive channel located in the logic region. In this embodiment, by providing barrier layers, the quality of each film layer of the formed RAM cell is improved, and because the top metal layer is respectively contacted with the upper electrode and the second conductive channel, electrical connection between the array region and the logic region in the RAM structure is achieved.

[0047] In some alternative implementations, the random access memory cell includes any one of a magnetic random access memory cell, a phase-change random access memory cell, and a resistive random access memory cell.

[0048] Specifically, any one of the above-mentioned magnetic random access memory units, phase change random access memory units, and resistive random access memory units can be replaced with the random access memory units mentioned in any embodiment of this application, thereby obtaining random access memory structures for different needs.

[0049] In the case where the aforementioned random access memory (RAM) unit is a magnetic random access memory (RAM) unit, the RAM unit may include a lower electrode, a magnetic tunnel junction, and an upper electrode stacked sequentially along the side away from the substrate. The magnetic tunnel junction includes a free magnetic layer, a tunnel gate layer, and a fixed magnetic layer stacked sequentially. The lower electrode is in contact with the first conductive channel. The material of the tunnel gate layer may include, but is not limited to, magnesium oxide or aluminum oxide. In this structure, the polarization direction of the magnetic tunnel junction can be changed by an applied magnetic field or electric field, causing the free magnetic layer and the fixed magnetic layer of the magnetic tunnel junction to exhibit both parallel and antiparallel states. Since the magnetoresistance (TMR) corresponding to these parallel and antiparallel states differs significantly, low resistance and high resistance can be used as the two different states of "0" and "1".

[0050] In the case where the aforementioned random access memory (RAM) unit is a phase-change RAM (PCM) unit, the PCM unit may include a lower electrode, a phase-change layer, and an upper electrode stacked sequentially along a side away from the substrate. The lower electrode is in contact with the first conductive channel. The material of the phase-change layer may include, but is not limited to, chalcogenides (represented by Intel), and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5 (represented by STMicroelectronics). In this structure, since the material corresponding to the phase-change layer can transition between crystalline (low-resistance state) and amorphous (high-resistance state), the difference in conductivity between the crystalline and amorphous states of the material corresponding to the phase-change layer can be used to store information.

[0051] In the case where the aforementioned random access memory (RAM) unit is a resistive switching RAM unit, the RAM unit may include a lower electrode, a thin dielectric layer, and a top electrode sequentially stacked along the side away from the substrate. The thin dielectric layer serves as an ion transport and storage medium and may include binary transition metal oxides (TMOs), perovskite compounds, solid electrolytes, and organic dielectric materials. The binary transition metal oxides may include, but are not limited to, any one of nickel oxide (NiO), titanium oxide (TiO2), and zinc oxide (ZnO). In this structure, the high and low resistance states of the structure can be detected by forming and breaking filaments (conductive filaments formed by ion transport between the upper and lower electrodes) in the thin dielectric layer.

[0052] In addition, in some alternative embodiments, in order to align the random access memory cell and the first conductive via, an alignment mark is provided in the substrate on the side near the random access memory cell. The alignment mark is usually provided on the periphery of the chip.

[0053] Exemplary embodiments of the method for fabricating a random access memory structure according to the present invention will now be described in more detail. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0054] In some alternative implementations, such as Figure 1 As shown, the inventors of this application provide a method for fabricating a random access memory (RAM) structure. The method includes: providing a substrate 10, which includes an array region and a logic region disposed adjacent to each other. The array region has a first conductive channel 40, and the logic region has a second conductive channel 50. At least a portion of the substrate 10 corresponding to the array region is etched to form a stepped structure in the substrate 10. The stepped structure has a first stepped surface corresponding to the array region and a second stepped surface corresponding to the logic region. The first conductive channel 40 extends from the first stepped surface to a first metal interconnect layer 20 in the array region, and the second conductive channel 50 extends from the second stepped surface to a second metal interconnect layer 30 in the logic region. A RAM cell 90 is formed on the first stepped surface, and the RAM cell 90 is in contact with the first conductive channel 40. A top metal layer 120 is formed, which is in contact with at least the side of the RAM cell 90 away from the first conductive channel 40. Optionally, a barrier material layer 130 may also be included between the RAM cell 90 and the first conductive channel 40. Optionally, the above-described random access memory structure further includes a protective layer 100, which covers the sidewalls and the first step surface of the random access memory cell 90. The dashed line in the figure can be understood as the boundary line between the array area and the logic area.

[0055] Specifically, in the above embodiments, such as Figure 2 As shown, a metal interconnect layer is also provided in the substrate 10. This metal interconnect layer includes a first metal interconnect layer 20 located in the array region and a second metal interconnect layer 30 located in the logic region. Further, the array region has a first conductive channel 40 in contact with the first metal interconnect layer 20, and the logic region has a second conductive channel 50 in contact with the second metal interconnect layer 30. Since etching the portion of the substrate 10 corresponding to the array region forms a step structure in the substrate 10, the array region has a first step surface corresponding to the step structure, and the logic region has a second step surface corresponding to the step structure. This allows the first conductive channel 40 to extend from the first step surface to the first metal interconnect layer 20 in the array region, and the second conductive channel 50 to extend from the second step surface to the second metal interconnect layer 30 in the logic region. Figure 3 As shown.

[0056] It is important to note that, such as Figure 2 The first conductive channel 40 and the second conductive channel 50 shown above are formed in the same etching step and the same filling step. Specifically, the substrate 10 provided first includes an array region and a logic region, and the array region has a first metal interconnect layer 20, and the logic region has a second metal interconnect layer 30. In order to form the first conductive channel 40 and the second conductive channel 50, a photolithography process is first used to form a photomask on the surface of the substrate 10 to form a first pattern on the surface of the substrate 10 corresponding to the array region and a second pattern on the surface of the substrate 10 corresponding to the logic region. Then, etching is performed according to the first pattern and the second pattern to form a first through-hole extending from the surface of the substrate 10 to the first metal interconnect layer 20 in the substrate 10 corresponding to the array region, and a second through-hole extending from the surface of the substrate 10 to the second metal interconnect layer 30 in the substrate 10 corresponding to the logic region. Next, a metal material is deposited on the surface of the substrate 10 through a deposition process, such that the metal material at least fills the first and second through holes. Further, a chemical mechanical polishing process can be used to remove the metal material located outside the first and second through holes to form the first conductive channel 40 and the second conductive channel 50. Further, at least the portion of the substrate corresponding to the array region is etched to form, as shown in the image. Figure 3 The stepped structure shown.

[0057] In the above-described fabrication method, the first conductive channel 40 serves as the bottom conductive channel in the random access memory (RAM) structure, and the second conductive channel 50 serves as the top conductive channel. Typically, at least two etching steps are used to form the bottom and top conductive channels in different process steps, leading to high fabrication costs. However, this application forms the first conductive channel 40 and the second conductive channel 50 in the same process step, requiring only one etching step to achieve the goal of using the first conductive channel 40 as the bottom conductive channel and the second conductive channel 50 as the top conductive channel. Furthermore, a RAM cell 90 is formed on the first conductive channel 40, in contact with it, and a top metal layer 120 is formed, at least in contact with the RAM cell 90. Therefore, this application reduces the number of etching steps and the corresponding number of photomasks, thereby significantly reducing the fabrication cost of the RAM structure.

[0058] In some alternative implementations, such as Figure 3 As shown, the steps for forming the above-mentioned stepped structure include: setting a first mask plate on the above-mentioned substrate 10, the first mask plate having a hollow area, the hollow area being at least corresponding to the array area; etching the substrate corresponding to the hollow area to remove part of the substrate 10 corresponding to the array area, thereby forming a stepped structure.

[0059] Specifically, such as Figure 3 As shown in the above embodiment, in order to make the first conductive channel 40 serve as the bottom conductive channel in the random access memory structure and the second conductive channel 50 serve as the top conductive channel in the random access memory structure, by setting the first mask and etching, a step structure is first formed in the array area and the logic area. Thus, in the direction perpendicular to the first step surface, the first conductive channel 40 has a first height and the second conductive channel 50 has a second height, and the first height is less than the second height. Thus, random access memory cells can be set on the first conductive channel 40 with the first height, so that the first conductive channel 40 with the first height serves as the bottom conductive channel of the random access memory structure.

[0060] Optionally, to align the formed random access memory (RAM) cells with the first conductive channel 40, the first mask includes a first cutout area and a second cutout area. The first cutout area corresponds to the array region and is used to form the stepped structure. The second cutout area corresponds to the substrate 10 located outside the array region and logic region and is used to form alignment marks. In this step, the same mask can be used to simultaneously etch the stepped structure and the alignment marks, thereby forming the bottom conductive channel (first conductive channel 40), the top conductive channel (second conductive channel 50), and the alignment marks of the RAM structure in the same process step, further simplifying the process flow and reducing the manufacturing cost of the RAM structure.

[0061] Furthermore, in order to make the array region and logic region of the random access memory structure electrically connected, after forming the random access memory cell 90 on the first step surface based on the step of forming a top metal layer 120 that contacts the side of the random access memory cell away from the first conductive channel 40, the above manufacturing method further includes: forming a top metal layer 120 that contacts the side of the random access memory cell away from the first conductive channel and the second conductive channel respectively, such as... Figure 1 As shown.

[0062] In some alternative implementations, such as Figure 4 and Figure 5 As shown, the step of forming a random access memory cell includes: forming a random access memory cell film layer 51 at least on the first step surface, such as... Figure 4As shown; a second mask is disposed on the random access memory cell film layer 51. The second mask has a preset pattern and exposes at least the remaining portion of the random access memory cell film layer 51 excluding the corresponding preset pattern; the random access memory cell film layer 51 is etched sequentially according to the preset pattern to remove the exposed random access memory cell film layer 51, forming a random access memory cell 90, as shown. Figure 5 As shown.

[0063] In the above embodiments, such as Figure 4 As shown, in order to form a random access memory (RAM) structure on the first conductive channel 40, a RAM cell film layer 51 can be formed at least on the first step surface. This RAM cell film layer 51 may include a lower electrode material layer 60, an intermediate material layer 70, and an upper electrode material layer 80 stacked together. Then, by providing a second mask with a pattern (preset pattern) corresponding to the RAM cell, during etching according to the second mask, the RAM cell film layer 51 corresponding to the preset pattern on the first conductive channel 40 can be retained, and the remaining RAM cell film layer 51 on the first step surface can be removed, thereby forming the aforementioned RAM cell 90. Optionally, after forming the RAM cell 90, a protective layer 100 is formed on the side of the RAM cell 90 away from the substrate 10, such as... Figure 5 As shown. Further, as... Figure 6 As shown, in Figure 5 An insulating dielectric layer 110 is formed on the side of the protective layer 100 away from the substrate 10. Further, a portion of the insulating dielectric layer 110 is removed by chemical mechanical polishing to form a flat upper surface, such as... Figure 7 As shown, a top metal layer 120 is formed on the side of the insulating dielectric layer 110 away from the protective layer 100.

[0064] Optionally, the random access memory cell film layer 51 can also be disposed on the first step surface and the second step surface. After etching according to the second mask, only the random access memory cell film layer 51 with the corresponding preset pattern on the first conductive channel 40 is retained, and the remaining random access memory cell film layers 51 on the first step surface and the second step surface are removed, thereby forming the random access memory cell 90.

[0065] In some alternative embodiments, in order to form a high-quality random access memory cell on the first conductive channel 40, the fabrication method further includes, after the step of forming the stepped structure and before the step of forming the random access memory cell, forming a barrier material layer 130 on the first step surface and the second step surface, such as... Figure 8As shown; in the step of forming a random access memory cell, a random access memory cell film layer is formed on the side of the barrier material layer 130 away from the first conductive channel 40, and the random access memory cell film layer is sequentially etched to form a random access memory cell and a barrier layer.

[0066] Optionally, the barrier material layer 130 is a conductive material layer, and the material of the barrier material layer 130 may be selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and tungsten nitride (WN).

[0067] In some alternative implementations, such as Figure 8 Wherever Figure 11 As shown, the step of forming the random access memory cell film layer after the step of forming the barrier material layer 130 and before the step of forming the random access memory cell and the barrier layer includes: forming a lower electrode material layer 60 covering the barrier material layer 130, such as... Figure 8 As shown; chemical mechanical polishing is used to remove part of the lower electrode material layer 60, so that the remaining lower electrode material layer 60 located in the array region has a first thickness in the first direction, such as... Figure 9 As shown; the remaining lower electrode material layer 60 located in the array region is thinned so that the thinned lower electrode material layer 60 has a second thickness in the first direction, the first thickness being greater than the second thickness, as shown. Figure 10 As shown; an intermediate material layer 70 is formed that covers at least the thinned lower electrode material layer 60, and an upper electrode material layer 80 is formed that covers the intermediate material layer 70. The thinned lower electrode material layer 60, intermediate material layer 70, and upper electrode material layer 80 form a random access memory cell film layer 51, as shown. Figure 11 As shown.

[0068] Optionally, the material of the lower electrode material layer 60 may be selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). It should be noted that the materials of the barrier material layer 130 and the lower electrode material layer 60 in the random access memory cell are different.

[0069] Specifically, when the random access memory unit is a magnetic random access memory unit, the intermediate material layer 70 is a material film layer corresponding to the magnetic tunnel junction, that is, the intermediate material layer 70 is a material layer corresponding to the free magnetic layer, the material layer corresponding to the tunnel gate layer, and the material layer corresponding to the fixed magnetic layer stacked sequentially; when the random access memory unit is a phase change random access memory unit, the intermediate material layer 70 is a material layer corresponding to the phase change layer; when the random access memory unit is a resistive switching random access memory unit, the intermediate material layer 70 is a material layer corresponding to the thin dielectric layer.

[0070] In the above embodiments, such as Figure 9 As shown, to facilitate the etching process of the lower electrode material, after the lower electrode material layer 60 is formed, it is first planarized by chemical mechanical polishing (CMP) to give it a flat surface. Specifically, to facilitate thickness control of the lower electrode material layer 60 during CMP, this planarization process removes the lower electrode material layer 60 located in the logic region, exposing the barrier material layer 130 in the logic region, while retaining the lower electrode material layer 60 located in the array region. Then, after the CMP step, the lower electrode material layer 60 located in the array region is thinned by etching, as shown... Figure 10 As shown, the thinned lower electrode material layer 60 is used to form the lower electrode of the magnetoresistive random access memory cell. Specifically, after removing part of the lower electrode material layer 60 using the aforementioned chemical mechanical polishing process, if a portion of the lower electrode material layer 60 remains on the barrier material layer 130 in the logic region, the remaining lower electrode material layer 60 on the barrier material layer 130 in the logic region is removed during the thinning process, exposing the barrier material layer 130 in the logic region. Then, by sequentially depositing the intermediate material layer 70 and the upper electrode material layer 80, the sequentially stacked lower electrode material layer 60, intermediate material layer 70, and upper electrode material layer 80 form the random access memory cell film layer 51. Figure 11 As shown.

[0071] Optionally, after forming the upper electrode material layer 80, a hard mask layer may be formed on the upper electrode material layer 80 and used as a sacrificial layer for etching to form the random access memory cell film layer 51, so as to remove the hard mask layer during the formation of the random access memory cell film layer 51.

[0072] Furthermore, in some embodiments, by first depositing a barrier material layer and a lower electrode material layer, and then through planarization and etching back, forming the respective film layers corresponding to the random access memory cells on the lower electrode material layer after etching back, the respective film layers corresponding to the random access memory cells can have a smoother surface, which is beneficial to the formation and performance improvement of the subsequent random access memory structure.

[0073] Further, the random access memory cell film layer 51 is etched to form the random access memory cell 90, forming a protective layer 100 covering the first step surface, the random access memory cell 90, and the second step surface, so that the protective layer 100 covers the exposed surface after the formation of the random access memory cell 90, such as... Figure 12 As shown, in the step of forming the top metal layer 120 after etching to form the random access memory cell 90, an insulating dielectric layer 110 is formed on the protective layer 100, such as... Figure 13 As shown; further, the insulating dielectric layer 110 and the protective layer 100 are sequentially etched to expose the surface of the random access memory cell 90 away from the first conductive channel 40, and to expose the second conductive channel 50 on the second step surface. Optionally, this process can be achieved using chemical mechanical polishing. Then, a top metal layer 120 is formed on the exposed surface of the random access memory cell 90 away from the first conductive channel 40; or further, the top metal layer 120 is formed on the exposed surface of the random access memory cell 90 away from the first conductive channel 40 and on the exposed second conductive channel 50, as shown. Figure 1 As shown.

[0074] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0075] Through this application, since the substrate of the random access memory structure includes an array region and a logic region disposed adjacently, and the substrate has a stepped structure, the stepped structure can have a first stepped surface corresponding to the array region and a second stepped surface corresponding to the logic region. Furthermore, since the substrate also has a first conductive channel and a second conductive channel, wherein the first conductive channel is located in the array region and the second conductive channel is located in the logic region, and the substrate also has a first metal interconnect layer located in the array region and a second metal interconnect layer located in the logic region, when the array region and the logic region correspond to the above-mentioned stepped structure, the first conductive channel extends from the first stepped surface to the first metal interconnect layer in the array region, and the second conductive channel extends from the second stepped surface to the second metal interconnect layer in the logic region. Thus, in a first direction perpendicular to the first stepped surface, the first conductive channel has a first height in the first direction, and the second conductive channel has a second height in the first direction, the first height being less than the second height. Consequently, a random access memory cell that contacts the first conductive channel can be disposed on the first stepped surface, and at least a top metal layer that contacts the random access memory cell can be disposed. In other words, the random access memory structure described in this application can form the first conductive channel and the second conductive channel in the random access memory cell in the same step. Compared with the prior art, which requires different etching steps to form the bottom via corresponding to the first conductive channel and the top via corresponding to the second conductive channel, this application reduces the number of etching masks, thereby greatly reducing the manufacturing cost of the random access memory structure.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A random access memory structure, characterized in that, include: The substrate includes an array area and a logic area disposed adjacent to each other. The substrate has a stepped structure, and the stepped structure has a first stepped surface corresponding to the array area and a second stepped surface corresponding to the logic area. A first conductive channel extends from the first stepped surface to a first metal interconnect layer in the array region; A second conductive channel extends from the second stepped surface to a second metal interconnect layer in the logic region; A random access memory unit, wherein the random access memory unit is disposed on the first step surface and is in contact with the first conductive channel; A top metal layer is disposed in contact with at least one side of the random access memory cell away from the first conductive channel.

2. The random access memory structure according to claim 1, characterized in that, Also includes: The top metal layer is respectively in contact with the side of the random access memory cell away from the first conductive channel and the second conductive channel.

3. The random access memory structure according to claim 1 or 2, characterized in that, Also includes: A barrier layer is provided in contact with the random access memory cell and the first conductive channel, respectively.

4. The random access memory structure according to claim 1 or 2, characterized in that, The random access memory unit includes any one of magnetic random access memory units, phase change random access memory units, and resistive random access memory units.

5. A method for fabricating a random access memory structure, characterized in that, The manufacturing method includes: A substrate is provided, the substrate including an array region and a logic region disposed adjacently, wherein the array region has a first conductive channel and the logic region has a second conductive channel, and the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step; At least the portion of the substrate corresponding to the array region is etched to form a step structure in the substrate. The step structure has a first step surface corresponding to the array region and a second step surface corresponding to the logic region. The first conductive channel extends from the first step surface to a first metal interconnect layer of the array region, and the second conductive channel extends from the second step surface to a second metal interconnect layer of the logic region. A random access memory cell is formed on the first step surface, and the random access memory cell is disposed in contact with the first conductive channel; A top metal layer is formed that is in contact with at least one side of the random access memory cell away from the first conductive channel.

6. The manufacturing method according to claim 5, characterized in that, The steps for forming the stepped structure include: A first mask plate is disposed on the aforementioned substrate. The first mask plate has a cutout area, and the cutout area is disposed at least corresponding to the array area. The substrate corresponding to the hollowed-out area is etched to remove a portion of the substrate corresponding to the array area, forming the stepped structure.

7. The manufacturing method according to claim 5, characterized in that, Also includes: A top metal layer is formed that is in contact with the side of the random access memory cell away from the first conductive channel and the second conductive channel, respectively.

8. The manufacturing method according to any one of claims 5 to 7, characterized in that, The steps for forming the random access memory cell include: At least one random access memory cell film layer is formed on the first step surface; A second mask is disposed on the random access memory cell film layer. The second mask has a preset pattern and exposes at least the remaining part of the random access memory cell film layer other than the preset pattern. The random access memory cell film layer is etched according to the preset pattern sequence to remove the exposed random access memory cell film layer and form the random access memory cell.

9. The manufacturing method according to claim 8, characterized in that, After the step of forming the stepped structure And prior to the step of forming the random access memory cell, the fabrication method further includes: A barrier material layer is formed on the first step surface and the second step surface; In the step of forming the random access memory cell, the random access memory cell film layer is formed on the side of the barrier material layer away from the first conductive channel, and the random access memory cell film layer is sequentially etched to form the random access memory cell and the barrier layer.

10. The manufacturing method according to claim 9, characterized in that, The step of forming the random access memory cell film layer after the step of forming the barrier material layer and before the steps of forming the random access memory cell and the barrier layer includes: A lower electrode material layer is formed covering the barrier material layer; Chemical mechanical polishing is used to remove part of the lower electrode material layer so that the remaining lower electrode material layer located in the array region has a first thickness in a first direction, the first direction being the direction perpendicular to the first step surface; The remaining lower electrode material layer in the array region is thinned so that the thinned lower electrode material layer has a second thickness in the first direction, the first thickness being greater than the second thickness; An intermediate material layer is formed that covers at least the thinned lower electrode material layer and an upper electrode material layer that covers the intermediate material layer. The thinned lower electrode material layer, the intermediate material layer and the upper electrode material layer form the random access memory cell film layer.

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