IGBT structure and semiconductor devices

Abstract

This application discloses an IGBT structure and semiconductor device. The IGBT structure includes: a substrate, a drift region, a collector region of a first conductivity type, an active gate, a body region of the first conductivity type, a first emitter region of a second conductivity type, and a dummy gate. The dummy gate extends from the second main surface of the substrate toward the first main surface of the substrate into the drift region. The drift region includes a first stud region of the first conductivity type and a second stud region of the second conductivity type, the first stud regions and the second stud regions being alternately arranged in a horizontal direction. The active gate extends from one end of the first main surface toward the first main surface into the second stud region, and the dummy gate extends from one end of the first main surface toward the first main surface into the first stud region. According to the IGBT structure and semiconductor device of this application, conduction losses can be significantly reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to an IGBT structure and a semiconductor device. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a MOS-bipolar compound transistor developed based on the power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It has the common advantages of power bipolar transistors and power MOSFETs, and has different advantages in on-state voltage drop and switching, making it a core device in power supply, drive and control circuits.

[0003] In order to meet different application scenarios, IGBT needs to achieve a good balance and trade-offs in conduction and switching, and should also achieve as low conduction loss as possible to improve power conversion efficiency.

[0004] In existing IGBT structures, the carrier flow path in the drift region is usually relatively single, resulting in large conduction losses.

[0005] Therefore, improvements are needed to at least partially solve the above problems. Summary of the Invention

[0006] The present invention aims to at least partially solve the above problems. To this end, one object of the present invention is to provide an IGBT structure with low conduction loss. Another object of the present invention is to provide a semiconductor device having the IGBT structure.

[0007] The IGBT structure according to an embodiment of the present invention includes:

[0008] a substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a vertical direction;

[0009] a drift region, the drift region being provided between the first main surface and the second main surface;

[0010] a collector region of a first conductivity type, the collector region being provided on a side of the drift region facing the first main surface, and a side of the collector region away from the drift region constituting at least a portion of the first main surface;

[0011] an active gate extending from the second main surface toward the first main surface into the drift region;

[0012] a body region of a first conductivity type, the body region being provided on a side of the drift region facing the second main surface and located on both sides of the active gate in a horizontal direction;

[0013] a first emitter region of a second conductivity type, the first emitter region being provided on a side of the body region facing the second main surface, and a side of the first emitter region away from the body region constituting a portion of the second main surface;

[0014] a dummy gate extending from the second main surface toward the first main surface into the drift region;

[0015] The drift region includes a first stud region of a first conductivity type and a second stud region of a second conductivity type, and the first stud region and the second stud region are alternately arranged in a horizontal direction;

[0016] One end of the active gate facing the first main surface extends into the second stud region, and one end of the dummy gate facing the first main surface extends into the first stud region.

[0017] Optionally, the IGBT structure further includes a second emitter region of the first conductivity type, the second emitter region is provided in the first emitter region, and a side of the second emitter region away from the first main surface constitutes at least a part of the second main surface.

[0018] Optionally, the IGBT structure further includes:

[0019] an insulating layer, the insulating layer being provided on the second main surface, and a contact hole being provided in a portion of the insulating layer corresponding to the second emitter region;

[0020] an emitter metal, the emitter metal being disposed on a side of the insulating layer away from the second main surface and in the contact hole, the emitter metal being in contact with the second emitter region;

[0021] A collector metal is provided on the first main surface.

[0022] Optionally, the dummy gate includes a first gate trench extending from the second main surface to the first main surface to the first column region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench;

[0023] The first polysilicon gate contacts the emitter metal.

[0024] Optionally, the dummy gate includes a first gate trench extending from the second main surface to the first main surface to the first column region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench;

[0025] The first polysilicon gate is a floating gate.

[0026] Optionally, the IGBT structure further includes a second conductive type doped region, which is located on both sides of the virtual gate in the horizontal direction and is in contact with the first emitter region, and the side of the doped region away from the first main surface constitutes at least part of the second main surface.

[0027] Optionally, the IGBT structure further includes a field stop region of the second conductivity type, and the field stop region is provided between the collector region and the drift region.

[0028] Optionally, the active gate includes a second gate trench extending from the second main surface to the first main surface to the second column region, a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on the side of the second gate dielectric layer away from the inner surface of the second gate trench.

[0029] Optionally, the first conductivity type is P type;

[0030] The second conductivity type is N type.

[0031] The semiconductor device according to the embodiment of the present invention includes the IGBT structure described above.

[0032] According to the IGBT structure and semiconductor device of the present invention, the drift region includes a first column region of the first conductivity type and a second column region of the second conductivity type alternately arranged in the horizontal direction. The arrangement of the first column region and the second column region can increase the carrier flow path, improve the unbalanced carrier injection efficiency, and reduce the conduction voltage drop of the drift region. The arrangement of the virtual gate can enhance the carrier storage effect in the first column region, further reduce the conduction voltage drop in the first column region, and thus significantly reduce the conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following drawings of this application are hereby incorporated as part of this application for understanding this application. The drawings show the embodiments of this application and their descriptions, and are used to explain the device and principle of this application. In the drawings,

[0034] Figure 1 is a schematic cross-sectional view of an IGBT structure according to an embodiment of the present application;

[0035] Figure 2Schematic diagram of the principle of the IGBT structure according to one embodiment of the present application;

[0036] Figure 3-Figure 9 Schematic cross-sectional views of various steps of a method for manufacturing an IGBT structure according to an embodiment of the present application.

[0037] Description of reference numerals:

[0038] 10-substrate, 11-first pillar, 12-second pillar, 13-first gate trench, 14-second gate trench, 15-second doping region;

[0039] 100 - substrate, 101 - first main surface, 102 - second main surface, 110 - drift region, 111 - first stud region, 112 - second stud region, 120 - collector region, 130 - active gate, 140 - body region, 150 - first emitter region, 160 - dummy gate, 170 - second emitter region, 180 - doped region, 190 - field stop region;

[0040] 200-insulating layer, 210-contact hole;

[0041] 300-emitter metal;

[0042] 400-Collector Metal. DETAILED DESCRIPTION

[0043] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0044] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0045] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0046] Spatially relative terms, such as "below," "beneath," "beneath," "above," "upper," etc., may be used herein for convenience to describe the relationship of one element or feature to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientations depicted in the figures.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present application should not be limited to the specific shapes shown herein, but rather include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of the present application.

[0049] Refer to the attached Figure 1 、 2 The structure of an IGBT according to an embodiment of the present invention is exemplified. In the following description, N and P represent the conductivity type of the semiconductor. The following description assumes that the first conductivity type is P-type and the second conductivity type is N-type.

[0050] The IGBT structure mainly includes: a base 100 , a drift region 110 , a collector region 120 of a first conductivity type, an active gate 130 , a body region 140 of a first conductivity type, a first emitter region 150 of a second conductivity type, and a dummy gate 160 .

[0051] The substrate 100 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101. The first main surface 101 and the second main surface 102 are perpendicular to each other in the vertical direction (ie, Figure 1 Interval setting in the up and down directions.

[0052] The drift region 110 is provided between the first main surface 101 and the second main surface 102. The drift region 110 determines the saturation voltage drop and voltage level of the IGBT and is the main region that affects the switching speed of the IGBT.

[0053] The collector region 120 of the first conductivity type is provided on a side of the drift region 110 facing the first main surface 101 , and a side of the collector region 120 away from the drift region 110 constitutes at least a portion of the first main surface 101 .

[0054] The active gate 130 extends from the second main surface 102 toward the first main surface 101 into the drift region 110. The active gate 130 is the gate structure that actually controls the IGBT and forms a conductive channel. When a gate voltage is applied to the active gate 130, a conductive channel forms around it, enabling electrons and holes to move within the channel, thereby controlling the IGBT's on and off state.

[0055] The first conductive type body region 140 is provided on the side of the drift region 110 facing the second main surface 102 and is located at the horizontal direction (ie, the horizontal direction) of the active gate 130. Figure 1 on both sides of the left and right directions).

[0056] The first emitter region 150 of the second conductivity type is provided on the side of the body region 140 facing the second main surface 102, and the side of the first emitter region 150 away from the body region 140 constitutes part of the second main surface 102. For example, the first emitter region 150 is also called a source region.

[0057] The dummy gate 160 extends from the second main surface 102 toward the first main surface 101 into the drift region 110. The dummy gate 160 is a gate structure that exists in the IGBT structure but does not directly participate in electrical conduction and generally cannot form a conductive channel. For example, the dummy gate 160 may also be referred to as a dummy cell narrow trench gate.

[0058] In this embodiment, the drift region 110 includes a first stud region 111 of a first conductivity type and a second stud region 112 of a second conductivity type. The first stud region 111 and the second stud region 112 (i.e., a P stud region and an N stud region) are alternately arranged in a horizontal direction, forming a superjunction structure in the drift region 110. The active gate 130 extends from one end facing the first main surface 101 into the second stud region 112, and the dummy gate 160 extends from one end facing the first main surface 101 into the first stud region 111.

[0059] On the one hand, the drift region 110 includes the first column region 111 and the second column region 112 which are alternately arranged to increase the carrier flow path. Figure 2 In addition to the fact that carriers (such as holes) can enter the second pillar region 112 from bottom to top, Figure 2As shown at A in the middle, carriers (e.g., holes) can also enter the second column region 112 horizontally from the first column region 111, and carriers (e.g., electrons) in the second column region 112 can also enter the first column region 111 horizontally. In a conventional IGBT structure, the drift region 110 is typically entirely of the second conductivity type, and carriers (e.g., holes) can only enter the second column region 112 from bottom to top. Thus, the IGBT structure of this embodiment effectively increases the number of unbalanced carrier flow paths, improves unbalanced carrier injection efficiency, enhances the conductivity modulation effect, reduces the on-state voltage drop in the drift region 110, and thus reduces conduction losses.

[0060] On the other hand, the drift region 110 forms a cellular structure in which the first column region 111 and the second column region 112 alternate in the horizontal direction. In the cut-off state, the first column region 111 and the second column region 112 constituting the super junction structure are in a completely depleted state, and the electric field distribution in the space charge region is approximately a rectangular distribution (e.g., Figure 2 As shown at B in the figure, the entire drift region 110 is more uniform when bearing voltage, and each part can effectively share the voltage, thereby effectively improving the forward voltage withstand capability of the IGBT structure.

[0061] In addition, since the end of the virtual gate 160 toward the first main surface 101 extends into the first column region 111, when the IGBT structure is turned on, no electron channel is generated at the virtual gate 160, and the path of holes reaching the emitter region through the first column region 111 is blocked (e.g., Figure 2 As shown in the middle C, the carrier storage effect in the first column region 111 is enhanced, which can effectively increase the number of unbalanced carriers in the drift region 110, further reduce the conduction voltage drop of the first column region 111, and thus reduce the conduction loss.

[0062] Further, see Appendix Figure 1 The IGBT structure further includes a second emitter region 170 of the first conductivity type. The second emitter region 170 is disposed within the first emitter region 150. The side of the second emitter region 170 facing away from the first main surface 101 constitutes at least a portion of the second main surface 102. The provision of the second emitter region 170 can effectively reduce on-resistance and increase switching speed. For example, the doping concentration of the second emitter region 170 is higher than the doping concentration of the body region 140.

[0063] Further, see Appendix Figure 1 The IGBT structure further includes: an insulating layer 200 , an emitter metal 300 and a collector metal 400 .

[0064] An insulating layer 200 is provided on the second main surface 102. A contact hole 210 is provided in the portion of the insulating layer 200 corresponding to the second emitter region 170. On the second main surface 102, the insulating layer 200 covers the side of the source gate 130 facing away from the first main surface 101, the side of the dummy gate 160 facing away from the first main surface 101, and the side of the first emitter region 150 facing away from the first main surface 101. The bottom of the contact hole 210 exposes the second emitter region 170. By way of example, the insulating layer 200 also serves as an interlayer dielectric layer and may be a silicon dioxide layer.

[0065] Emitter metal 300 is disposed on the side of insulating layer 200 away from second primary surface 102 and in contact hole 210. Emitter metal 300 contacts second emitter region 170, forming a conductive connection. Collector metal 400 is disposed on first primary surface 101, contacting collector region 120, forming a conductive connection. Emitter metal 300 and collector metal 400 are used to electrically connect second emitter region 170 and collector region 120, respectively.

[0066] Furthermore, the dummy gate 160 includes a first gate trench extending from the second main surface 102 toward the first main surface 101 to the first stud region 111, a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench. The active gate 130 includes a second gate trench extending from the second main surface 102 toward the first main surface 101 to the second stud region 112, a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench.

[0067] The first polysilicon gate contacts the emitter metal 300 (the specific contact position is not shown in the figure), that is, the virtual gate 160 is short-circuited with the emitter. By short-circuiting the virtual gate 160 with the emitter, the virtual gate 160 can have the same properties as the emitter, that is, negatively charged. When a large number of holes pass through the second column region 112 and the body region 140, some holes can be attracted to transfer to the virtual gate 160 (such as Figure 2 As shown in D in the figure, the number of holes flowing under the first emitter is reduced, that is, the number of holes flowing in the channel is reduced, thereby reducing the risk of latch-up effect under high current conditions.

[0068] In some other embodiments, the first polysilicon gate in the dummy gate 160 may be a floating gate, that is, a gate that is not directly electrically connected to an external circuit. Surrounded by insulating layers (i.e., the first gate dielectric layer and the insulating layer 200), the first polysilicon gate is in a "floating" state and is not directly connected to a fixed potential point such as a power supply or ground.

[0069] Further, see Appendix Figure 1The IGBT structure further includes doped regions 180 of the second conductivity type. The doped regions 180 are located on both sides of the dummy gate 160 in the horizontal direction and are in contact with the first emitter region 150. The side of the doped regions 180 away from the first main surface 101 constitutes at least a portion of the second main surface 102. Specifically, in this embodiment, the body region 140 is provided on the side of the second pillar region 112 facing the second main surface 102 and is located on both sides of the active gate 130 in the horizontal direction. The portion of the first pillar 11 on the side of the dummy gate 160 facing the active gate 130 also serves to implement the function of the body region 140. The doped regions 180 located on the side of the dummy gate 160 facing the active gate 130 are in contact with the first emitter region 150 and serve to implement the function of the first emitter region 150. The doped regions 180 located on the side of the dummy gate 160 away from the active gate 130 can act as a barrier, limiting the movement of holes and thereby enhancing the carrier storage effect. In this embodiment, the doped region 180 located on the side of the dummy gate 160 facing the active gate 130 may also be in contact with the second emitter region 170 .

[0070] In some other embodiments, the first emitter region 150 may be provided only on both sides of the active gate 130 , without providing the doped region 180 on both sides of the dummy gate 160 , and the side of the first column region 111 away from the first main surface 101 constitutes part of the second main surface 102 .

[0071] Further, see Appendix Figure 1 The IGBT structure also includes a field stop region 190 of the second conductivity type. The field stop region 190 is arranged between the collector region 120 and the drift region 110. The doping concentration of the field stop region 190 is higher than the doping concentration of the drift region 110. The main function of the field stop region 190 is to terminate the electric field when the IGBT is in the off state, preventing the electric field from penetrating into the collector region 120, thereby improving the voltage withstand capability of the device. When a high voltage is applied, the field stop region 190 can withstand a part of the electric field, so that the electric field gradually weakens before reaching the collector region 120, avoiding the breakdown of the collector region 120. The field stop region 190 can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce the turn-off loss.

[0072] Please refer to the attached Figure 3-9 Attachment Figure 1 The manufacturing method of the semiconductor device shown in FIG. 1 is exemplarily described.

[0073] First, see the attached Figure 3 , providing a substrate 10 of a second conductivity type.

[0074] Then, see the attached Figure 4, first pillars 11 and second pillars 12 are alternately formed on substrate 10. First pillars 11 and second pillars 12 are of a first conductivity type and a second conductivity type, respectively. Specifically, trenches can be etched on substrate 10 at locations corresponding to first pillars 11, and the trenches are then filled with a material of the first conductivity type to form first pillars 11. The remaining substrate 10 after etching forms second pillars 12.

[0075] Then, see the attached Figure 5 A first gate trench and a second gate trench are etched on the first pillar 11 and the second pillar 12 respectively.

[0076] Then, see the attached Figure 6 , a dummy gate 160 and an active gate 130 are respectively formed in the first gate trench 13 and the second gate trench 14. Specifically, a first gate oxide layer and a second gate oxide layer can be respectively formed on the inner surfaces of the first gate trench 13 and the second gate trench 14 by a thermal oxidation process, and then polysilicon is respectively deposited in the first gate trench 13 and the second gate trench 14 to form a first polysilicon gate and a second polysilicon gate.

[0077] Then, see the attached Figure 7 First, dopant ions of the first conductivity type are implanted on both sides of the active gate 130 above the second pillar 12 to form a first doped region. Then, dopant ions of the second conductivity type are implanted above the first doped region and on both sides of the dummy gate 160 above the first pillar 11 to form a second doped region 15. The portions of the first pillar 11 and the second pillar 12 that are not implanted with dopant ions are the first pillar region 111 and the second pillar region 112, respectively. The portion of the first doped region between the second pillar region 112 and the second doped region 15 is the body region 140. The portion of the first pillar region 111 facing the active gate 130 also functions as the body region 140.

[0078] Then, see the attached Figure 8 An insulating layer 200 is formed on the first emitter region 150, the active gate 130 and the dummy gate 160, and a contact hole 210 is etched in the insulating layer 200. Then, dopant ions of the first conductive type are implanted in the contact hole 210 to form a second emitter region 170 in the second doping region 15. The portions of the second doping region 15 on both sides of the active gate 130 that have not been implanted with dopant ions constitute the first emitter region 150, and the portions of the second doping region 15 on both sides of the dummy gate 160 that have not been implanted with dopant ions constitute the doping region 180.

[0079] Then, see the attached Figure 9Metal is deposited on the insulating layer 200 and in the contact hole 210 to form an emitter metal 300. A field stop region 190, a collector region 120, and a collector metal 400 are sequentially formed under the first and second stud regions 111 and 112.

[0080] The present application also provides a semiconductor device, which includes the above-mentioned IGBT structure. The semiconductor device may be a power semiconductor device.

[0081] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present application. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units described is merely a logical function division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not performing some features.

[0083] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0084] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach of the present application should not be interpreted as reflecting the intention that the application claimed for protection requires more features than those explicitly recited in each claim. More precisely, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present application.

[0085] Those skilled in the art will understand that, except where mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus disclosed herein may be combined in any combination. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0086] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

[0087] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. An IGBT structure, characterized in that: include: A substrate (100), the substrate (100) having a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), the first main surface (101) and the second main surface (102) being spaced apart in a vertical direction; a drift region (110), the drift region (110) being provided between the first main surface (101) and the second main surface (102); a collector region (120) of a first conductivity type, the collector region (120) being provided on a side of the drift region (110) facing the first main surface (101), and a side of the collector region (120) away from the drift region (110) constituting at least a portion of the first main surface (101); an active gate (130), the active gate (130) extending from the second main surface (102) toward the first main surface (101) into the drift region (110); a body region (140) of a first conductive type, the body region (140) being provided on a side of the drift region (110) facing the second main surface (102) and being located on both sides of the active gate (130) in a horizontal direction; a first emission region (150) of a second conductivity type, the first emission region (150) being arranged on a side of the body region (140) facing the second main surface (102), and a side of the first emission region (150) away from the body region (140) constituting a portion of the second main surface (102); a virtual gate (160), the virtual gate (160) extending from the second main surface (102) toward the first main surface (101) into the drift region (110); The drift region (110) comprises a first column region (111) of a first conductive type and a second column region (112) of a second conductive type, and the first column region (111) and the second column region (112) are alternately arranged in a horizontal direction; One end of the active gate (130) facing the first main surface (101) extends into the second column region (112), and one end of the dummy gate (160) facing the first main surface (101) extends into the first column region (111); The IGBT structure further includes a doped region (180) of a second conductive type, the doped region (180) being located on both sides of the virtual gate (160) in the horizontal direction and in contact with the first emitter region (150), and the side of the doped region (180) away from the first main surface (101) constituting at least a portion of the second main surface (102).

2. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a second emitter region (170) of the first conductivity type, wherein the second emitter region (170) is arranged in the first emitter region (150), and a side of the second emitter region (170) away from the first main surface (101) constitutes at least a portion of the second main surface (102).

3. The IGBT structure according to claim 2, characterized in that: The IGBT structure further includes: an insulating layer (200), the insulating layer (200) being provided on the second main surface (102), and a contact hole (210) being provided in a portion of the insulating layer (200) corresponding to the second emission region (170); an emitter metal (300), the emitter metal (300) being arranged on a side of the insulating layer (200) away from the second main surface (102) and in the contact hole (210), the emitter metal (300) being in contact with the second emitter region (170); A collector metal (400), wherein the collector metal (400) is provided on the first main surface (101).

4. The IGBT structure according to claim 3, characterized in that: The virtual gate (160) comprises a first gate trench extending from the second main surface (102) to the first main surface (101) to the first column region (111), a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench; The first polysilicon gate is in contact with the emitter metal (300).

5. The IGBT structure according to claim 1, wherein: The virtual gate (160) comprises a first gate trench extending from the second main surface (102) to the first main surface (101) to the first column region (111), a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench; The virtual gate (160) is a floating gate.

6. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a field stop region (190) of a second conductive type, wherein the field stop region (190) is provided between the collector region (120) and the drift region (110).

7. The IGBT structure according to claim 1, characterized in that: The active gate (130) comprises a second gate trench extending from the second main surface (102) to the first main surface (101) to the second column region (112), a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench.

8. The IGBT structure according to any one of claims 1 to 7, characterized in that: The first conductivity type is P type; The second conductivity type is N type.

9. A semiconductor device, characterized in that: The invention comprises the IGBT structure according to any one of claims 1 to 8.

Images