A method for manufacturing a trench gate silicon carbide VDMOS with low on-resistance

Abstract

The application provides a preparation method of a trench gate silicon carbide VDMOS with low on-resistance, which comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, etching, ion implanting to form a freewheeling region and a P-type source region; re-forming the barrier layer, etching, ion implanting to form a P-type well region, a mask layer and an N-type source region; re-forming the barrier layer, etching to form a groove, then oxidizing to form a gate dielectric layer, wherein a trench is arranged in the gate dielectric layer; re-forming the barrier layer, etching the barrier layer to form a via, depositing metal to form a gate metal layer; re-forming the barrier layer, etching the barrier layer to form a via, etching the drift layer, depositing metal to form a source metal layer, removing the barrier layer, and completing the preparation; and the device can effectively reduce the on-resistance of the device, reduce the on-resistance loss of the body diode of the device, and improve the switching speed of the device.

Description

Technical Field

[0001] The invention relates to a method for preparing a trench gate silicon carbide VDMOS with low on-resistance. Background Art

[0002] Silicon carbide MOSFETs are a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. Different fields have different performance requirements for silicon carbide power MOSFETs, but overall, they require lower on-resistance, faster switching speeds, higher reliability (including gate reliability and drain voltage surge reliability), and lower body diode conduction losses. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method for preparing a trench gate silicon carbide VDMOS with low on-resistance, which can effectively reduce the on-resistance of the device, reduce the body diode conduction loss of the device, and improve the switching speed of the device.

[0004] The present invention is achieved as follows: a method for preparing a low on-resistance trench gate silicon carbide VDMOS comprises the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a freewheeling region;

[0007] Step 3: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type source region;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the freewheeling region to form a P-type well region;

[0009] Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the freewheeling region to form a masking layer;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the freewheeling region to form an N-type source region;

[0011] Step 7: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the freewheeling region to form a groove, and then oxidizing to form a gate dielectric layer with a trench provided therein;

[0012] Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and deposit metal to form a gate metal layer;

[0013] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] The advantages of the present invention are:

[0015] 1. The present invention adopts a trench gate structure to construct a freewheeling region in the conductive channel of the device, thereby reducing the on-resistance below the P-type well region of the device and directly below the gate metal layer. While reducing the on-resistance, it also directs the current from the left and right sides of the trench gate to flow below the gate metal layer, thus avoiding current concentration in the device.

[0016] Second, the present invention constructs two body diode paths. One is that the source metal layer of the device directly contacts the P-type source region to form an ohmic contact. The P-type source region and the N-type drift layer form a silicon carbide pn junction with a conduction voltage drop of about 2.5V. The other is that the source metal layer of the device and the N-type freewheeling region form a Schottky junction, forming a Schottky diode with a conduction voltage drop of about 1.2V. In traditional devices, only the silicon carbide pn junction has a large conduction voltage drop, and the body diode freewheeling loss is large.

[0017] 3. A shielding layer was constructed for the device to protect the gate corners of the device from being broken down by concentrated electric fields, thereby improving the reliability of the device gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1 The present invention is a flow chart of a method for preparing a trench gate silicon carbide VDMOS with low on-resistance.

[0020] Figure 2 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0021] Figure 3 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0022] Figure 4 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0023] Figure 5 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0024] Figure 6 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0025] Figure 7 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0026] Figure 8 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0027] Figure 9 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0028] Figure 10 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0029] Figure 11 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0030] Figure 12 This is a cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0031] Figure 13 This is a schematic diagram of a low on-resistance trench gate silicon carbide VDMOS according to the present invention. DETAILED DESCRIPTION

[0032] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0035] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0036] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a trench gate silicon carbide VDMOS with low on-resistance, comprising the following steps:

[0038] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8, and epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0039] Step 2: forming a barrier layer a above the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a freewheeling region 4, with an ion implantation energy of 100-400 keV;

[0040] Step 3: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the drift layer 2 to form a P-type source region 3. The ion implantation energy is 100-400 keV.

[0041] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the freewheeling region 4 to form a P-type well region 43. The ion implantation energy is 200-300 keV.

[0042] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the freewheeling region 4 to form a masking layer 42. The ion implantation energy is 300-370keV.

[0043] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the freewheeling region 4 to form an N-type source region 44. The ion implantation energy is 100-200 keV.

[0044] Step 7: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 2 and the freewheeling region 4 to form a groove 41, and then oxidize to form a gate dielectric layer 5, wherein the gate dielectric layer 5 has a trench 51;

[0045] Step 8: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and deposit metal to form a gate metal layer 6;

[0046] Step 9: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 2, deposit metal to form a source metal layer 7, remove the barrier layer a, and complete the preparation.

[0047] like Figure 13 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0048] Silicon carbide substrate 1,

[0049] a drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0050] A P-type source region 3, wherein the lower side of the P-type source region 3 is connected to the upper side of the drift layer 2;

[0051] A freewheeling region 4, wherein the lower side of the freewheeling region 4 is connected to the upper side of the drift layer 2, and the outer side of the freewheeling region 4 is connected to the inner side of the P-type source region 3; a groove 41 is provided in the freewheeling region 4, and a masking layer 42 is provided at the bottom of the groove 41; a P-type well region 43 and an N-type source region 44 are provided in the freewheeling region 4, and the upper side of the P-type well region 43 is connected to the lower side of the N-type source region 44;

[0052] a gate dielectric layer 5, wherein the lower portion of the gate dielectric layer 5 is disposed within the recess 41, the outer sides of the gate dielectric layer 5 are connected to the N-type source region 44 and the P-type well region 43, respectively, and the lower side of the gate dielectric layer 5 is connected to the upper side of the masking layer 42; and a trench 51 is provided on the gate dielectric layer 5;

[0053] a gate metal layer 6 disposed in the trench 51;

[0054] A source metal layer 7, the source metal layer 7 is respectively connected to the P-type source region 3, the freewheeling region 4 and the N-type source region 44;

[0055] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0056] The silicon carbide substrate 1, the drift layer 2 and the freewheeling region 4 are all N-type; the masking layer 42 is P-type, and the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 1e16cm -3 The doping concentration of the freewheeling region 4 is 1e17 cm -3 The doping concentration of the masking layer 42 is 1e18cm -3 The doping concentration of the P-type well region 43 is 5e17cm -3 The doping concentration of the N-type source region 44 is 2e18cm -3 The doping concentration of the P-type source region 3 is 1e19cm -3 The concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the N-type freewheeling region 4 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 7; the P-type shielding layer 42 is to suppress the electric field concentration at the gate corner of the device and suppress the influence of the drain voltage shock on the device gate; the doping concentration of the N-type source region 44 and the P-type source region 3 is to form an ohmic contact with the source metal layer 7 and reduce the contact resistance.

[0057] The thickness of the N-type silicon carbide substrate 1 of the present invention is 1 μm, and the thickness of the N-type drift layer 2 is 15-25 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the P-type well region 43 is 300 nm. The N-type freewheeling region 4 in the area below the P-type shielding layer 42 can effectively shield the capacitance effect of the gate to the drain, reduce the gate-drain charge of the device, and improve the switching speed of the device. The thickness of the P-type shielding layer 42 is 200 nm, which is to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the gate corner. The sidewall thickness of the gate dielectric layer 5 is 50 nm, the thickness of the P-type source region 3 is 900 nm, the thickness of the N-type source region 44 is 250 nm, and the thickness of the P-type well region 43 is 300 nm; the distance between the lower side of the shielding layer 42 and the upper side of the drift layer 2 is 100 nm.

[0058] The present invention adopts a trench gate structure and constructs an N-type freewheeling region 4 in the conductive channels on the left and right sides of the device, thereby reducing the on-resistance below the P-type well region 43 of the device and directly below the gate. While reducing the on-resistance, it also directs the current from the left and right sides of the device trench gate to flow below the device gate, thus avoiding current concentration in the device.

[0059] The present invention constructs two body diode paths. One is that the device source metal layer 7 directly contacts the P-type source region 3 to form an ohmic contact. The P-type source region 3 and the N-type drift layer 2 constitute a silicon carbide pn junction with a conduction voltage drop of about 2.5V. The other is that the device source metal layer 7 and the N-type freewheeling region 4 constitute a Schottky junction, forming a Schottky diode with a conduction voltage drop of about 1.2V. In traditional devices, only the silicon carbide pn junction has a large conduction voltage drop, and the body diode freewheeling loss is large.

[0060] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a low on-resistance trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a freewheeling region; Step 3: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation into the drift layer to form a P-type source region, and connect the outer side of the freewheeling region to the inner side of the P-type source region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the freewheeling region to form a P-type well region; Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the freewheeling region to form a masking layer; Step 6: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation into the freewheeling region to form an N-type source region, and connect the upper side of the P-type well region to the lower side of the N-type source region; Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer and the freewheeling region to form a groove, the groove is located in the freewheeling region, and then oxidize to form a gate dielectric layer, the gate dielectric layer is provided with a trench, the lower portion of the gate dielectric layer is located in the groove, the outer side of the gate dielectric layer is connected to the N-type source region and the P-type well region, and the lower side of the gate dielectric layer is connected to the upper side of the masking layer; Step 8: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal to form a gate metal layer, and the gate metal layer is arranged in the trench; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation; The silicon carbide substrate, drift layer and freewheeling region are all N-type; The masking layer is of P type.

2. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, wherein: The doping concentration of the silicon carbide substrate is 2e18cm -3 The doping concentration of the drift layer is 1e16cm -3 The doping concentration of the freewheeling region is 1e17 cm -3 The doping concentration of the masking layer is 1e18cm -3 The doping concentration of the P-type well region is 5e17 cm -3 The doping concentration of the N-type source region is 2e18cm -3 The doping concentration of the P-type source region is 1e19cm -3 .

3. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, wherein: The thickness of the P-type source region is equal to the thickness of the freewheeling region.

4. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, wherein: The thickness of the masking layer is 200 nm.

5. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, wherein: The distance between the lower side of the masking layer and the upper side of the drift layer is 100 nm.

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