Imaging device and light detection device

Abstract

An imaging device according to an embodiment of the present disclosure includes: a light receiving pixel configured to generate a pixel signal including a pixel voltage corresponding to a received amount of light; a first connection terminal connected to the first external capacitor; a first voltage generation circuit configured to generate a voltage at the first connection terminal; a driving circuit configured to drive the light receiving pixel based on a voltage at the first connection terminal; a reference signal generation circuit configured to generate a reference signal having a ramp waveform; a noise correction circuit configured to generate a noise correction signal corresponding to a voltage at the first connection terminal, and configured to superimpose the noise correction signal on the reference signal; a comparison circuit configured to compare between the pixel signal and the reference signal on which the noise correction signal is superimposed; and a processing circuit configured to calculate a pixel value based on a comparison result of the comparison circuit.

Description

Technical Field

[0001] The present disclosure relates to an imaging device that captures a subject image and a light detection device that detects light. Background Art

[0002] For example, in an imaging device, the image quality of a captured image may be degraded due to various noises. Patent Document 1 discloses a technology in which a noise correction circuit is provided to reduce the degradation of image quality caused by power supply noise.

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. WO2017 / 159394 Summary of the invention

[0006] By the way, in imaging devices and light detection devices, various voltages are generated. These voltages are usually stabilized by external capacitors. Noise can even be superimposed on these voltages. Therefore, it is desirable to reduce the influence of noise on imaging results and detection results.

[0007] It is desirable to provide an imaging device and a light detecting device that enable the influence of noise to be reduced.

[0008] An imaging device according to an embodiment of the present disclosure includes a light receiving pixel, a first connection terminal, a first voltage generating circuit, a driving circuit, a reference signal generating circuit, a noise correction circuit, a comparison circuit, and a processing circuit. The light receiving pixel is configured to generate a pixel signal including a pixel voltage corresponding to the amount of light received. The first connection terminal is connected to a first external capacitor. The first voltage generating circuit is configured to generate a voltage at the first connection terminal. The driving circuit is configured to drive the light receiving pixel based on the voltage at the first connection terminal. The reference signal generating circuit is configured to generate a reference signal having a ramp waveform. The noise correction circuit is configured to generate a noise correction signal corresponding to the voltage at the first connection terminal, and is configured to superimpose the noise correction signal on the reference signal. The comparison circuit is configured to compare between the pixel signal and the reference signal superimposed with the noise correction signal. The processing circuit is configured to calculate a pixel value based on the comparison result of the comparison circuit.

[0009] According to an embodiment of the present disclosure, a light detection device includes a light receiving circuit, a first connection terminal, a first voltage generating circuit, a driving circuit, a reference signal generating circuit, a noise correction circuit, a comparison circuit, and a processing circuit. The light receiving circuit is configured to generate a detection signal including a voltage corresponding to the amount of light received. The first connection terminal is connected to a first external capacitor. The first voltage generating circuit is configured to generate a voltage at the first connection terminal. The driving circuit is configured to drive the light receiving circuit based on the voltage at the first connection terminal. The reference signal generating circuit is configured to generate a reference signal having a ramp waveform. The noise correction circuit is configured to generate a noise correction signal corresponding to the voltage at the first connection terminal, and is configured to superimpose the noise correction signal on the reference signal. The comparison circuit is configured to compare between the detection signal and the reference signal superimposed with the noise correction signal. The processing circuit is configured to calculate a detection value based on the comparison result of the comparison circuit.

[0010] In an imaging device according to an embodiment of the present disclosure, the light receiving pixel generates a pixel signal including a pixel voltage corresponding to the amount of light received. A first voltage generating circuit generates a voltage at a first connection terminal, and the first connection terminal is connected to a first external capacitor. The driving circuit drives the light receiving pixel based on the voltage at the first connection terminal. The reference signal generating circuit generates a reference signal having a ramp waveform. The noise correction circuit generates a noise correction signal corresponding to the voltage at the first connection terminal, and superimposes the noise correction signal on the reference signal. The comparison circuit compares the pixel signal and the reference signal superimposed with the noise correction signal. Thereafter, the processing circuit calculates a pixel value based on the comparison result of the comparison circuit.

[0011] In a light detection device according to an embodiment of the present disclosure, the light receiving circuit generates a pixel signal including a voltage corresponding to the amount of light received. A first voltage generating circuit generates a voltage at a first connection terminal, and the first connection terminal is connected to a first external capacitor. The driving circuit drives the light receiving circuit based on the voltage at the first connection terminal. The reference signal generating circuit generates a reference signal having a ramp waveform. The noise correction circuit generates a noise correction signal corresponding to the voltage at the first connection terminal, and superimposes the noise correction signal on the reference signal. The comparison circuit compares the detection signal and the reference signal superimposed with the noise correction signal. Thereafter, the processing circuit calculates a detection value based on the comparison result of the comparison circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 A circuit diagram of an example configuration of a light receiving pixel shown.

[0014] Figure 3 It is shown Figure 1 An explanatory diagram of an example of arrangement of light receiving pixels in a pixel array shown.

[0015] Figure 4 It is shown Figure 1 A block diagram of an example configuration of a readout unit is shown.

[0016] Figure 5 It is shown Figure 1 A block diagram of a specific example of a noise correction unit shown in FIG.

[0017] Figure 6 It is shown Figure 5 A circuit diagram of a specific example of a noise correction unit shown in FIG.

[0018] Fig. 7A It is shown Figure 6 1 is an explanatory diagram of an operation example of the noise correction unit shown.

[0019] Figure 7B It is shown Figure 6 FIG. 2 is an explanatory diagram of another operation example of the noise correction unit shown in FIG.

[0020] Figure 7C It is shown Figure 6 FIG. 2 is an explanatory diagram of another operation example of the noise correction unit shown in FIG.

[0021] Figure 8 It is shown Figure 1 A timing chart showing an operation example of the imaging device shown.

[0022] Fig. 9 It is shown Figure 1 A timing waveform diagram of an operation example of the imaging device shown.

[0023] Fig. 10A is an explanatory diagram showing an example of noise correction according to the first embodiment.

[0024] Fig. 10B is another explanatory diagram showing an example of noise correction according to the first embodiment.

[0025] Fig.11 It is shown Figure 1 A characteristic diagram showing an example of characteristics of the noise removal ratio in the imaging device shown.

[0026] Fig.12is another explanatory diagram showing an example of noise correction according to the first embodiment.

[0027] Fig.13 is a block diagram showing a configuration example of an imaging device according to the second embodiment.

[0028] Fig.14 It is shown Fig.13 A circuit diagram of an example configuration of a light receiving pixel shown.

[0029] Fig.15 It is shown Fig.13 An explanatory diagram of an example of arrangement of light receiving pixels in a pixel array shown.

[0030] Fig.16 It is shown Fig.13 A block diagram of a specific example of a noise correction unit shown in FIG.

[0031] Fig.17 It is shown Fig.13 A timing waveform diagram of an operation example of the imaging device shown.

[0032] Fig.18A It is shown Fig.13 Another timing waveform diagram of the operation example of the imaging device shown.

[0033] Fig.18B It is shown Fig.13 Another timing waveform diagram of the operation example of the imaging device shown.

[0034] Fig.19A It is shown Fig.14 An explanatory diagram of an example of an operating state of a light-receiving pixel shown.

[0035] Fig.19B It is shown Fig.14 FIG. 2 is an explanatory diagram of another example of the operating state of the light receiving pixel shown.

[0036] Fig.19C It is shown Fig.14 FIG. 2 is an explanatory diagram of another example of the operating state of the light receiving pixel shown.

[0037] Fig. 20 It is shown Fig.13 An explanatory diagram of an operation example of the signal processing unit shown.

[0038] Fig.21 : is a block diagram showing a specific example of a noise correction section according to a modification of the second embodiment.

[0039] Fig. 22 It is shown Fig.21 A circuit diagram of a specific example of a noise correction unit shown in FIG.

[0040] Fig.23 is a timing waveform chart showing an operation example of the imaging device according to the modification example of the second embodiment.

[0041] Fig.24 : is a block diagram showing a specific example of a noise correction unit according to another modification of the second embodiment.

[0042] Fig.25 It is shown Fig.24 A circuit diagram of a specific example of a noise correction unit shown in FIG.

[0043] Fig.26 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0044] Fig. 27 1 is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging portion.

[0045] Fig.28 This is a block diagram showing a configuration example of a distance measuring device to which the present technology is applied. DETAILED DESCRIPTION

[0046] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the description is given in the following order.

[0047] 1. First Implementation Method

[0048] 2. Second Implementation Method

[0049] 3. Application examples for mobile objects

[0050] <1. First Implementation Method>

[0051] [Configuration example]

[0052] Figure 1 The imaging device 1 includes a pixel array 11, a drive unit 12, a readout unit 20, a charge pump 14, a noise correction unit 15, a reference signal generation unit 16, a signal processing unit 17, and an imaging control unit 18.

[0053] The pixel array 11 includes a plurality of light-receiving pixels P arranged in a matrix shape. The light-receiving pixels P are configured to generate a pixel signal SIG including a pixel voltage Vpix corresponding to the amount of received light.

[0054] Figure 2 FIG. 1 shows an example of the structure of a light receiving pixel P. The pixel array 11 includes a plurality of control lines TRGL, a plurality of control lines RSTL, a plurality of control lines SELL, and a plurality of signal lines VSL. The control line TRGL is arranged in the horizontal direction ( Figure 2The control line SELL extends in the horizontal direction and one end is connected to the drive section 12. The drive section 12 supplies the control signal SSEL to the control line SELL. The signal line VSL extends in the vertical direction ( Figure 2 The signal line VSL extends in the longitudinal direction (in the longitudinal direction) and one end is connected to the readout section 20. The signal line VSL transmits the pixel signal SIG generated by the light receiving pixel P to the readout section 20. Figure 1 and Figure 2 A plurality of light receiving pixels P arranged side by side in a row (in the lateral direction) constitute a pixel line L.

[0055] The light receiving pixel P includes a photodiode PD, a transistor TRG, a floating diffusion FD, and transistors RST, AMP, and SEL. In this example, the transistors TRG, RST, AMP, and SEL are N-type metal oxide semiconductor (MOS) transistors.

[0056] The photodiode PD is a photoelectric conversion element that generates an amount of charge corresponding to the amount of received light and accumulates the generated charge therein. The anode of the photodiode PD is grounded, and the cathode is connected to the source of the transistor TRG.

[0057] The transistor TRG has a gate connected to the control line TRGL, a source connected to the cathode of the photodiode PD, and a drain connected to the floating diffusion FD.

[0058] The floating diffusion FD is configured to accumulate charges transferred from the photodiode PD via the transistor TRG. For example, the floating diffusion FD is configured using a diffusion layer formed on the surface of the semiconductor substrate. Figure 2 In FIG. 1 , the floating diffusion FD is represented by the symbol of a capacitor.

[0059] The transistor RST has a gate connected to the control line RSTL, a drain connected to a power supply node of a power supply voltage VDDH, and a source connected to the floating diffusion FD.

[0060] The transistor AMP has a gate connected to the floating diffusion FD, a drain connected to a power supply node of a power supply voltage VDDH, and a source connected to the drain of the transistor SEL.

[0061] The gate of the transistor SEL is connected to the control line SELL, the drain is connected to the source of the transistor AMP, and the source is connected to the signal line VSL.

[0062] By this configuration, in the light receiving pixel P, for example, based on the control signals STRG and SRST, the transistors TRG and RST are turned on, thereby discharging the charge accumulated in the photodiode PD to the power supply node of the power supply voltage VDDH. Thereafter, the exposure period T is started by turning off the transistors TRG and RST, and the charge corresponding to the amount of light received is accumulated in the photodiode PD. Thereafter, after the exposure period T ends, the light receiving pixel P outputs a pixel signal SIG including a reset voltage Vreset and a pixel voltage Vpix to the signal line VSL. Specifically, first, the light receiving pixel P is electrically connected to the signal line VSL by turning on the transistor SEL based on the control signal SSEL. As a result, the transistor AMP is connected to the constant current source 21 (described later) of the readout section 20 and operates as a so-called source follower. Thereafter, as described later, during the P phase (pre-charge phase) period TP after the voltage of the floating diffusion section FD is reset by turning on the transistor RST, the light receiving pixel P outputs a voltage corresponding to the voltage of the floating diffusion section FD at that time as the reset voltage Vreset. In addition, in the D phase (data phase) period TD after the charge is transferred from the photodiode PD to the floating diffusion FD through the turn-on transistor TRG, the light receiving pixel P outputs a voltage corresponding to the voltage of the floating diffusion FD at that time as the pixel voltage Vpix. The difference voltage between the pixel voltage Vpix and the reset voltage Vreset corresponds to the amount of light received by the light receiving pixel P in the exposure period T. In this way, the light receiving pixel P outputs a pixel signal SIG including the reset voltage Vreset and the pixel voltage Vpex to the signal line VSL.

[0063] Figure 3 An example of the configuration of the pixel array 11 is shown. In the pixel array 11, a unit pixel PP including four light receiving pixels P (light receiving pixels PR, PGr, PGb, PB) is arranged side by side. The pixel PR includes a red (R) color filter and is configured to receive red light. The light receiving pixels PGr and PGb each include a green (G) color filter and are configured to receive green light. The light receiving pixel PB includes a blue (B) color filter and is configured to receive blue light. In the unit pixel PP, the light receiving pixel PR is arranged in the upper left corner, the light receiving pixel PGr is arranged in the upper right corner, the light receiving pixel PGb is arranged in the lower left corner, and the light receiving pixel PB is arranged in the lower right corner. In this way, the four pixels PR, PGr, PGb and PB are configured in a so-called Bayer arrangement.

[0064] Driving unit 12( Figure 1) is configured to sequentially drive the plurality of light-receiving pixels P in the pixel array 11 in units of pixel lines L based on an instruction from the imaging control section 18. Specifically, the driving section 12 supplies a plurality of control signals STRG to a plurality of control lines TRGL in the pixel array 11, supplies a plurality of control signals SRST to a plurality of control lines RSTL in the pixel array 11, and supplies a plurality of control signals SSEL to a plurality of control lines SELL in the pixel array 11, thereby driving the plurality of light-receiving pixels P in the pixel array 11 in units of pixel lines L. The driving section 12 is supplied with a voltage VRL generated by the charge pump 14. The driving section 12 drives the plurality of light-receiving pixels P using the voltage VRL as a low-level voltage of each of the control signals STRG, SRST, and SSEL.

[0065] The readout section 20 is configured to generate image data DT0 by performing AD conversion based on the pixel signal SIG supplied from the pixel array 11 via the signal line VSL based on an instruction from the imaging control section 18 .

[0066] Figure 4 FIG. 2 shows an example of the configuration of the readout section 20. Note that, in addition to the readout section 20, Figure 4 A noise correction section 15, a reference signal generation section 16, a signal processing section 17, and an imaging control section 18 are also shown. The readout section 20 includes a plurality of constant current sources 21, a plurality of analog-to-digital (AD) converters ADC, and a transmission control section 27. The plurality of constant current sources 21 and the plurality of AD converters ADC are respectively provided corresponding to the plurality of signal lines VSL. The constant current source 21 and the AD converter ADC corresponding to a certain signal line VSL are described below.

[0067] The constant current source 21 is configured to flow a predetermined current through the corresponding signal line VSL. One end of the constant current source 21 is connected to the corresponding signal line VSL, and the other end is connected to the ground node.

[0068] The AD converter ADC is configured to perform AD conversion based on the pixel signal SIG in the corresponding signal line VSL. The AD converter ADC includes capacitors 22 and 23 , a comparison circuit 24 , a counter 25 , and a latch 26 .

[0069] One end of the capacitor 22 is connected to the signal line VSL and supplied with the signal SIG, and the other end is connected to the comparison circuit 24. One end of the capacitor 23 is supplied with the reference signal RAMP supplied from the reference signal generating section 16, and the other end is connected to the comparison circuit 24. The reference signal RAMP is a signal having a so-called ramp waveform whose voltage level gradually changes with time.

[0070] The comparison circuit 24 is configured to generate a signal CP by performing a comparison operation based on the pixel signal SIG supplied from the light receiving pixel P via the signal line VSL and the capacitor 22 and the reference signal RAMP supplied from the reference signal generating section 16 via the capacitor 23. The comparison circuit 24 sets an operation point by setting the voltages of the capacitors 22 and 23 based on the control signal AZSW supplied from the imaging control section 18. Thereafter, the comparison circuit 24 performs a comparison operation in the P phase period TP to perform a comparison between the reset voltage Vreset included in the pixel signal SIG and the voltage of the reference signal RAMP, and performs a comparison operation in the D phase period TD to perform a comparison between the pixel voltage Vpix included in the pixel signal SIG and the voltage of the reference signal RAMP.

[0071] The counter 25 is configured to perform a counting operation based on the signal CP supplied from the comparison circuit 24 to count the pulses of the clock signal CLK supplied from the imaging control section 18. Specifically, the counter 25 generates a count value CNT by counting down the pulses of the clock signal CLK in the P phase period TP until the signal CP transitions and counting up the pulses of the clock signal CLK in the D phase period TD until the signal CP transitions. Thereafter, the counter 25 outputs the count value CNT as a digital code having a plurality of bits.

[0072] The latch 26 is configured to temporarily hold the digital code supplied from the counter 25 , and output the digital code to the bus wiring BUS based on an instruction from the transmission control section 27 .

[0073] The transmission control section 27 is configured to control the latches 26 of the plurality of AD converters ADC so as to sequentially output digital codes to the bus wiring BUS based on the control signal CTL supplied from the imaging control section 18. The readout section 20 sequentially transmits the plurality of digital codes supplied from the plurality of AD converters ADC as image data DT0 to the signal processing section 17 using the bus wiring BUS.

[0074] Charge pump 14( Figure 1 ) is configured to generate a voltage VRL by performing a predetermined pump operation. The charge pump 14 is connected to the capacitor Cext1 via the terminal TVRL. The capacitor Cext1 is provided outside the imaging device 1. In this example, the voltage VRL is a voltage lower than the ground voltage. The charge pump 14 generates the voltage VRL by charging and discharging the capacitor Cext1.

[0075] The noise correction section 15 is configured to generate a noise correction signal corresponding to the noise superimposed on the power supply voltage VDDH and a noise correction signal corresponding to the noise superimposed on the voltage VRL based on an instruction from the imaging control section 18, and superimpose these noise correction signals on the reference signal RAMP generated by the reference signal generation section 16. The power supply voltage VDDH is supplied to the imaging device 1 via the power supply terminal TVDDH. The voltage VRL is generated by charging and discharging the capacitor Cext1 provided outside the imaging device 1 by the charge pump 14. Therefore, for example, noise caused by the external environment may be superimposed on the power supply voltage VDDH and the voltage VRL. The noise correction section 15 generates a noise correction signal corresponding to the noise, and superimposes the generated noise correction signal on the reference signal RAMP generated by the reference signal generation section 16.

[0076] The reference signal generating section 16 is configured to generate a reference signal RAMP based on an instruction from the imaging control section 18. The reference signal RAMP has a so-called ramp waveform whose voltage level gradually changes over time in two periods (P phase period TP and D phase period TD) during which the readout section 20 performs AD conversion. The reference signal generating section 16 supplies such a reference signal RAMP to the readout section 20.

[0077] Figure 5 FIG. 1 shows an example of the configuration of the driving unit 12, the noise correction unit 15, and the reference signal generating unit 16. Note that, in addition to the driving unit 12, the noise correction unit 15, and the reference signal generating unit 16, Figure 5 Also shown are the light receiving pixels P, the charge pump 14 and the readout section 20.

[0078] The driving section 12 includes a signal generating circuit 31 and a driver section 32. For example, the signal generating circuit 31 is configured using a shift register, and is configured to generate a plurality of control signals as a source of a plurality of control signals STRG, a plurality of control signals as a source of a plurality of control signals SRST, and a plurality of control signals as a source of a plurality of control signals SSEL. The driver section 32 includes a plurality of drivers. The driver section 32 is configured to generate a plurality of control signals STRG, a plurality of control signals SRST, and a plurality of control signals SSEL based on a plurality of control signals supplied from the signal generating circuit 31. The driver section 32 is supplied with a power supply voltage VDDH and a voltage VRL. The driver section 32 uses the power supply voltage VDDH as a high-level voltage and uses the voltage VRL as a low-level voltage to generate the control signals STRG, SRST, and SSEL.

[0079] The noise correction section 15 includes a noise correction section 40 and a noise correction section 50. The noise correction section 40 is configured to generate a noise correction signal corresponding to noise superimposed on the power supply voltage VDDH. The noise correction section 50 is configured to generate a noise correction signal corresponding to noise superimposed on the voltage VRL.

[0080] The noise correction section 40 includes a high pass filter (HPF) 41, an adjustment circuit 42, and a current source 43. The high pass filter 41 is configured to supply a noise signal as an AC component superimposed on the power supply voltage VDDH to the adjustment circuit 42. The adjustment circuit 42 is configured to adjust the amplitude and phase of the noise signal supplied from the high pass filter 41 based on an instruction from the imaging control section 18. The current source 43 is configured to convert the noise signal adjusted by the adjustment circuit 42 into a current signal.

[0081] The noise correction section 50 includes a high pass filter (HPF) 51, an adjustment circuit 52, and a current source 53. The high pass filter 51 is configured to supply a noise signal as an AC component superimposed on the voltage VRL to the adjustment circuit 52. The adjustment circuit 52 is configured to adjust the amplitude and phase of the noise signal supplied from the high pass filter 51 based on an instruction from the imaging control section 18. The current source 53 is configured to convert the noise signal adjusted by the adjustment circuit 52 into a current signal.

[0082] The noise correction unit 15 supplies the current signal generated by the noise correction unit 40 to the reference signal generation unit 16, thereby superimposing the noise correction signal as a voltage signal corresponding to the current signal on the reference signal RAMP. Similarly, the noise correction unit 15 supplies the current signal generated by the noise correction unit 50 to the reference signal generation unit 16, thereby superimposing the noise correction signal as a voltage signal corresponding to the current signal on the reference signal RAMP.

[0083] The reference signal generating section 16 includes a control circuit 61, a current source 62, and a resistance element 63. The control circuit 61 is configured to set the amount of current flowing through the current source 62 based on an instruction from the imaging control section 18. The current source 62 is connected to the resistance element 63, and is configured to cause a current of the amount of current to flow through the resistance element 63 according to an instruction from the control circuit 61. One end of the resistance element 63 is connected to the current source 62, and the other end is connected to a ground node. The current supplied from the current source 62 flows through the resistance element 63. Therefore, the reference signal generating section 16 generates a reference signal RAMP as a voltage signal corresponding to the current. The current signal supplied from the noise correction section 15 also flows through the resistance element 63. Therefore, the noise correction signal as a voltage signal corresponding to the current signal is superimposed on the reference signal RAMP.

[0084] Figure 6FIG. 5 shows an example of the configuration of the noise correction unit 50. Note that the same applies to the noise correction unit 40. In addition to the noise correction unit 50, Figure 6 The reference signal generating section 16, the imaging control section 78A, and the imaging control section 18 are also shown. The noise correction section 50 includes a capacitor C1, a resistor element R1, a transistor MN1, a current source CS1, a switch SW1, a resistor element R2, a transistor MN2, a current source CS2, a capacitor C2, transistors MP1 and MP2, and a capacitor C3. The transistors MN1 and MN2 are N-type MOS transistors. The transistors MP1 and MP2 are P-type transistors. The capacitor C1 corresponds to Figure 5 The high pass filter 51 shown. The resistor element R1, the transistor MN1, the current source CS1, the switch SW1, the resistor element R2, the transistor MN2, the current source CS2, the capacitor C2, the transistor MP1 and the capacitor C3 correspond to Figure 5 The regulation circuit 52 shown. Transistor MP2 corresponds to Figure 5 A current source 53 is shown.

[0085] One end of the capacitor C1 is supplied with voltage VRL, and the other end is connected to the switch SW1 and the gate of the transistor MN2. One end of the resistor R1 is connected to the source of the transistor MN1, and the other end is connected to the ground node. The gate of the transistor MN1 is connected to the switch SW1, the drain of the transistor MN1 and the current source CS1, the drain is connected to the current source CS1, the gate of the transistor MN1 and the switch SW1, and the source is connected to one end of the resistor R1. One end of the current source CS1 is connected to the power supply node of the power supply voltage VDD, and the other end is connected to the drain, gate and switch SW1 of the transistor MN1. One end of the switch SW1 is connected to the gate, drain and the other end of the current source CS1 of the transistor MN1, and the other end is connected to the other end of the capacitor C1 and the gate of the transistor MN2. The switch SW1 is turned on or off based on an instruction from the imaging control unit 18. One end of the resistor R2 is connected to the source of the transistor MN2, and the other end is connected to the ground node. The gate of transistor MN2 is connected to the other end of capacitor C1 and the other end of switch SW1, the drain is connected to current source CS2, capacitor C2, the drain of transistor MP1, and the gates of transistors MP1 and MP2, and the source is connected to one end of resistor element R2. One end of current source CS2 is connected to the power supply node of power supply voltage VDD, and the other end is connected to the drain of transistor MN2, capacitor C2, the drain of transistor MP1, and the gates of transistors MP1 and MP2. Current source CS2 is configured to change the amount of current based on an instruction from imaging control section 18. One end of capacitor C2 is connected to the power supply node of power supply voltage VDD, and the other end is connected to the drain of transistor MN2, the other end of current source CS2, the drain of transistor MP1, and the gates of transistors MP1 and MP2. Capacitor C2 is configured to change the capacity value based on an instruction from imaging control section 18. The gate of the transistor MP1 is connected to the gate of the transistor MP2, the drain of the transistor MP1, the drain of the transistor MN2, the other end of the current source CS2, and the other end of the capacitor C2, the source is connected to the power supply node of the power supply voltage VDD, and the drain is connected to the gates of the transistors MP1 and MP2, the drain of the transistor MN2, the other end of the current source CS2, and the other end of the capacitor C2. The gate of the transistor MP2 is connected to the gate of the transistor MP1, the drains of the transistors MP1 and MN2, the other end of the current source CS2, and the other end of the capacitor C2, the source is connected to the power supply node of the power supply voltage VDD, and the drain is connected to the capacitor C3 and connected to the reference signal generation section 16. The transistor MP2 is configured to change the gate width of the transistor to be operated based on the instruction from the imaging control section 18. One end of the capacitor C3 is supplied with the voltage VRL, and the other end is connected to the drain of the transistor MP2 and connected to the reference signal generation section 16. The capacitor C3 is configured to change the capacity value based on the instruction from the imaging control section 18.

[0086] With this configuration, the operating point of the noise correction section 50 is set by turning on the switch SW1, and then the switch SW1 is turned off. Therefore, a noise signal that is an AC component superimposed on the voltage VRL is applied to the gate of the transistor MN2, and a current corresponding to the voltage of the gate of the transistor MN2 flows through the transistor MN2. The current source CS2 causes a DC current to flow. This causes a current other than the DC current of the current source CS2 among the currents flowing through the transistor MN2 to flow through the transistor MP1. The transistors MP1 and MP2 constitute a current mirror circuit, and a current corresponding to the current flowing through the transistor MP1 flows through the transistor MP2. This causes the noise correction section 50 to output a current signal corresponding to the noise signal superimposed on the voltage VRL. This current signal flows through the resistor element 63 of the reference signal generating section 16. Therefore, a noise correction signal that is a voltage signal corresponding to the current signal is generated.

[0087] The current source CS2, capacitors C2 and C3, and transistor MP2 in the noise correction section 50 operate based on the adjustment parameters supplied from the imaging control section 18. This allows the adjustment circuit 52 of the noise correction section 50 to adjust the amplitude and phase of the noise correction signal.

[0088] Figures 7A to 7C Operation examples of the adjustment circuit 52 are respectively shown. Fig. 7A An example of adjusting the amplitude of the noise correction signal is shown, and Figure 7B and Figure 7C An example of adjusting the phase of the noise correction signal is shown.

[0089] For example, in the case where the gate width of the transistor to be operated in the transistor MP2 is changed, the current mirror ratio in the transistors MP1 and MP2 is changed. This changes the gain in the noise correction section 50, such as Fig. 7A Specifically, the adjustment circuit 52 is configured to increase the amplitude of the noise correction signal by increasing the gate width of the transistor to be operated in the transistor MP2.

[0090] The amplitude ΔVo of the noise correction signal can be expressed by the following equation.

[0091] ΔVo=1 / Rs×m×Ro×ΔV

[0092] Here, ΔV is the voltage amplitude of the noise signal in the transistor MN2, Rs is the resistance value of the resistance element R2, and m is the current mirror ratio in the transistors MP1 and MP2, and represents the current flowing through the transistor MP2 based on the current flowing through the transistor MP1 being "1". Ro is the resistance value of the resistance element 63. Therefore, changing the current mirror ratio can change the amplitude of the noise correction signal.

[0093] For example, when the capacitance value of capacitor C2 is changed, Figure 7B Specifically, the adjustment circuit 52 is configured to delay the phase of the noise correction signal by increasing the capacitance value of the capacitor C2.

[0094] For example, in the case where the capacitance value of capacitor C3 is changed, such as Figure 7C Specifically, the adjustment circuit 52 is configured to advance the phase of the noise correction signal by increasing the capacitance value of the capacitor C3.

[0095] Signal processing unit 17 ( Figure 1 ) is configured to generate image data DT by performing predetermined image processing based on the image data DT0 and an instruction from the imaging control section 18. Examples of the predetermined image processing include black level correction processing for correcting a black level and processing for reducing noise.

[0096] The imaging control section 18 is configured to supply control signals to the driving section 12, the readout section 20, the noise correction section 15, the reference signal generation section 16, and the signal processing section 17, and control the operations of these circuits, thereby controlling the operation of the imaging device 1. Specifically, the imaging control section 18 supplies a control signal to the driving section 12, thereby controlling the driving section 12 so that the driving section 12 sequentially drives the plurality of light receiving pixels P in the pixel array 11 in units of pixel lines L. In addition, the imaging control section 18 supplies a control signal to the noise correction section 15, thereby controlling the noise correction section 15 so that the noise correction section 15 adjusts, for example, the amplitude and phase of the noise correction signal. In addition, the imaging control section 18 supplies a control signal to the reference signal generation section 16, thereby controlling the reference signal generation section 16 so that the reference signal generation section 16 generates a reference signal RAMP. In addition, the imaging control section 18 supplies a control signal to the readout section 20, thereby controlling the readout section 20 so that the readout section 20 generates the image data DT0 by performing AD conversion based on the pixel signal SIG. In addition, the imaging control section 18 supplies a control signal to the signal processing section 17 , thereby controlling image processing in the signal processing section 17 .

[0097] Here, the light receiving pixel P corresponds to a specific example of a “light receiving pixel” in one embodiment of the present disclosure. The terminal TVRL corresponds to a specific example of a “first connection terminal” in one embodiment of the present disclosure. The capacitor Cext1 corresponds to a specific example of a “first external capacitor” in one embodiment of the present disclosure. The charge pump 14 corresponds to a specific example of a “first voltage generating circuit” in one embodiment of the present disclosure. The driving unit 12 corresponds to a specific example of a “driving circuit” in one embodiment of the present disclosure. The reference signal RAMP corresponds to a specific example of a “reference signal” in one embodiment of the present disclosure. The reference signal generating unit 16 corresponds to a specific example of a “reference signal generating circuit” in one embodiment of the present disclosure. The noise correction unit 50 corresponds to a specific example of a “noise correction circuit” in one embodiment of the present disclosure. The comparison circuit 24 corresponds to a specific example of a “comparison circuit” in one embodiment of the present disclosure. The counter 25 corresponds to a specific example of a “processing circuit” in one embodiment of the present disclosure.

[0098] [Operation and function]

[0099] Next, a description is given of the operation and effect of the image forming apparatus 1 according to the present embodiment.

[0100] (Overview of overall operation)

[0101] First, refer to Figure 1 and Figure 4An overview of the overall operation of the imaging device 1 is described. The charge pump 14 charges and discharges the capacitor Cext1 provided outside the imaging device 1, thereby generating a voltage VRL. The driving section 12 sequentially drives a plurality of light receiving pixels P in the pixel array 11 in units of pixel lines L based on an instruction from the imaging control section 18. The reference signal generating section 16 generates a reference signal RAMP based on an instruction from the imaging control section 18. The noise correction section 15 generates a noise correction signal corresponding to the noise superimposed on the power supply voltage VDDH and a noise correction signal corresponding to the noise superimposed on the voltage VRL based on an instruction from the imaging control section 18, and superimposes these generated noise correction signals on the reference signal RAMP generated by the reference signal generating section 16. The light receiving pixel P outputs a reset voltage Vreset as a pixel signal SIG in the P phase period TP, and outputs a pixel voltage Vpix corresponding to the amount of received light as a pixel signal SIG in the D phase period TD. The readout section 20 generates image data DT0 based on the pixel signal SIG supplied from the pixel array 11 via the signal line VSL, the reference signal RAMP supplied from the reference signal generating section 16, and the instruction from the imaging control section 18. Specifically, in the readout section 20, the AD converter ADC performs AD conversion based on the pixel signal SIG and the reference signal RAMP, thereby generating a count value CNT, and outputs the count value CNT as a digital code having a plurality of bits. The readout section 20 sequentially supplies a plurality of digital codes including the count value CNT generated by the plurality of AD converters ADC to the signal processing section 17 via the bus wiring BUS as image data DT0. The signal processing section 17 performs predetermined image processing based on the image data DT0 and the instruction from the imaging control section 18, thereby generating image data DT.

[0102] (Detailed operation)

[0103] In the imaging device 1, a plurality of light receiving pixels P respectively accumulate charges corresponding to the amount of light received, and generate a pixel signal SIG including a pixel voltage Vpix corresponding to the amount of light received. Thereafter, the readout section 20 performs AD conversion based on the pixel signal SIG and the reference signal RAMP. This operation is described in detail below.

[0104] Figure 8 An example of an operation of scanning a plurality of light-receiving pixels P in the pixel array 11 in units of pixel lines L is shown.

[0105] During the period from time t0 to t1, the imaging device 1 performs exposure start drive D1 on the pixel array 11 sequentially from the top in the vertical direction. Specifically, for example, the driving section 12 generates control signals STRG and SRST, thereby sequentially selecting the pixel line L and sequentially turning on the transistors TRG and RST in the light receiving pixel P for a predetermined length of time. This causes the voltage of the floating diffusion FD and the voltage of the cathode of the photodiode PD to be set to the power supply voltage VDDH in the light receiving pixel P. Thereafter, with the transistors TRG and RST disconnected, the photodiode PD begins to accumulate charges corresponding to the amount of light received. In this way, the exposure period T is sequentially started in a plurality of light receiving pixels P.

[0106] After that, during the period from time t2 to time t3, the imaging device 1 performs readout drive D2 on the pixel array 11 in the vertical direction, for example, from the top in sequence. Specifically, as described below, the drive section 12 generates control signals STRG, SRST, and SSEL to sequentially select the pixel lines L. This causes the light receiving pixel P to output the reset voltage Vreset as the pixel signal SIG in the P phase period TP, and to output the pixel voltage Vpix as the pixel signal SIG in the D phase period TD. The readout section 20 performs AD conversion based on the pixel signal SIG including the reset voltage Vriset and the pixel voltage Vpix output from the light receiving pixel P.

[0107] The imaging device 1 repeats such exposure start drive D1 and such readout drive D2. This allows the imaging device 1 to obtain a series of captured images.

[0108] Next, the readout drive D2 is described in detail. The following focuses on a certain light receiving pixel P, and the operations of the light receiving pixel P and the AD converter ADC connected to the light receiving pixel P are described.

[0109] Fig. 9 1 and 2 show an operation example of the readout driver D2, wherein (A) shows the waveform of the control signal SSEL, (B) shows the waveform of the control signal SRST, (C) shows the waveform of the control signal STRG, (D) shows the waveform of the control signal AZSW, (E) shows the waveform of the reference signal RAMP, (F) shows the waveform of the pixel signal SIG, (G) shows the waveform of the clock signal CLK, (H) shows the waveform of the signal CP, and (I) shows the counting operation of the counter 25. Fig. 9 In (E) and (F) of FIG. 1 , the waveforms of the reference signal RAMP and the pixel signal SIG are shown using the same voltage axis. In addition, in this specification, Fig. 9 The waveform of the reference signal RAMP shown in (E) is a waveform of a voltage supplied to the input terminal of the comparison circuit 24 via the capacitor 23, and Fig. 9The waveform of the pixel signal SIG shown in (F) is a waveform of a voltage supplied to the input terminal of the comparison circuit 24 via the capacitor 22 .

[0110] First, at time t11, the horizontal period H starts. This causes the drive unit 12 to change the voltage of the control signal SSEL from a low level to a high level ( Fig. 9 (A)). This turns on the transistor SEL in the light receiving pixel P, and the light receiving pixel P is electrically connected to the signal line VSL. At this time t11, the drive section 12 changes the voltage of the control signal SRST from a low level to a high level ( Fig. 9 (B)). This turns on the transistor RST in the light receiving pixel P, and the voltage of the floating diffusion FD is set to the power supply voltage VDDH (reset operation). Thereafter, the light receiving pixel P outputs a voltage corresponding to the voltage of the floating diffusion FD at that time. At this time t11, the imaging control section 18 changes the voltage of the control signal AZSW from a low level to a high level ( Fig. 9 This causes the comparison circuit 24 of the AD converter ADC to set the voltages of the capacitors 22 and 23, thereby setting the operating point. In this way, the voltage of the pixel signal SIG is set to the reset voltage Vreset, and the voltage of the reference signal RAMP is set to the same voltage as the voltage of the pixel signal SIG (reset voltage Vreset) ( Fig. 9 (E) and (F)).

[0111] Then, at time t12, the driving unit 12 changes the voltage of the control signal SRST from a high level to a low level ( Fig. 9 (B)). This turns off the transistor RST in the light-receiving pixel P, and the reset operation ends.

[0112] Next, at time t13, the imaging control section 18 changes the voltage of the control signal AZSW from the high level to the low level ( Fig. 9 This allows the comparison circuit 24 to complete the setting of the operating point.

[0113] At time t13, the reference signal generating unit 16 sets the voltage of the reference signal RAMP to the voltage V1 ( Fig. 9 (E)). This makes the voltage of the reference signal RAMP higher than the voltage of the pixel signal SIG. Therefore, the comparison circuit 24 changes the voltage of the signal CP from a low level to a high level ( Fig. 9 (H)).

[0114] After that, during the period from time t14 to t16 (P phase period TP), the AD converter ADC performs AD conversion based on the pixel signal SIG. Specifically, first, at time t14, the reference signal generating unit 16 starts to reduce the voltage of the reference signal RAMP from the voltage V1 at a predetermined rate of change ( Fig. 9 In addition, at this time t14, the imaging control unit 18 starts to generate the clock signal CLK ( Fig. 9 The counter 25 of the AD converter ADC performs a count operation of down counting, thereby counting the pulses of the clock signal CLK ( Fig. 9 (I)).

[0115] Then, at time t15, the voltage of the reference signal RAMP drops to a voltage lower than the voltage of the pixel signal SIG (reset voltage Vreset) ( Fig. 9 (E) and (F)). This causes the comparison circuit 24 of the AD converter ADC to change the voltage of the signal CP from a high level to a low level ( Fig. 9 The counter 25 of the AD converter ADC stops the counting operation based on the transition of the signal CP ( Fig. 9 The amount of change in the count value between time t14 and time t15 is a value corresponding to the reset voltage Vreset.

[0116] Next, at time t16, the imaging control unit 18 stops generating the clock signal CLK ( Fig. 9 In addition, at time t16, the reference signal generating unit 16 sets the voltage of the reference signal RAMP to the voltage V2 ( Fig. 9 (E)).

[0117] Next, at time t17, the imaging control unit 18 sets the voltage of the reference signal RAMP to the voltage V1 ( Fig. 9 (E)). This makes the voltage of the reference signal RAMP higher than the voltage of the pixel signal SIG (reset voltage Vreset). Therefore, the comparison circuit 24 changes the voltage of the signal CP from a low level to a high level ( Fig. 9 (H)).

[0118] Next, at time t18, the driving unit 12 changes the voltage of the control signal STRG from a low level to a high level ( Fig. 9 (C)). This turns on the transistor TRG in the light receiving pixel P, and the charge generated by the photodiode PD is transferred to the floating diffusion FD (charge transfer operation). Thereafter, the light receiving pixel P outputs a voltage corresponding to the voltage of the floating diffusion FD at that time. In this way, the voltage of the pixel signal SIG is set to the pixel voltage Vpix ( Fig. 9(F)).

[0119] Then, at time t19, the driving unit 12 changes the voltage of the control signal STRG from high level to low level ( Fig. 9 (C)). This turns off the transistor TRG in the light receiving pixel P, and the charge transfer operation ends.

[0120] After that, during the period from time t20 to t22 (D phase period TD), the AD converter ADC performs AD conversion based on the signal SIG. Specifically, first, at time t20, the reference signal generating unit 16 starts to reduce the voltage of the reference signal RAMP from the voltage V1 at a predetermined rate of change ( Fig. 9 In addition, at this time t20, the imaging control unit 18 starts to generate the clock signal CLK ( Fig. 9 The counter 25 of the AD converter ADC performs an up-counting operation, thereby counting the pulses of the clock signal CLK ( Fig. 9 (I)).

[0121] Then, at time t21, the voltage of the reference signal RAMP drops to a value lower than the voltage of the pixel signal SIG (pixel voltage Vpix) ( Fig. 9 (E) and (F)). This causes the comparison circuit 24 of the AD converter ADC to change the voltage of the signal CP from a high level to a low level ( Fig. 9 The counter 25 of the AD converter ADC stops the counting operation based on the transition of the signal CP ( Fig. 9 (I)). The change in the count value from time t20 to t21 is a value corresponding to the pixel voltage Vpix. The latch 26 holds the count value (count value CNT) of the counter 25 at that time. The count value CNT corresponds to the difference voltage between the pixel voltage Vpix and the reset voltage Vreset, and corresponds to the amount of light received by the light receiving pixel P during the exposure period T. Therefore, the imaging device 1 obtains a pixel value corresponding to the amount of light received by the light receiving pixel P using the correlated double sampling (CDS) principle.

[0122] Next, at time t22, the imaging control unit 18 stops generating the clock signal CLK ( Fig. 9 In addition, at time t22, the reference signal generating unit 16 sets the voltage of the reference signal RAMP to the voltage V3 ( Fig. 9 (E)). Thereafter, during a period from the time t22 or later, the reading unit 20 supplies the count value CNT stored in the latch 26 to the signal processing unit 17 as the image data DT0.

[0123] Next, at time t23, the driving unit 12 changes the voltage of the control signal SSEL from the high level to the low level ( Fig. 9 This turns off the transistor SEL in the light-receiving pixel P, and the light-receiving pixel P is electrically separated from the signal line VSL. Thereafter, the counter 25 resets the count value ( Fig. 9 (I)).

[0124] In this manner, the readout section 20 supplies the image data DT0 including the count value CNT to the signal processing section 17. For example, the signal processing section 17 performs predetermined processing based on the count value CNT included in the image data DT0, thereby generating the image data DT.

[0125] The noise correction section 15 generates a noise correction signal corresponding to the noise superimposed on the power supply voltage VDDH and a noise correction signal corresponding to the noise superimposed on the voltage VRL, and superimposes these noise correction signals on the reference signal RAMP generated by the reference signal generation section 16. The operations of the noise correction section 50 and the noise correction section 40 are described in detail below.

[0126] (Regarding Operation of Noise Correction Section 50)

[0127] Fig. 10A and Fig. 10B Each of the diagrams shows an operation example of the noise correction unit 50 . Fig. 10A The operation related to the light receiving pixel P to be subjected to the readout drive D2 is shown. Fig. 10B 2 shows the operation of the light receiving pixel P which will not be subjected to the readout drive D2. Fig. 10A and Fig. 10B In FIG. 5 , wirings indicated by bold lines represent wirings related to the operation of the noise correction section 50 .

[0128] The capacitor Cext1 is provided outside the imaging device 1, which easily causes noise to be superimposed on the voltage VRL. The driver section 32 of the driving section 12 uses the voltage VRL as a low-level voltage to generate the control signals STRG, SRST, and SSEL. Therefore, for example, in the case where the control signal STRG is at a low level, noise is superimposed on the control signal STRG. The same applies to the control signals SRST and SSEL.

[0129] like Fig. 9 As shown, the driving section 12 supplies a high-level control signal SSEL and low-level control signals STRG and SRST to the light receiving pixel P to be subjected to the readout drive D2 during the P-phase period TP and the D-phase period TD. Fig. 10AAs shown, in the light receiving pixel P, the noise corresponding to the noise of the voltage VRL is superimposed on the gate voltages of the transistors TRG and RST. The control signal STRG is at a low level; therefore, the transistor TRG is disconnected. However, the noise at the gate of the transistor TRG is transmitted to the gate of the transistor AMP via the parasitic capacitance between the gate and the drain of the transistor TRG. Similarly, the control signal SRST is at a low level; therefore, the transistor RST is disconnected. However, the noise at the gate of the transistor RST is transmitted to the gate of the transistor AMP via the parasitic capacitance between the gate and the source of the transistor RST. The control signal SSEL is at a high level; therefore, the transistor SEL is turned on, and the transistor AMP and the constant current source 21 operate as a source follower. Therefore, the noise at the gate of the transistor AMP is transmitted to the signal line VSL. In this way, the light receiving pixel P outputs a pixel signal SIG superimposed with noise.

[0130] On the other hand, the driving section 12 supplies the control signals STRG, SRST and SSEL of low level to the light receiving pixels P which are not to be subjected to the readout drive D2. Fig. 10B As shown, in the light receiving pixel P, the noise corresponding to the noise of the voltage VRL is superimposed on the gate voltages of the transistors TRG, RST and SEL. For example, the control signal SSEL is at a low level; therefore, the transistor SEL is disconnected. However, the noise at the gate of the transistor SEL is transmitted to the source of the transistor SEL via the parasitic capacitance between the gate and the source of the transistor SEL. Therefore, the light receiving pixel P causes the noise to be superimposed on the pixel signal SIG generated by the light receiving pixel P to be read out and driven D2.

[0131] In this manner, the pixel signal SIG on which noise is superimposed is supplied to the comparison circuit 24 via the capacitor 22 .

[0132] like Fig. 10A and Fig. 10B As shown, the noise correction section 50 generates a noise correction signal corresponding to the noise superimposed on the voltage VRL, and superimposes the noise correction signal on the reference signal RAMP generated by the reference signal generating section 16. The reference signal RAMP superimposed with the noise correction signal is supplied to the comparison circuit 24 via the capacitor 23. The amplitude and phase of the noise correction signal are pre-adjusted so as to be approximately the same as the amplitude and phase of the noise superimposed on the pixel signal SIG. This allows the noise and the noise correction signal, which are in phase with each other, to be superimposed on the pixel signal SIG and the reference signal RAMP to be supplied to the comparison circuit 24, respectively. The comparison circuit 24 operates based on the difference between the two supplied signals. This reduces the influence of noise on the signal CP generated by the comparison circuit 24. As a result, in the imaging device 1, the influence of the noise of the voltage VRL on the captured image can be reduced.

[0133] In other words, for example, in the case where the noise correction section 50 is not provided, the noise correction signal is not superimposed on the reference signal RAMP. Therefore, the comparison circuit 24 performs a comparison operation based on the pixel signal SIG superimposed with noise and the reference signal RAMP without the noise correction signal superimposed. As a result, in the imaging device 1, the noise of the voltage VRL affects the captured image. For example, the same noise is superimposed on the pixel signal SIG output from a plurality of light receiving pixels P belonging to the pixel line L; therefore, transverse stripes corresponding to the noise may appear on the captured image. On the other hand, the imaging device 1 includes the noise correction section 50; therefore, the noise and the noise correction signal in phase with each other are superimposed on the pixel signal SIG and the reference signal RAMP to be supplied to the comparison circuit 24, respectively. Therefore, in the imaging device 1, the influence of the noise of the voltage VRL on the captured image can be reduced.

[0134] Fig.11 An example of the characteristics of the noise removal ratio regarding the noise superimposed on the voltage VRL is shown, where the horizontal axis represents the frequency and the vertical axis represents the noise removal ratio. The noise removal ratio is the ratio between the voltage of the noise superimposed on the voltage VRL and the value converted from the pixel value in the captured image into the voltage, and indicates that the smaller the value is, the more noise is removed. Fig.11 , the solid line indicates the characteristics of the imaging device 1 according to the present embodiment, and the dotted line indicates the characteristics of the imaging device not including the noise correction section 50. The imaging device 1 includes the noise correction section 50, which can reduce the noise removal ratio.

[0135] (Regarding Operation of Noise Correction Section 40)

[0136] Fig.12 An operation example of the noise correction unit 40 is shown. Fig.12 2 shows the operation related to the light receiving pixel P to be subjected to the readout drive D2. Fig.12 In FIG. 4 , wirings indicated by bold lines represent wirings related to the operation of the noise correction section 40 .

[0137] The power supply voltage VDDH is supplied from the outside of the imaging device 1, which easily causes noise to be superimposed on the power supply voltage VDDH. The driver section 32 of the driving section 12 uses the power supply voltage VDDH as a high-level voltage to generate control signals STRG, SRST, and SSEL. Therefore, for example, in the case where the control signal SSEL is at a high level, noise is superimposed on the control signal SSEL.

[0138] like Fig. 9 As shown, the driving unit 12 supplies a high-level control signal SSEL and low-level control signals STRG and SRST to the light receiving pixel P to be read out and driven D2 during the P-phase period TP and the D-phase period TD. Fig.12 As shown, in the light receiving pixel P, the noise corresponding to the noise of the power supply voltage VDDH is superimposed on the gate voltage of the transistor SEL. In addition, in the light receiving pixel P, the noise corresponding to the noise of the power supply voltage VDDH is superimposed on the gate voltage of the transistor AMP via the parasitic capacitance between the power supply wiring of the power supply voltage VDDH and the floating diffusion FD. The control signal SSEL is at a high level; therefore, the transistor SEL is turned on, and the transistor AMP and the constant current source 21 operate as a source follower. In addition, the power supply voltage VDDH superimposed with noise is supplied to the drain of the transistor AMP. Therefore, the light receiving pixel P outputs a pixel signal SIG superimposed with noise.

[0139] The noise correction section 40 generates a noise correction signal corresponding to the noise superimposed on the power supply voltage VDDH, and superimposes the noise correction signal on the reference signal RAMP generated by the reference signal generation section 16. The reference signal RAMP superimposed with the noise correction signal is supplied to the comparison circuit 24 via the capacitor 23. The amplitude and phase of the noise correction signal are pre-adjusted so as to be approximately the same as the amplitude and phase of the noise superimposed on the pixel signal SIG. This allows the noise and the noise correction signal, which are in phase with each other, to be superimposed on the pixel signal SIG and the reference signal RAMP, respectively, to be supplied to the comparison circuit 24. As a result, in the imaging device 1, the influence of the noise of the power supply voltage VDDH on the captured image can be reduced. The characteristics of the noise removal ratio are similar to those of the noise correction section 50 ( Fig.11 ).

[0140] In this way, the imaging device 1 includes a light receiving pixel P, a terminal TVRL, a charge pump 14, a driving section 12, a reference signal generating section 16, a noise correction section 50, a comparison circuit 24, and a signal processing section 17. The light receiving pixel P is configured to generate a pixel signal SIG including a pixel voltage Vpix corresponding to the amount of light received. The terminal TVRL is connected to the capacitor Cext1. The charge pump 14 is configured to generate a voltage at the terminal TVRL. The driving section 12 is configured to drive the light receiving pixel P based on the voltage at the terminal TVRL. The reference signal generating section 16 is configured to generate a reference signal RAMP having a ramp waveform. The noise correction section 50 is configured to generate a noise correction signal corresponding to the voltage at the terminal TVRL, and is configured to superimpose the noise correction signal on the reference signal RAMP. The comparison circuit 24 is configured to compare between the pixel signal SIG and the reference signal RAMP superimposed with the noise correction signal. The signal processing section 17 is configured to calculate a pixel value based on the comparison result of the comparison circuit 24. Therefore, for example, noise and a noise correction signal in phase with each other are respectively superimposed on the pixel signal SIG and the reference signal RAMP to be supplied to the comparison circuit 24. This can reduce the influence of the noise of the voltage VRL on the captured image.

[0141] [Effect]

[0142] As described above, in the present embodiment, a light receiving pixel, a terminal connected to a capacitor, a charge pump, a driving unit, a reference signal generating unit, a noise correction unit, a comparison circuit and a signal processing unit are provided. The light receiving pixel is configured to generate a pixel signal including a pixel voltage corresponding to the amount of light. The charge pump is configured to generate a voltage at the terminal. The driving unit is configured to drive the light receiving pixel based on the voltage at the terminal. The reference signal generating unit is configured to generate a reference signal having a ramp waveform. The noise correction unit is configured to generate a noise correction signal corresponding to the voltage at the terminal, and is configured to superimpose the noise correction signal on the reference signal. The comparison circuit is configured to compare between the pixel signal and the reference signal superimposed with the noise correction signal. The signal processing unit is configured to calculate the pixel value based on the comparison result of the comparison circuit. Therefore, the influence of noise can be reduced.

[0143] <2. Second Implementation Method>

[0144] Next, a description is given of an imaging device 2 according to a second embodiment. This embodiment is an example in which the circuit configuration of the light receiving pixel P is changed and two external capacitors are provided. Note that substantially the same constituent parts as those of the imaging device 1 according to the above-described first embodiment are denoted by the same reference numerals, and description thereof is appropriately omitted.

[0145] Fig.13 An example of the configuration of an imaging device 2 according to the second embodiment is shown. The imaging device 2 includes a pixel array 71 , a drive section 72 , a bias circuit 74 , a noise correction section 75 , a signal processing section 77 , and an imaging control section 78 .

[0146] Like the pixel array 11 according to the first embodiment described above, the pixel array 71 includes a plurality of light-receiving pixels P arranged in a matrix.

[0147] Fig.14 FIG. 7 shows an example of the structure of a light receiving pixel P. The pixel array 71 includes a plurality of control lines TGLL, a plurality of control lines FDGL, a plurality of control lines RSTL, a plurality of control lines FCGL, a plurality of control lines TGSL, a plurality of control lines SELL, and a plurality of signal lines VSL. The control lines TGLL are arranged in the horizontal direction ( Fig.14The control line FDGL extends in the horizontal direction and is connected to the driving section 72 at one end. The driving section 72 supplies the control signal STGL to the control line TGLL. The control line FDGL extends in the horizontal direction and is connected to the driving section 72 at one end. The driving section 72 supplies the control signal SFDG to the control line FDGL. The control line RSTL extends in the horizontal direction and is connected to the driving section 72 at one end. The driving section 72 supplies the control signal SRST to the control line RSTL. The control line FCGL extends in the horizontal direction and is connected to the driving section 72 at one end. The driving section 72 supplies the control signal SFCG to the control line FCGL. The control line TGSL extends in the horizontal direction and is connected to the driving section 72 at one end. The driving section 72 supplies the control signal STGS to the control line TGSL. The control line SELL extends in the horizontal direction and is connected to the driving section 72 at one end. The driving section 72 supplies the control signal SSEL to the control line SELL.

[0148] The light receiving pixel P includes a photodiode PD1, a transistor TGL, a photodiode PD2, a transistor TGS, a capacitor FC, transistors FCG, RST and FDG, a floating diffusion FD, and transistors AMP and SEL. In this example, the transistors TGL, TGS, FCG, RST, FDG, AMP and SEL are N-type MOS transistors.

[0149] The photodiode PD1 is a photoelectric conversion element that generates an amount of charge corresponding to the amount of light received and accumulates the charge therein. The light receiving area in which the photodiode PD1 can receive light is wider than the light receiving area in which the photodiode PD2 can receive light. The anode of the photodiode PD1 is grounded, and the cathode is connected to the source of the transistor TGL.

[0150] The transistor TGL has a gate connected to the control line TGLL, a source connected to the cathode of the photodiode PD1 , and a drain connected to the floating diffusion FD.

[0151] The photodiode PD2 is a photoelectric conversion element that generates an amount of charge corresponding to the amount of light received and accumulates the charge therein. The light receiving area in which the photodiode PD2 can receive light is narrower than the light receiving area in which the photodiode PD1 can receive light. The anode of the photodiode PD2 is grounded, and the cathode is connected to the source of the transistor TGS.

[0152] The gate of the transistor TGS is connected to the control line TGSL, the source is connected to the cathode of the photodiode PD2, and the drain is connected to the capacitor FC and the source of the transistor FCG.

[0153] One end of the capacitor FC is connected to the drain of the transistor TGS and the source of the transistor FCG, and the other end is supplied with the control signal FCVDD.

[0154] The gate of the transistor FCG is connected to the control line FCGL, the source is connected to one end of the capacitor FC and the drain of the transistor TGS, and the drain is connected to the source of the transistor RST and the drain of the transistor FDG.

[0155] The gate of the transistor RST is connected to the control line RSTL, the drain is supplied with the power supply voltage VDDH, and the source is connected to the drains of the transistors FCG and FDG.

[0156] The gate of the transistor FDG is connected to the control line FDGL, the drain is connected to the source of the transistor RST and the drain of the transistor FCG, and the source is connected to the floating diffusion FD.

[0157] The floating diffusion FD is configured to accumulate charges supplied from the photodiodes PD1 and PD2. For example, the floating diffusion FD is configured using a diffusion layer formed on the surface of a semiconductor substrate. Fig.14 In FIG. 1 , the floating diffusion FD is represented by the symbol of a capacitor.

[0158] With this configuration, in the light receiving pixel P, based on the control signal SSEL, the transistor SEL is turned on, thereby electrically connecting the light receiving pixel P to the signal line VSL. As a result, the transistor AMP is connected to the constant current source 21 of the readout section 20, and operates as a so-called source follower. Thereafter, the light receiving pixel P outputs a pixel voltage VP corresponding to the voltage in the floating diffusion section FD as a pixel signal SIG to the signal line VSL. Specifically, as described later, the light receiving pixel P sequentially outputs eight pixel voltages VP (VP1 to VP8) during eight periods (conversion periods T1 to T8) within the so-called horizontal period H.

[0159] Fig.15 An example of the configuration of the photodiodes PD1 and PD2 in the pixel array 71 is shown. Fig.15 , "R" represents a red color filter, "Gr" and "Gb" represent green color filters, respectively, and "B" represents a blue color filter. In the light receiving pixel P, the photodiode PD2 is formed at the upper right corner of the photodiode PD1. Color filters of the same color are formed on the two photodiodes PD1 and PD2 in the light receiving pixel P. In this example, the photodiode PD1 has an octagonal shape, and the photodiode PD2 has a quadrilateral shape. As shown in the figure, the light receiving area in which the photodiode PD1 can receive light is wider than the light receiving area in which the photodiode PD2 can receive light.

[0160] Driving unit 72( Fig.13) is configured to sequentially drive the plurality of light receiving pixels P in the pixel array 71 in units of pixel lines L based on an instruction from the imaging control section 78. Specifically, the driving section 72 supplies a plurality of control signals STGL to the plurality of control lines TGLL in the pixel array 71, supplies a plurality of control signals SFDG to the plurality of control lines FDGL in the pixel array 71, supplies a plurality of control signals SRST to the plurality of control lines RSTL in the pixel array 71, supplies a plurality of control signals SFCG to the plurality of control lines FCGL in the pixel array 71, supplies a plurality of control signals STGS to the plurality of control lines TGSL in the pixel array 71, and supplies a plurality of control signals SSEL to the plurality of control lines SELL in the pixel array 71, thereby driving the plurality of light receiving pixels P in the pixel array 71 in units of pixel lines L. In addition, the driving section 72 supplies the control signal FCVDD to the plurality of light receiving pixels P in the pixel array 71. The driving section 72 is supplied with the voltage VRL generated by the charge pump 14, and is supplied with the voltage VRH generated by the bias circuit 74.

[0161] The bias circuit 74 is configured to generate a voltage VRH. The bias circuit 74 is connected to a capacitor Cext2 provided outside the imaging device 2 via a terminal TVRH. In this example, the voltage VRH is a voltage higher than the ground voltage and lower than the power supply voltage VDDH. Note that in this example, the bias circuit 74 is provided, but this is not restrictive. For example, a charge pump may be provided instead of the bias circuit 74. In this case, for example, the voltage VRH can be set to a voltage higher than the power supply voltage VDDH.

[0162] The noise correction unit 75 is constructed to generate a noise correction signal corresponding to the noise superimposed on the power supply voltage VDDH, a noise correction signal corresponding to the noise superimposed on the voltage VRL, and a noise correction signal corresponding to the noise superimposed on the voltage VRH based on an instruction from the imaging control unit 78, and superimpose these noise correction signals on the reference signal RAMP generated by the reference signal generation unit 16.

[0163] Fig.16 Specific examples of the driving unit 72 and the noise correction unit 75 are shown. Note that in addition to the driving unit 72 and the noise correction unit 75, Fig.16 Also shown are the light receiving pixels P, the charge pump 14 , the bias circuit 74 , the reference signal generating section 16 , and the readout section 20 .

[0164] The driving section 72 includes a signal generating circuit 81, a driver section 82, and a driver 83. For example, the signal generating circuit 81 is configured using a shift register, and is configured to generate a plurality of control signals as a source of a plurality of control signals STGL, a plurality of control signals as a source of a plurality of control signals SFDG, a plurality of control signals as a source of a plurality of control signals SRST, a plurality of control signals as a source of a plurality of control signals SFCG, a plurality of control signals as a source of a plurality of control signals STSG, and a plurality of control signals as a source of a plurality of control signals SSEL. In addition, the signal generating circuit 81 also has a function of generating a control signal as a source of a control signal SFCVDD. The driver section 82 includes a plurality of drivers. The driver section 82 is configured to generate a plurality of control voltages STGL, a plurality of control signals SFDG, a plurality of control signals SRST, a plurality of control signals SFCG, a plurality of control signals STSG, and a plurality of control signals SSEL based on a plurality of control signals supplied from the signal generating circuit 81. The driver section 82 is supplied with a power supply voltage VDDH and a voltage VRL. The driver section 82 uses the power supply voltage VDDH as a high-level voltage and uses the voltage VRL as a low-level voltage to generate control signals STGL, SFDG, SRST, SFCG, STGS, and SSEL. The driver 83 is configured to generate a control signal SFCVDD based on the control signal supplied from the signal generating circuit 81. The driver 83 is supplied with the voltage VRH. The driver 83 outputs the voltage VRH as the control signal SFCVDD.

[0165] The noise correction section 75 includes a noise correction section 90. The noise correction section 90 is configured to generate a noise correction signal corresponding to the noise superimposed on the voltage VRL and a noise correction signal corresponding to the noise superimposed on the voltage VRH. The noise correction section 90 includes a high-pass filter (HPF) 91, an adjustment circuit 92, a current source 93, a high-pass filter (HPF) 94, an adjustment circuit 95, and a current source 96. The high-pass filter 91 is configured to supply the noise signal as an AC component superimposed on the voltage VRH to the adjustment circuit 92. The adjustment circuit 92 is configured to adjust the amplitude and phase of the noise signal supplied from the high-pass filter 91 based on an instruction from the imaging control section 78. The current source 93 is configured to convert the noise signal adjusted by the adjustment circuit 92 into a current signal. The high-pass filter 94 is configured to supply the noise signal as an AC component superimposed on the voltage VRL to the adjustment circuit 95. The adjustment circuit 95 is configured to adjust the amplitude and phase of the noise signal supplied from the high-pass filter 94 based on an instruction from the imaging control section 78. The current source 96 is configured to convert the noise signal regulated by the regulating circuit 95 into a current signal. Each of the high-pass filters 91 and 94 has the same structure as the high-pass filter 51 ( Figure 6Each of the adjustment circuits 92 and 95 has a circuit configuration similar to that of the adjustment circuit 52 ( Figure 6 ) is a circuit configuration similar to that of the current sources 93 and 96. Each of the current sources 93 and 96 has the same configuration as that of the current source 53 ( Figure 6 )A similar circuit configuration.

[0166] Signal processing unit 77 ( Fig.13 ) is configured to generate image data DT by performing predetermined image processing based on the image data DT0 and an instruction from the imaging control section 78.

[0167] The imaging control section 78 is configured to supply control signals to the driving section 72 , the readout section 20 , the noise correction section 75 , the reference signal generation section 16 , and the signal processing section 77 , and control the operations of these circuits, thereby controlling the operation of the imaging device 2 .

[0168] Here, the terminal TVRH corresponds to a specific example of the "second connection terminal" in one embodiment of the present disclosure. The capacitor Cext2 corresponds to a specific example of the "second external capacitor" in one embodiment of the present disclosure. The bias circuit 74 corresponds to a specific example of the "second voltage generating circuit" in one embodiment of the present disclosure. The imaging control unit 78 corresponds to a specific example of the "control circuit" in one embodiment of the present disclosure.

[0169] Next, the readout drive D2 is described in detail. The following focuses on a certain light receiving pixel P, and the operations of the light receiving pixel P and the AD converter ADC connected to the light receiving pixel P are described.

[0170] Fig.17 , Fig.18A and Fig.18B FIG. 2 shows an operation example of the imaging device 2. Fig.17 , Fig.18A and Fig.18B , (A) shows the waveform of the horizontal synchronization signal XHS, (B) shows the waveform of the control signal SSEL, (C) shows the waveform of the control signal SRST, (D) shows the waveform of the control signal SFDG, (E) shows the waveform of the control signal STGL, (F) shows the waveform of the control signal SFCG, (G) shows the waveform of the control signal STGS, (H) shows the waveform of the reference signal RAMP, (I) shows the waveform of the pixel signal SIG, and (J) shows the operation of the counter 25. Fig.17 , (K) shows adjustment parameters related to the voltage VRL in the noise correction section 90 , and (L) shows adjustment parameters related to the voltage VRH in the noise correction section 90 . Fig.18A Shows Fig.17 The first half of the operation shown is performed, and Fig.18B Shows Fig.17 The second half of the operation shown is performed. Fig.17 (J), Fig.18A (J) and Fig.18B In (J), the oblique line shaded portion indicates that the counter 25 is performing a counting operation.

[0171] Figures 19A to 19C 1 shows the state of the light receiving pixel P. Figures 19A to 19C , transistors TGL, RST, FDG, TGS, FCG, and SEL are respectively illustrated using switches corresponding to the operating states of the transistors.

[0172] First, at time t101, the horizontal period H starts. This causes the drive unit 72 to change the voltage of the control signal SSEL from a low level to a high level at time t102 ( Fig.18A (B)). This turns on the transistor SEL in the light-receiving pixel P, and the light-receiving pixel P is electrically connected to the signal line VSL.

[0173] During the period until time t111, the driving unit 72 changes the control signals SRST and SFDG to high level ( Fig.18A (C) and (D) of FIG. 1 ). This turns on the transistors RST and FDG in the light receiving pixel P, and the voltage of the floating diffusion FD is set to the power supply voltage VDDH, and the floating diffusion FD is reset.

[0174] (Operation at time t111 to t121)

[0175] Next, at time t111, the driving unit 72 changes the voltage of the control signal SFDG from a high level to a low level ( Fig.18A This turns off the transistor FDG in the light receiving pixel P. Next, at time t112, the drive section 72 changes the voltage of the control signal SRST from a high level to a low level ( Fig.18A This turns off the transistor RST in the light receiving pixel P. Next, at time t113, the drive section 72 changes the voltage of the control signal SFDG from a low level to a high level ( Fig.18A (D)). This turns on the transistor FDG in the light receiving pixel P. In addition, the comparison circuit 24 sets the operating point based on the control signal AZSW during the period from time t113 to t114.

[0176] Next, at time t114, the comparison circuit 24 completes the setting of the operating point. Thereafter, at this time t114, the reference signal generation unit 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18A (H)).

[0177] Therefore, if Fig.19A As shown, in the light receiving pixel P, transistors FDG and SEL are turned on, and all other transistors are turned off. Transistor FDG is turned on, which makes the floating diffusion part FD and transistor FDG constitute a combined capacitance. The combined capacitance serves as a conversion capacitor that converts charge into a voltage in the light receiving pixel P. In the light receiving pixel P, transistor FDG is turned on in this way; therefore, the conversion capacitance in the light receiving pixel P is large. Therefore, the conversion efficiency from charge to voltage is low. When the floating diffusion part FD is reset in the period until t112, the conversion capacitance holds the charge. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP1) corresponding to the voltage in the floating diffusion part FD at that time.

[0178] Next, during the period from time t115 to t117 (conversion period T1), the AD converter ADC performs AD conversion based on the pixel voltage VP1. Specifically, at time t115, the imaging control unit 78 starts to generate the clock signal CLK, and at the same time, the reference signal generation unit 16 starts to reduce the voltage of the reference signal RAMP from the voltage V1 at a predetermined rate of change ( Fig.18A Therefore, the counter 25 of the AD converter ADC starts the counting operation ( Fig.18A In this example, the counter 25 continuously performs the counting operation of counting up, thereby counting the pulses of the clock signal CLK.

[0179] Then, at time t116, the voltage of the reference signal RAMP drops to a voltage lower than the voltage of the pixel signal SIG (pixel voltage VP1) ( Fig.18A (H) and (I)). Therefore, the comparison circuit 24 of the AD converter ADC changes the voltage of the signal CP, and as a result, the counter 25 stops the counting operation ( Fig.18A When the counting operation stops, the count value CNT of the counter 25 corresponds to the pixel voltage VP1. The AD converter ADC performs AD conversion based on the pixel voltage VP1 in this way, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE1 ( Fig.18A (J)).

[0180] Then, at time t117, the imaging control unit 78 stops generating the clock signal CLK when the conversion period T1 ends, and the reference signal generating unit 16 stops changing the voltage of the reference signal RAMP ( Fig.18A (H)), and the counter 25 resets the count value CNT.

[0181] (Operation at time t121 to t131)

[0182] Next, at time t121, the driving unit 72 changes the voltage of the control signal SFDG from a high level to a low level ( Fig.18A (D)). This turns off the transistor FDG in the light receiving pixel P. In addition, the comparison circuit 24 sets the operation point based on the control signal AZSW during the period from time t121 to time t122.

[0183] Next, at time t122, the comparison circuit 24 completes the setting of the operating point. At this time t122, the reference signal generation unit 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18A (H)).

[0184] Therefore, if Fig.19B As shown, in the light receiving pixel P, the transistor SEL is turned on, and all other transistors are turned off. In the light receiving pixel P, the transistor FDG is turned off in this way; therefore, the conversion capacitance in the light receiving pixel P is low. Therefore, the conversion efficiency from charge to voltage is high. When the floating diffusion FD is reset in the period until t112, the conversion capacitance holds the charge. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP2) corresponding to the voltage in the floating diffusion FD at that time.

[0185] Next, during the period from time t123 to t125 (conversion period T2), the AD converter ADC performs AD conversion based on the pixel voltage VP2. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP2, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE2 ( Fig.18A (J)).

[0186] (Operation at time t131 to t141)

[0187] Next, at time t131, the driving unit 72 changes the voltage of the control signal STGL from a low level to a high level ( Fig.18A (E)). This turns on the transistor TGL in the light receiving pixel P, and the charge generated by the photodiode PD1 is transferred to the floating diffusion FD. In addition, at this time t131, the reference signal generating section 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18A (H)).

[0188] Next, at time t132, the driving unit 72 changes the voltage of the control signal STGL from the high level to the low level ( Fig.18A This turns off the transistor TGL in the light receiving pixel P.

[0189] Therefore, if Fig.19B As shown, in the light receiving pixel P, the transistor FDG is disconnected; therefore, the conversion capacitance in the light receiving pixel P is small. Therefore, the conversion efficiency from charge to voltage is high. The conversion capacitance holds the charge transferred from the photodiode PD1 at time t131 to t132. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP3) corresponding to the voltage in the floating diffusion portion FD at that time.

[0190] Next, during the period from time t133 to t135 (conversion period T3), the AD converter ADC performs AD conversion based on the pixel voltage VP3. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP3, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE3 ( Fig.18A The digital code CODE3 corresponds to the digital code CODE2 obtained when the conversion efficiency is also high (conversion period T2).

[0191] (Operation at time t141 to t151)

[0192] Next, at time t141, the driving unit 72 changes the voltage of the control signal SFDG from a low level to a high level, and changes the voltage of the control signal STGL from a high level to a low level ( Fig.18A (D) and (E)). This turns on the transistors FDG and TGL in the light receiving pixel P. In addition, at this time t141, the reference signal generating section 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18A Next, at time t142, the driving unit 72 changes the voltage of the control signal STGL from the high level to the low level ( Fig.18A This turns off the transistor TGL in the light receiving pixel P.

[0193] Therefore, if Fig.19A As shown, in the light receiving pixel P, the transistor FDG is turned on, which makes the floating diffusion part FD and the transistor FDG constitute a combined capacitance (conversion capacitance). Therefore, the conversion capacitance in the light receiving pixel P is large; therefore, the conversion efficiency from charge to voltage is low. The conversion capacitance holds the charge transferred from the photodiode PD1 at time t131 to t132 and at time t141 to t142. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP4) corresponding to the voltage in the floating diffusion part FD at that time.

[0194] Next, during the period from time t143 to t145 (conversion period T4), the AD converter ADC performs AD conversion based on the pixel voltage VP4. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP4, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE4 ( Fig.18A The digital code CODE4 corresponds to the digital code CODE1 obtained when the conversion efficiency is also low (conversion period T1).

[0195] (Operation at time t151 to t161)

[0196] Next, at time t151, the driving unit 72 changes the voltage of the control signal SRST from a low level to a high level ( Fig.18B (C)). This turns on the transistor RST in the light receiving pixel P. The transistor FDG turns on, which sets the voltage of the floating diffusion FD to the power supply voltage VDDH and resets the floating diffusion FD. Next, at time t152, the drive section 72 changes the voltage of the control signal SRST from a high level to a low level ( Fig.18B (C)). This turns off the transistor RST in the light receiving pixel P. In addition, at this time t152, the reference signal generating section 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18B (H)).

[0197] Next, at time t153, the driving unit 72 changes the voltage of the control signal SFCG from a low level to a high level ( Fig.18B (F)). This turns on the transistor FCG in the light receiving pixel P. In addition, the comparison circuit 24 sets the operating point based on the control signal AZSW during the period from time t153 to t154.

[0198] Next, at time t154, the comparison circuit 24 completes the setting of the operating point. In addition, at time t154, the reference signal generation unit 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18A (H)).

[0199] Therefore, if Fig.19CAs shown, in the light receiving pixel P, transistors FDG, FCG and SEL are turned on, and all other transistors are turned off. Transistors FDG and FCG are turned on, which makes the floating diffusion FD, transistors FDG and FCG and capacitor FC form a combined capacitance (conversion capacitance). The conversion capacitance holds the charge generated by the photodiode PD2 before time t153, and is supplied to the capacitor FC via the transistor TGS and accumulated therein. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP5) corresponding to the voltage in the floating diffusion FD at that time.

[0200] Next, during the period from time t155 to t157 (conversion period T5), the AD converter ADC performs AD conversion based on the pixel voltage VP5. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP5, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE5 ( Fig.18B (J)).

[0201] (Operation at time t161 to t171)

[0202] Then, at time t161, the driving unit 72 changes the voltage of the control signal STGS from a low level to a high level ( Fig.18B (G)). This turns on the transistor TGS in the light receiving pixel P. Therefore, the charge generated by the photodiode PD2 is transferred to the floating diffusion FD and the capacitor FC. In addition, at this time t161, the reference signal generating unit 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18B (H)).

[0203] Next, at time t162, the driving unit 72 changes the voltage of the control signal STGS from the high level to the low level ( Fig.18B This turns off the transistor TGS in the light receiving pixel P.

[0204] Therefore, if Fig.19C As shown, in the light receiving pixel P, the transistors FDG and FCG are turned on, which makes the floating diffusion FD, the transistors FDG, FCG and the capacitor FC constitute a combined capacitance (conversion capacitance). In addition to the charge generated by the photodiode PD2 before the time t53 and supplied to the capacitor FC via the transistor TGS and accumulated therein, the conversion capacitance also holds the charge transferred from the photodiode PD2 at the time t161 to t162. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP6) corresponding to the voltage in the floating diffusion FD at that time.

[0205] Next, during the period from time t163 to t165 (conversion period T6), the AD converter ADC performs AD conversion based on the pixel voltage VP6. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP6, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE6 ( Fig.18B (J)). This digital code CODE6 corresponds to the digital code CODE5 obtained when the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance.

[0206] (Operation at time t171 to t181)

[0207] Thereafter, the comparison circuit 24 sets the operating point based on the control signal AZSW during a period from time t171 to time t172.

[0208] Next, at time t172, the comparison circuit 24 completes the setting of the operating point and electrically separates the positive input terminal and the negative input terminal from each other. In addition, at time t72, the reference signal generation unit 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18B (H)).

[0209] Therefore, if Fig.19C As shown, in the light receiving pixel P, the transistors FDG and FCG are turned on, which makes the floating diffusion FD, the transistors FDG, FCG and the capacitor FC constitute a combined capacitance (conversion capacitance). In addition to the charge generated by the photodiode PD2 before the time t153 and supplied to the capacitor FC via the transistor TGS and accumulated therein, the conversion capacitance also holds the charge transferred from the photodiode PD2 at the time t161 to t162. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP7) corresponding to the voltage in the floating diffusion FD at that time.

[0210] Next, during the period from time t173 to t175 (conversion period T7), the AD converter ADC performs AD conversion based on the pixel voltage VP7. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP7, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE7 ( Fig.18B (J)).

[0211] (Operation at time t181 to t191)

[0212] Next, at time t181, the driving unit 72 changes the voltage of the control signal SRST from a low level to a high level ( Fig.18B (C)). This turns on the transistor RST in the light receiving pixel P. The transistors FDG and FCG are turned on, which sets the voltage of the floating diffusion FD and the voltage of the capacitor FC to the power supply voltage VDDH and resets the floating diffusion FD and the capacitor FC.

[0213] Next, at time t182, the driving unit 72 changes the voltage of the control signal SFCG from the high level to the low level ( Fig.18B This turns off the transistor FCG in the light receiving pixel P.

[0214] Next, at time t183, the driving unit 72 changes the voltage of the control signal SRST from the high level to the low level ( Fig.18B This turns off the transistor RST in the light receiving pixel P.

[0215] Next, at time t184, the driving unit 72 changes the voltage of the control signal SFCG from a low level to a high level ( Fig.18B This turns on the transistor FCG in the light receiving pixel P. In addition, at this time t184, the reference signal generating section 16 changes the voltage of the reference signal RAMP to the voltage V1 ( Fig.18B (H)).

[0216] Therefore, if Fig.19C As shown, in the light receiving pixel P, the transistors FDG and FCG are turned on, which makes the floating diffusion FD, the transistors FDG, FCG and the capacitor FC form a combined capacitance (conversion capacitance). When the floating diffusion FD and the capacitor FC are reset in time t181-t182, the conversion capacitance holds the charge. The light receiving pixel P outputs a pixel voltage VP (pixel voltage VP8) corresponding to the voltage in the floating diffusion FD at that time.

[0217] Next, during the period from time t185 to t187 (conversion period T8), the AD converter ADC performs AD conversion based on the pixel voltage VP8. This operation is similar to the operation in the conversion period T1. The AD converter ADC performs AD conversion based on the pixel voltage VP8, and the latch 26 of the AD converter ADC holds the count value CNT of the counter 25 and outputs the held count value CNT as the digital code CODE8 ( Fig.18B (J)). This digital code CODE8 corresponds to the digital code CODE7 obtained when the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance.

[0218] Next, at time t191, the driving unit 72 changes the voltage of the control signal SFDG from a high level to a low level, and changes the voltage of the control signal SFCG from a low level to a high level ( Fig.18B (D) and (F)). This disconnects the transistors FDG and FCG in the light receiving pixel P.

[0219] Thereafter, at time t192, the driving unit 72 changes the voltage of the control signal SSEL from a high level to a low level ( Fig.18B (B)). This turns off the transistor SEL in the light-receiving pixel P, and the light-receiving pixel P is electrically separated from the signal line VSL.

[0220] Next, a description is given of image synthesis processing in the signal processing section 77. The signal processing section 77 generates four images PIC (images PIC1 to PIC4) based on the digital code CODE supplied from the readout section 20. Thereafter, the signal processing section 77 synthesizes the four images PIC to generate one captured image PICA.

[0221] Fig. 20 The image synthesis process is schematically illustrated. Fig. 20 The waveforms shown in (A) to (G) are similar to Fig.17 The waveforms shown in (A) to (G) are the same. Fig.17 , Fig.18A and Fig.18B As described above, the readout unit 20 generates the digital code CODE1 based on the operation during the period from time t111 to t121, generates the digital code CODE2 based on the operation during the period from time t121 to t131, generates the digital code CODE3 based on the operation during the period from time t131 to t141, generates the digital code CODE4 based on the operation during the period from time t141 to t151, generates the digital code CODE5 based on the operation during the period from time t151 to t161, generates the digital code CODE6 based on the operation during the period from time t161 to t171, generates the digital code CODE7 based on the operation during the period from time t171 to t181, and generates the digital code CODE8 based on the operation during the period from time t181 to t191.

[0222] The signal processing unit 77 generates a pixel value VAL1 based on the digital code CODE2 and the digital code CODE3. Specifically, the signal processing unit 77 calculates the pixel value VAL1 by subtracting the digital code CODE2 from the digital code CODE3 (CODE3-CODE2). That is, the imaging device 2 uses the correlated double sampling principle to calculate the pixel value VAL1 using the digital code CODE2 corresponding to the P phase (pre-charge phase) data and the digital code CODE3 corresponding to the D phase (data phase) data.

[0223] Similarly, the signal processing unit 77 generates a pixel value VAL2 based on the digital code CODE1 and the digital code CODE4. Specifically, the signal processing unit 77 calculates the pixel value VAL2 (CODE4-CODE1) by subtracting the digital code CODE1 from the digital code CODE4. That is, the imaging device 2 uses the correlated double sampling principle to calculate the pixel value VAL2 using the digital code CODE1 corresponding to the P-phase data and the digital code CODE4 corresponding to the D-phase data.

[0224] Similarly, the signal processing unit 77 generates a pixel value VAL3 based on the digital code CODE5 and the digital code CODE6. Specifically, the signal processing unit 77 calculates the pixel value VAL3 by subtracting the digital code CODE5 from the digital code CODE6 (CODE6-CODE5). That is, the imaging device 2 uses the correlated double sampling principle to calculate the pixel value VAL3 using the digital code CODE5 corresponding to the P-phase data and the digital code CODE6 corresponding to the D-phase data.

[0225] After that, the signal processing section 77 generates the pixel value VAL4 based on the digital code CODE7 and the digital code CODE8. Specifically, the signal processing section 77 calculates the pixel value VAL4 by subtracting the digital code CODE8 from the digital code CODE7 (CODE7-CODE8). That is, the imaging device 2 calculates the pixel value VAL4 using the digital code CODE7 before resetting the floating diffusion FD and the capacitor FC and the digital code CODE8 after resetting the floating diffusion FD and the capacitor FC using the so-called double data sampling (DDS) principle.

[0226] Then, the signal processing section 77 generates an image PIC1 based on the pixel value VAL1 of all the light receiving pixels P in the pixel array 71, generates an image PIC2 based on the pixel value VAL2 of all the light receiving pixels P in the pixel array 71, generates an image PIC3 based on the pixel value VAL3 of all the light receiving pixels P in the pixel array 71, and generates an image PIC4 based on the pixel value VAL4 of all the light receiving pixels P in the pixel array 71. Then, the signal processing section 77 synthesizes these images PIC1 to PIC4, thereby generating a captured image PICA.

[0227] In the imaging device 2, as Fig. 20 As shown, the readout section 20 outputs the digital codes CODE2 and CODE3, and the signal processing section 77 calculates the pixel value VAL1 by subtracting the digital code CODE2 from the digital code CODE3 (CODE3-CODE2), but this is not restrictive. Alternatively, the imaging device 1 ( Fig. 9), the readout section 20 can output the digital code CODE corresponding to the difference between the digital codes CODE2 and CODE3 by inverting the polarity of the count value after the conversion period T2. The same applies to the digital codes CODE5 and CODE6, and the same applies to the digital codes CODE7 and CODE8.

[0228] In addition, for example, in the imaging device 2, as Fig. 20 As shown, the readout section 20 outputs digital codes CODE1 and CODE4, and the signal processing section 77 calculates the pixel value VAL2 by subtracting the digital code CODE1 (CODE4-CODE1) from the digital code CODE4, but this is not restrictive. Alternatively, the AD converter ADC of the readout section 20 may temporarily store the count value at that time after the conversion period T1, and may set the stored count value on the counter 25 and invert the polarity of the count value. In this case as well, the signal processing section 77 is able to obtain the digital code CODE corresponding to the difference between the digital codes CODE1 and CODE4.

[0229] (Operation of Noise Correction Section 90)

[0230] The capacitor Cext1 is provided outside the imaging device 2, which easily causes noise to be superimposed on the voltage VRL. The driver section 82 of the driving section 72 uses the voltage VRL as a low-level voltage to generate the control signals STGL, SFDG, SRST, SFCG, STSG, and SSEL. Therefore, for example, in the case where the control signal STGL is at a low level, noise is superimposed on the control signal STGL. The same applies to the control signals SFDG, SRST, SFCG, STSG, and SSEL.

[0231] Therefore, as in the above-mentioned first embodiment, for example, noise corresponding to the noise of the voltage VRL is superimposed on the pixel signal SIG. Specifically, for example, in the light receiving pixel P to be subjected to the readout drive D2, the noise of the voltage VRL is transmitted to the gate of the transistor AMP via the transistors TGL and FDG. Therefore, the light receiving pixel P outputs the pixel signal SIG superimposed with noise. In addition, in the light receiving pixel P not to be subjected to the readout drive D2, the noise of the voltage VRL is transmitted to the source of the transistor SEL via the disconnected transistor SEL. Therefore, the light receiving pixel P causes the noise to be superimposed on the pixel signal SIG generated by the light receiving pixel P to be subjected to the readout drive D2.

[0232] High-pass filter 94 , adjustment circuit 95 , and current source 96 of noise correction section 90 generate a noise correction signal corresponding to the noise superimposed on voltage VRL, and superimpose the noise correction signal on reference signal RAMP generated by reference signal generation section 16 .

[0233] The amplitude and phase of the noise correction signal are pre-adjusted to be approximately the same as the amplitude and phase of the noise associated with the voltage VRL superimposed on the pixel signal SIG. Fig.17 As shown in (K), the amplitude and phase of the noise correction signal are adjusted by adjusting parameter SA during the period from time t111 to t121, by adjusting parameter SB during the period from time t121 to t141, by adjusting parameter SA during the period from time t141 to t151, by adjusting parameter SC during the period from time t151 to t171, and by adjusting parameter SD during the period from time t171 to t191. In other words, the transfer function from the terminal TVRL to the signal line VSL is different between the period from time t111 to t121 and the period from time t141 to t151, the period from time t121 to t141, the period from time t151 to t171, and the period from time t171 to t191. Therefore, the adjustment parameter SA is used during the time periods t111 to t121 and t141 to t151, the adjustment parameter SB is used during the time period t121 to t141, the adjustment parameter SC is used during the time period t151 to t171, and the adjustment parameter SD is used during the time period t171 to t191. The adjustment parameters SA to SD are supplied from the imaging control unit 78.

[0234] In addition, the capacitor Cext2 is provided outside the imaging device 2, which easily causes noise to be superimposed on the voltage VRH. The driver 83 outputs the voltage VRH as the control signal SFCVDD. Therefore, noise is superimposed on the control signal SFCVDD.

[0235] Therefore, for example, noise corresponding to the noise of the voltage VRH is superimposed on the pixel signal SIG. Specifically, in the light receiving pixel P to be read out and driven D2, the noise of the voltage VRH is transmitted to the gate of the transistor AMP via the capacitor FC, the turned-on transistor FCG, and the turned-on transistor FDG. Therefore, the light receiving pixel P outputs the pixel signal SIG superimposed with noise.

[0236] High-pass filter 91 , adjustment circuit 92 , and current source 93 of noise correction section 90 generate a noise correction signal corresponding to the noise superimposed on voltage VRH, and superimpose the noise correction signal on reference signal RAMP generated by reference signal generation section 16 .

[0237] The amplitude and phase of the noise correction signal are pre-adjusted to be approximately the same as the amplitude and phase of the noise associated with the voltage VRH superimposed on the pixel signal SIG. Fig.17As shown in (L), the amplitude and phase of the noise correction signal are adjusted by adjusting parameter SE during the period from time t111 to t121, by adjusting parameter SF during the period from time t121 to t141, by adjusting parameter SE during the period from time t141 to t151, by adjusting parameter SG during the period from time t151 to t171, and by adjusting parameter SH during the period from time t171 to t191. In other words, the transfer function from the terminal TVRH to the signal line VSL is different between the period from time t111 to t121 and the period from time t141 to t151, the period from time t121 to t141, the period from time t151 to t171, and the period from time t171 to t191. Therefore, the adjustment parameter SE is used during the time periods t111 to t121 and t141 to t151, the adjustment parameter SF is used during the time period t121 to t141, the adjustment parameter SG is used during the time period t151 to t171, and the adjustment parameter SH is used during the time period t171 to t191. The adjustment parameters SE to SH are supplied from the imaging control unit 78.

[0238] The image signal SIG on which the noise associated with the voltage VRL and the noise associated with the voltage VRH are superimposed is supplied to the comparison circuit 24 via the capacitor 22. Likewise, the reference signal RAMP on which these noise correction signals are superimposed by the noise correction section 90 is supplied to the comparison circuit 24 via the capacitor 23. The comparison circuit 24 operates based on the difference between the two supplied signals, which reduces the influence of the noise on the signal CP generated by the comparison circuit 24. As a result, in the imaging device 2, the influence of the noise of the voltage VRL and the noise of the voltage VRH on the captured image can be reduced.

[0239] Therefore, the imaging device 2 includes a terminal TVRH connected to the capacitor Cext2 and a bias circuit 74 configured to generate a voltage at the terminal TVRH. The driving section 72 drives the light receiving pixel P based on the voltage at the terminal TVRL and the voltage at the terminal TVRH. The noise correction section 90 generates a noise correction signal based on the voltage at the terminal TVRR and the voltage at the terminal TVRH. Therefore, for example, noise and the noise correction signal in phase with each other are superimposed on the pixel signal SIG and the reference signal RAMP, respectively, which can reduce the influence of the noise of the voltage VRL and the noise of the voltage VRH on the captured image.

[0240] [Modifications]

[0241] In the above embodiment, if Fig.16 As shown, the noise correction section 90 includes two high pass filters 91 and 94, two adjustment circuits 92 and 95, and two current sources 93 and 96, but this is not limitative. Some examples are described in detail below.

[0242] Fig.21 An example of the configuration of an imaging device 2A according to the present modification is shown. The imaging device 2A includes a noise correction section 75A. The noise correction section 75A includes a noise correction section 90A. The noise correction section 90A includes high-pass filters 91 and 94, a switch 97, an adjustment circuit 92, and a current source 93. The high-pass filter 91 is configured to supply a noise signal as an AC component superimposed on a voltage VRH to the switch 97. The high-pass filter 94 is configured to supply a noise signal as an AC component superimposed on a voltage VRL to the switch 97. The switch 97 is configured to supply one of the noise signal supplied from the high-pass filter 91 and the noise signal supplied from the high-pass filter 94 to the adjustment circuit 92 based on an instruction from an imaging control section 78A (described later). The adjustment circuit 92 is configured to adjust the amplitude and phase of the noise signal supplied from the switch 97 based on an instruction from the imaging control section 78A. The current source 93 is configured to convert the noise signal adjusted by the adjustment circuit 92 into a current signal.

[0243] Fig. 22 FIG. 2 shows an example of the configuration of the noise correction unit 90A. In addition to the noise correction unit 90A, Fig. 22 The reference signal generating section 16, the readout section 20, and the imaging control section 78A are also shown. The noise correction section 90A includes capacitors C4 and C5, a switch SW2, capacitors C6 and C7, and a switch SW3. The capacitor C4 corresponds to Fig.21 The high pass filter 91 is shown. Capacitor C5 corresponds to Fig.21 The high pass filter 94 is shown. The switch SW2 corresponds to the switch 97. The resistor element R1, the transistor MN1, the current source CS1, the switch SW1, the resistor element R2, the transistor MN2, the current source CS2, the capacitor C2, the transistor MP1, the capacitors C6 and C7, and the switch SW3 correspond to Fig.21 The regulation circuit 92 shown. Transistor MP2 corresponds to Fig.21 A current source 93 is shown.

[0244] One end of the capacitor C4 is supplied with a voltage VRH, and the other end is connected to the switch SW2. One end of the capacitor C5 is supplied with a voltage VRL, and the other end is connected to the switch SW2. The switch SW2 is configured to connect one of the other end of the capacitor C4 and the other end of the capacitor C5 to the gate of the transistor MN2 and the switch SW1 based on an instruction from the imaging control section 78A. One end of the capacitor C6 is supplied with a voltage VRH, and the other end is connected to the switch SW3. One end of the capacitor C7 is supplied with a voltage VRL, and the other end is connected to the switch SW3. The capacitors C6 and C7 are configured to change the capacity value based on an instruction from the imaging control section 78A. The switch SW3 is configured to connect one of the other end of the capacitor C6 and the other end of the capacitor C7 to the drain of the transistor MP2 based on an instruction from the imaging control section 78A.

[0245] Here, the high-pass filter 94 corresponds to a specific example of the "first high-pass filter" in one embodiment of the present disclosure. The high-pass filter 91 corresponds to a specific example of the "second high-pass filter" in one embodiment of the present disclosure. The switch 97 corresponds to a specific example of the "switch" in one embodiment of the present disclosure. The adjustment circuit 92, the current source 93 and the resistor element 63 correspond to a specific example of the "generation circuit" in one embodiment of the present disclosure.

[0246] Fig.23 An operation example of the imaging device 2A is shown, wherein (A) shows a waveform of the horizontal synchronization signal XHS, (B) shows a waveform of the control signal SSEL, (C) shows a waveform of the control signal SRST, (D) shows a waveform of the control signal SFDG, (E) shows a waveform of the control signal STGL, (F) shows a waveform of the control signal SFCG, (G) shows a waveform of the control signal STGS, (H) shows a waveform of the reference signal RAMP, (I) shows a waveform of the pixel signal SIG, (J) shows the operation of the counter 25, (K) shows an adjustment parameter of the noise correction unit 90A, and (L) shows a voltage to be corrected by the noise correction unit 90A. Fig.23 (A) to (J) and the above-mentioned implementation scheme ( Fig.17 , Fig.18A and Fig.18B ) is similar to (A) to (J).

[0247] For example, during the period from time t111 to time t151 ( Fig.23), as in the above-mentioned first embodiment, the noise corresponding to the noise of the voltage VRL is superimposed on the pixel signal SIG. Specifically, for example, in the light receiving pixel P that is to be subjected to the readout drive D2, the noise of the voltage VRL is transmitted to the gate of the transistor AMP via the transistors TGL and FDG. Therefore, the light receiving pixel P outputs the pixel signal SIG superimposed with the noise. In addition, in the light receiving pixel P that is not to be subjected to the readout drive D2, the noise of the voltage VRL is transmitted to the source of the transistor SEL via the disconnected transistor SEL. Therefore, the light receiving pixel P causes the noise to be superimposed on the pixel signal SIG generated by the light receiving pixel P that is to be subjected to the readout drive D2.

[0248] like Fig.23 As shown in (L), during the period from time t111 to t151, the noise correction unit 90A regards the voltage VRL as the correction target voltage. Specifically, during this period, the switch SW2 connects the other end of the capacitor C5 to the gate of the transistor MN2 and the switch SW1, and the switch SW3 connects the other end of the capacitor C7 to the drain of the transistor MP2. During this period, the noise correction unit 90A generates a noise correction signal corresponding to the noise superimposed on the voltage VRL, and superimposes the noise correction signal on the reference signal RAMP generated by the reference signal generation unit 16. During this period, the noise correction unit 90A does not generate a noise correction signal corresponding to the noise superimposed on the voltage VRH.

[0249] The amplitude and phase of the noise correction signal are pre-adjusted to be approximately the same as the amplitude and phase of the noise associated with the voltage VRL superimposed on the pixel signal SIG. Fig.23 As shown in (K), the amplitude and phase of the noise correction signal are adjusted by the adjustment parameter SI during the period from time t111 to t121, by the adjustment parameter SJ during the period from time t121 to t141, and by the adjustment parameter SI during the period from time t141 to t151. In other words, the transfer function from the terminal TVRL to the signal line VSL is different between the period from time t111 to t121 and the period from time t141 to t151 and the period from time t121 to t141. Therefore, the adjustment parameter SI is used during the period from time t111 to t121 and the period from time t141 to t151, and the adjustment parameter SJ is used during the period from time t121 to t141. The adjustment parameters SI and SJ are supplied from the imaging control unit 78A.

[0250] Therefore, during the period from time t111 to t151, noise and a noise correction signal in phase with each other are respectively superimposed on the pixel signal SIG and the reference signal RAMP to be supplied to the comparison circuit 24. The comparison circuit 24 operates based on the difference between the two supplied signals, which reduces the influence of noise on the signal CP generated by the comparison circuit 24. As a result, in the imaging device 2A, the influence of the noise of the voltage VRL on the captured image can be reduced.

[0251] In addition, for example, during the period from time t151 to time t191 ( Fig.23 ), the noise corresponding to the noise of the voltage VRH is superimposed on the pixel signal SIG. Specifically, for example, in the light receiving pixel P to be subjected to the readout drive D2, the noise of the voltage VRH is transmitted to the gate of the transistor AMP via the capacitor FC, the turned-on transistor FCG, and the turned-on transistor FDG. Therefore, the light receiving pixel P outputs the pixel signal SIG superimposed with the noise.

[0252] like Fig.23 As shown in (L), during the period from time t151 to t191, the noise correction unit 90A regards the voltage VRH as the correction target voltage. Specifically, during this period, the switch SW2 connects the other end of the capacitor C4 to the gate of the transistor MN2 and the switch SW1, and the switch SW3 connects the other end of the capacitor C6 to the drain of the transistor MP2. During this period, the noise correction unit 90A generates a noise correction signal corresponding to the noise superimposed on the voltage VRH, and superimposes the noise correction signal on the reference signal RAMP generated by the reference signal generation unit 16. During this period, the noise correction unit 90A does not generate a noise correction signal corresponding to the noise superimposed on the voltage VRL.

[0253] The amplitude and phase of the noise correction signal are pre-adjusted to be approximately the same as the amplitude and phase of the noise associated with the voltage VRH superimposed on the pixel signal SIG. Fig.23 As shown in (K), the amplitude and phase of the noise correction signal are adjusted by the adjustment parameter SK during the period from time t151 to t171, and are adjusted by the adjustment parameter SL during the period from time t171 to t191. In other words, the transfer function from the terminal TVRH to the signal line VSL is different between the period from time t151 to t171 and the period from time t171 to t191. Therefore, the adjustment parameter SK is used during the period from time t151 to t171, and the adjustment parameter SL is used during the period from time t171 to t191. The adjustment parameters SK and SL are supplied from the imaging control unit 78A.

[0254] Therefore, during the period from time t151 to t191, noise and the noise correction signal in phase with each other are respectively superimposed on the pixel signal SIG and the reference signal RAMP to be supplied to the comparison circuit 24. The comparison circuit 24 operates based on the difference between the two supplied signals, which reduces the influence of noise on the signal CP generated by the comparison circuit 24. As a result, in the imaging device 2A, the influence of the noise of the voltage VRH on the captured image can be reduced.

[0255] Fig.24 An example of the configuration of another imaging device 2B according to the present modification is shown. The imaging device 2B includes a noise correction section 75B. The noise correction section 75B includes a noise correction section 90B. The noise correction section 90B includes a switch 98, a high-pass filter 91, an adjustment circuit 92, and a current source 93. The switch 98 is configured to supply one of the voltage VRH and the voltage VRL to the high-pass filter 91 based on an instruction from the imaging control section 78B. The high-pass filter 91 is configured to supply a noise signal as an AC component superimposed on one of the voltages VRH and VRL supplied from the switch 98 to the adjustment circuit 92. The adjustment circuit 92 is configured to adjust the amplitude and phase of the noise signal supplied from the switch 97 based on an instruction from the imaging control section 78B. The current source 93 is configured to convert the noise signal adjusted by the adjustment circuit 92 into a current signal.

[0256] Fig.25 FIG. 2 shows an example of the configuration of the noise correction unit 90B. In addition to the noise correction unit 90B, Fig.25 The reference signal generation unit 16, the readout unit 20, and the imaging control unit 78B are also shown. The noise correction unit 90B includes a switch SW4. The switch SW4 corresponds to Fig.24 The switch 98 shown. The switch SW4 is configured to supply one of the voltage VRH and the voltage VRL to the capacitors C1 and C2 based on an instruction from the imaging control section 78B.

[0257] Here, the switch 98 corresponds to a specific example of a "switch" in one embodiment of the present disclosure. The high-pass filter 91 corresponds to a specific example of a "high-pass filter" in one embodiment of the present disclosure. The adjustment circuit 92, the current source 93 and the resistor element 63 correspond to a specific example of a "generation circuit" in one embodiment of the present disclosure.

[0258] The operation of the imaging device 2B is similar to that of the imaging device 2A ( Fig.23 ).

[0259] like Fig.23 As shown in (L), during the period from time t111 to t151, the noise correction unit 90B regards the voltage VRL as the correction target voltage. Specifically, during this period, the switch SW4 supplies the voltage VRL to the capacitors C1 and C3. Fig.23 As shown in (K), the amplitude and phase of the noise correction signal are adjusted by adjusting parameter SI during the period from time t111 to t121, by adjusting parameter SJ during the period from time t121 to t141, and by adjusting parameter SI during the period from time t141 to t151.

[0260] In addition, during the period from time t151 to t191, the noise correction unit 90B regards the voltage VRH as the correction target voltage. Specifically, during this period, the switch SW4 supplies the voltage VRH to the capacitors C1 and C3. During the period from time t151 to t171, the amplitude and phase of the noise correction signal are adjusted by the adjustment parameter SK, and during the period from time t171 to t191, they are adjusted by the adjustment parameter SL.

[0261] <3. Application examples of mobile objects>

[0262] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device to be installed on any type of mobile body such as an automobile, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0263] Fig.26 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0264] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.26 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0265] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating the drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, etc.

[0266] The main system control unit 12020 controls the operation of various devices provided in the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, a fog light, etc. In this case, a radio wave transmitted from a portable device or a signal of various switches instead of a key may be input to the main system control unit 12020. The main system control unit 12020 receives the input radio wave or signal and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0267] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a process of detecting an object such as a person, a car, an obstacle, a sign, text on the road, or a process of detecting a distance therefrom.

[0268] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information related to the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays.

[0269] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the state of the driver. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver has fallen asleep.

[0270] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device based on the information related to the inside or outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of the vehicle, following driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0271] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so as to realize automatic driving that allows the vehicle to drive autonomously without relying on the driver's operation.

[0272] In addition, the microcomputer 12051 can output a control instruction to the main system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the positions of the front vehicle or the oncoming vehicle detected by the exterior information detection unit 12030 to perform coordinated control to achieve glare prevention such as switching the high beam to the low beam.

[0273] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or information outside the vehicle. Fig.26 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0274] Fig. 27 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0275] exist Fig. 27 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0276] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are arranged at the positions of the front of the vehicle 12100, the side mirrors, the rear bumper, and the rear door, and the upper side of the windshield in the vehicle. The imaging unit 12101 arranged in the front of the vehicle and the imaging unit 12105 arranged on the upper side of the windshield in the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged in the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 arranged in the rear bumper or the rear door mainly obtains images on the rear of the vehicle 12100. The imaging unit 12105 on the upper side of the windshield in the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0277] By the way, Fig. 27An example of the shooting range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front of the vehicle. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104 on each other, a bird's-eye view image of the vehicle 12100 as seen from above is obtained.

[0278] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0279] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each solid object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed to the vehicle 12100), thereby extracting a solid object located on the driving route of the vehicle 12100, especially the closest solid object, and traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 as the front vehicle. In addition, the microcomputer 12051 can set the distance between the vehicles that is previously ensured in front of the front vehicle, and perform automatic braking control (including tracking travel stop control), automatic acceleration control (including tracking travel start control), etc. Therefore, coordinated control such as automatic driving that aims at autonomous driving of the vehicle without relying on the operation of the driver can be performed.

[0280] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk indicating the degree of danger of collision with each obstacle. When the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062 or performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can assist driving to avoid collisions.

[0281] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian exists in the captured images of the imaging units 12101 to 12104. For example, the identification of the pedestrian is performed by extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points indicating the outline of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that the pedestrian exists in the captured images of the imaging units 12101 to 12104 and thereby identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a quadrilateral contour line for emphasis in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon indicating the pedestrian is displayed at a desired position.

[0282] An example of a vehicle control system to which the technology of the present disclosure is applicable has been described above. The technology of the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. In the imaging device installed on the vehicle, the influence of noise can be reduced, thereby improving the image quality of the captured image. As a result, this allows the vehicle control system 12000 to achieve collision avoidance or collision mitigation of the vehicle, follow-up driving based on the vehicle-to-vehicle distance, vehicle speed maintenance driving function, vehicle collision warning function, vehicle lane departure warning function, etc. with high precision.

[0283] Although the present technology has been described above with reference to some embodiments, modified examples, and specific application examples thereof, the present technology is not limited to these embodiments and the like, and can be modified in various ways.

[0284] For example, in the above-described embodiments, the present technology is applied to an imaging device, but this is not limitative, and the present technology can be applied to various devices that detect light. Fig.28 The distance measuring device 3 to which the present technology is applied is shown in FIG. The distance measuring device 3 is an indirect time-of-flight (ToF) sensor and is configured to measure the distance to the measurement object OBJ. The distance measuring device 3 includes a light emitting unit 101 , an optical system 102 , a light detecting unit 103 , and a control unit 104 .

[0285] The light emitting section 101 is configured to emit a light pulse L0 toward the measuring object OBJ based on an instruction from the control section 104. The light emitting section 101 emits the light pulse L0 by performing a light emitting operation of alternately repeating light emission and non-light emission based on an instruction from the control section 104. For example, the light emitting section 101 includes a light source that emits infrared light. For example, the light source is configured using a laser light source, a light emitting diode (LED), or the like.

[0286] The optical system 102 includes a lens that forms an image on the light receiving surface S of the light detecting section 103. A light pulse (reflected light pulse L1) emitted from the light emitting section 101 and reflected by the measuring object OBJ is incident thereon.

[0287] The light detection section 103 is configured to generate a distance image by detecting light based on an instruction from the control section 104. Each of the plurality of pixel values ​​included in the distance image represents a value related to the distance to the measuring object OBJ. Thereafter, the light detection section 103 outputs the generated distance image as image data DT2.

[0288] The control section 104 is configured to supply control signals to the light emitting section 101 and the light detecting section 103 and control the operations thereof, thereby controlling the operation of the distance measuring device 3 .

[0289] The present technology can also be applied to such a distance measuring device 3. Applying the present technology to the distance measuring device 3 can improve the distance measurement accuracy.

[0290] Note that the effects described herein are merely illustrative and not restrictive, and other effects may also be included.

[0291] Note that the present technology may have the following configurations. According to the present technology having the following configurations, the influence of noise can be reduced.

[0292] (1) An imaging device comprising:

[0293] a light receiving pixel configured to generate a pixel signal including a pixel voltage corresponding to an amount of received light;

[0294] a first connection terminal connected to a first external capacitor;

[0295] a first voltage generating circuit configured to generate a voltage at a first connection terminal;

[0296] a driving circuit configured to drive the light receiving pixel based on a voltage at the first connection terminal;

[0297] a reference signal generating circuit configured to generate a reference signal having a ramp waveform;

[0298] a noise correction circuit configured to generate a noise correction signal corresponding to the voltage at the first connection terminal and configured to superimpose the noise correction signal on the reference signal;

[0299] a comparison circuit configured to compare between the pixel signal and the reference signal on which the noise correction signal is superimposed; and

[0300] A processing circuit is configured to calculate a pixel value based on a comparison result of the comparison circuit.

[0301] (2) The imaging device according to (1), further comprising:

[0302] a second connection terminal connected to a second external capacitor; and

[0303] A second voltage generating circuit is configured to generate a voltage at a second connection terminal, wherein

[0304] The driving circuit is configured to drive the light receiving pixel based on a voltage at the first connection terminal and a voltage at the second connection terminal, and

[0305] The noise correction circuit is configured to generate the noise correction signal based on a voltage at the first connection terminal and a voltage at the second connection terminal.

[0306] (3) The imaging device according to (2), wherein the noise correction circuit is configured to generate the noise correction signal corresponding to one or both of a voltage at the first connection terminal and a voltage at the second connection terminal.

[0307] (4) The imaging device according to any one of (1) to (3), further comprising a control circuit configured to control the operation of the noise correction circuit, wherein

[0308] The noise correction circuit is configured to adjust the noise correction signal based on an adjustment parameter supplied from the control circuit.

[0309] (5) The imaging device according to (4), wherein the adjustment parameter is configured to adjust one or both of an amplitude of the noise correction signal and a phase of the noise correction signal.

[0310] (6) The imaging device according to (3), wherein

[0311] The light receiving pixel is configured to output the pixel signal during a predetermined period.

[0312] The noise correction circuit is configured to generate the noise correction signal corresponding to the voltage at the first connection terminal in a first period within the predetermined period, and

[0313] The noise correction circuit is configured to generate the noise correction signal corresponding to a voltage at the second connection terminal in a second period within the predetermined period.

[0314] (7) The imaging device according to (6), further comprising a control circuit configured to control the operation of the noise correction circuit, wherein

[0315] the noise correction circuit being configured to adjust the noise correction signal based on an adjustment parameter supplied from the control circuit,

[0316] The control circuit is configured to set the adjustment parameter to a first adjustment parameter during a first period, and

[0317] The control circuit is configured to set the adjustment parameter to a second adjustment parameter during a second period.

[0318] (8) The imaging device according to (7), wherein

[0319] The first period includes a first sub-period and a second sub-period,

[0320] The first adjustment parameter includes a first parameter and a second parameter,

[0321] The control circuit is configured to set the adjustment parameter to a first parameter in a first sub-period, and

[0322] The control circuit is configured to set the adjustment parameter to a second parameter in a second sub-period.

[0323] (9) The imaging device according to (3), wherein

[0324] The noise correction circuit includes

[0325] a first high-pass filter that extracts a first noise signal superimposed on the voltage at the first connection terminal,

[0326] a second high pass filter that extracts a second noise signal superimposed on the voltage at the second connection terminal,

[0327] a switch that selects one of the first noise signal and the second noise signal, and

[0328] A generating circuit generates the noise correction signal based on the noise signal selected by the switch.

[0329] (10) The imaging device according to (3), wherein

[0330] The noise correction circuit includes

[0331] a switch that selects one of a voltage at the first connection terminal and a voltage at the second connection terminal,

[0332] a high-pass filter that extracts the noise signal superimposed on the voltage selected by the switch, and

[0333] A generating circuit generates the noise correction signal based on the noise signal.

[0334] (11) The imaging device according to any one of (1) to (10), wherein the first voltage generating circuit includes a charge pump configured to generate a voltage outside a voltage range between a power supply voltage and a ground voltage.

[0335] (12) The imaging device according to any one of (1) to (11), wherein the first voltage generating circuit includes a bias circuit configured to generate a voltage within a voltage range between a power supply voltage and a ground voltage.

[0336] (13) A light detection device comprising:

[0337] a light receiving circuit configured to generate a detection signal including a voltage corresponding to an amount of received light;

[0338] a first connection terminal connected to a first external capacitor;

[0339] a first voltage generating circuit configured to generate a voltage at a first connection terminal;

[0340] a driving circuit configured to drive the light receiving circuit based on a voltage at the first connection terminal;

[0341] a reference signal generating circuit configured to generate a reference signal having a ramp waveform;

[0342] a noise correction circuit configured to generate a noise correction signal corresponding to the voltage at the first connection terminal and configured to superimpose the noise correction signal on the reference signal;

[0343] a comparison circuit configured to compare between the detection signal and the reference signal on which the noise correction signal is superimposed; and

[0344] A processing circuit is configured to calculate a detection value based on a comparison result of the comparison circuit.

[0345] This application claims the benefit of Japanese Priority Patent Application JP2022-111406 filed in the Japan Patent Office on Jul. 11, 2022, the entire contents of which are incorporated herein by reference.

[0346] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made according to design requirements and other factors as long as they are within the scope of protection of the appended claims or the equivalents thereof.

Claims

1. An imaging device, comprising: a light receiving pixel configured to generate a pixel signal including a pixel voltage corresponding to an amount of received light; a first connection terminal connected to a first external capacitor; a first voltage generating circuit configured to generate a voltage at the first connection terminal; a driving circuit configured to drive the light receiving pixel based on a voltage at the first connection terminal; a reference signal generating circuit configured to generate a reference signal having a ramp waveform; a noise correction circuit configured to generate a noise correction signal corresponding to the voltage at the first connection terminal and configured to superimpose the noise correction signal on the reference signal; a comparison circuit configured to compare between the pixel signal and the reference signal on which the noise correction signal is superimposed; and A processing circuit is configured to calculate a pixel value based on the comparison result of the comparison circuit.

2. The imaging device according to claim 1, further comprising: a second connection terminal connected to a second external capacitor; and A second voltage generating circuit is configured to generate a voltage at a second connection terminal, wherein The driving circuit is configured to drive the light receiving pixel based on a voltage at the first connection terminal and a voltage at the second connection terminal, and The noise correction circuit is configured to generate the noise correction signal based on a voltage at the first connection terminal and a voltage at the second connection terminal. 3 . The imaging device according to claim 2 , wherein the noise correction circuit is configured to generate the noise correction signal corresponding to one or both of a voltage at the first connection terminal and a voltage at the second connection terminal.

4. The imaging device according to claim 1, further comprising a control circuit configured to control the operation of the noise correction circuit, wherein The noise correction circuit is configured to adjust the noise correction signal based on an adjustment parameter supplied from the control circuit. 5 . The imaging device according to claim 4 , wherein the adjustment parameter is configured to adjust one or both of an amplitude of the noise correction signal and a phase of the noise correction signal.

6. The imaging device according to claim 3, wherein The light receiving pixel is configured to output the pixel signal during a predetermined period. The noise correction circuit is configured to generate the noise correction signal corresponding to the voltage at the first connection terminal in a first period within the predetermined period, and The noise correction circuit is configured to generate the noise correction signal corresponding to a voltage at the second connection terminal in a second period within the predetermined period.

7. The imaging device according to claim 6, further comprising a control circuit configured to control the operation of the noise correction circuit, wherein the noise correction circuit being configured to adjust the noise correction signal based on an adjustment parameter supplied from the control circuit, The control circuit is configured to set the adjustment parameter to a first adjustment parameter during a first period, and The control circuit is configured to set the adjustment parameter to a second adjustment parameter during a second period.

8. The imaging device according to claim 7, wherein The first period includes a first sub-period and a second sub-period, The first adjustment parameter includes a first parameter and a second parameter, The control circuit is configured to set the adjustment parameter to a first parameter in a first sub-period, and The control circuit is configured to set the adjustment parameter to a second parameter in a second sub-period.

9. The imaging device according to claim 3, wherein The noise correction circuit includes a first high-pass filter that extracts a first noise signal superimposed on the voltage at the first connection terminal, a second high pass filter that extracts a second noise signal superimposed on the voltage at the second connection terminal, a switch that selects one of the first noise signal and the second noise signal, and A generating circuit generates the noise correction signal based on the noise signal selected by the switch.

10. The imaging device according to claim 3, wherein The noise correction circuit includes a switch that selects one of a voltage at the first connection terminal and a voltage at the second connection terminal, a high-pass filter that extracts the noise signal superimposed on the voltage selected by the switch, and A generating circuit generates the noise correction signal based on the noise signal. 11 . The imaging device according to claim 1 , wherein the first voltage generating circuit comprises a charge pump configured to generate a voltage outside a range of a voltage between a power supply voltage and a ground voltage. 12 . The imaging device according to claim 1 , wherein the first voltage generating circuit comprises a bias circuit configured to generate a voltage within a voltage range between a power supply voltage and a ground voltage.

13. A light detection device, comprising: a light receiving circuit configured to generate a detection signal including a voltage corresponding to an amount of received light; a first connection terminal connected to a first external capacitor; a first voltage generating circuit configured to generate a voltage at the first connection terminal; a driving circuit configured to drive the light receiving circuit based on a voltage at the first connection terminal; a reference signal generating circuit configured to generate a reference signal having a ramp waveform; a noise correction circuit configured to generate a noise correction signal corresponding to the voltage at the first connection terminal and configured to superimpose the noise correction signal on the reference signal; a comparison circuit configured to compare between the detection signal and the reference signal on which the noise correction signal is superimposed; and A processing circuit is configured to calculate a detection value based on a comparison result of the comparison circuit.

Images