A method and system for defect detection and location in multilayer packaged semiconductor devices.

Abstract

This invention belongs to the field of device testing and localization technology, specifically relating to a method and system for defect detection and localization of stacked packaged semiconductor devices, aiming to solve the problem of difficulty in locating defects in stacked packaged semiconductor devices. The method includes: acquiring the structural and material parameters of the failed stacked packaged semiconductor device; if the stacked packaged semiconductor device is a ceramic package, it is prepared, ground, and then non-destructively removed and an excitation signal is applied; if it is a plastic package, an excitation signal is directly applied; acquiring the side temperature of the stacked packaged semiconductor device to determine the position of the defect in the X-axis-Z-axis plane; constructing a temperature-time series, performing a Fourier transform to calculate the phase angle, and obtaining the defect phase difference-frequency relationship; using a heat conduction algorithm to establish a Y-axis depth defect solution model, and combining the defect phase difference-frequency relationship to determine the defect location. This invention improves the accuracy of defect detection and localization.

Description

Technical Field

[0001] This invention belongs to the field of device testing and positioning technology, specifically relating to a method and system for defect detection and positioning of stacked packaged semiconductor devices. Background Technology

[0002] As Moore's Law gradually slows down, semiconductor devices are facing severe challenges brought about by the development trends of multifunctionality, miniaturization, portability, high speed, and low power consumption. The industry recognizes three-dimensional stacked packaging as the best solution to expand the application of high-density semiconductor devices, including stacked bare chips, package stacking, and through-silicon via interconnects, which promotes the development of highly integrated and multifunctional electronic products.

[0003] However, during failure analysis, when using phase-locked thermal imaging for Z-axis positioning of stacked packaged semiconductor devices (such as staggered stacked types), the positioning deviation of defects at the edge of multi-layer chips is large, making it difficult to determine which layer of the chip the failure occurred on, which brings great difficulties to failure analysis.

[0004] Therefore, accurately detecting and locating defects at the edge of stacked packaged semiconductor devices has become a pressing problem. Based on this, this invention proposes a method for defect detection and location in stacked packaged semiconductor devices. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, specifically the difficulty in locating defects in stacked packaged semiconductor devices, particularly chip edge defects, the present invention, in its first aspect, proposes a method for defect detection and location in stacked packaged semiconductor devices, comprising:

[0006] S100: Obtain the structural and material parameters of the failed multilayer packaged semiconductor device; if the multilayer packaged semiconductor device is a plastic packaged device, proceed to S400; if the multilayer packaged semiconductor device is a ceramic packaged device, proceed to S200.

[0007] S200, after preparing the sample of the stacked packaged semiconductor device, the sample is ground;

[0008] S300, the stacked packaged semiconductor device is removed from the polished sample without damage;

[0009] S400, apply an excitation signal to the failure internal pressure point of the stacked packaged semiconductor device to generate a heat source; control the frequency of the excitation signal to change the heating frequency of the heat source;

[0010] S500, collect the side temperature of the stacked packaged semiconductor device to obtain the location of the heat source of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then determine the location of the defect in the X-axis-Z-axis plane;

[0011] S600: Based on the collected side temperature and the corresponding time, a temperature-time series is constructed; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship;

[0012] S700, based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

[0013] In some preferred embodiments, after the multilayer packaged semiconductor device is sampled, it is ground. The method is as follows: after the multilayer packaged semiconductor device is sampled with resin, the sides of the multilayer packaged semiconductor device are ground and the packaging of at least two opposite sides is removed to expose the chip.

[0014] In some preferred embodiments, when grinding the sides of the stacked packaged semiconductor device, a grinding wheel with a roughness of 200 to 400 grit is used to quickly remove the ceramic shell.

[0015] In some preferred embodiments, the stacked packaged semiconductor device is removed from the polished sample without damage, by means of:

[0016] Heat the resin sample after grinding to a temperature of 150℃~180℃ for 20~30 minutes; then remove the heated resin sample and place it in an ice-water mixture for 1~2 minutes to cool it down quickly.

[0017] After repeating the heating and cooling process a set number of times, the stacked packaged semiconductor device is removed from the resin.

[0018] After removal, the stacked packaged semiconductor device is subjected to three ultrasonic cleanings. The ultrasonic cleaning frequency is set to 20kHz to 40kHz, and the cleaning solutions are acetone, alcohol and pure water, respectively. Each ultrasonic cleaning lasts for 3 to 5 minutes to remove residual resin.

[0019] In some preferred embodiments, when an excitation signal is applied to the failure internal pressure point of the stacked packaged semiconductor device, the defect heating power is 100uW to 1mW, and the heat source heating frequency is 0.5Hz to 20Hz.

[0020] In some preferred embodiments, the side temperature of the stacked packaged semiconductor device is collected by means of:

[0021] The side temperature of the stacked packaged semiconductor device is collected by an infrared detector, the lens of which is parallel to the horizontal plane.

[0022] In some preferred embodiments, when the side temperature of the stacked packaged semiconductor device is collected by an infrared detector, at least four temperature points are collected in each excitation cycle, and the integration time is not less than 1 minute.

[0023] In some preferred embodiments, the phase angle is calculated after the Fourier transform of the temperature-time series, using the following method:

[0024] The temperature-time series is subjected to a Fourier transform. After the transform, the phase angle is calculated using the real and imaginary parts of the complex signal.

[0025]

[0026] Where Φ(ω) represents the phase angle, ImF(ω) represents the imaginary part of the complex signal, and ReF(ω) represents the real part of the complex signal.

[0027] In some preferred embodiments, the location of the defect is determined by:

[0028] Based on the established three-dimensional Cartesian coordinate system, the positions of the X and Z axes, as well as the minimum increment ΔY in the Y direction, are obtained. Then, the geometric structure model of the heat conduction path of the excitation signal at different positions is analyzed to confirm the material and related properties at different Y values.

[0029] Based on the material and related properties at different Y values, and using the heat conduction algorithm, the phase deviation of the geometric model at different positions on the Y-axis in the plane formed by the X and Z axes is calculated:

[0030]

[0031] Where θ represents the phase deviation, i is the number, i.e., the quantity of material, n is the upper limit of the value of i, and ρ i C is the material density. i κ is the specific heat capacity of the material. i Y represents the thermal conductivity of the material. i Here, f is the material thickness value, and f is the frequency of the excitation signal;

[0032] On the same plane formed by the X and Z axes, when the phase deviations obtained by S600 and S700 are equal, the position on the Y axis corresponding to the phase deviation in the heat conduction model is the defect position.

[0033] In a second aspect, the present invention provides a defect detection and localization system for multilayer packaged semiconductor devices. The system includes: an excitation signal source, a probe, a microscope, a localization plate, a test platform, a computer, and an infrared detector; the microscope, the infrared detector, and the excitation signal source are all communicatively linked to the computer.

[0034] The excitation signal source is used to generate an excitation signal and apply voltage by contacting the failure internal pressure point of the stacked packaged semiconductor device through the probe;

[0035] The microscope includes an optical microscope for observing the probe when a voltage is applied;

[0036] The infrared detector is used to collect the side temperature of the stacked packaged semiconductor device;

[0037] The positioning piece is fixed on the test platform, and the positioning piece is used to fix the stacked packaged semiconductor device;

[0038] The sample preparation and grinding unit is used to grind the multilayer packaged semiconductor device after sample preparation, and to remove the multilayer packaged semiconductor device from the ground sample without damage.

[0039] The computer is used to acquire the structural and material parameters of the failed multilayer packaged semiconductor device, control the excitation signal source to apply an excitation signal to the failure internal pressure point of the multilayer packaged semiconductor device to generate a heat source, and control the frequency of the excitation signal to change the heating frequency of the heat source.

[0040] The infrared detector is controlled to collect the side temperature of the stacked packaged semiconductor device to obtain the heat source position of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then the position of the defect in the X-axis-Z-axis plane is determined.

[0041] The side temperature and corresponding time collected by the infrared detector are controlled to construct a temperature-time series; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship;

[0042] Based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

[0043] The beneficial effects of this invention are:

[0044] This invention improves the accuracy of defect detection and location.

[0045] 1) Based on the properties of resin, this invention uses an oven to heat and a mixture of ice and water to rapidly cool the resin, thereby denaturing it and allowing for the non-destructive removal of metallographic samples. This ensures efficiency while avoiding damage to the samples caused by traditional sampling methods and reducing environmental pollution from organic reagents.

[0046] 2) When performing hotspot localization and analysis on the device from the side, this invention uses a positioning plate to assist in sample placement, effectively saving time consumed in the detection and localization process;

[0047] 3) This invention establishes a heat conduction model at any location within the geometric model to obtain the phase deviation generated by excitation signals of different frequencies. Combined with thermal infrared technology, the position on the Y-axis is determined, reducing the destructive testing step of opening the plastic-encapsulated device and optimizing the destructive test into a non-destructive test. This avoids damage to the plastic-encapsulated multilayer device and effectively improves the success rate of defect detection and location. Compared with existing technologies, it has higher accuracy in detecting defects located on the bottom layer of the chip and at the edge, especially for ceramic-packaged devices. Attached Figure Description

[0048] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0049] Figure 1 This is a flowchart illustrating a method for defect detection and location in a multilayer packaged semiconductor device according to an embodiment of the present invention.

[0050] Figure 2 This is a cross-sectional structural diagram of an interleaved stacked package device according to an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of non-destructive sampling of resin according to an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of a defect detection and location system for a multilayer packaged semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0054] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0055] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0056] A method for defect detection and localization of a multilayer packaged semiconductor device according to a first embodiment of the present invention includes the following steps:

[0057] S100: Obtain the structural and material parameters of the failed multilayer packaged semiconductor device; if the multilayer packaged semiconductor device is a plastic packaged device, proceed to S400; if the multilayer packaged semiconductor device is a ceramic packaged device, proceed to S200.

[0058] S200, after preparing the sample of the stacked packaged semiconductor device, the sample is ground;

[0059] S300, the stacked packaged semiconductor device is removed from the polished sample without damage;

[0060] S400, apply an excitation signal to the failure internal pressure point of the stacked packaged semiconductor device to generate a heat source; control the frequency of the excitation signal to change the heating frequency of the heat source;

[0061] S500, collect the side temperature of the stacked packaged semiconductor device to obtain the location of the heat source of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then determine the location of the defect in the X-axis-Z-axis plane;

[0062] S600: Based on the collected side temperature and the corresponding time, a temperature-time series is constructed; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship;

[0063] S700, based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

[0064] To more clearly illustrate the defect detection and location method for a multilayer packaged semiconductor device according to the present invention, the following description is in conjunction with the accompanying drawings. Figure 1 The steps of one embodiment of the method of the present invention will be described in detail below.

[0065] This invention provides a method for accurately locating the chip layer where defects are located, solving the problem of difficult defect location in multilayer packaged semiconductor devices, especially defects at chip edges. This invention is applicable to ceramic and plastic packaged multilayer chip packaging. The types of multilayer packaged semiconductor devices include, but are not limited to, integrated circuits, and the stacking types include, but are not limited to, same-size stacking, staggered stacking, and pyramid stacking. It can significantly improve the accuracy of defect detection and location, and avoids the step of opening the plastic package during defect location. Details are as follows:

[0066] S100: Obtain the structural and material parameters of the failed multilayer packaged semiconductor device; if the multilayer packaged semiconductor device is a plastic packaged device, proceed to S400; if the multilayer packaged semiconductor device is a ceramic packaged device, proceed to S200.

[0067] In this embodiment, the structural parameters and material parameters include the dimensional parameters of each structure, and the density, thermal conductivity, and specific heat capacity parameters of each material.

[0068] S200, after preparing the sample of the stacked packaged semiconductor device, the sample is ground;

[0069] In this embodiment, the resin (preferably thermosetting epoxy resin in this invention) and curing agent are preferably mixed in a 7:3 ratio and then added to the mold, which is then placed in a low vacuum environment of 0.1 Pa to 10 Pa for 12 hours for curing. After metallographic sample preparation of the device, two sides are selected for grinding using a 200-400 mesh roughness grinding wheel to quickly remove the outer shell and expose the chip side.

[0070] S300, the stacked packaged semiconductor device is removed from the polished sample without damage;

[0071] In this embodiment, the resin sample is softened by heating (preferably by placing it in an oven); the oven temperature is 150℃~180℃, and the heating time is 20~30 minutes; after the softened resin sample is removed from the oven, it is immersed in an ice-water mixture for 1~2 minutes for rapid cooling, and the resin hardens. This process is repeated a set number of times (preferably three times in this invention), causing the resin to denature and become brittle, allowing the stacked packaged semiconductor device to be easily removed from the resin with a small amount of external force. The stacked packaged semiconductor device is further subjected to three ultrasonic cleanings using acetone, alcohol, and pure water as cleaning solutions, with the ultrasonic cleaning frequency set to 20kHz~40kHz and the cleaning time 3~5 minutes each time, to remove residual resin.

[0072] S400, apply an excitation signal to the failure internal pressure point of the stacked packaged semiconductor device to generate a heat source; control the frequency of the excitation signal to change the heating frequency of the heat source;

[0073] In this embodiment, the failed stacked packaged semiconductor device is fixed on a platform using a positioning plate. Using a 10x magnifying optical microscope, a probe is brought into contact with the internal pressure point of the device failure and a voltage (i.e., an excitation signal) is applied to generate a heat source, so that the defect heating power is 100uW to 1mW. The frequency of the excitation signal is controlled to change the heating frequency of the heat source, and the frequency can be adjusted in the range of 0.5 to 20Hz.

[0074] S500, collect the side temperature of the stacked packaged semiconductor device to obtain the location of the heat source of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then determine the location of the defect in the X-axis-Z-axis plane;

[0075] In this embodiment, the side temperature of the device is collected by an infrared detector (i.e., phase-locked thermal imaging). At least four temperature points are collected in each excitation cycle, and the integration time is not less than 1 minute. The infrared detector lens is parallel to the horizontal plane. The device under test is placed based on the positioning plate. The position of the device under test and the infrared lens is adjusted by a mechanical device to obtain the heat source position information of the sample under test on the plane formed by the X-axis and Z-axis, and the position of the defect in the X-axis-Z-axis plane (i.e., the chip layer where the defect is located) is determined. In this invention, the infrared detector lens can be adjusted up and down, left and right, and forward and backward, and the detection lens can be selected with 1x, 4x, or 10x magnification.

[0076] S600: Based on the collected side temperature and the corresponding time, a temperature-time series is constructed; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship;

[0077] In this embodiment, the defect phase-frequency relationship is obtained by computer according to the surface temperature processing algorithm. During the temperature acquisition process of infrared camera, the sample surface temperature is recorded once every 3ms by default, and the total acquisition time is not less than 1 minute, forming a temperature-time series.

[0078] Perform a Fourier transform on the recorded temperature-time series, i.e.:

[0079] F(ω)=A(ω)e jΦ(ω)

[0080] In the formula, A(ω) is the amplitude and Φ(ω) is the phase angle.

[0081] The phase angle can be obtained by calculating the real and imaginary parts of the complex signal, that is:

[0082]

[0083] Where Φ(ω) represents the phase angle, ImF(ω) represents the imaginary part of the complex signal, and ReF(ω) represents the real part of the complex signal.

[0084] S700, based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

[0085] In this embodiment, based on the established three-dimensional Cartesian coordinate system (i.e., the three-dimensional Cartesian coordinate system constructed in this invention), the X-axis and Z-axis positions, and the minimum increment ΔY in the Y-axis direction are obtained. Geometric structural model analysis is performed on the heat conduction path of the excitation signal at different positions. For example, for a device with a Y-axis length of 1000 μm, given X = 50 μm, Z = 50 μm, and ΔY = 50 μm, the following analysis is performed at X = 50 μm and Z = 50 μm for Y = 1*ΔY = 50 μm, Y = 2*ΔY = 100 μm, ..., Y = 20*ΔY = 1000 μm, respectively. The material and related properties at different Y values ​​are confirmed, as shown in Table 2. According to the heat conduction algorithm, the phase deviation of the geometric model at different positions on the Y-axis in the plane formed by the X and Z axes is:

[0086]

[0087] Where θ represents the phase deviation, i is the number, i.e., the quantity of material, n is the upper limit of the value of i, and ρ i C is the material density. i κ is the specific heat capacity of the material. i Y represents the thermal conductivity of the material. i denoted as the material thickness, and f as the frequency of the excitation signal.

[0088] On the plane formed by the X-axis and Z-axis, when the phase deviations obtained from the infrared detector test and the model calculation are basically equal (i.e., when the phase deviations obtained from S600 and S700 are equal), the corresponding position on the Y-axis in the heat conduction model is the defect location.

[0089] To facilitate a further understanding of this invention, examples are given below:

[0090] Stacked packaged semiconductor device structure such as Figure 2 As shown, it generally includes a plastic / ceramic shell 1, a chip 2, adhesive 3, an adapter board 4, and a failure point 5, etc. The location defect detection process is as follows:

[0091] Step 1: Analyze the structural and material parameters of the devices, including the dimensional parameters of each structure and the density, thermal conductivity, and specific heat capacity of each material, as shown in Table 1:

[0092] Table 1

[0093]

[0094]

[0095] Step 2: Prepare a sample of the multilayer packaged semiconductor device. The resin component is thermosetting epoxy resin. Mix the resin and curing agent in a 7:3 ratio and add it to the mold. Place the mold in a low vacuum environment of 0.1 Pa to 10 Pa for 12 hours for curing. After metallographic preparation of the device, select two sides for grinding. Use a 200-400 grit grinding wheel to quickly remove the outer shell and expose the chip side.

[0096] Step 3: As Figure 3 As shown, the resin sample was placed in an oven and heated to soften it. The oven temperature was 150℃~180℃, and the heating time was 20~30 minutes. After the softened resin sample was removed from the oven, it was immersed in an ice-water mixture for 1~2 minutes for rapid cooling, and the resin hardened. The above steps were repeated three times. The resin became denatured and brittle, and the stacked packaged semiconductor device could be easily removed from the resin with a small amount of external force. The stacked packaged semiconductor device was further subjected to three ultrasonic cleanings using acetone, alcohol, and pure water, respectively. The ultrasonic cleaning frequency was set to 20kHz~40kHz, and the cleaning time was 3~5 minutes each time to remove residual resin.

[0097] Step 4: Apply an excitation signal to make the defect heating power 100uW~1mW; and control the frequency of the excitation signal to change the heating frequency of the heat source. The frequency can be adjusted in the range of 0.5~20Hz.

[0098] Step 5: As Figure 4 As shown, the side temperature of the device is collected by an infrared detector. The infrared detector lens is parallel to the horizontal plane. The device under test is placed based on the positioning plate. The position of the device under test and the infrared lens are adjusted by a mechanical device to obtain the heat source position information of the sample under test on the plane formed by the X-axis and Z-axis, and the position of the defect in the X-axis-Z-axis plane is determined.

[0099] Step 6: The computer obtains the defect phase-frequency relationship based on the surface temperature processing algorithm. During the infrared camera temperature acquisition process, the sample surface temperature is recorded every 3ms by default, and the total acquisition time is no less than 1 minute, forming a temperature-time series. The recorded temperature-time series is then subjected to a Fourier transform, and the phase angle can be obtained by calculating the real and imaginary parts of the complex signal.

[0100] Step 7: Based on the established three-dimensional Cartesian coordinate system, obtain the X-axis and Z-axis positions, as well as the minimum increment ΔY in the Y-axis direction. Then, perform geometric structural model analysis on the heat conduction path of the excitation signal at different positions to confirm the material and related properties at different Y values.

[0101] Based on the material and related properties at different Y values, and using the heat conduction algorithm, the phase deviation of the geometric model at different positions on the Y axis in the plane formed by the X and Z axes is calculated.

[0102] On the same plane formed by the X and Z axes, when the phase deviations obtained by S600 and S700 are equal, the position on the Y axis corresponding to the phase deviation in the heat conduction model is the defect position.

[0103] In summary, this invention creatively proposes a method for defect detection and localization in stacked packaged semiconductor devices, solving the problem of difficulty in locating defects in stacked packaged semiconductor devices, especially defects at the chip edge. This method is applicable to both ceramic-encapsulated and plastic-encapsulated stacked bare chip packages, such as same-size stacking, staggered stacking, and pyramid stacking. While ensuring efficiency, it avoids the damage to samples caused by plastic-encapsulated stacked devices and traditional sampling methods, reduces environmental pollution from organic reagents, and significantly improves the accuracy of defect detection and localization.

[0104] A defect detection and localization system for multilayer packaged semiconductor devices according to a second embodiment of the present invention includes: an excitation signal source, a probe, a microscope, a localization plate, a test platform, a computer, and an infrared detector. The microscope, the infrared detector, and the excitation signal source are all communicatively linked to the computer. Figure 4 As shown:

[0105] The excitation signal source is used to generate an excitation signal and apply voltage by contacting the failure internal pressure point of the stacked packaged semiconductor device through the probe;

[0106] The microscope includes an optical microscope for observing the probe when a voltage is applied;

[0107] The infrared detector is used to collect the side temperature of the stacked packaged semiconductor device;

[0108] The positioning piece is fixed on the test platform, and the positioning piece is used to fix the stacked packaged semiconductor device;

[0109] The sample preparation and grinding unit is used to grind the multilayer packaged semiconductor device after sample preparation, and to remove the multilayer packaged semiconductor device from the ground sample without damage.

[0110] The computer is used to acquire the structural and material parameters of the failed multilayer packaged semiconductor device; control the excitation signal source to apply an excitation signal to the failure internal pressure point of the multilayer packaged semiconductor device to generate a heat source; control the frequency of the excitation signal to change the heating frequency of the heat source; that is, if the multilayer packaged semiconductor device is a ceramic packaged device, the computer controls the sample preparation and grinding unit to process the multilayer packaged semiconductor device, and after processing, controls the excitation signal source to apply an excitation signal to the failure internal pressure point of the multilayer packaged semiconductor device to generate a heat source; and controls the frequency of the excitation signal to change the heating frequency of the heat source; if the multilayer packaged semiconductor device is a plastic packaged device, the computer controls the excitation signal source to apply an excitation signal to the failure internal pressure point of the multilayer packaged semiconductor device to generate a heat source; and controls the frequency of the excitation signal to change the heating frequency of the heat source.

[0111] The infrared detector is controlled to collect the side temperature of the stacked packaged semiconductor device to obtain the heat source position of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then the position of the defect in the X-axis-Z-axis plane is determined.

[0112] The side temperature and corresponding time collected by the infrared detector are controlled to construct a temperature-time series; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship;

[0113] Based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

[0114] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process and related descriptions of the system described above can be found in the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0115] It should be noted that the defect detection and location system for multilayer packaged semiconductor devices provided in the above embodiments is only an example of the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be further decomposed or combined. For example, the modules in the above embodiments can be merged into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the various modules or steps and are not considered as an improper limitation of the present invention.

[0116] A defect detection and location device for a multilayer packaged semiconductor device according to a third embodiment of the present invention includes at least one processor and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to implement the aforementioned defect detection and location method for a multilayer packaged semiconductor device.

[0117] A fourth embodiment of the present invention provides a computer-readable storage medium storing computer instructions, which are executed by the computer to implement the above-described method for defect detection and location of a multilayer packaged semiconductor device.

[0118] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process and related descriptions of the above-described defect detection and location equipment for multilayer packaged semiconductor devices and readable storage medium can be referred to the corresponding process in the aforementioned method examples, and will not be repeated here.

[0119] Those skilled in the art will recognize that the modules and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. The programs corresponding to the software modules and method steps can be placed in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. To clearly illustrate the interchangeability of electronic hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the invention.

[0120] The terms “first,” “second,” “third,” etc., are used to distinguish similar objects, not to describe or indicate a specific order or sequence.

[0121] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A method for defect detection and location in a multilayer packaged semiconductor device, characterized in that, The method includes: S100: Obtain the structural and material parameters of the failed multilayer packaged semiconductor device; if the multilayer packaged semiconductor device is a plastic packaged device, proceed to S400; if the multilayer packaged semiconductor device is a ceramic packaged device, proceed to S200. S200, the stacked packaged semiconductor device is sampled using resin, and then the sample is ground. S300, the stacked packaged semiconductor device is removed from the polished sample without damage, and the method is as follows: Heat the resin sample after grinding, then remove the heated resin sample and place it in an ice-water mixture to cool it down quickly. After repeating the heating and cooling process a set number of times, the stacked packaged semiconductor device is removed from the resin. After removal, the stacked packaged semiconductor device is subjected to three ultrasonic cleanings using acetone, alcohol, and pure water, respectively, to remove residual resin. S400, apply an excitation signal to the failure internal pressure point of the stacked packaged semiconductor device to generate a heat source; control the frequency of the excitation signal to change the heating frequency of the heat source; S500, collect the side temperature of the stacked packaged semiconductor device to obtain the location of the heat source of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then determine the location of the defect in the X-axis-Z-axis plane; S600: Based on the collected side temperature and the corresponding time, a temperature-time series is constructed; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship; S700, based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

2. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 1, characterized in that, The method for grinding the sample after prototyping the stacked packaged semiconductor device is as follows: after prototyping the stacked packaged semiconductor device with resin, the sides of the stacked packaged semiconductor device are ground and at least two opposite sides of the package are removed to expose the chip.

3. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 2, characterized in that, When grinding the sides of the stacked packaged semiconductor device, a grinding wheel with a roughness of 200-400 grit is used to quickly remove the ceramic shell.

4. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 3, characterized in that, The method for non-destructively removing the stacked packaged semiconductor device from the polished sample is as follows: Heat the resin sample after grinding to 150℃~180℃ for 20~30 minutes; then remove the heated resin sample and place it in an ice-water mixture for 1~2 minutes to cool it down quickly. After repeating the heating and cooling process a set number of times, the stacked packaged semiconductor device is removed from the resin. After removal, the stacked packaged semiconductor device is subjected to three ultrasonic cleanings. The ultrasonic cleaning frequency is set to 20kHz~40kHz, and the cleaning solutions are acetone, alcohol and pure water, respectively. Each ultrasonic cleaning lasts for 3~5 minutes to remove residual resin.

5. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 4, characterized in that, When an excitation signal is applied to the failure internal pressure point of the stacked packaged semiconductor device, the defect heating power is 100uW~1mW, and the heating frequency of the heat source is 0.5Hz~20Hz.

6. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 5, characterized in that, The method for collecting the side temperature of the stacked packaged semiconductor device is as follows: The side temperature of the stacked packaged semiconductor device is collected by an infrared detector, the lens of which is parallel to the horizontal plane.

7. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 6, characterized in that, When collecting the side temperature of the stacked packaged semiconductor device using an infrared detector, at least four temperature points are collected in each excitation cycle, and the integration time is not less than 1 minute.

8. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 6, characterized in that, The method for calculating the phase angle after Fourier transform of the temperature-time series is as follows: The temperature-time series is subjected to a Fourier transform. After the transform, the phase angle is calculated using the real and imaginary parts of the complex signal. ； in, Indicates the phase angle. Represents the imaginary part of a complex signal. It represents the real part of a complex signal.

9. The method for defect detection and location of a multilayer packaged semiconductor device according to claim 6, characterized in that, The method for determining the location of the defect is as follows: Based on the established three-dimensional Cartesian coordinate system, the positions of the X and Z axes, as well as the minimum increment ∆Y in the Y direction, are obtained. Then, the geometric structure model of the heat conduction path of the excitation signal at different positions is analyzed to confirm the material and related properties at different Y values. Based on the material and related properties at different Y values, and using the heat conduction algorithm, the phase deviation of the geometric model at different positions on the Y-axis in the plane formed by the X and Z axes is calculated: ； in, Indicates phase deviation, The number indicates the quantity of materials. for The upper limit of the value, For material density, For the specific heat capacity of the material, For the thermal conductivity of the material, This is the material thickness value. The frequency of the excitation signal; On the same plane formed by the X and Z axes, when the phase deviations obtained by S600 and S700 are equal, the position on the Y axis corresponding to the phase deviation in the heat conduction model is the defect position.

10. A defect detection and location system for multilayer packaged semiconductor devices, characterized in that, The system includes: an excitation signal source, a probe, a microscope, a positioning plate, a test platform, a computer, and an infrared detector; the microscope, the infrared detector, and the excitation signal source are all communicatively linked to the computer. The excitation signal source is used to generate an excitation signal and apply voltage by contacting the failure internal pressure point of the stacked packaged semiconductor device through the probe; The microscope includes an optical microscope for observing the probe when a voltage is applied; The infrared detector is used to collect the side temperature of the stacked packaged semiconductor device; The positioning piece is fixed on the test platform, and the positioning piece is used to fix the stacked packaged semiconductor device; The sample preparation and grinding unit is used to grind the multilayer packaged semiconductor device after sample preparation, and to remove the multilayer packaged semiconductor device from the ground sample without damage. The computer is used to acquire the structural and material parameters of the failed multilayer packaged semiconductor device, control the excitation signal source to apply an excitation signal to the failure internal pressure point of the multilayer packaged semiconductor device to generate a heat source, and control the frequency of the excitation signal to change the heating frequency of the heat source. The infrared detector is controlled to collect the side temperature of the stacked packaged semiconductor device to obtain the heat source position of the stacked packaged semiconductor device on the plane formed by the X-axis and Z-axis, and then the position of the defect in the X-axis-Z-axis plane is determined. The side temperature and corresponding time collected by the infrared detector are controlled to construct a temperature-time series; the phase angle is calculated after Fourier transform of the temperature-time series to obtain the defect phase difference-frequency relationship; Based on the position of the defect in the X-Z plane, the heat conduction algorithm is used to analyze the heat conduction path of the excitation signal at the depth position in the Y-axis direction, establish a Y-axis depth defect solution model, and determine the position of the defect by combining the defect phase difference-frequency relationship.

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