Efficient testing device and method for FPGA processing module
By designing efficient testing devices and methods for FPGA processing modules, using software switching between modules to achieve mutual testing, the problems of aging and high cost of dedicated modules are solved, and an efficient and reliable testing process is achieved.
Patent Information
- Application Number
- CN202411184076.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-01-10
AI Technical Summary
During the testing process of FPGA processing module in harsh environments, the dedicated test module is prone to aging or damage, resulting in unreliable test results and high testing costs.
Design an efficient testing device and method for FPGA processing modules. Through interconnected test racks and control computers, use software switching between FPGA processing modules to achieve mutual testing to avoid the use of special test modules. The test software is responsible for controlling and encouraging Generate and respond to detection.
It realizes efficient testing of zero-accompaniment modules except for passive fixtures, reduces testing costs, improves testing efficiency, and avoids the unreliability and high cost problems caused by dedicated modules.
Smart Images
Figure CN119291449A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of testing technology, and in particular to an efficient testing device and method for an FPGA processing module. Background Art
[0002] During the development and production of FPGA processing modules, it is usually necessary to test the functions and performance of module products in special environments such as high temperature, low temperature, temperature shock, temperature altitude, vibration, impact, damp heat, mold, low pressure, etc. For this purpose, it is usually necessary to develop dedicated test modules to complete test control, stimulus generation, response detection and other functions, and build a dedicated test system. However, these dedicated test modules will inevitably age or be damaged gradually during the "accompanying test" process as they repeatedly experience tests in harsh environments, and their functional performance will no longer be reliable. On the one hand, this may cause unreliable test results, and on the other hand, damaged test modules will also increase the test cost. Summary of the invention
[0003] In view of the problems existing in the prior art, an efficient testing device and method for FPGA processing module are provided. Starting from module product design, test software design, test environment construction, test management and control software design and other aspects, efficient testing with zero "accompanying test modules" except for some passive fixtures is finally achieved.
[0004] The first aspect of the present invention proposes an efficient testing device for an FPGA processing module, comprising an interconnected test rack and a control computer, wherein the test rack comprises at least one pair of interconnected FPGA processing modules A and FPGA processing modules B, wherein both the FPGA processing modules A and the FPGA processing modules B are integrated with functional software and test software; during testing, only the test rack is placed in a test environment, and the control computer switches the software loaded in the FPGA processing modules A and the FPGA processing modules B by issuing control instructions, thereby completing mutual testing between the FPGA processing modules A and the FPGA processing modules B.
[0005] As a preferred solution, the control computer controls the loading of the test software of FPGA processing module A to complete the functional test of FPGA processing module B, or loads the test software of FPGA processing module B to complete the functional test of FPGA processing module A.
[0006] As a preferred solution, the test software at least has the functions of test control, digital stimulus generation and digital response detection.
[0007] As a preferred solution, the test rack includes a motherboard, and the FPGA processing module A and the FPGA processing module B are integrated on the motherboard, and the motherboard provides a clock interface, a power interface, a RF input / output interface and a control interface.
[0008] As a preferred solution, it also includes a test instrument, which is connected to the test rack and the control computer respectively, and the control computer provides power, clock and radio frequency excitation.
[0009] As a preferred solution, the test instrument includes a first signal source, a second signal source, a power supply, a spectrum analyzer and a switch matrix; wherein the first signal source is connected to the clock interface of the motherboard through a power divider to provide a clock signal for each FPGA processing module; the power supply is connected to the power interface of the motherboard to supply power to each FPGA processing module; the second signal source and the spectrum analyzer are respectively connected to the RF input / output interface on the motherboard through the switch matrix to provide RF excitation to each FPGA processing module and receive the RF response of the FPGA processing module to complete RF detection.
[0010] A second aspect of the present invention provides an efficient testing method for an FPGA processing module, comprising:
[0011] Integrate at least one pair of interconnected FPGA processing modules A and FPGA processing modules B into a test rack; wherein each FPGA processing module is converted into a reconfigurable functional software and test software in a memory based on the programmable characteristics of the FPGA;
[0012] Place the test rack in the test environment and connect it to the test instrument and control computer;
[0013] The control computer controls the test instrument to apply RF excitation to each FPGA processing module to be tested in the test rack and receive RF response; and controls the loading of the test software of FPGA processing module A to complete the functional test of FPGA processing module B, or loads the test software of FPGA processing module B to complete the functional test of FPGA processing module A.
[0014] As a preferred solution, the test instrument includes a first signal source, a second signal source, a power supply, a spectrum analyzer and a switch matrix; wherein the first signal source is connected to the clock interface of the motherboard through a power divider to provide a clock signal for each FPGA processing module; the power supply is connected to the power interface of the motherboard to supply power to each FPGA processing module; the second signal source and the spectrum analyzer are respectively connected to the RF input / output interface on the motherboard through the switch matrix to provide RF excitation to each FPGA processing module and receive the RF response of the FPGA processing module to complete RF detection.
[0015] As a preferred solution, the test software generates a digital excitation signal and applies it to the FPGA processing module to be tested, and receives the output digital output signal to complete detection and judgment; the second signal source generates RF excitation and applies it to the FPGA processing module to be tested, and receives the RF output signal through the spectrum analyzer to complete detection and judgment.
[0016] As a preferred solution, the specific sub-steps include:
[0017] Initialize the test instruments and communication interfaces;
[0018] Load the test software of FPGA processing module A and the functional software of FPGA processing module B, select the test items, and complete the test with the test instrument;
[0019] Switch to loading software, load the test software of FPGA processing module B and load the functional software of FPGA processing module A, select the test items, cooperate with the test instrument and complete the test;
[0020] Select Generate Test Report.
[0021] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: the present invention realizes batch "mutual testing" between the FPGA processing modules under test through special design, avoiding the problems of unreliable testing and high testing costs caused by using special "accompanying test" modules, and also greatly improves the testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Schematic diagram of an efficient testing device for an FPGA processing module proposed in the present invention.
[0023] Figure 2 It is a schematic diagram of the FPGA processing module test in one embodiment of the present invention.
[0024] Figure 3 Schematic diagram of the FPGA processing module testing environment in one embodiment of the present invention.
[0025] Figure 4 Flow chart of an efficient testing method for FPGA processing module in one embodiment of the present invention DETAILED DESCRIPTION
[0026] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limitations on the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.
[0027] Example 1
[0028] In order to solve the problem that the test device will gradually age or be damaged and its functional performance will no longer be reliable after repeatedly experiencing the test in the harsh environment during the "accompanying test", the present invention proposes an efficient test device for FPGA processing modules, which utilizes the programmable and reloadable characteristics of FPGA and realizes efficient mutual testing between FPGA processing modules through the controlled online reloading of FPGA processing module programs, thereby greatly reducing the production test cost in mass production and improving production test efficiency. At the same time, through the design of the test rack, the loss of the test device can be effectively reduced.
[0029] Please refer to Figure 1 The efficient test device of the FPGA processing module includes an interconnected test rack and a control computer, wherein the test rack includes at least one pair of interconnected FPGA processing modules A and FPGA processing modules B, wherein both the FPGA processing modules A and B are integrated with functional software and test software. During the test, the test rack only needs to be placed in the environment, and the control computer switches the software loaded in the FPGA processing modules A and B by issuing control instructions, thereby completing the mutual test between the FPGA processing modules A and B.
[0030] In actual testing, mutual testing can be achieved by slightly designing the FPGA program memory to be tested, which basically does not increase the hardware cost. The main functions of the FPGA processing module are implemented by the FPGA software. Based on the programmable characteristics of the FPGA, the functions of the module can be reconfigured by reprogramming. In this embodiment, when designing the FPGA, it should be ensured that the program memory FLASH has sufficient storage space to store both the functional software and the test software, and then the control calculation is used to select whether to load the test software or the functional software.
[0031] In this embodiment, the test process is described by taking the mutually tested FPGA processing module A and FPGA processing module B as an example. When FPGA processing module A is used as the module under test, the module loads the functional software, and at this time, FPGA processing module B loads the test software, and completes the test of FPGA processing module A under the control of the control computer. Afterwards, the control computer executes the switching command, that is, FPGA processing module A loads the test software, FPGA processing module B loads the functional software, and completes the test of FPGA processing module B under the control of the control computer. By exchanging the identities between the two FPGA processing modules, rapid testing between the two modules can be achieved.
[0032] In traditional test systems, a dedicated "companion test" module is generally designed to complete functions such as test control, stimulus generation, and response detection. In this embodiment, the test software is used in the FPGA processing module to be tested to implement functions such as test control, stimulus generation, and response detection, thereby having the ability to test other modules. The test software uses the FPGA processing capability of the FPGA processing module to generate digital stimuli for testing, while receiving and detecting some output signals of the module under test, designing a processing algorithm to determine whether the response function of the module under test is normal, and reporting the test results. The programmable capability of the FPGA chip and the fact that the interface of the FPGA processing module can generally be redefined through FPGA program programming are mainly utilized here.
[0033] In one embodiment, in order to better implement batch testing of FPGA processing modules, the test rack includes a motherboard, on which all FPGA processing modules are arranged, and interconnected in pairs to implement mutual testing. The motherboard is provided with a clock interface, a power interface, a radio frequency input / output interface, and a control interface, etc., which are interconnected with an external test and control computer to complete the reception of instructions and external radio frequency excitation.
[0034] Further, to improve the testing of the FPGA processing module, please refer to Figure 2 , Figure 3 ,During the test, the test instrument is also included to establish a complete test environment.,Among them, the test instrument is connected to the test rack and the control computer respectively, and the control computer and the control provide power, clock and RF excitation.
[0035] For details, please refer to Figure 3 The test instrument includes a first signal source, a second signal source, a power supply, a spectrum analyzer and a switch matrix; wherein the first signal source is connected to the clock interface of the motherboard through a power divider to provide a clock signal for each FPGA processing module; the power supply is connected to the power interface of the motherboard to supply power to each FPGA processing module; the second signal source and the spectrum analyzer are respectively connected to the RF input / output interface on the motherboard through the switch matrix to provide RF excitation to each FPGA processing module and receive the RF response of the FPGA processing module to complete RF detection.
[0036] In actual testing, the test rack only contains the FPGA processing module to be tested, which can improve test efficiency. At the same time, when doing various environmental tests, only simple high-reliability materials such as the test rack and motherboard accompany the target module to participate in harsh environmental tests, which is not easy to cause damage. Signal sources, power dividers, switch matrices, and spectrum analyzers are not placed in the rack and do not need to experience harsh environments.
[0037] For the FPGA processing module to be tested, the test software generates a digital excitation signal, the second signal source in the test instrument provides RF excitation, and is distributed to the FPGA processing module through the switch matrix; the digital output signal generated by the module under test is sent to the test software for detection and judgment, and the generated RF output signal is sent to the spectrum analyzer outside the test rack through the switch matrix for detection and judgment.
[0038] In one embodiment, the control computer is connected to the test rack via a universal interface card to complete the test rack control, which is simple and efficient. The control computer completes the control of all instruments via a GPIB bus.
[0039] In one embodiment, the control computer includes test management and control software, which is used to control the test instrument, the test rack, and the universal interface card, thereby managing the entire test process.
[0040] Due to environmental restrictions such as temperature chambers and vibration tables, a typical test rack can have 8 effective slots, and a typical traditional test solution generally requires at least 1 test module. In one round of testing, the traditional test solution produces 7 target FPGA processing modules, while the test device proposed in the present invention can produce 8 target FPGA processing modules, which improves efficiency by 15%. This process does not calculate the efficiency reduction caused by troubleshooting of the test module and the design cycle of debugging the test module.
[0041] The typical cost of the accompanying test module is calculated at 200,000 yuan. Assuming that it is replaced every 20 rounds of tests, and 140 target FPGA processing modules are produced in 20 rounds of tests, the test cost allocated to each target FPGA processing module increases by about 1,400 yuan. The costs caused by damage to the rack and motherboard, as well as the test software development costs, instrument costs, labor costs, etc., are basically the same for traditional methods and this method. Therefore, for each target FPGA processing module produced, the present invention can save about 1,400 yuan in costs. If 5,000 pieces of a type of FPGA processing module are produced, the present invention can save 7 million yuan in costs. The cost of designing and debugging the accompanying test module is not included here.
[0042] Example 2
[0043] This embodiment proposes an efficient testing method for an FPGA processing module, including: integrating at least one pair of interconnected FPGA processing modules A and FPGA processing modules B into a test rack; wherein each FPGA processing module is converted into a functional software and a test software in a memory based on the programmable characteristics of the FPGA;
[0044] The test rack is placed in a test environment and interconnected with the test instrument and the control computer; the control computer controls the test instrument to apply RF excitation to each FPGA processing module to be tested in the test rack and receive RF response; and controls the loading of the test software of FPGA processing module A to complete the functional test of FPGA processing module B, or loads the test software of FPGA processing module B to complete the functional test of FPGA processing module A.
[0045] During the test process, the test instrument includes a first signal source, a second signal source, a power supply, a spectrum analyzer and a switch matrix; wherein the first signal source is connected to the clock interface of the motherboard through a power divider to provide a clock signal for each FPGA processing module; the power supply is connected to the power interface of the motherboard to supply power to each FPGA processing module; the second signal source and the spectrum analyzer are respectively connected to the RF input / output interface on the motherboard through the switch matrix to provide RF excitation to each FPGA processing module and receive the RF response of the FPGA processing module to complete RF detection.
[0046] Furthermore, the test software generates a digital excitation signal and applies it to the FPGA processing module to be tested, and receives the output digital output signal to complete detection and judgment; the second signal source generates RF excitation and applies it to the FPGA processing module to be tested, and receives the RF output signal through the spectrum analyzer to complete detection and judgment.
[0047] Please refer to Figure 4 , this embodiment proposes a specific control computer control to complete the mutual testing process:
[0048] Step 1: Initialize the test instrument and determine whether it is successful. If so, go to step 2; otherwise, go to step 7.
[0049] Step 2: Initialize the communication interface and determine whether it is successful. If so, proceed to step 3; otherwise, proceed to step 7.
[0050] Step 3: Load the test software of FPGA processing module A and load the functional software of FPGA processing module B. If yes, proceed to step 4; otherwise, proceed to step 7.
[0051] Step 4: Select the test item. In actual testing, various index tests of FPGA processing module A can be completed according to requirements.
[0052] Step 5, load the test software of FPGA processing module B, load the functional software of FPGA processing module A, if yes, go to step 6, otherwise go to step 7.
[0053] Step 6: Select the test item. In actual testing, various index tests of FPGA processing module B can be completed according to requirements.
[0054] Step 7: Determine whether to generate a report. If yes, go to step 8; otherwise, go to step 9.
[0055] Step 8: Generate a test report.
[0056] Step 9, end.
[0057] The testing method proposed in the present invention can realize batch "mutual testing" between the modules under test, avoiding the problems of unreliable testing and high testing costs caused by using a special "accompanying test" module, and also greatly improving the testing efficiency.
[0058] It should be noted that in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "setting" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations.
[0059] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. An efficient testing device for FPGA processing module, characterized in that: The invention comprises an interconnected test rack and a control computer, wherein the test rack comprises at least one pair of interconnected FPGA processing modules A and FPGA processing modules B, wherein both the FPGA processing modules A and FPGA processing modules B are integrated with functional software and test software. During testing, only the test rack is placed in a test environment, and the control computer switches the software loaded in the FPGA processing modules A and FPGA processing modules B by issuing control instructions, thereby completing mutual testing between the FPGA processing modules A and FPGA processing modules B.
2. The efficient testing device for FPGA processing module according to claim 1, characterized in that: The control computer controls the loading of the test software of the FPGA processing module A to complete the functional test of the FPGA processing module B, or loads the test software of the FPGA processing module B to complete the functional test of the FPGA processing module A.
3. The efficient testing device for FPGA processing module according to claim 1 or 2, characterized in that: The test software at least has the functions of test control, digital stimulus generation and digital response detection.
4. The efficient testing device for FPGA processing module according to claim 1 or 2, characterized in that: The test rack includes a motherboard, and the FPGA processing module A and the FPGA processing module B are integrated on the motherboard, and the motherboard provides a clock interface, a power interface, a radio frequency input / output interface, and a control interface.
5. The efficient testing device for FPGA processing module according to claim 4, characterized in that: It also includes a test instrument, which is connected to the test rack and the control computer respectively, and the control computer provides power, clock and radio frequency excitation.
6. The high-efficiency testing device for FPGA processing module according to claim 5, characterized in that: The test instrument includes a first signal source, a second signal source, a power supply, a spectrum analyzer and a switch matrix; wherein the first signal source is connected to the clock interface of the motherboard through a power divider to provide a clock signal for each FPGA processing module; the power supply is connected to the power interface of the motherboard to supply power to each FPGA processing module; the second signal source and the spectrum analyzer are respectively connected to the RF input / output interface on the motherboard through the switch matrix to provide RF excitation to each FPGA processing module and receive the RF response of the FPGA processing module to complete RF detection.
7. An efficient testing method for an FPGA processing module, characterized in that: include: Integrate at least one pair of interconnected FPGA processing modules A and FPGA processing modules B into a test rack; wherein each FPGA processing module is converted into a reconfigurable functional software and test software in a memory based on the programmable characteristics of the FPGA; Place the test rack in the test environment and connect it to the test instrument and control computer; The control computer controls the test instrument to apply RF excitation to each FPGA processing module to be tested in the test rack and receive RF response; and controls the loading of the test software of FPGA processing module A to complete the functional test of FPGA processing module B, or loads the test software of FPGA processing module B to complete the functional test of FPGA processing module A.
8. The efficient testing method for FPGA processing module according to claim 7, characterized in that: The test instrument includes a first signal source, a second signal source, a power supply, a spectrum analyzer and a switch matrix; wherein the first signal source is connected to the clock interface of the motherboard through a power divider to provide a clock signal for each FPGA processing module; the power supply is connected to the power interface of the motherboard to supply power to each FPGA processing module; the second signal source and the spectrum analyzer are respectively connected to the RF input / output interface on the motherboard through the switch matrix to provide RF excitation to each FPGA processing module and receive the RF response of the FPGA processing module to complete RF detection.
9. The efficient testing method for FPGA processing module according to claim 8, characterized in that: The test software generates a digital excitation signal and applies it to the FPGA processing module to be tested, and receives the output digital output signal to complete detection and judgment; the second signal source generates a radio frequency excitation and applies it to the FPGA processing module to be tested, and receives the radio frequency output signal through the spectrum analyzer to complete detection and judgment.
10. The efficient testing method for FPGA processing module according to claim 8, characterized in that: The specific sub-steps include: Initialize the test instruments and communication interfaces; Load the test software of FPGA processing module A and the functional software of FPGA processing module B, select the test items, and complete the test with the test instrument; Switch to loading software, load the test software of FPGA processing module B and load the functional software of FPGA processing module A, select the test items, cooperate with the test instrument and complete the test; Select Generate Test Report.