Reference circuit and electronic device

Abstract

The invention discloses a reference circuit and electronic equipment, and relates to the technical field of electronic circuits. The reference circuit comprises: a first current source for providing a first current; the resistor unit is connected with the first current source and used for generating target voltage according to the first current; the first transconductance amplifier is connected with the resistor unit and is used for outputting a second current according to the target voltage; the second current source is used for providing target current; the output unit is connected with the second current source and is used for outputting a first voltage according to the target current and the control signal; the second transconductance amplifier is connected with the output unit and is used for outputting a third current according to the first voltage; and the control unit is respectively connected with the first transconductance amplifier, the second transconductance amplifier and the output unit and is used for generating a control signal according to the second current and the third current so as to control the first voltage output by the output unit to be equal to the target voltage. According to the reference circuit, the specific target voltage and the specific target current can be output at the same time.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a reference circuit and an electronic device. Background Art

[0002] In the related art, according to Ohm's law U=I*R, a specific voltage U or a specific current I is generally output by adjusting the resistor R. However, it is very difficult to simultaneously meet the requirements of outputting a specific voltage U and a specific current I. Currently, there are few technologies that can simultaneously meet the requirements of outputting a specific voltage U and a specific current I by adjusting the resistor R. Summary of the invention

[0003] The present application aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the purpose of the present application is to propose a reference circuit and an electronic device to simultaneously meet the requirements of outputting a target voltage and a target current.

[0004] In the first aspect, the present application proposes a reference circuit, comprising: a first current source for providing a first current; a resistance unit connected to the first current source, for generating a target voltage according to the first current; a first transconductance amplifier connected to the resistance unit, for outputting a second current according to the target voltage; a second current source for providing a target current; an output unit connected to the second current source, for outputting a first voltage according to the target current and a control signal; a second transconductance amplifier connected to the output unit, for outputting a third current according to the first voltage; a control unit connected to the first transconductance amplifier, the second transconductance amplifier and the output unit, respectively, for generating the control signal according to the second current and the third current, so as to control the first voltage output by the output unit to be equal to the target voltage.

[0005] According to one embodiment of the present application, the circuit also includes: a bias voltage source connected to the first transconductance amplifier, used to provide a bias voltage for the first transconductance amplifier so that the common mode voltage of the first transconductance amplifier input matches the common mode voltage of the second transconductance amplifier input.

[0006] According to an embodiment of the present application, the resistance unit includes a diode, an anode of the diode is connected to the first current source and a positive input terminal of the first transconductance amplifier respectively, and a cathode of the diode is connected to a negative input terminal of the first transconductance amplifier.

[0007] According to one embodiment of the present application, the control unit includes: a subtractor, connected to the output end of the first transconductance amplifier and the output end of the second transconductance amplifier, respectively, for calculating the difference between the second current and the third current; an amplifier, connected to the subtractor and the output unit, respectively, for amplifying the difference to generate the control signal, and outputting the control signal to the output unit.

[0008] According to one embodiment of the present application, the output unit includes: a first switch tube and a load, the control end of the first switch tube is connected to the control unit to receive the control signal, the first end of the first switch tube is respectively connected to the second current source and the positive input end of the second transconductance amplifier, the second end of the first switch tube is connected to the negative input end of the second transconductance amplifier, and is grounded through the load.

[0009] According to one embodiment of the present application, the circuit further includes: a first chopping unit, connected to the resistance unit, the first transconductance amplifier, the output unit and the second transconductance amplifier respectively, for periodically swapping the inputs of the first transconductance amplifier and the second transconductance amplifier.

[0010] According to an embodiment of the present application, the circuit further includes: a low-pass filtering unit connected to the output unit and configured to perform low-pass filtering on the first voltage output by the output unit.

[0011] According to an embodiment of the present application, the circuit further includes: a sampling unit connected to the output unit, configured to perform multiple samplings on the first voltage output by the output unit according to a target timing, and obtain a target output voltage according to the multiple sampling results.

[0012] According to an embodiment of the present application, the circuit further includes: an auto-zero amplifier, connected to the first transconductance amplifier, the second transconductance amplifier and the output unit respectively, and used to correct the offset voltage generated in the reference circuit.

[0013] According to one embodiment of the present application, the control unit includes: a differential amplifier, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, a third current source and a fourth current source; the positive input terminal of the differential amplifier is connected to the third current source, the output terminal of the first transconductance amplifier, the output terminal of the second transconductance amplifier, and the first terminal of the second switch tube respectively, the negative input terminal of the differential amplifier is connected to the fourth current source, the output terminal of the first transconductance amplifier, the output terminal of the second transconductance amplifier, and the first terminal of the third switch tube respectively, the positive output terminal of the differential amplifier is connected to the control terminal of the second switch tube The negative output end of the differential amplifier is connected to the control end of the third switch tube, the first end of the fourth switch tube is connected to the second end of the second switch tube and is used to output the control signal, the control end of the fourth switch tube is connected to the control end of the fifth switch tube, the first end of the fifth switch tube is connected to the second end of the third switch tube, the control end of the sixth switch tube and the control end of the seventh switch tube respectively, the first end of the sixth switch tube is connected to the second end of the fourth switch tube, the second end of the sixth switch tube is connected to the second end of the seventh switch tube and is grounded, and the first end of the seventh switch tube is connected to the second end of the fifth switch tube.

[0014] According to one embodiment of the present application, the control unit also includes: a first chopping sub-unit and a second chopping sub-unit, the first chopping sub-unit is connected between the positive input terminal, the negative input terminal of the differential amplifier and the output terminal of the first transconductance amplifier and the output terminal of the second transconductance amplifier, and the second chopping sub-unit is connected between the second end of the fourth switch tube, the second end of the fifth switch tube and the first end of the sixth switch tube and the first end of the seventh switch tube.

[0015] In a second aspect, the present application proposes an electronic device, comprising: the reference circuit described in the first aspect above.

[0016] In the reference circuit and electronic device of the embodiment of the present application, the first voltage obtained by the output unit according to the target current is provided as feedback information to the second transconductance amplifier, and the second transconductance amplifier obtains the third current fed back according to the feedback information, and the control unit generates a control signal according to the error between the third current and the second current obtained by the first transconductance amplifier according to the target voltage, so as to control the first voltage output by the output unit until the first voltage is equal to the target voltage. Thus, it is achieved that a specific target voltage and a specific target current can be output at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the structure of the reference circuit of the first embodiment of the present application;

[0018] Figure 2 is a schematic structural diagram of a reference circuit according to a second embodiment of the present application;

[0019] Figure 3 is a schematic diagram of the structure of the reference circuit of the first specific embodiment of the present application;

[0020] Figure 4 is a schematic diagram of the structure of a reference circuit in a second specific embodiment of the present application;

[0021] Figure 5 is a schematic structural diagram of a reference circuit in a third specific embodiment of the present application;

[0022] FIG6( a ) is a schematic diagram of the structure of a reference circuit according to a third embodiment of the present application;

[0023] FIG6( b ) is a schematic diagram of the structure of a reference circuit according to a fourth specific embodiment of the present application;

[0024] FIG. 7( a ) is a schematic diagram of the structure of a reference circuit according to a fourth embodiment of the present application;

[0025] FIG7( b ) is a schematic diagram of the structure of a reference circuit according to a fifth specific embodiment of the present application;

[0026] Figure 8 is a schematic structural diagram of a reference circuit according to a fifth embodiment of the present application;

[0027] Fig. 9 is a schematic structural diagram of a reference circuit according to a sixth embodiment of the present application;

[0028] Fig.10 is a schematic structural diagram of a reference circuit according to a seventh embodiment of the present application;

[0029] Fig.11 It is a structural block diagram of an electronic device according to an embodiment of the present application.

[0030] Description of reference numerals:

[0031] A first current source IB1, a resistance unit 10, a first transconductance amplifier GM1, a second current source IB2, an output unit 20, a control unit 30, a bias voltage source Vbias, a diode D, a subtractor 31, a gain device Gain, a first switch tube M1, a load LOAD, an auto-zero amplifier 50, a differential amplifier 32, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8, a ninth switch tube M9, a third current source IB3, a fourth current source IB4, a first capacitor C1, a second capacitor C2, a first controllable switch K1, a second controllable switch K2, a fifth current source IB5, a first chopping sub-unit 33, a second chopping sub-unit 34, a first chopping unit 60, a low-pass filter unit LPF, a sampling unit 70, and an electronic device 100. DETAILED DESCRIPTION

[0032] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0033] The reference circuit of the embodiment of the present application is described below with reference to the accompanying drawings.

[0034] Figure 1 It is a schematic diagram of the structure of the reference circuit of the first embodiment of the present application.

[0035] like Figure 1 As shown, the reference circuit includes: a first current source IB1 , a resistance unit 10 , a first transconductance amplifier GM1 , a second current source IB2 , an output unit 20 and a control unit 30 .

[0036] Among them, the first current source IB1 is used to provide a first current (which may be a high-order current). The resistance unit 10 is connected to the first current source IB1, and is used to generate a target voltage according to the first current. The first transconductance amplifier GM1 is connected to the resistance unit 10, and is used to output a second current according to the target voltage. The second current source IB2 is used to provide a target current. The output unit 20 is connected to the second current source IB2, and is used to output a first voltage according to the target current and a control signal. The second transconductance amplifier GM2 is connected to the output unit 20, and is used to output a third current according to the first voltage. The control unit 30 is respectively connected to the first transconductance amplifier GM1, the second transconductance amplifier GM2 and the output unit 20, and is used to generate a control signal according to the second current and the third current to control the first voltage output by the output unit 20 to be equal to the target voltage.

[0037] Specifically, the target current is the specific current that needs to be output, which can be a PTAT (Proportional To Absolute Temperature, proportional to absolute temperature) current. The first voltage obtained according to the specific current is provided to the second transconductance amplifier GM2 as feedback information, and the second transconductance amplifier GM2 obtains the feedback current (i.e., the third current) according to the feedback information. If the third current is inconsistent with the second current output by the first transconductance amplifier GM1 according to the target voltage, it means that the first voltage is not equal to the specific voltage that needs to be output (i.e., the target voltage). At this time, the control unit 30 generates a control signal according to the error between the third current and the second current to control the first voltage (which can be the voltage across the adjustable resistor) output by the output unit 20 (which can be regarded as an adjustable resistor) until the first voltage is equal to the target voltage. Therefore, by adjusting the output unit 20, it is possible to output a specific voltage and a specific current at the same time.

[0038] In some embodiments of the present application, Figure 2 As shown, the reference circuit further includes: a bias voltage source Vbias. The bias voltage source Vbias is connected to the first transconductance amplifier GM1 and is used to provide a bias voltage for the first transconductance amplifier GM1 so that the common mode voltage input to the first transconductance amplifier GM1 matches the common mode voltage input to the second transconductance amplifier GM2.

[0039] By setting the bias voltage source Vbias, the first transconductance amplifier GM1 and the second transconductance amplifier GM2 can be well matched, and the common modes of the two inputs of the first transconductance amplifier GM1 and the two inputs of the second transconductance amplifier GM2 can be roughly the same, thereby improving the accuracy of the output target current and target voltage.

[0040] In some embodiments of the present application, Figure 3 As shown, the resistance unit 10 includes a diode D, an anode of the diode D is connected to the first current source IB1 and the positive input terminal of the first transconductance amplifier GM1 respectively, and a cathode of the diode D is connected to the negative input terminal of the first transconductance amplifier GM1.

[0041] Specifically, the high-order current generated by the first current source IB1 can generate a target voltage after flowing through the diode D.

[0042] In some embodiments of the present application, Figure 4 As shown, the control unit 30 includes: a subtractor 31 and a gain Gain.

[0043] The subtractor 31 is connected to the output end of the first transconductance amplifier GM1 and the output end of the second transconductance amplifier GM2, respectively, for calculating the difference between the second current and the third current. The gain device Gain is connected to the subtractor 31 and the output unit 20, respectively, for amplifying the difference to generate a control signal, and outputting the control signal to the output unit 20.

[0044] Specifically, if the feedback current (i.e., the third current) and the current output by the first transconductance amplifier GM1 (i.e., the second current) are inconsistent, the error between the two currents is amplified by the post-stage gain device Gain to adjust the output unit 20, so that V(SenseP-SenseN)=the input of the first transconductance amplifier GM1 (i.e., the target voltage) can be achieved through negative feedback. Wherein, V(SenseP-SenseN) is the first voltage.

[0045] In some embodiments of the present application, Figure 5 As shown, the output unit 20 includes: a first switch tube M1 and a load LOAD.

[0046] Among them, the control end of the first switch tube M1 is connected to the control unit 30 to receive a control signal, the first end (SenseP end) of the first switch tube M1 is connected to the second current source IB2 and the positive input end of the second transconductance amplifier GM2 respectively, the second end (SenseN end) of the first switch tube M1 is connected to the negative input end of the second transconductance amplifier GM2, and is grounded through the load LOAD.

[0047] Specifically, the first switch tube M1 may be a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor), and the load LOAD may include a resistor with a preset resistance. The control signal output by the control unit 30 may control the on-off of the first switch tube M1, and the voltage between the SenseP terminal and the SenseN terminal, i.e., the first voltage, may be adjusted by the on-off of the first switch tube M1, thereby adjusting the first voltage to the target voltage.

[0048] For ease of understanding, the following Figure 5 The illustrated embodiment describes the working principle of the reference circuit:

[0049] See also Figure 5 , through the feedback loop, the following equation holds:

[0050] (Vimi*G1-V(SenseP-SenseN)*G2)*Rout*Ga*I2*Lmx=V(SenseP-SenseN)

[0051] Wherein, Vimi represents the voltage across the resistor unit 10 (i.e., the target voltage), G1 and G2 represent the voltage-to-current coefficients of the first transconductance amplifier GM1 and the second transconductance amplifier GM2, respectively, Vimi*G1 represents the second current, V(SenseP-SenseN)*G2 represents the third current, Ga represents the gain coefficient of the gain device Gain, Rout represents the impedance of the current summing point (i.e., the subtractor 31), and Lmx represents the output device ( Figure 5 I2 represents the target current provided by the second current source IB2.

[0052] Transform the above formula to get:

[0053]

[0054] It can be seen that, consistent with the theory of transconductance amplifiers, when the gain Ga of the gain device Gain is large enough, the error between the output (i.e., the first voltage V(SenseP-SenseN)) and the input (i.e., the target voltage Vimi) is only determined by the first transconductance amplifier GM1 and the second transconductance amplifier GM2. Therefore, by selecting the first transconductance amplifier GM1, the second transconductance amplifier GM2, and the gain device Gain in the reference circuit, it is possible to adjust the output unit 20 to achieve the output of a specific voltage and a specific current.

[0055] In some embodiments of the present application, as shown in FIG6(a), the reference circuit further includes an auto-zero amplifier 50. The auto-zero amplifier 50 is connected to the first transconductance amplifier GM1, the second transconductance amplifier GM2 and the output unit 20, respectively, for correcting the offset voltage generated in the reference circuit.

[0056] In some embodiments of the present application, as shown in Figures 6 and 7, the control unit 30 includes: a differential amplifier 32, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, a third current source IB3 and a fourth current source IB4.

[0057] Among them, the positive input end of the differential amplifier 32 is connected to the third current source IB3, the output end of the first transconductance amplifier GM1, the output end of the second transconductance amplifier GM2, and the first end of the second switch tube M2 respectively; the negative input end of the differential amplifier 32 is connected to the fourth current source IB4, the output end of the first transconductance amplifier GM1, the output end of the second transconductance amplifier GM2, and the first end of the third switch tube M3 respectively; the positive output end of the differential amplifier 32 is connected to the control end of the second switch tube M2; the negative output end of the differential amplifier 32 is connected to the control end of the third switch tube M3; A first end of the fourth switch tube M4 is connected to the second end of the second switch tube M2 and is used to output a control signal. A control end of the fourth switch tube M4 is connected to a control end of the fifth switch tube M5. A first end of the fifth switch tube M5 is respectively connected to the second end of the third switch tube M3, the control end of the sixth switch tube M6 and the control end of the seventh switch tube M7. A first end of the sixth switch tube M6 is connected to the second end of the fourth switch tube M4. A second end of the sixth switch tube M6 is connected to the second end of the seventh switch tube M7 and is grounded. A first end of the seventh switch tube M7 is connected to the second end of the fifth switch tube M5.

[0058] The second switch tube M2 , the third switch tube M3 , the fourth switch tube M4 , the fifth switch tube M5 , the sixth switch tube M6 , and the seventh switch tube M7 may all be MOS tubes.

[0059] Referring to FIG. 7( a), the control unit 30 may further include: a first chopping sub-unit 33 and a second chopping sub-unit 34, wherein the first chopping sub-unit 33 is connected between the positive input terminal, the negative input terminal of the differential amplifier 32 and the output terminal of the first transconductance amplifier GM1 and the output terminal of the second transconductance amplifier GM2, and the second chopping sub-unit 34 is connected between the second end of the fourth switch tube M4, the second end of the fifth switch tube M5 and the first end of the sixth switch tube M6 and the first end of the seventh switch tube M7.

[0060] It should be noted that the input and output of the first transconductance amplifier GM1 and the second transconductance amplifier GM2 are both differential signals. The internal structures of the first transconductance amplifier GM1 and the second transconductance amplifier GM2 can be shown in Figure 6(b) and Figure 7(b), including two switch tubes and a current source, and the control ends of the two switch tubes are used as voltage input ends. Referring to Figures 6(b) and 7(b), the signals output by the first transconductance amplifier GM1 and the second transconductance amplifier GM2 are respectively output to the two input ends of the differential amplifier 32 in a differential form. In some examples, referring to Figure 6(b), the auto-zero amplifier 50 may include a first capacitor C1, a second capacitor C2, an eighth switch tube M8, a ninth switch tube M9, a first controllable switch K1, a second controllable switch K2, and a fifth current source IB5. Of course, the structural composition of the auto-zero amplifier 50 in Figure 6(b) and the structural composition of the transconductance amplifier in Figures 6(b) and 7(b) are exemplary, and other devices may also be included.

[0061] The eighth switch tube M8 , the ninth switch tube M9 , and the switch tubes in the first transconductance amplifier GM1 and the second transconductance amplifier GM2 may all be MOS tubes.

[0062] 6(a), 6(b), 7(a), and 7(b), by using the above-mentioned AutoZero (self-zeroing) or Chop (chopping) method, the accuracy of the transconductance amplifier can be improved.

[0063] In some embodiments of the present application, Figure 8 As shown, the reference circuit further includes a first chopping unit 60. The first chopping unit 60 is connected to the resistance unit 10, the first transconductance amplifier GM1, the output unit 20 and the second transconductance amplifier GM2 respectively, and is used to periodically swap the inputs of the first transconductance amplifier GM1 and the second transconductance amplifier GM2.

[0064] Specifically, the first chopping unit 60 may include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch. The first switch is connected between one end of the resistance unit 10 connected to the first current source IB1 and the positive input end of the first transconductance amplifier GM1, the second switch is connected between one end of the resistance unit 10 connected to the bias voltage source Vbias and the negative input end of the first transconductance amplifier GM1, the third switch is connected between the SenseP terminal and the positive input end of the second transconductance amplifier GM2, and the fourth switch is connected between the SenseN terminal and the negative input end of the second transconductance amplifier GM2; the fifth switch is connected between one end of the resistance unit 10 connected to the first current source IB1 and the positive input end of the second transconductance amplifier GM2, the sixth switch is connected between one end of the resistance unit 10 connected to the bias voltage source Vbias and the negative input end of the second transconductance amplifier GM2, the seventh switch is connected between the SenseP terminal and the positive input end of the first transconductance amplifier GM1, and the fourth switch is connected between the SenseN terminal and the negative input end of the first transconductance amplifier GM1. When adjusting the first voltage, the first to fourth switches can be controlled to be closed in the current cycle, and the first transconductance amplifier GM1 outputs the second current according to the target voltage, and the second transconductance amplifier GM2 outputs the third current according to the first voltage; in the next cycle, the fifth to eighth switches can be controlled to be closed, and the first transconductance amplifier GM1 outputs the third current according to the first voltage, and the second transconductance amplifier GM2 outputs the second current according to the target voltage. In this way, the function of modulating VOS (Offset Voltage) to high frequency can be realized.

[0065] In some examples, the first switch and the fifth switch may also be implemented by a single-pole double-throw switch. Similarly, the second switch and the sixth switch, the third switch and the seventh switch, and the fourth switch and the eighth switch may also be implemented by a single-pole double-throw switch.

[0066] The embodiments shown in FIG6 and FIG7 are mainly for amplifier processing offset. Figure 8Compared with the embodiments shown in FIG. 6 and FIG. 7 , the embodiment shown can achieve more targeted offset elimination. Specifically, when the feedback loop of the reference circuit is stable, Vin1–Vin2=0, where Vin1 and Vin2 represent the inputs of the first transconductance amplifier GM1 and the second transconductance amplifier GM2, respectively. If the reference circuit itself has a mismatch, Vin1–Vin2=Vos, where Vos represents the mismatch voltage of the first transconductance amplifier GM1 and the second transconductance amplifier GM2 caused by the circuit mismatch. After the inputs of the first transconductance amplifier GM1 and the second transconductance amplifier GM2 are swapped by the first chopping unit 60, Vin1–Vin2=-Vos. Therefore, by periodically swapping the inputs of the first transconductance amplifier GM1 and the second transconductance amplifier GM2, the function of modulating VOS to a high frequency can be achieved.

[0067] In some embodiments of the present application, Fig. 9 As shown, the reference circuit further includes: a low-pass filter unit LPF. The low-pass filter unit LPF is connected to the output unit 20 and is used to perform low-pass filtering on the first voltage output by the output unit 20.

[0068] Specifically, see Fig. 9 Since the feedback of the output unit 20 is the final output in the architecture of the reference circuit of the present application, it is not necessary to add a set of switches to modulate the signal back to a low frequency as in the traditional chopping technology, but only a low-pass filter is needed at the output end of the output unit 20. Compared with the notch filter, the implementation of the low-pass filter is simpler.

[0069] In some embodiments of the present application, Fig.10 As shown, the reference circuit further includes a sampling unit 70. The sampling unit 70 is connected to the output unit 20 and is used to perform multiple samplings on the first voltage output by the output unit 20 according to the target timing and obtain the target output voltage according to the multiple sampling results.

[0070] In this embodiment, the first voltage output by the output unit 20 can be output to the sampling unit 70. At this time, filtering is not required. The accuracy required for the target output voltage can be obtained by performing timing alignment and ensuring that the sampling is uniform in two phases.

[0071] Specifically, without filtering, the SenseP and SenseN terminals may have ripples Vripple. That is, in the positive half cycle of the clock (the control clock for input switching), it is expressed as VSense (ideal output) + Vripple; in the negative half cycle, it is expressed as VSense - Vripple. The sampling unit 60 can sample the output multiple times, one sampling happens in the positive half cycle, and another sampling happens in the negative half cycle. It can be seen that after superposition, Vripple is offset, so that an accurate output value can be obtained.

[0072] Based on the reference circuit of the above embodiment, the present application proposes an electronic device.

[0073] Fig.11 It is a structural block diagram of an electronic device according to an embodiment of the present application.

[0074] like Fig.11 As shown, the electronic device 100 includes the reference circuit of the above embodiment.

[0075] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0076] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0077] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0078] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0079] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0080] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A reference circuit, characterized in that: include: A first current source, used to provide a first current; a resistance unit, connected to the first current source, and configured to generate a target voltage according to the first current; a first transconductance amplifier, connected to the resistance unit, and configured to output a second current according to the target voltage; A second current source, used for providing a target current; an output unit, connected to the second current source, and configured to output a first voltage according to the target current and a control signal; a second transconductance amplifier, connected to the output unit, and configured to output a third current according to the first voltage; A control unit is connected to the first transconductance amplifier, the second transconductance amplifier and the output unit respectively, and is used to generate the control signal according to the second current and the third current to control the first voltage output by the output unit to be equal to the target voltage.

2. The reference circuit according to claim 1, characterized in that: The circuit further comprises: A bias voltage source is connected to the first transconductance amplifier and is used to provide a bias voltage for the first transconductance amplifier so that a common mode voltage input to the first transconductance amplifier matches a common mode voltage input to the second transconductance amplifier.

3. The reference circuit according to claim 1 or 2, characterized in that: The resistance unit includes a diode, an anode of the diode is connected to the first current source and a positive input terminal of the first transconductance amplifier respectively, and a cathode of the diode is connected to a negative input terminal of the first transconductance amplifier.

4. The reference circuit according to claim 1 or 2, characterized in that: The control unit comprises: a subtractor, connected to the output end of the first transconductance amplifier and the output end of the second transconductance amplifier respectively, and used to calculate the difference between the second current and the third current; An amplifier is connected to the subtractor and the output unit respectively, and is used to amplify the difference to generate the control signal, and output the control signal to the output unit.

5. The reference circuit according to claim 1 or 2, characterized in that: The output unit comprises: A first switch tube and a load, wherein the control end of the first switch tube is connected to the control unit to receive the control signal, the first end of the first switch tube is respectively connected to the second current source and the positive input end of the second transconductance amplifier, the second end of the first switch tube is connected to the negative input end of the second transconductance amplifier and is grounded through the load.

6. The reference circuit according to claim 1 or 2, characterized in that: The circuit further comprises: The first chopping unit is connected to the resistance unit, the first transconductance amplifier, the output unit and the second transconductance amplifier respectively, and is used to periodically swap the inputs of the first transconductance amplifier and the second transconductance amplifier.

7. The reference circuit according to claim 6, characterized in that: The circuit further comprises: A low-pass filtering unit is connected to the output unit and is used to perform low-pass filtering on the first voltage output by the output unit.

8. The reference circuit according to claim 6, characterized in that: The circuit further comprises: The sampling unit is connected to the output unit and is used to sample the first voltage output by the output unit multiple times according to the target timing, and obtain the target output voltage according to the multiple sampling results.

9. The reference circuit according to claim 1 or 2, characterized in that: The circuit further comprises: The auto-zero amplifier is connected to the first transconductance amplifier, the second transconductance amplifier and the output unit respectively, and is used to correct the offset voltage generated in the reference circuit.

10. The reference circuit according to claim 1 or 2, characterized in that: The control unit includes: a differential amplifier, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, a third current source and a fourth current source; The positive input terminal of the differential amplifier is connected to the third current source, the output terminal of the first transconductance amplifier, the output terminal of the second transconductance amplifier, and the first terminal of the second switch tube respectively; the negative input terminal of the differential amplifier is connected to the fourth current source, the output terminal of the first transconductance amplifier, the output terminal of the second transconductance amplifier, and the first terminal of the third switch tube respectively; the positive output terminal of the differential amplifier is connected to the control terminal of the second switch tube; the negative output terminal of the differential amplifier is connected to the control terminal of the third switch tube; the first terminal of the fourth switch tube is connected to the second terminal of the second switch tube and is used to output the control signal; the control terminal of the fourth switch tube is connected to the control terminal of the fifth switch tube; the first terminal of the fifth switch tube is connected to the second terminal of the third switch tube, the control terminal of the sixth switch tube, and the control terminal of the seventh switch tube respectively; the first terminal of the sixth switch tube is connected to the second terminal of the fourth switch tube; the second terminal of the sixth switch tube is connected to the second terminal of the seventh switch tube and is grounded; the first terminal of the seventh switch tube is connected to the second terminal of the fifth switch tube.

11. The reference circuit according to claim 10, characterized in that: The control unit also includes: a first chopping sub-unit and a second chopping sub-unit, the first chopping sub-unit is connected between the positive input terminal, the negative input terminal of the differential amplifier and the output terminal of the first transconductance amplifier and the output terminal of the second transconductance amplifier, and the second chopping sub-unit is connected between the second end of the fourth switch tube, the second end of the fifth switch tube and the first end of the sixth switch tube and the first end of the seventh switch tube.

12. An electronic device, characterized in that: include: A reference circuit according to any one of claims 1 to 11.

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