A novel low-noise and low-power bandgap reference

Abstract

The present invention discloses a novel low-noise and low-power bandgap reference, belonging to the field of analog integrated circuits. It is composed of a network structure formed by multiple ΔV BE cells, where a single ΔV BE cell includes transistors Q 1A -Q 1B and current source I1; the emitter area of transistor Q 1A is N times the emitter area of transistor Q 1B , and N is a positive integer greater than 1; the emitter of transistor Q 1A can generate the required ΔV BE voltage. The present invention has the advantages of low noise and low power consumption, and is suitable for high-precision and low-power applications.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a novel low-noise and low-power bandgap reference. Background Art

[0002] In existing high-precision bandgap reference voltage sources, in order to reduce noise, it is usually necessary to greatly increase power consumption. Specifically, for every 4-fold increase in power consumption, the noise can only be reduced by 2-fold. This method of reducing noise, although effective, greatly wastes power consumption. Summary of the Invention

[0003] In order to solve the above problems, the present invention proposes a novel low-noise and low-power bandgap reference.

[0004] The technical solution of the present invention is: a novel low-noise and low-power bandgap reference, which is composed of a network structure formed by multiple ΔV BE units, where a single ΔV BE unit includes transistors Q 1A -Q 1B and a current source I1; the positive pole of the current source I1 is connected to the power supply voltage V DD ; the emitter of the transistor Q 1B is grounded; the negative pole of the current source I1 and the collector of the transistor Q 1A are connected, and the connection point is also connected to the base of the transistor Q 1A and the base of the transistor Q 1B ; the emitter of the transistor Q 1A and the collector of the transistor Q 1B are connected; the emitter area of the transistor Q 1A is N times the emitter area of the transistor Q 1B , and N is a positive integer greater than 1; the emitter of the transistor Q 1A can generate the required ΔV BE voltage.

[0005] Further, the network structure can adopt a series form, including ΔV BE unit 1-ΔV BE unit 9 and a current source I1; the ΔV BE unit x includes transistors Q xA -Q xB , where x represents the numbers 1 to 9, the collector of the transistor Q xA is connected to the base of the transistor Q xB , and the emitter of the transistor Q xA is connected to the collector of the transistor Q xB ; in the ΔV BE unit x, the transistor Q xAThe emitter of and ΔV BE The base of transistor Q in unit x + 1 (x+1)A is connected, ΔV BE The emitter of transistor Q in unit x xB and ΔV BE The base of transistor Q in unit x + 1 (x+1)B is connected, where x represents the numbers 1 - 8, and this connection method is ΔV BE The series form of the unit; the ΔV BE The base and collector of transistor Q in unit 1 1A are connected; the ΔV BE The collector of transistor Q in unit 1 1A is connected to the negative electrode of current source I1, thereby realizing ΔV BE The current of unit 1 is provided by current source I1; the positive electrode of current source I1 is connected to the power supply voltage V DD is connected; the ΔV BE The emitter of transistor Q in unit 9 9B is grounded; the emitter of the transistor Q 9A can generate the required voltage ΔV BE ×9, the base of transistor Q 9A can generate the required reference voltage V REF .

[0006] Furthermore, the network structure can also adopt series and parallel forms, including ΔV BE Unit 1 - ΔV BE Unit 9, current source I1, current source I4, current source I7; the ΔV BE Unit x includes transistor Q xA -Q xB , where x represents the numbers 1 - 9, the collector of transistor Q xA is connected to the base of transistor Q xB , the emitter of transistor Q xA is connected to the collector of transistor Q xB ; the ΔV BE The emitter of transistor Q in unit x xA and ΔV BE The base of transistor Q in unit x + 1 (x+1)A is connected, ΔV BE The emitter of transistor Q in unit x xB and ΔV BE The base of transistor Q in unit x + 1 (x+1)B is connected, where x represents the numbers 1, 2, 4, 5, 7, 8, and this connection method is the series form of ΔV BE Unit; the ΔV BE The collector of transistor Q in unit x xB and ΔVBE The emitter of transistor Q in unit x + 3 (x+3)B is connected, where x represents the numbers 3 and 6, and this connection method is ΔV BE in the parallel form of the unit; the ΔV BE The base and collector of transistor Q in unit x xA are connected, where x represents the numbers 1, 4, 7; the ΔV BE The collector of transistor Q in unit x xA is connected to the negative electrode of current source I x to realize ΔV BE The current of unit x is provided by current source I x , where x represents the numbers 1, 4, 7; the positive electrode of the current source I x is connected to the power supply voltage V DD , where x represents the numbers 1, 4, 7; the ΔV BE The emitter of transistor Q in unit 3 3B is grounded; the ΔV BE The emitter of transistor Q in unit 9 9A can generate the required voltage ΔV BE ×9, and the base of transistor Q 9A can generate the required reference voltage V REF .

[0007] Furthermore, the network structure can also adopt another series and parallel form, including ΔV BE Unit 1 - ΔV BE Unit 8, current source I1, current source I5; the ΔV BE Unit x includes transistor Q xA -Q xB , where x represents numbers 1 - 8, and the collector of transistor Q xA is connected to the base of transistor Q xB , and the emitter of transistor Q xA is connected to the collector of transistor Q xB ; the ΔV BE The emitter of transistor Q in unit x xA is connected to the base of transistor Q BE in unit x + 1, and the ΔV (x+1)A The emitter of transistor Q in unit x BE is connected to the base of transistor Q xB in unit x + 1, and the ΔV BE The emitter of transistor Q in unit x + 1 (x+1)B is connected, where x represents the numbers 1, 2, 3, 5, 6, 7, and this connection method is the series form of ΔV BE in the unit; the ΔV BE The collector of transistor Q in unit 4 4B is connected to the ΔVBE The emitter of transistor Q in unit 8 8B is connected, and this connection method is ΔV BE in the parallel form of the unit; the said ΔV BE The base and collector of transistor Q in unit x xA are connected, where x represents the numbers 1 and 5; the said ΔV BE The collector of transistor Q in unit x xA is connected to the negative pole of current source I x so as to realize that the current of ΔV BE unit x is provided by current source I x , where x represents the numbers 1 and 5; the positive pole of the said current source I x is connected to power supply voltage V DD , where x represents the numbers 1 and 5; the said ΔV BE The emitter of transistor Q in unit 4 is grounded; the said ΔV 4B The emitter of transistor Q in unit 8 BE can generate the required voltage ΔV 8A ×8, the base of transistor Q BE can generate the required reference voltage V 8A . REF

[0008] The beneficial effects of the present invention are: low noise and low power consumption, suitable for high-precision and low-power applications. Description of the Drawings

[0009] Figure 1 is the schematic diagram of the ΔV BE unit;

[0010] Figure 2 is the novel low-noise and low-power bandgap reference (Embodiment 1);

[0011] Figure 3 is the novel low-noise and low-power bandgap reference (Embodiment 2);

[0012] Figure 4 is the novel low-noise and low-power bandgap reference (Embodiment 3). Specific Embodiments

[0013] The following further describes the embodiments of the present invention with reference to the drawings.

[0014] The present invention provides a novel low-noise and low-power bandgap reference, which is composed of a network structure formed by multiple ΔV BE units, where a single ΔV BE unit includes transistor Q 1A -Q 1B , current source I1, such as Figure 1As shown; the positive pole of the current source I1 is connected to the power supply voltage V DD ; the emitter of the triode Q 1B is grounded; the negative pole of the current source I1 and the collector of the triode Q 1A are connected, and the connection point is also connected to the base of the triode Q 1A ; the emitter of the triode Q 1B is connected to the base of the triode Q 1A ; the emitter of the triode Q 1B is connected to the collector of the triode Q 1A ; the emitter area of the triode Q 1B is N times the emitter area of the triode Q 1A , where N is a positive integer greater than 1; the emitter of the triode Q BE can generate the required ΔV

[0015] The following is described in three embodiments, as shown respectively in Figure 2 , Figure 3 , Figure 4 shown.

[0016] Embodiment 1:

[0017] In the first embodiment of the present invention, as Figure 2 shown, the network structure can adopt a series form, including ΔV BE Unit 1-ΔV BE Unit 9, current source I1; the ΔV BE Unit x includes the triode Q xA -Q xB , where x represents the numbers 1 to 9. The collector of the triode Q xA is connected to the base of the triode Q xB , and the emitter of the triode Q xA is connected to the collector of the triode Q xB ; the emitter of the triode Q BE in the ΔV xA Unit x is connected to the base of the triode Q BE in the ΔV (x+1)A Unit x+1, and the emitter of the triode Q BE in the ΔV xB Unit x is connected to the base of the triode Q BE in the ΔV (x+1)B Unit x+1, where x represents the numbers 1 to 8. This connection method is the series form of the ΔV BE Unit; the base and collector of the triode Q BE in the ΔV 1A Unit 1 are connected; the triode Q BE in the ΔV 1AThe collector is connected to the negative electrode of the current source I1, thereby achieving ΔV BE The current of unit 1 is provided by the current source I1; the positive electrode of the current source I1 is connected to the power supply voltage V DD The ΔV BE In unit 9, the emitter of the triode Q 9B is grounded; the emitter of the triode Q 9A can generate the required voltage ΔV BE ×9, the base of the triode Q 9A can generate the required reference voltage V REF .

[0018] Embodiment 2:

[0019] In the second embodiment of the present invention, as Figure 3 shown, the network structure can adopt a series and parallel form, including ΔV BE Unit 1 - ΔV BE Unit 9, current source I1, current source I4, current source I7; the ΔV BE Unit x includes the triode Q xA -Q xB , x represents the numbers 1 - 9, the collector of the triode Q xA is connected to the base of the triode Q xB , the emitter of the triode Q xA is connected to the collector of the triode Q xB ; the emitter of the triode Q BE in the ΔV xA unit x is connected to the base of the triode Q BE in the ΔV (x+1)A unit x + 1, the emitter of the triode Q BE in the ΔV xB unit x is connected to the base of the triode Q BE in the ΔV (x+1)B unit x + 1, x represents the numbers 1, 2, 4, 5, 7, 8, and this connection method is the series form of the ΔV BE unit; the collector of the triode Q BE in the ΔV xB unit x is connected to the emitter of the triode Q BE in the ΔV (x+3)B unit x + 3, x represents the numbers 3 and 6, and this connection method is the parallel form of the ΔV BE unit; the base and collector of the triode Q BE in the ΔV xA unit x are connected, x represents the numbers 1, 4, 7; the collector of the triode Q BE in the ΔV xA unit x is connected to the current source I xis connected to the negative electrode to achieve ΔV BE The current of unit x is provided by current source I x where x represents the numbers 1, 4, 7; the positive electrode of the current source I x is connected to the power supply voltage V DD where x represents the numbers 1, 4, 7; the ΔV BE In unit 3, the emitter of transistor Q 3B is grounded; the ΔV BE In unit 9, the emitter of transistor Q 9A can generate the required voltage ΔV BE ×9, the base of transistor Q 9A can generate the required reference voltage V REF .

[0020] Embodiment Three:

[0021] In Embodiment Three of the present invention, as Figure 4 shown, the network structure can adopt another series and parallel form, including ΔV BE unit 1 - ΔV BE unit 8, current source I1, current source I5; the ΔV BE unit x includes transistor Q xA -Q xB , where x represents the numbers 1 - 8, the collector of transistor Q xA is connected to the base of transistor Q xB , the emitter of transistor Q xA is connected to the collector of transistor Q xB ; the ΔV BE In unit x of transistor Q xA the emitter and ΔV BE In unit x + 1 of transistor Q (x+1)A the base is connected, the ΔV BE In unit x of transistor Q xB the emitter and ΔV BE In unit x + 1 of transistor Q (x+1)B the base is connected, where x represents the numbers 1, 2, 3, 5, 6, 7, this connection method is the series form of the ΔV BE unit; the ΔV BE In unit 4 of transistor Q 4B the collector and ΔV BE In unit 8 of transistor Q 8B the emitter is connected, this connection method is the parallel form of the ΔV BE unit; the ΔV BE In unit x of transistor Q xA the base and collector are connected, where x represents the numbers 1 and 5; the ΔV BE In unit x of transistor QxA The collector of and current source I x is connected to the negative electrode, thus achieving ΔV BE The current of unit x is provided by current source I x , where x represents the numbers 1 and 5; the positive electrode of the current source I x is connected to the power supply voltage V DD , where x represents the numbers 1 and 5; the ΔV BE In unit 4, the emitter of transistor Q 4B is grounded; the ΔV BE In unit 8, the emitter of transistor Q 8A can generate the required voltage ΔV BE ×8, the base of transistor Q 8A can generate the required reference voltage V REF .

[0022] Those of ordinary skill in the art will realize that the embodiments described herein are to assist the reader in understanding the principles of the present invention and should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations without departing from the essence of the present invention based on these technical revelations disclosed in the present invention, and these deformations and combinations are still within the scope of protection of the present invention.

Claims

1. A low-noise, low-power bandgap reference, characterized in that, It is composed of a network structure formed by multiple ΔV BE units. The network structure is in series form and includes ΔV BE unit 1 - ΔV BE unit 9, and current source I1; The ΔV BE unit x includes triode Q xA -Q xB , where x represents the numbers 1 - 9. The collector of triode Q xA is connected to the base of triode Q xB , and the emitter of triode Q xA is connected to the collector of triode Q xB ; The emitter of triode Q BE in the ΔV 1A unit 1 is connected to the base of triode Q BE in the ΔV 2A unit 2. The emitter of triode Q BE in the ΔV 2A unit 2 is connected to the base of triode Q BE in the ΔV 3A unit 3. The emitter of triode Q BE in the ΔV 3A unit 3 is connected to the base of triode Q BE in the ΔV 4A unit 4. The emitter of triode Q BE in the ΔV 4A unit 4 is connected to the base of triode Q BE in the ΔV 5A unit 5. The emitter of triode Q BE in the ΔV 5A unit 5 is connected to the base of triode Q BE in the ΔV 6A unit 6. The emitter of triode Q BE in the ΔV 6A unit 6 is connected to the base of triode Q BE in the ΔV 7A unit 7. The emitter of triode Q BE in the ΔV 7A unit 7 is connected to the base of triode Q BE in the ΔV 8A unit 8. The emitter of triode Q BE in the ΔV 8A unit 8 is connected to the base of triode Q BE in the ΔV 9A unit 9. The emitter of triode Q BE in the ΔV 1B unit 1 is connected to the base of triode Q BE in the ΔV 2B is connected to the base, and the ΔV BE The triode Q in unit 2 2B is connected to the emitter and ΔV BE The triode Q in unit 3 3B is connected to the base, and the ΔV BE The triode Q in unit 3 3B is connected to the emitter and ΔV BE The triode Q in unit 4 4B is connected to the base, and the ΔV BE The triode Q in unit 4 4B is connected to the emitter and ΔV BE The triode Q in unit 5 5B is connected to the base, and the ΔV BE The triode Q in unit 5 5B is connected to the emitter and ΔV BE The triode Q in unit 6 6B is connected to the base, and the ΔV BE The triode Q in unit 6 6B is connected to the emitter and ΔV BE The triode Q in unit 7 7B is connected to the base, and the ΔV BE The triode Q in unit 7 7B is connected to the emitter and ΔV BE The triode Q in unit 8 8B is connected to the base, and the ΔV BE The triode Q in unit 8 8B is connected to the emitter and ΔV BE The triode Q in unit 9 9B is connected to the base, and this connection method is ΔV BE The series form of the unit; the ΔV BE The base and collector of the triode Q in unit 1 1A are connected; the ΔV BE The collector of the triode Q in unit 1 1A is connected to the negative electrode of the current source I1, so as to realize ΔV BE The current of unit 1 is provided by the current source I1; the positive electrode of the current source I1 is connected to the power supply voltage V DD is connected; the ΔV BE The emitter of the triode Q in unit 9 9B is grounded; the emitter of the triode Q 9A can generate the required voltage ΔV BE ×9, and the base of the triode Q 9A can generate the required reference voltage V REF .

2. A low-noise, low-power bandgap reference, characterized in that, It is composed of a network structure formed by multiple ΔV BE units, and the network structure adopts series and parallel forms, including ΔV BE unit 1 - ΔV BE unit 9, current source I1, current source I4, current source I7; ΔV BE unit x includes transistor Q xA -Q xB , where x represents the numbers from 1 to 9, and the collector of transistor Q xA is connected to the base of transistor Q xB , and the emitter of transistor Q xA is connected to the collector of transistor Q xB ; the emitter of transistor Q BE in ΔV 1A unit 1 is connected to the base of transistor Q BE in ΔV 2A unit 2, and the emitter of transistor Q BE in ΔV 2A unit 2 is connected to the base of transistor Q BE in ΔV 3A unit 3, the emitter of transistor Q BE in ΔV 4A unit 4 is connected to the base of transistor Q BE in ΔV 5A unit 5, the emitter of transistor Q BE in ΔV 5A unit 5 is connected to the base of transistor Q BE in ΔV 6A unit 6, the emitter of transistor Q BE in ΔV 7A unit 7 is connected to the base of transistor Q BE in ΔV 8A unit 8, the emitter of transistor Q BE in ΔV 8A unit 8 is connected to the base of transistor Q BE in ΔV 9A unit 9, the emitter of transistor Q BE in ΔV 1B unit 1 is connected to the base of transistor Q BE in ΔV 2B unit 2, the emitter of transistor Q BE in ΔV 2B unit 2 is connected to the base of transistor Q BE in ΔV 3B unit 3, the emitter of transistor Q BE in ΔV 4B unit 4 is connected to the base of transistor Q BE in ΔV unit 5 5B is connected to the base, and the ΔV BE In unit 5, the emitter of transistor Q 5B and ΔV BE In unit 6, the base of transistor Q 6B is connected, and the ΔV BE In unit 7, the emitter of transistor Q 7B and ΔV BE In unit 8, the base of transistor Q 8B is connected, and the ΔV BE In unit 8, the emitter of transistor Q 8B and ΔV BE In unit 9, the base of transistor Q 9B is connected, and this connection method is the series form of the ΔV BE unit; the ΔV BE In unit 3, the collector of transistor Q 3B and ΔV BE In unit 6, the emitter of transistor Q 6B is connected, and the ΔV BE In unit 6, the collector of transistor Q 6B and ΔV BE In unit 9, the emitter of transistor Q 9B is connected, and this connection method is the parallel form of the ΔV BE unit; the ΔV BE In unit 1, the base and collector of transistor Q 1A are connected, and the ΔV BE In unit 4, the base and collector of transistor Q 4A are connected, and the ΔV BE In unit 7, the base and collector of transistor Q 7A are connected; the ΔV BE In unit 1, the collector of transistor Q 1A is connected to the negative electrode of current source I1, so as to realize ΔV BE The current of unit 1 is provided by current source I1, and the ΔV BE In unit 4, the collector of transistor Q 4A is connected to the negative electrode of current source I4, so as to realize ΔV BE The current of unit 4 is provided by current source I4, and the ΔV BE In unit 7, the collector of transistor Q 7A is connected to the negative electrode of current source I7, so as to realize ΔV BE The current of unit 7 is provided by current source I7; the positive electrode of current source I1 is connected to power supply voltage V DD is connected, the positive electrode of current source I4 is connected to power supply voltage V DD is connected, the positive electrode of current source I7 is connected to power supply voltage V DD Connection; the ΔV BE The emitter of transistor Q in unit 3 3B is grounded; the ΔV BE The emitter of transistor Q in unit 9 9A can generate the required voltage ΔV BE ×9, the base of transistor Q 9A can generate the required reference voltage V REF .

3. A low-noise, low-power bandgap reference, characterized in that, It is composed of multiple ΔV BE The network structure is composed of a series and parallel connection, including ΔV BE Unit 1-ΔV BE Unit 8, current source I1, current source I5; ΔV BE Unit x includes transistor Q xA -Q xB , x represents the number 1-8, transistor Q xA The collector and transistor Q xB The base connection of transistor Q xA The emitter and transistor Q xB The collector connection of BE Transistor Q in unit 1 1A The emitter and ΔV BE Transistor Q in unit 2 2A The base connection, the ΔV BE Transistor Q in unit 2 2A The emitter and ΔV BE Transistor Q in unit 3 3A The base connection, the ΔV BE Transistor Q in unit 3 3A The emitter and ΔV BE Transistor Q in unit 4 4A The base connection, the ΔV BE Transistor Q in unit 5 5A The emitter and ΔV BE Transistor Q in unit 6 6A The base connection, the ΔV BE Transistor Q in unit 6 6A The emitter and ΔV BE Transistor Q in unit 7 7A The base connection, the ΔV BE Transistor Q in unit 7 7A The emitter and ΔV BE Transistor Q in unit 8 8A The base connection, the ΔV BE Transistor Q in unit 1 1B The emitter and ΔV BE Transistor Q in unit 2 2B The base connection, the ΔV BE Transistor Q in unit 2 2B The emitter and ΔV BE Transistor Q in unit 3 3B The base connection, the ΔV BE Transistor Q in unit 3 3B The emitter and ΔV BE Transistor Q in unit 4 4B is connected to the base, and the ΔV BE In unit 5, the triode Q 5B is connected to the emitter and ΔV BE In unit 6, the triode Q 6B is connected to the base, and the ΔV BE In unit 6, the triode Q 6B is connected to the emitter and ΔV BE In unit 7, the triode Q 7B is connected to the base, and the ΔV BE In unit 7, the triode Q 7B is connected to the emitter and ΔV BE In unit 8, the triode Q 8B is connected to the base, and this connection method is the series form of the ΔV BE unit; the ΔV BE In unit 4, the triode Q 4B is connected to the collector and ΔV BE In unit 8, the triode Q 8B is connected to the emitter, and this connection method is the parallel form of the ΔV BE unit; the ΔV BE In unit 1, the triode Q 1A is connected to the base and the collector, and the ΔV BE In unit 5, the triode Q 5A is connected to the base and the collector; the ΔV BE In unit 1, the triode Q 1A is connected to the collector and the negative electrode of the current source I1, so as to realize ΔV BE The current of unit 1 is provided by the current source I1, and the ΔV BE In unit 5, the triode Q 5A is connected to the collector and the negative electrode of the current source I5, so as to realize ΔV BE The current of unit 5 is provided by the current source I5; the positive electrode of the current source I1 is connected to the power supply voltage V DD is connected, and the positive electrode of the current source I5 is connected to the power supply voltage V DD is connected; the ΔV BE In unit 4, the triode Q 4B is grounded at the emitter; the ΔV BE In unit 8, the triode Q 8A can generate the required voltage ΔV BE ×8, the base of the triode Q 8A can generate the required reference voltage V REF .

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