Data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a data processing method and device, electronic equipment and a storage medium, and belongs to the technical field of computers, and the method comprises the steps that to-be-processed data is stored in a memory array; reading data in the memory array cycle by cycle in an assembly line mode; wherein all data read from the memory array presents a parallelogram-like data structure in time sequence. According to the data processing method and device, the electronic equipment and the storage medium provided by the invention, the data structure entering the subsequent data operation unit is changed by changing the data reading mode, that is, the data of the original rectangular block is serially input into the subsequent processing unit according to the parallelogram-like data structure, so that the data processing efficiency is improved. Therefore, the data processing capacity of the data operation unit is gradually started and excited, the power consumption change of the data operation unit during starting is slowed down, and the problem of power consumption transient impact is effectively avoided.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data processing method, device, electronic equipment and storage medium. Background Art

[0002] With the widespread application of deep learning in various industries, conventional general-purpose processors can no longer meet performance requirements. Field-Programmable Gate Array (FPGA) can accelerate processing performance, but its high cost limits its further use. With the in-depth application of neural networks in vertical fields, application-specific integrated circuits (ASIC) have emerged due to their high performance and low cost in large-scale mass production, and processors (Neural Processing Unit, NPU) specifically used to accelerate neural network processing have emerged.

[0003] After the NPU parses the instruction and sends it to the execution module, the execution module needs to start a large number of data computing units within 1 cycle (about 1.6ns), and requires each data computing unit to switch from idle state to busy state (idle state -> busy state) in a very short time. This instantaneous large-scale change in logic power consumption will introduce the risk of power instantaneous impact (PI), and ultimately cause NPU operation errors.

[0004] In order to avoid PI risk, it can usually be solved by reducing the frequency or increasing the voltage. However, reducing the frequency will reduce the NPU performance, while increasing the voltage will bring greater power consumption, so both are not the optimal solution. Summary of the invention

[0005] The present invention provides a data processing method, device, electronic device and storage medium, which are used to solve the PI problem introduced by the NPU processor during the service startup phase due to sudden changes in power consumption, including large-scale logic circuits flipping simultaneously in a very short time, thereby slowing down the power consumption change and solving the PI problem when each internal data operation unit changes from idle->busy.

[0006] The present invention provides a data processing method, comprising: The data to be processed is stored in a memory array; The data in the memory array are read cycle by cycle in a pipeline manner; wherein all the data read from the memory array present a parallelogram-like data structure in terms of timing.

[0007] According to the data processing method provided by the present invention, before reading the data in the memory array cycle by cycle in a pipeline manner, the method further includes: Dividing the data into multiple rows of data; The multiple rows of data are written in parallel to each storage unit in the memory array by row in each cycle, and each row of data is located at the same storage address of each storage unit; wherein the storage address when writing to the storage unit in a subsequent cycle is the next storage address when writing to the storage unit in a previous cycle.

[0008] According to the data processing method provided by the present invention, the data in the memory array is read cycle by cycle in a pipeline manner, comprising: Reading data from the memory array in any cycle until all data in the memory array are read; Among them, before the number of rows of data read out in any cycle reaches the preset number, the data read out in any cycle increases by at least one row of data relative to the data read out in the previous cycle; after the number of rows of data read out in any cycle reaches the preset number, the data read out decreases by at least one row of data relative to the data read out in the previous cycle.

[0009] According to the data processing method provided by the present invention, the number of storage units in the memory array is not less than the number of rows into which the data is divided.

[0010] According to the data processing method provided by the present invention, the memory array is a FIFO array.

[0011] According to the data processing method provided by the present invention, before the number of rows of data read out in any cycle reaches a preset number, the method includes: in any target cycle, according to the order in which the data is written to each storage unit in the memory array, in a first-in-first-out manner, one row of the data written in parallel in each cycle before the target cycle is read from the memory array in sequence without repetition.

[0012] According to the data processing method provided by the present invention, after the number of rows of data read out in any cycle reaches the preset number, the method comprises: in any target cycle, according to the order in which data is written into each storage unit in the memory array, in a first-in-first-out manner, reading one row of data written in parallel in each cycle before the target cycle from the memory array in sequence without repetition; If the data written into the memory array in parallel in any cycle before the target cycle have been read, the data of any cycle read in the target cycle is empty.

[0013] The present invention also provides a data processing device, comprising: A data reading unit is used to read the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in time sequence.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any of the above-mentioned data processing methods is implemented.

[0015] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the data processing method described above is implemented.

[0016] The data processing method, device, electronic device and storage medium provided by the present invention change the data reading method so that the data structure entering the subsequent data operation unit changes, that is, by serially inputting the original rectangular block data into the subsequent data operation unit according to a parallelogram-like data structure, the data processing capability of the data operation unit is gradually started and stimulated, the power consumption change when the data operation unit is started is slowed down, and the problem of transient power consumption impact is effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a flow chart of the data processing method provided by the present invention.

[0019] Figure 2 It is a schematic diagram comparing the data formats entering the MAC module between the prior art and the data processing method provided by the present invention.

[0020] Figure 3 It is a schematic diagram of reading and writing data in the first cycle of the data processing method provided by the present invention.

[0021] Figure 4 It is a schematic diagram of reading and writing data in the second cycle in the data processing method provided by the present invention.

[0022] Figure 5 It is a schematic diagram of reading and writing data in the third cycle in the data processing method provided by the present invention.

[0023] Figure 6 It is a schematic diagram of reading and writing data in the fourth cycle in the data processing method provided by the present invention.

[0024] Figure 7 It is a schematic diagram of reading and writing data in the fifth cycle in the data processing method provided by the present invention.

[0025] Figure 8 It is a schematic diagram of reading and writing data in the eighth cycle in the data processing method provided by the present invention.

[0026] Fig. 9 It is a data structure before the number of rows of data read out in the data processing method provided by the present invention reaches the maximum number of addresses; Fig.10 It is a data structure after the number of rows of data read out in the data processing method provided by the present invention reaches the maximum number of addresses; Fig.11 It is a structural schematic diagram of the data processing device provided by the present invention.

[0027] Fig.12 It is a circuit flow diagram of the data processing device provided by the present invention when it is running.

[0028] Fig.13 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The orientation or position relationship indicated by the terms "up and down", "left and right", "front and back" and the like are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0032] In the practical application of Convolutional Neural Network (CNN), layer data processing often becomes one of the performance bottlenecks. Traditional data reading and processing methods have the following shortcomings: Low data reading efficiency: The traditional serial reading method cannot fully utilize the system's parallel processing capabilities, resulting in low data reading efficiency. Reading a large amount of data at one time may lead to waste of system resources and peak power consumption.

[0033] Poor power management: Sudden changes in data processing (such as processing large amounts of data simultaneously) can cause dramatic fluctuations in system power consumption, putting pressure on the power supply system. Fluctuations in power consumption can also cause changes in the system's internal temperature, affecting the stability and life of hardware components.

[0034] Poor scalability and adaptability: Traditional data reading and processing methods are often difficult to adapt to data processing requirements of different scales and types. When processing larger data sets or more complex network structures, system performance may be severely limited.

[0035] In order to solve the above problems, the present invention proposes an innovative data reading and processing method, which can realize efficient parallel processing of data and smooth power consumption management by changing the way data enters the data operation unit in the processor, that is, by serially reading the original rectangular block data according to a parallelogram-like data structure, and introducing a pipeline reading strategy. At the same time, the method also has good scalability and adaptability, and can meet the data processing needs of different scales and types.

[0036] Combine the following Figure 1-Figure 11 The data processing method, device, electronic device and storage medium provided by the present invention are described.

[0037] The process of the data processing method provided by the present invention includes but is not limited to the following steps: The data to be processed is stored in a memory array; The data in the memory array are read cycle by cycle in a pipeline manner; wherein all the data read from the memory array present a parallelogram-like data structure in terms of timing.

[0038] Before reading the data in the memory array cycle by cycle in a pipeline manner, the method may further include writing the data to be processed into the memory array cycle by cycle.

[0039] therefore, Figure 1 It is a flow chart of the data processing method provided by the present invention, such as Figure 1 As shown, including but not limited to the following steps: Step 101 , writing the data to be processed into the memory array cycle by cycle.

[0040] Step 102, reading the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in terms of timing.

[0041] In order to further explain the data reading and processing method provided by the present invention, the background system architecture of the present invention is briefly introduced before this, so as to facilitate the understanding of the implementation environment and overall design concept of the present invention.

[0042] The system architecture of the present invention is mainly designed around the data processing flow of the neural network, and is particularly optimized for the reading and processing of large amounts of data in the layer. The system mainly includes the following key components: a data preprocessing module, a memory array, a data operation unit, and a control logic module.

[0043] The data preprocessing module is responsible for dividing the original data (such as image data), usually by rows (or columns) to meet the needs of subsequent parallel processing. The divided data is written into the memory array in parallel, and each storage cell in the memory array corresponds to one (or several) rows of data.

[0044] The FIFO array is a first-in-first-out storage structure used to temporarily store data. When reading data, the FIFO array is used to cache the data to be processed so that the data can be written, read and post-processed in a pipeline manner. As the core component of the data cache, the FIFO array consists of multiple independent FIFO storage units. Each FIFO storage unit has an independent read and write interface, which can process different data rows at the same time and realize parallel access of data. The number of FIFO storage units, the number of storage addresses of each unit, the data width and other parameters are designed according to specific application requirements to ensure efficient processing and storage of data.

[0045] As an optional embodiment, the memory array mentioned in the present invention can be a First-In-First-Out (FIFO) memory array, a register file, a static random access memory (SRAM), a dynamic random access memory (DRAM), or an embedded memory such as EEPROM, FRAM, etc., as long as it can meet the sequential storage and sequential reading of data, there is no limitation on the type of the memory array.

[0046] The FIFO array may be considered as the memory array to execute the data processing method provided by the present invention, mainly based on its advantages in data flow control, implementation complexity, power consumption performance and resource utilization.

[0047] First, the FIFO array is naturally suitable for data flow control, and can store and forward data packets in the data flow to ensure that the data is processed in the correct order. The main improvement of the present invention over the prior art is to ensure that all data read from the memory array presents a parallelogram-like data structure in timing, so the use of the FIFO array to change the way data enters the data operation unit can most effectively achieve data being sent to the data operation unit in the correct order and format.

[0048] In addition, FIFO arrays are relatively simple to implement, especially where a fixed-size buffer is required. They can be easily implemented in hardware such as shift registers or dual-port RAM.

[0049] In addition, when frequent reading and writing are required but the amount of data is not particularly large, the power consumption of the FIFO array is relatively low. This is crucial to reducing the power consumption of the processor and the risk of PI.

[0050] Of course, the above description is only from the perspective of comparison to consider the selection of FIFO array as the memory array to execute the data processing method provided by the present invention, but it does not exclude the possibility of using other memory arrays. For the convenience of description, the subsequent embodiments are all described by taking FIFO array as an example, which is not regarded as a specific limitation on the protection scope of the present invention.

[0051] The data operation unit is responsible for serially reading data from the FIFO array cycle by cycle and sending it to the data operation unit for operation. The reading operation adopts a pipeline method, and the number of data rows read in each cycle is dynamically adjusted (increased or decreased) to achieve smooth power consumption changes and efficient data processing. After the read data is processed by the data operation unit, the output result is used by the subsequent layer.

[0052] As an optional embodiment, the processor mentioned in the present invention may be an NPU processor, or a CPU processor, etc. Taking the NPU processor as an example, it may contain various types of data operation units, such as an accumulator array, a multiplier array, or a multiplier-adder array. These data operation units are usually large in logic scale and concentrated, and are prone to PI problems introduced due to sudden changes in power consumption during the service startup phase. For example, it refers to the multiplier-accumulator array (MAC) array. In the NPU processor, the MAC array introduces the PI problem due to sudden changes in power consumption during the service startup phase. The reason for the sudden change in power consumption is generally caused by the large-scale logic circuits flipping simultaneously in a very short time, causing a sudden change in power consumption. For ease of explanation, the subsequent embodiments are all explained by taking the solution of the PI problem of the MAC array in the NPU as an example.

[0053] The control logic module is responsible for the scheduling and control of the entire system, including data preprocessing, data writing to the FIFO array, synchronization and coordination of data reading and processing, etc. At the same time, it can dynamically adjust the reading strategy according to the real-time status and processing requirements of the system to ensure efficient and stable operation of the system.

[0054] Among them, the pipeline method is a parallel processing technology that speeds up the overall processing speed by breaking down complex tasks into multiple simple subtasks and executing these subtasks in parallel at different time steps. In data reading, pipeline processing achieves efficient calculation by continuously reading data from the FIFO array and inputting it into the MAC array for processing.

[0055] A parallelogram-like data structure is a data pattern presented in time series, which reflects the change in the amount of data during the data reading process, that is, the figure formed by connecting the four vertices of the data structure of all the data read out in time series is a parallelogram, and this data structure is called a parallelogram-like data structure. For example, when reading data written to the FIFO array, the four vertices formed by all the data read out are connected into lines, and the maximum closed area surrounded by these four lines is equivalent to a parallelogram figure; therefore, by setting the reading control strategy of the FIFO array, the read data can present a parallelogram-like data structure in time series, which helps to optimize the performance and power consumption of the processor.

[0056] Figure 2 FIG. 1 is a schematic diagram comparing the data formats entering the MAC module in the prior art and the data processing method provided by the present invention. Figure 2 As shown in the upper figure in the prior art, it is the data before entering the MAC array (that is, the parallelogram-like pipeline processing is not performed in the manner provided by the present invention), and the feature data read from the on-chip cache is generally a rectangular block (for example Figure 2 As shown, 64 points are read in each cycle, 8 points in each row and column). If no processing is done, the data corresponding to the rectangular block will directly enter the MAC array, which will cause large-scale logic circuits to flip simultaneously in a very short time, causing sudden changes in power consumption, thereby causing PI problems.

[0057] To optimize this problem, refer to Figure 2As shown in the following figure, the present invention adds a circuit pipeline between fetching data and reading data input to the MAC array, that is, introduces a FIFO array to change the data structure of the data input to the MAC array, so as to utilize it to transform the rectangular blocks input to the MAC array into a data structure that is similar to a parallelogram in timing (that is, from the perspective of an extended time interval, that is, 8 cycles of the prior art are extended to 16 cycles, so that the entire filling pattern is similar to a parallelogram), so that the power consumption change of the MAC array can be slowed down, thereby solving the PI problem when the MAC array changes from an idle state to a busy state.

[0058] The present invention provides a specific optional embodiment, which details how to read data, as described below: First, before reading data, clear each FIFO storage unit in the FIFO array, that is, ensure that the FIFO array is empty, and configure the relevant parameters of each FIFO storage unit in the FIFO array as needed, such as storage depth (equivalent to the number of addresses), data width (equivalent to the storable data width of each storage address in each FIFO storage unit), etc.

[0059] The data to be processed is divided into multiple parts (for example, by row, by column or by block). In each cycle, a part of the divided data is written to the available address of a FIFO storage unit in the FIFO array. This step is repeated until all the data to be processed are written into the FIFO array; for example, if the data to be processed is a data array composed of M data blocks (the structure of the data block can be a rectangular block), each data block is composed of N points in each row and column (each point is equivalent to 1 bit), for each data block, it can be divided by row and then input into the available address of a FIFO storage unit in the FIFO array by row, and each available address is equivalent to storing 1 row of N points. In the first cycle, the first data block is divided into N rows by row (each row has 8 points, which is equivalent to 8 bits, thus forming 1 data, so N rows can also be represented as N data), and written to the same address of 8 different FIFOs respectively, for example, in the first cycle, it is written to address 0 of 8 different FIFOs respectively; in the second cycle, the second data block is written to address 1 of 8 different FIFOs in the above manner.

[0060] Data can be serially read from the FIFO array during the process of writing the data to be processed into the FIFO array, or at the beginning of the next cycle after the data in the first data block of the data to be processed are all written into the FIFO array. It should be noted that the data read follows the first-in-first-out principle of the FIFO array, that is, the data written first is read first.

[0061] The read data is directly input into the MAC array for calculation in each cycle.

[0062] The present invention designs a data read and write strategy, controls the writing and reading mode and rate, so that the data read from the FIFO array presents a parallelogram-like data structure in timing. Assuming that all the data to be processed are read after 16 cycles (that is, for 8 8*8 data blocks, the data is read in a manner of gradually increasing by 1 row per cycle before the first node and gradually decreasing by 1 row per cycle after the first node, and the eighth cycle is the first node at which the number of rows of the read data reaches a preset number, and the preset number can be freely set according to the capacity of the storage unit or the needs of the subsequent data operation unit, for example, the preset number can be set to the maximum address number of the storage unit in the memory array), then the leftmost data in the data read in the first cycle of data reading is used as the vertex of the lower left corner, the bottommost and rightmost data in the data read in the eighth cycle is used as the vertex of the lower right corner, the topmost and leftmost data in the data read in the eighth cycle is used as the vertex of the upper left corner, and the rightmost data in the data read in the last cycle (that is, the 16th cycle) is used as the vertex of the lower left corner.

[0063] refer to Figure 2 The following picture in (it should be noted that Figures 2 to 10 The cycle in the description represents the cycle in the present invention), which can be understood as that, in the initial stage, the amount of data read from the FIFO array gradually increases (corresponding to the rising edge of the quasi-parallelogram), and then gradually decreases (corresponding to the falling edge of the quasi-parallelogram). It should be noted that the first node can be used as a boundary. Before the first node, the data read from the FIFO array can be gradually increased cycle by cycle in a pipeline manner, and all the data read out form the falling edge of the quasi-parallelogram in timing; after the first node, the data read from the FIFO array can be gradually reduced cycle by cycle in a pipeline manner, and all the data read out form the falling edge of the quasi-parallelogram in timing. The first node is the time node when the number of rows of the read data reaches a preset number.

[0064] The data processing method provided by the present invention changes the way in which data in the NPU enters the MAC, that is, by serially inputting the original rectangular block data into the MAC array according to the parallelogram-like data structure, thereby gradually starting the MAC array. Since the parallelogram-like data structure presents a "diagonal filling" mode in timing, that is, the data is not fully loaded into the MAC array at one time, but is gradually read out serially from the FIFO array as the clock cycle advances, the load and power consumption of the processor can be balanced. On the rising and falling edges of the parallelogram-like data structure, the load of the processor is lighter, so the power consumption change when the MAC array is started can be slowed down, thereby effectively avoiding the problem of transient power consumption impact.

[0065] Based on the content of the above embodiment, as an optional embodiment, before reading the data in the memory array cycle by cycle in a pipeline manner, the method further includes: Dividing the data into multiple rows of data; The multiple rows of data are written in parallel to each storage unit in the memory array by row in each cycle, and each row of data is located at the same storage address of each storage unit; wherein the storage address when writing to the storage unit in a subsequent cycle is the next storage address when writing to the storage unit in a previous cycle.

[0066] As an optional embodiment, each data block in the data to be processed can be divided into rows. This is usually based on the original format of the data and the processing capability of the neural network processor to determine the amount of data in each row and the number of rows to be divided. By dividing the data blocks into rows and writing them in parallel into multiple storage units of the FIFO array, the parallel processing capability of the neural network processor can be fully utilized to improve the efficiency of data writing.

[0067] It should be noted that the data partitioning and writing strategy can be dynamically adjusted according to the real-time load of the neural network processor and the characteristics of the data to be processed. For example, when the processor load is light, the number of parallel write rows can be increased to improve the writing efficiency; when the processor load is heavy, the number of parallel write rows can be reduced to balance the processor load.

[0068] In each cycle, the divided multiple rows of data are written into the FIFO array in parallel. Here, "parallel" means writing into multiple FIFO storage units of the FIFO array at the same time, rather than writing multiple data in parallel in a single FIFO storage unit.

[0069] It should be noted that the data is a data block in a data array of any size. It is assumed that the data to be processed is a data array composed of M data blocks, each data block consists of N points in rows and columns, and each data block can be divided by rows. Subsequently, each data block consists of the first row of data, the second row of data, ..., the Nth row of data. At this time, the number of FIFO storage units of the called FIFO memory will be set to N, and the number of addresses of each FIFO storage unit of the called FIFO memory is M.

[0070] For example, for each data block, it will be written to the same storage address of all FIFO storage units, that is, any row in the above data block will be written to the same storage address of N FIFO storage units. For example, in a certain cycle, the first data block will be written to the first address of N FIFO storage units, and in the next cycle, the second data block will be written to the second address of N FIFO storage units, and so on until all data are written. That is to say, the storage address when writing to the storage unit in the next cycle is the next storage address of the storage address when writing to the storage unit in the previous cycle, and 1 data is stored at each storage address. In addition, for data writing in a single cycle, for example, in the first cycle, the first row of data (referring to the data block) will be written to the first address of the first FIFO in the FIFO array, the second row of data will be written to the first address of the second FIFO in the FIFO array, and in the second cycle, the first row of the second row of data will be written to the second address of the first FIFO in the FIFO array, and the second row of data will be written to the second address of the second FIFO in the FIFO array, and so on.

[0071] Therefore, in the next cycle, when a new data block needs to be written, the previously written data is not overwritten, but the data in the new data block is written to the next storage address. That is, the storage address written to the FIFO storage unit in the next cycle is the next storage address of the address written in the previous cycle. By updating the storage address in each cycle, the orderly storage and correct reading of data in the FIFO array can be ensured. At the same time, this address management method also supports the possibility of data presenting a parallelogram-like data structure in timing.

[0072] In addition, by introducing an intelligent address management mechanism, such as predicting the data address that needs to be read in the future and writing the data to the corresponding location in advance, or dynamically adjusting the write rate according to the read rate, the data storage and reading efficiency can be further optimized.

[0073] The data processing method provided by the present invention can significantly reduce the time of data writing compared to serial writing due to the use of parallel writing, thereby improving the overall processing efficiency of the neural network processor. At the same time, by dividing by rows and writing in parallel, the data is stored in an orderly manner in the FIFO array, which facilitates subsequent serial or parallel reading and processing. Since data writing is carried out in parallel and address updates are carried out cycle by cycle, the power consumption of the processor can be controlled more finely, and efficient processing under low power consumption can be achieved. The key is to provide a basis for reading out a data structure that presents a parallelogram-like shape.

[0074] Based on the content of the above embodiment, as an optional embodiment, the reading of data from the memory array cycle by cycle in a pipeline manner includes the following steps: Reading data from the memory array in any cycle until all data in the memory array are read; Among them, before the number of rows of data read out in any cycle reaches a preset number, the data read out in any cycle increases by at least one row of data relative to the data read out in the previous cycle; after the number of rows of data read out in any cycle reaches the preset number, the data read out decreases by at least one row of data relative to the data read out in the previous cycle.

[0075] It should be noted that the pipelined reading of data in the memory array cycle by cycle starts at the next cycle after the data is written to the memory array, and the preset number can be freely set according to the storage unit capacity or the computing requirements of the subsequent data computing unit. For example, the preset number can be set to the maximum address number of the storage unit in the memory array. If you want to further reduce power consumption and reduce the amount of data output to the data computing unit on this basis, you can also choose to set the preset number to three quarters of the maximum address number of the storage unit in the memory array. The present invention does not impose any restrictions on this.

[0076] If data is read from the FIFO array cycle by cycle in a pipeline manner, a serial reading method can be adopted, that is, data is serially read from the FIFO array in any cycle until all data in the memory array is read. For example, according to the first-in first-out rule, assuming that in cycle 1, the 0th row of data is written to address 0 of FIFO 0, the 1st row of data is written to address 0 of FIFO 1, the 2nd row of data is written to address 0 of FIFO 2, ..., and the 7th row of data is written to address 0 of FIFO 7; in cycle 2, the 0th row of data is written to address 1 of FIFO 0, the 1st row of data is written to address 1 of FIFO 1, the 2nd row of data is written to address 1 of FIFO 2, ..., and the 7th row of data is written to address 1 of FIFO 7. At the same time, the address 0 output of FIFO 0 can be read; therefore, in cycle 2, the 0th row of data is written to address 2 of FIFO 0, the 1st row of data is written to address 2 of FIFO 1, the 2nd row of data is written to address 2 of FIFO 2, ..., and the 7th row of data is written to address 1 of FIFO 7. 7, and at the same time, read address 1 of FIFO 0, and read address 0 of FIFO 1 for output. Among them, for "read address 1 of FIFO 0, read address 0 of FIFO 1 for output", serial reading can be performed in a first-in-first-out manner, first reading address 0 of FIFO 1 for output, and then reading address 1 of FIFO 0 for output, but it can also be controlled by instructions to read address 0 of FIFO 1 and address 1 of FIFO 0 for output at the same time; especially for general memory arrays, when reading data in a single cycle, a parallel reading method can be used to read the data written to the memory array in the cycle before this cycle, as long as the data finally read between cycles is in a parallelogram-like timing sequence. It should be noted that the above embodiment sets the preset number as the maximum number of addresses of storage units in the memory array.

[0077] Therefore, as an optional embodiment, the reading of data from the FIFO array cycle by cycle in a pipeline manner includes the following steps: Reading data from the FIFO array in any cycle until all data in the FIFO array are read; Among them, before the number of rows of data read out in any cycle reaches the preset number, the data read out in any cycle increases by at least one row of data relative to the data read out in the previous cycle; after the number of rows of data read out in any cycle reaches the preset number, the data read out decreases by at least one row of data relative to the data read out in the previous cycle.

[0078] In addition, the present invention determines the number of data rows read in the next cycle based on whether the number of data rows read in any cycle reaches the preset number, so that the data structure read (or input to the MAC array) within the entire time axis range presents a parallelogram-like result.

[0079] Since the preset number is the maximum address number of the FIFO storage unit in the FIFO array, when the number of rows of data read out in any cycle reaches the maximum address number of the storage unit in the FIFO array, the number of rows of data read out is the maximum address number.

[0080] It should be noted that Figure 2 The examples shown are all based on the case where before the number of rows of data read out in any cycle reaches the maximum number of addresses of storage units in the FIFO array, the number of rows of data read out in the next cycle increases by one row relative to the number of rows of data read out in the previous cycle, and after the number of rows of data read out in any cycle reaches the maximum number of addresses of storage units in the FIFO array, the number of rows of data read out in the next cycle increases by one row relative to the number of rows of data read out in the previous cycle. However, this is not regarded as the only implementation mode of the present invention and can be flexibly adjusted according to the situation of the MAC array, as long as all data input to the MAC array presents a parallelogram-like data structure in timing.

[0081] Theoretically, the number of rows of data read out in the next cycle that increases or decreases can be 2 rows, 3 rows, or other settings, and can be reasonably set according to the actual computing power of the MAC array. The present invention does not limit the number of rows of data read out in the next cycle to a fixed value, and can also be dynamically adjusted according to the state of the MAC array when processing the current cycle. However, for the convenience of description of the subsequent embodiments, the number of rows increased or decreased is set to 1 for illustration.

[0082] Specifically, the above-mentioned serial reading implementation steps of reading the data in the memory array cycle by cycle in a pipeline manner can be expressed as the following implementation steps (similarly, for different types of memory arrays, a more flexible reading method can be adopted for reading data in a single cycle according to the read and write rules of the memory array, for example, data can be read from the memory array in parallel in a single cycle): Step 1, serially reading data from the FIFO array in one cycle, the data read out increases by at least one row of data compared with the data read out in the previous cycle; Step 2, repeating step 1 until the number of rows of data read out in one cycle reaches the preset number; Step 3, continue to read data serially from the FIFO array in one cycle, and the data read out is reduced by at least one row of data compared with the data read out in the previous cycle; Step 4, repeat step 3 until the number of rows of data read out in one cycle is empty, then execute step 1; Step 5, iteratively executing steps 1 to 4 until all data in the FIFO array are read.

[0083] Specifically, in one cycle, data is read serially from the FIFO array. The key here is that the data read out must increase by at least one row compared to the data read out in the previous cycle. This usually means that as the cycle increases, the amount of data read each time also gradually increases, forming a process similar to the rising edge of a parallelogram-like data structure.

[0084] Repeat step 1, and the amount of data read each time continues to increase. This process continues until the number of rows of data read in one cycle reaches a preset number, at which point the amount of data read reaches a maximum value, corresponding to the top of the parallelogram-like data structure.

[0085] After reaching the preset data volume, data is continuously read serially from the FIFO array in one cycle, but the data read out at this time is at least one row less than the data read out in the previous cycle. This indicates that the parallelogram-like data structure begins to enter the descending edge, and the amount of data read is gradually reduced.

[0086] Repeat step 3 to continue reducing the number of data rows read in each cycle. This process continues until the number of data rows read in a cycle is empty, that is, all data in the FIFO array has been read.

[0087] Steps 1 to 4 are executed iteratively, which is usually to process continuous data blocks or new data. Each iteration re-reads the data in the FIFO array according to the process of steps 1 to 4 until all the data to be processed are read.

[0088] The above embodiment adopts a serial reading strategy between cycles according to the properties of the FIFO array when reading data. When reading data in any cycle, a serial reading strategy of the data written to the memory array in the previous cycle is also adopted. In order to further improve the processing efficiency, in actual application scenarios, a parallel reading strategy can be adopted when reading data in a cycle according to the actual computing power of the MAC array. For example, the following can be adopted: Step 1, reading data in parallel from the memory array in one cycle, the data read out increases by at least one row of data compared with the data read out in the previous cycle; Step 2, repeating step 1 until the number of rows of data read out in one cycle reaches a preset number; Step 3, continue to read data in parallel from the memory array in one cycle, and the data read out is reduced by at least one row of data compared with the data read out in the previous cycle; Step 4, repeat step 3 until the number of rows of data read out in one cycle is empty, then execute step 1; Step 5, iteratively executing steps 1 to 4 until all data in the memory array are read.

[0089] As an optional embodiment, a layer of data cache can be added between the FIFO array and the MAC array to cache the data to be processed, which can reduce the number of times data is directly read from the FIFO array, further reduce power consumption and improve processing efficiency.

[0090] The present invention adopts this pipeline serial reading strategy, making full use of the storage characteristics of the FIFO array and the data processing requirements of the neural network processor. By gradually increasing and then reducing the number of data rows read in each cycle, a parallelogram-like data structure is formed, which helps to balance the processor load, optimize power consumption, and improve data processing efficiency.

[0091] As an optional embodiment, the number of rows into which each data in the data to be processed is divided can be defined as 8 rows. Correspondingly, the number of FIFO storage units in the FIFO array is 8, and the number of storage addresses of each FIFO storage unit (i.e., the depth of the FIFO storage unit) is 8, and the storable data width of each storage address (i.e., the width of the FIFO storage unit) is 8 bytes. For the predefined FIFO array, by adding a pre-set read-write control strategy to it, the transformation of the data structure of all the data read out in the timing sequence to present a parallelogram-like shape can be realized.

[0092] As an optional embodiment, for different structural types of data to be processed, the data to be processed can be a data array, each data block in the data array is divided into multiple rows of data, and the number of storage units in the memory array is not less than the number of rows divided by any data block in the data array.

[0093] Of course, the above-mentioned settings of parameters such as the number of rows for data division, the number of FIFO storage units in the FIFO array, the number of storage addresses of each FIFO storage unit (i.e., depth), and the storable data width of each storage address (i.e., width), for example, the selection of the FIFO storage unit depth may not be less than the number of data blocks divided from the data to be processed, allow for customization and optimization according to specific application scenarios and performance requirements, for example, there may be other implementable methods.

[0094] For example, if any data block in the data to be processed is divided and the number of rows after division is 12, the number of FIFO storage units in the FIFO array is set to 12, and the number of storage addresses of each FIFO storage unit can be customized according to the core size and data flow requirements, for example, set to 24, and according to the data type and precision requirements, the storable data width of each storage address is set to 32 bits.

[0095] In summary, when setting the above parameters, it is necessary to ensure that the number of rows of data division matches the number of FIFO storage units to avoid data read and write conflicts or resource waste, and to reasonably set the depth and width of each FIFO storage unit to balance storage efficiency and data processing speed. At the same time, the parameter setting should always consider possible future changes in demand to ensure that the method provided by the present invention has certain scalability.

[0096] Combine the following Figure 3-Figure 8 As shown, the specific implementation process of serially reading data from the FIFO array cycle by cycle in a pipeline manner is described in detail.

[0097] As an optional embodiment, before the number of rows of data read out in any cycle reaches a preset number, it includes: in any target cycle, according to the order in which the data is written to each storage unit in the memory array, in a first-in-first-out manner, one row of the data written in parallel in each cycle before the target cycle is read from the memory array in sequence without repetition.

[0098] Figure 3 Schematic diagram of reading and writing data in cycle 0 in the data processing method provided by the present invention. Figure 3As shown, the preset number is set as the maximum address number of the FIFO storage unit in the FIFO array, and in cycle 0, the data to be processed is written to the first-in-first-out FIFO array cycle by cycle, including: writing the 0th row of the divided data to address 0 of FIFO 0, writing the 1st row of data to address 0 of FIFO 1, writing the 2nd row of data to address 0 of FIFO 2, ..., writing the 7th row of data to address 0 of FIFO 7. In cycle 0, only data writing is involved, and there is no data that can be read, that is, the data read-out bit is empty.

[0099] As an optional embodiment, the reading of data from the memory array cycle by cycle in a pipeline manner starts in the next cycle after the data is written into the memory array.

[0100] Figure 4 Schematic diagram of reading and writing data in cycle 1 in the data processing method provided by the present invention. Figure 4 As shown, in cycle 1, the data to be processed is written into the first-in-first-out FIFO array cycle by cycle, including: writing the 0th row of divided data into address 1 of FIFO 0, writing the 1st row of data into address 1 of FIFO 1, writing the 2nd row of data into address 1 of FIFO 2, ..., writing the 7th row of data into address 1 of FIFO 7.

[0101] At the same time, in cycle 1, the data to be processed is written into the first-in-first-out FIFO array cycle by cycle, including: the address 0 of the read FIFO 0 is input into the MAC array.

[0102] Figure 5 Schematic diagram of reading and writing data in cycle 2 in the data processing method provided by the present invention. Figure 5 As shown, in cycle 2, the divided data row 0 is written into address 2 of FIFO 0, the data row 1 is written into address 2 of FIFO 1, the data row 2 is written into address 2 of FIFO 2, ..., the data row 7 is written into address 2 of FIFO 7.

[0103] At the same time, address 1 of FIFO 0 is read and address 0 of FIFO 1 is read. That is, one row of data is added in cycle 1 relative to the data read in cycle 0.

[0104] Figure 6 Schematic diagram of reading and writing data in cycle 3 in the data processing method provided by the present invention. Figure 6As shown, in cycle 3, the divided data row 0 is written into address 3 of FIFO 0, the data row 1 is written into address 3 of FIFO 1, the data row 2 is written into address 3 of FIFO 2, ..., the data row 7 is written into address 3 of FIFO 7.

[0105] At the same time, address 2 of FIFO 0 is read, address 1 of FIFO 1 is read, and address 0 of FIFO 2 is read and output. That is, in cycle 1, one row of data is added compared to the data read out of cycle 0, and two rows of data are added compared to the data read out of cycle 0.

[0106] Figure 7 FIG. 4 is a schematic diagram of reading and writing data in cycle 4 in the data processing method provided by the present invention. Figure 7 As shown, in cycle 4, the divided data row 0 is written into address 4 of FIFO 0, the data row 1 is written into address 4 of FIFO 1, the data row 2 is written into address 4 of FIFO 2, ..., the data row 7 is written into address 4 of FIFO 7.

[0107] At the same time, address 3 of FIFO 0 is read, address 2 of FIFO 1 is read, address 1 of FIFO 2 is read, and address 0 of FIFO 3 is read out.

[0108] Figure 8 FIG. 1 is a schematic diagram of reading and writing data in cycle 7 in the data processing method provided by the present invention. Figure 8 As shown, and so on until cycle 7, which will not be described in detail in this embodiment.

[0109] If any FIFO storage unit in the FIFO array needs to continue writing after writing to address 7, it will jump to FIFO 0 of each FIFO storage unit, and the read address of each FIFO storage unit will be set accordingly.

[0110] For example, based on the above embodiment, when cycle 8 needs to continue writing, data line 0 is written to address 0 of FIFO 0, data line 1 is written to address 0 of FIFO 1, data line 2 is written to address 0 of FIFO 2, ..., data line 7 is written to address 0 of FIFO 7.

[0111] At the same time, address 7 of FIFO 0 is read, address 6 of FIFO 1 is read, address 5 of FIFO 2, ..., address 0 of FIFO 7 is read and output.

[0112] Fig. 9 It is a data structure before the number of rows of data read out in the data processing method provided by the present invention reaches a preset number, such as Fig. 9 As shown, taking the case where the number of FIFO storage units in the FIFO array is 8, the number of storage addresses of each of the FIFO storage units is 8, and the storable data width of each of the storage addresses is 8 bytes as an example, before the number of rows of data read out reaches the maximum number of addresses of the storage unit, one row of data written in parallel in each cycle before the target cycle will be read from the memory array in a first-in-first-out manner without repetition, and the data read out in the next cycle increases by one row of data relative to the data read out in the previous cycle, until cycle 8. It should be noted that for FIFO arrays or other types of memory arrays, a reading strategy of reading in parallel from the memory array without repetition at least one row of data written in parallel in each cycle before the target cycle can also be adopted, that is, data reading in a single cycle can adopt serial reading of data at multiple addresses or parallel simultaneous reading of data at multiple addresses.

[0113] Fig.10 It is a data structure after the number of rows of data read out in the data processing method provided by the present invention reaches the maximum number of addresses, such as Fig.10 As shown, as another optional embodiment, after the number of rows of data read out in any cycle reaches the preset number, the method includes: in any target cycle, according to the order in which data is written to each storage unit in the memory array, in a first-in-first-out manner, one row of data written in parallel in each cycle before the target cycle is read from the memory array in sequence without repetition; If the data written into the memory array in parallel in any cycle before the target cycle has been read, the data of any cycle read in the target cycle is empty.

[0114] Specifically, the preset number is set as the maximum address of the storage unit in the memory array. After the number of rows of data read out reaches the maximum address number of the storage unit, one row of data written in parallel in each cycle before any target cycle will be read from the FIFO array in a first-in-first-out manner according to the order of data writing, and the data read out in the next cycle increases by one row of data relative to the data read out in the previous cycle, until cycle 15, the above-mentioned writing and reading control logic is iteratively executed cycle by cycle until the processing of all the data to be processed is completed. It should be noted that the data reading in a single cycle can adopt serial reading of data at multiple addresses or parallel simultaneous reading of data at multiple addresses.

[0115] comprehensive Fig. 9 and Fig.10As shown, the data processing method provided by the present invention makes the data structure input to the MAC array present a parallelogram-like format by reasonably designing the data writing and reading control logic, and can start 2048 MACs in multiple cycles (8 cycles), and start 256 MACs per cycle on average, so that the MAC array changes from the idle state to the busy state in a relatively long time, slowing down the power consumption change of the MAC array logic, thereby reducing the PI risk and ensuring the smooth and accurate operation of the NPU.

[0116] It should be noted that the number of FIFO storage units in the FIFO array is not less than the number of rows into which the data is divided.

[0117] In this embodiment, by limiting the number of FIFO storage units in the FIFO array to be no less than the number of rows into which each data block in the data to be processed is divided, the FIFO array can accommodate all the data blocks to be processed. This requirement ensures that the FIFO array has sufficient storage capacity to accommodate all the data blocks. By allocating an independent FIFO storage unit to each data block, parallel writing and serial reading of each row of data in the data block can be achieved, thereby improving the efficiency and stability of data processing. In addition, this design also helps to simplify the complexity of data management and reduce the possibility of errors.

[0118] Specifically, first, the number of rows of data to be processed is determined based on the original format of the data and the processing requirements of the neural network processor. This is usually calculated based on factors such as the kernel size, step size, and padding.

[0119] Then, according to the number of rows divided by the determined data block, the number of FIFO storage units in the FIFO array is designed. The key here is to ensure that the number of FIFO storage units is not less than the number of rows of data. This is done to ensure that each data row can be stored independently in a FIFO storage unit.

[0120] According to the parallel writing strategy described above, the data to be processed is written into the FIFO array row by row. Since the number of FIFO storage units is sufficient, it can be ensured that each data row can be correctly written into the corresponding FIFO storage unit.

[0121] According to the pipeline serial read strategy described above, data is read from the FIFO array. Since each data row is stored in an independent FIFO storage unit, the continuity and stability of the reading process can be ensured.

[0122] Corresponding to the above method embodiment, the disclosed embodiment of the present invention further provides a data processing device, including: A data reading unit is used to read the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in time sequence.

[0123] The data processing device provided by the disclosed embodiment of the present invention further includes: A data writing unit, used for writing the data to be processed into the memory array cycle by cycle; therefore, Fig.11 is a schematic diagram of the structure of the data processing device provided by the present invention, such as Fig.11 As shown, the present invention also provides a data processing device, which is located in a neural network processor and mainly includes: A data writing unit 91 is used to write the data to be processed into the memory array cycle by cycle; The data reading unit 92 is used to read the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in terms of time sequence.

[0124] It should be noted that the data processing device provided by the present invention can execute the data processing method described in any of the above embodiments during specific operation, which will not be elaborated in this embodiment.

[0125] The data processing device provided by the present invention changes the data reading method in the NPU so that the data structure entering the MAC subsequent data operation unit changes. That is, the data of the original rectangular block is serially input into the MAC array subsequent processing unit according to a parallelogram-like data structure, thereby gradually starting and stimulating the data processing capability of the MAC array data operation unit, slowing down the power consumption change when the MAC array data operation unit is started, and effectively avoiding the problem of transient power consumption impact.

[0126] Fig.12 is a schematic diagram of the circuit flow of the data processing device provided by the present invention when it is running, such as Fig.12 As shown, compared with the prior art, the present invention adds a circuit flow module for adjusting the data structure input to the MAC array between the data acquisition module and the MAC array, so that the data input to the MAC array presents a parallelogram-like data structure in timing, so that the MAC array takes a longer time to change from the idle state to the busy state, slowing down the power consumption change of the MAC array logic, thereby reducing the PI risk and ensuring the smooth and accurate operation of the NPU.

[0127] Furthermore, a post-processing module is set after the MAC array, which is responsible for sorting, converting and optimizing the results output by the MAC array, improving the overall computing efficiency and reducing power consumption. By working in conjunction with the circuit flow module and the MAC array, the NPU can run smoothly and accurately and support a variety of different application scenarios and neural network structures.

[0128] Fig.13 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Fig.13 As shown, the electronic device may include: a processor 110, a communication interface 120, a memory 130 and a communication bus 140, wherein the processor 110, the communication interface 120 and the memory 130 communicate with each other through the communication bus 140. The processor 110 may call the logic instructions in the memory 130 to execute the data processing method, which includes: storing the data to be processed in the memory array; reading the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in time sequence.

[0129] In addition, the logic instructions in the above-mentioned memory 130 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0130] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the data processing methods provided in the above-mentioned embodiments, and the method includes: storing the data to be processed in a memory array; reading the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in time sequence.

[0131] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the data processing method provided by the above-mentioned embodiments, the method comprising: storing the data to be processed in a memory array; reading the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in time sequence.

[0132] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0133] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method, characterized in that: include: The data to be processed is stored in a memory array; The data in the memory array are read cycle by cycle in a pipeline manner; wherein all the data read from the memory array present a parallelogram-like data structure in terms of timing.

2. The data processing method according to claim 1, characterized in that: Before reading the data in the memory array cycle by cycle in a pipeline manner, the method further includes: Dividing the data into multiple rows of data; The multiple rows of data are written in parallel to each storage unit in the memory array by row in each cycle, and each row of data is located at the same storage address of each storage unit; wherein the storage address when writing to the storage unit in a subsequent cycle is the next storage address when writing to the storage unit in a previous cycle.

3. The data processing method according to claim 1, characterized in that: The step of reading the data in the memory array cycle by cycle in a pipeline manner comprises: Reading data from the memory array in any cycle until all data in the memory array are read; Among them, before the number of rows of data read out in any cycle reaches the preset number, the data read out in any cycle increases by at least one row of data relative to the data read out in the previous cycle; after the number of rows of data read out in any cycle reaches the preset number, the data read out decreases by at least one row of data relative to the data read out in the previous cycle.

4. The data processing method according to claim 2, characterized in that: The number of storage cells in the memory array is not less than the number of rows into which the data is divided.

5. The data processing method according to any one of claims 3 to 4, characterized in that: The memory array is a FIFO array.

6. The data processing method according to claim 5, characterized in that: Before the number of rows of data read out in any cycle reaches a preset number, the method includes: in any target cycle, according to the order in which the data is written to each storage unit in the memory array, in a first-in-first-out manner, reading one row of data written in parallel in each cycle before the target cycle from the memory array in sequence without repetition.

7. The data processing method according to claim 5, characterized in that: After the number of rows of data read out in any cycle reaches the preset number, the method further comprises: in any target cycle, according to the order in which the data is written into each storage unit in the memory array, in a first-in-first-out manner, reading one row of data written in parallel in each cycle before the target cycle from the memory array in sequence without repetition; If the data written into the memory array in parallel in any cycle before the target cycle have been read, the data of any cycle read in the target cycle is empty.

8. A data processing device, characterized in that: The data processing device is located in a neural network processor and includes: The data reading unit is used to read the data in the memory array cycle by cycle in a pipeline manner; wherein all the data read from the memory array presents a parallelogram-like data structure in time sequence.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the data processing method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 7 is implemented.

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