Synchronous circuit and chip
By introducing a count threshold control logic into the synchronization circuit, data synchronization is performed only when the number of write operations reaches the threshold, which solves the high power consumption problem caused by the counter constantly toggling and improves data access efficiency and bandwidth utilization.
Patent Information
- Application Number
- CN202411346290.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2044-09-26
AI Technical Summary
In existing synchronous circuits, the counter constantly flips, resulting in high dynamic power consumption. Furthermore, the counter's preset threshold is set too low, leading to low data access efficiency and wasted access bandwidth.
A threshold control logic is adopted to perform data synchronization only when the number of write operations reaches the threshold. The write control module generates a trigger signal, and the synchronization control module generates an enable signal based on the count value to realize the synchronization of data between the cache module and the storage module.
It reduces dynamic power consumption, decreases the number of write-back memory modules, and improves bandwidth utilization and data access efficiency.
Smart Images
Figure CN119292526B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of storage, in particular to a synchronization circuit and a chip. BACKGROUND
[0002] With the continuous progress of storage technology, the requirement for data access speed is increasing. In the related art, a synchronization circuit stores all data in a memory unit, and a short time access end may only need to frequently access a small part of the data, at which time the small part of data is stored in a cache unit close to the access source to speed up the access of the access end to the data, but to ensure data consistency, a synchronization controller needs to be set to refresh the latest value back to the memory unit once every period of time.
[0003] The write controller in the synchronization circuit can select a write cache unit or a write memory unit. The read controller in the synchronization circuit obtains whether the corresponding cache unit is valid by querying the bitmap, and if it is valid, reads the cache unit, and if it is invalid, reads the memory unit, and when the result of reading the memory unit is returned, writes the result to the cache unit and sets the corresponding position of the bitmap to valid. The synchronization controller in the synchronization circuit controls the counter to count according to whether the corresponding position of the bitmap is valid, reads the cache unit when the count value reaches a preset time threshold, clears the count value, sets the corresponding position of the bitmap to invalid, and writes the result to the memory unit. When the write controller writes the memory unit, the corresponding position of the bitmap is set to invalid.
[0004] Based on the above, the synchronization circuit in the related art controls whether the data is written to the cache unit or the memory unit by the counter timing, and when the bitmap is valid, the counter is always flipping, which has very high dynamic power consumption. Moreover, if the preset threshold of the counter is set to be small, the data will be updated to the memory unit before the next use, and the content in the memory unit is the latest, and if the latest value is to be obtained, the memory unit needs to be read again, which wastes the access bandwidth and has low access efficiency. SUMMARY
[0005] Therefore, it is necessary to provide a synchronization circuit and a chip, which reduce dynamic power consumption and improve bandwidth utilization and data access efficiency.
[0006] In a first aspect, an embodiment of the present application provides a synchronization circuit, comprising:
[0007] a cache module, configured to store data;
[0008] a storage module, configured to store data;
[0009] a write control module, configured to determine write address information according to a received write command, and generate a trigger signal in a case where the write address information is an address in the cache module.
[0010] a synchronization control module, configured to determine a current count value according to the trigger signal and the write address information, and generate a first synchronization enable signal by adding one to the current count value to obtain a processed count value and generating the first synchronization enable signal when the current count value is less than a count threshold value, and generate a second synchronization enable signal by resetting the current count value to obtain a processed count value and generating the second synchronization enable signal when the current count value is equal to the count threshold value;
[0011] The write control module is further configured to write the write data corresponding to the write command into the corresponding address of the cache module according to the first synchronization enable signal and the write address information, and / or write the write data corresponding to the write command into the storage module according to the second synchronization enable signal and the write address information.
[0012] In one of the embodiments, the synchronization control module comprises:
[0013] a storage unit, configured to store a current count value of cache data at the corresponding address of the cache module, and output the current count value according to the trigger signal;
[0014] a comparator, configured to determine whether the current count value is less than a count threshold value, and generate the first synchronization enable signal if the current count value is less than the count threshold value, otherwise generate the second synchronization enable signal and reset the current count value in the storage unit;
[0015] an adder, configured to add one to the current count value to obtain a processed count value;
[0016] a multiplexer, configured to write the processed count value after addition into the corresponding address of the storage unit, or write the processed count value after resetting into the corresponding address of the storage unit.
[0017] In one of the embodiments, the synchronization circuit further comprises a bitmap,
[0018] The bitmap is configured to store identification information of whether the storage data at the corresponding address of the cache module is valid;
[0019] The write control module is further configured to write the write data corresponding to the write command into the storage module when the write address information is an address in the storage module.
[0020] The write control module is further configured to set the identification information corresponding to the write address information in the bitmap as invalid.
[0021] In one of the embodiments, the synchronization circuit further comprises a read control module,
[0022] The read control module is configured to determine read address information according to the received read command, read identification information at a corresponding address in the bitmap in a case where the read address information is a storage address in the cache module, read data from the read address of the cache module in a case where the identification information is determined to be valid, and read data from the read address of the storage module in a case where the identification information is determined to be invalid.
[0023] In one of the embodiments, the write control module is further configured to write the data read from the read address of the storage module to a corresponding address of the cache module, and set identification information corresponding to the write address information in the bitmap to be valid.
[0024] In one of the embodiments, the read control module is further configured to generate a read response after reading the data, the read response comprising the data read by the read control module.
[0025] In one of the embodiments, the synchronization circuit further comprises a decoding module,
[0026] The decoding module is configured to receive and analyze a data access command, send write address information and write data corresponding to the write command to the write control module in a case where the data access command is a write command, and send read address information corresponding to the read command to the read control module in a case where the data access command is a read command.
[0027] In one of the embodiments, the synchronization circuit further comprises an access interface, the access interface being connected with the write control module, the read control module and the storage module respectively, and the access interface being configured to convert the write command and / or the read command into an interface signal to access the storage module.
[0028] In one of the embodiments, the synchronization control module is further configured to receive and store the number threshold.
[0029] In a second aspect, the embodiments of the present application provide a chip, characterized in that the chip comprises the synchronization circuit as described above.
[0030] The synchronization circuit and the chip receive a write command through the write control module, generate a trigger signal in the case that write address information of the write command is an address in the cache module, the synchronization control module determines a current count value according to the trigger signal and the write address information, compares the current count value with a count threshold value, if the current count value is less than the count threshold value, in this case, a processed count value is obtained by adding one to the current count value and a first synchronization enable signal is generated, if the current count value is equal to the count threshold value, in this case, a processed count value is obtained by resetting the current count value and a second synchronization enable signal is generated, the write control module writes write data corresponding to the write command into a corresponding address of the cache module according to the first synchronization enable signal and the write address information and / or writes the write data corresponding to the write command into the storage module according to the second synchronization enable signal and the write address information. The application only counts in the case that the write control module performs a write operation on the cache module, does not need to keep counting flip all the time, reduces dynamic power consumption, and only generates a write-back storage module once in the case that the current count value reaches the count threshold value, which can obviously reduce the number of access buses, thereby improving bandwidth utilization and data access efficiency. BRIEF DESCRIPTION OF DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.
[0032] Figure 1 It is a structural schematic diagram of a synchronization controller;
[0033] Figure 2 It is a structural schematic diagram of a synchronization circuit provided by an embodiment;
[0034] Figure 3 It is a structural schematic diagram of a synchronization control module provided by an embodiment;
[0035] Figure 4 It is a structural schematic diagram of a cache module, a bitmap and a storage unit provided by an embodiment;
[0036] Figure 5 It is a structural schematic diagram of a chip provided by an embodiment.
[0037] Explanation of reference signs:
[0038] 10 - cache module, 20 - storage module, 30 - write control module, 40 - synchronization control module, 410 - storage unit, 420 - comparator, 430 - adder, 440 - multiplexer, 50 - bitmap, 60 - read control module, 70 - access interface, 80 - decoding module, 100 - synchronization circuit. DETAILED DESCRIPTION
[0039] For the purpose of promoting an understanding of the present application, the present application will now be described in greater detail with reference to the relevant drawings. The embodiments of the present application are illustrated in the drawings. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0041] It should be understood that the terms "first", "second" and so on used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, a cache module can be referred to as a storage module without departing from the scope of the present application, and similarly, a storage module can be referred to as a cache module. Both the cache module and the storage module are storage modules, but they are not the same storage module.
[0042] It should be understood that "connection" in the following embodiments means that the circuits, modules, units, etc. connected to each other have an electrical signal or data transmission between each other, which should be understood as "electrical connection", "communication connection", etc.
[0043] It should be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of the element" means part or all of the element. As used herein, the singular forms "a", "an" and "the" can also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprise / contain" or "have" or the like specifies the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in the specification includes any and all combinations of the related listed items.
[0044] As described in the background, in order to ensure the data consistency between the cache and the memory, the data synchronization operation must be performed periodically. In the related art, the synchronization controller counts the data storage time in the cache through the counter, and when the time threshold is reached, the data in the cache is flushed back to the memory. It can be seen from the structure shown in Figure 1 that the synchronization controller realizes timing through the counter. When the data in the cache is valid, the counter is always flipping, and the dynamic power consumption is very high. Moreover, if the preset time threshold is set to be small, the data will be updated to the memory before the next use, and the content in the memory is the latest. If the latest value is to be obtained, the memory needs to be read again, which wastes the access bandwidth and has low access efficiency.
[0045] The present application provides a synchronization circuit and a chip. When the number of write operations on the cache module reaches the number threshold, the data synchronization operation is performed, that is, the number threshold control logic is adopted, the dynamic power consumption is reduced, and the number of write-back is reduced to a certain extent, the bandwidth utilization and the data access efficiency are improved.
[0046] In one embodiment, as shown in Figure 2 , a synchronization circuit is provided. The synchronization circuit includes a cache module 10, a storage module 20, a write control module 30, and a synchronization control module 40. The cache module 10 is configured to store data. The storage module 20 is configured to store data. In the embodiment of the present application, the cache module 10 has no refresh requirement, and the storage module 20 has a refresh requirement. For example, the cache module 10 can be a static random access memory (SRAM) or a register, and the storage module 20 can be a double data rate synchronous dynamic random access memory (DDR).
[0047] The write control module 30 is connected with the cache module 10 and the storage module 20 respectively. The write control module 30 is configured to determine the write address information according to the received write command, and generate a trigger signal when the write address information is the address in the cache module 10. The write address information is used to indicate the write position of the write data corresponding to the write command, and the write address information includes the address of the cache module 10 or the address of the storage module 20. The trigger signal is used to trigger the synchronization control module 40 to determine whether to perform the data synchronization operation.
[0048] The synchronization control module 40 is connected with the write control module 30. The synchronization control module 40 is configured to determine a current count value according to the trigger signal and the write address information, and generate a first synchronization enable signal by adding one to the current count value to obtain a processed count value in a case that the current count value is less than a count threshold value, and generate a second synchronization enable signal by resetting the current count value to obtain the processed count value in a case that the current count value is equal to the count threshold value. The current count value is used to represent the number of times that the write control module 30 currently performs the write operation on the address in the cache module 10, and each count value corresponds to an address in the storage module 20. For example, the address 0 of the cache module 10 corresponds to the current count value 3, which means that the write control module 30 currently performs the write operation on the address 0 of the cache module 10 for 3 times. The count threshold value is a pre-set value, which can be set according to the synchronization requirement of the internal synchronization circuit, for example, the count threshold value can be 5, 10, 20 or other appropriate values, which are not limited herein. In the case that the current count value is equal to the count threshold value, the synchronization control module 40 resets the current count value, which can be understood as resetting the current count value to a reset value, or an initial value. The reset value is pre-set and less than the count threshold value, for example, the reset value is 0, and the reset value can also be other values such as 1, 2, etc., which are not limited herein.
[0049] The write control module 30 is further configured to write the write data corresponding to the write command into the corresponding address of the cache module 10 according to the first synchronization enable signal and the write address information, and / or write the write data corresponding to the write command into the storage module 20 according to the second synchronization enable signal and the write address information.
[0050] For example, the count threshold value is 5, and the write control module 30 receives a write command and determines the write address information of the write command as the address 0 in the cache module 10, and then generates a trigger signal. If the synchronization control module 40 determines that the current count value corresponding to the address 0 is 3 which is less than the count threshold value 5 according to the trigger signal and the write address information, the synchronization control module 40 adds one to the current count value 3 to obtain the processed count value 4 and generates a first synchronization enable signal, and the write control module 30 writes the write data corresponding to the write command into the corresponding address 0 of the cache module 10 according to the first synchronization enable signal and the write address information. If the synchronization control module 40 determines that the current count value corresponding to the address 0 is 5 which is equal to the count threshold value 5 according to the trigger signal and the write address information, the synchronization control module 40 resets the current count value 5 to obtain the processed count value 0 and generates a second synchronization enable signal, and the write control module 30 writes the write data corresponding to the write command into the address 0 of the storage module 20 according to the second synchronization enable signal and the write address information.
[0051] The synchronization circuit receives a write command through the write control module 30, and in the case that the write address information of the write command is an address in the cache module 10, it indicates that the write command aims to update a new value for the address in the cache module 10. In this case, the synchronization circuit generates a trigger signal through the write control module 30 to instruct the synchronization control module 40 to determine whether to perform a data synchronization operation. Specifically, the synchronization circuit determines a current count value according to the trigger signal and the write address information through the synchronization control module 40, and compares the current count value with a count threshold value. If the current count value is less than the count threshold value, it indicates that the number of write operations on the address of the cache module 10 by the write control module 30 does not reach the data synchronization condition. In this case, the current count value is incremented by one to obtain a processed count value, and a first synchronization enable signal is generated, so that the write control module 30 writes the write data corresponding to the write command to the corresponding address of the cache module according to the first synchronization enable signal and the write address information, that is, does not perform the data synchronization operation. If the current count value is equal to the count threshold value, it indicates that the number of write operations on the address of the cache module 10 by the write control module 30 reaches the data synchronization condition. In this case, the current count value is reset to obtain a processed count value, and a second synchronization enable signal is generated, so that the write control module 30 writes the write data corresponding to the write command to the storage module according to the second synchronization enable signal and the write address information, that is, performs the data synchronization operation, thereby achieving automatic refreshing of the storage module 20 according to the number of write operations on the cache module 10.
[0052] The synchronization circuit of the embodiment only counts in the case of write operation on the cache module 10 by the write control module 30, and does not need to keep counting flip all the time, thereby reducing dynamic power consumption. Moreover, the storage module is only backed up once in the case that the current count value reaches the count threshold value, which can significantly reduce the number of access bus, thereby improving bandwidth utilization and data access efficiency.
[0053] In one embodiment, the synchronization control module 40 is further configured to receive and store the count threshold value, so that the current count value can be compared with the count threshold value to write data to the cache module 10 in the case that the current count value is less than the count threshold value, or to write data to the storage module 20 in the case that the current count value is greater than or equal to the count threshold value, thereby taking the number of write operations on the cache module 10 as a threshold comparison object to reduce dynamic power consumption and improve bandwidth utilization and data access efficiency.
[0054] In one embodiment, as shown in FIG. 4, the synchronization control module 40 includes a storage unit 410, a comparator 420, an adder 430, and a multiplexer 440. Figure 3
[0055] The storage unit 410 is configured to store the current count value of the cache data at the corresponding address of the cache module 10, and output the current count value according to the trigger signal. For example, the storage unit 410 includes a storage entity. For example, as shown in FIG. 4, the cache module 10 has N addresses, i.e., addr0, add1, …, addrN, and each address of the cache module 10 stores corresponding data, for example, addr0 stores data0, addr1 stores data1, and addrN stores dataN. Correspondingly, the storage unit 410 stores the current count value of the N addresses of the cache module 10, for example, the current count value corresponding to addr0 is cnt_val0, the current count value corresponding to addr1 is cnt_val1, and the current count value corresponding to addrN is cnt_valN. Figure 4
[0056] The comparator 420 is connected with the storage unit 410. The comparator 420 is configured to determine whether the current count value is less than the count threshold value, and generate a first synchronization enable signal if the current count value is less than the count threshold value, or generate a second synchronization enable signal if the current count value is not less than the count threshold value, and reset the current count value in the storage unit 410. In an application, the comparator 420 obtains the current count value corresponding to the write address information from the storage unit 410 according to the trigger signal and the write address information, and generates a comparison result according to the current count value and the count threshold value. The comparator 420 generates the first synchronization enable signal if the comparison result is that the current count value is less than the count threshold value, and generates the second synchronization enable signal if the comparison result is that the current count value is equal to the count threshold value. The comparator 420 stores the count threshold value.
[0057] The adder 430 is configured to perform a plus one operation on the current count value to obtain a processed count value if the comparison result is that the current count value is less than the count threshold value. In an application, the adder 430 can obtain the current count value corresponding to the write address information from the storage unit 410 according to the trigger signal and the write address information, and perform a plus one operation on the current count value to obtain a processed count value.
[0058] The multiplexer 440 is connected with the adder 430 and the comparator 420. The multiplexer 440 is configured to write the processed count value of the adder 430 into the corresponding address of the storage unit 410, or write the reset processed count value into the corresponding address of the storage unit 410.
[0059] For example, the write command received by the write control module 30 is applied, and the write address information determined according to the write command is address 0 in the cache module 10, and a trigger signal is generated. If the current count value of address 0 stored in the storage unit 410 is 3, the comparator 420 compares the current count value 3 with the count threshold value 5, and generates the first synchronization enable signal if the current count value 3 is less than the count threshold value 5. The adder 430 processes the current count value 3 by adding 1 to obtain the processed count value 4, and the multiplexer 440 writes the count value 4 after the addition into the corresponding address 0 of the storage unit 410. If the current count value of address 0 stored in the storage unit 410 is 5, the comparator 420 compares the current count value 5 with the count threshold value 5, and generates the second synchronization enable signal if the current count value 5 is equal to the count threshold value 5, and resets the current count value to obtain the processed count value 0, and the multiplexer 440 writes the count value 0 after the reset into the corresponding address 0 of the storage unit 410.
[0060] The above-mentioned synchronization circuit stores the current count value of the cache data at the corresponding address of the cache module 10 in the storage unit 410, determines whether the current count value is less than the count threshold value through the comparator 420, generates the first synchronization enable signal if the current count value is less than the count threshold value, otherwise generates the second synchronization enable signal and resets the current count value in the storage unit 410, processes the current count value by adding 1 through the adder 430 to obtain the processed count value, and writes the count value after the addition into the corresponding address of the storage unit 410 through the multiplexer 440, and writes the count value after the reset into the corresponding address of the storage unit 410, thereby counting the number of write operations of the write control module 30 on the cache module 10, and writing the write data into the storage module 20 when the current count value is equal to the count threshold value, thereby realizing the data synchronization between the cache module 10 and the storage module 20.
[0061] In one embodiment, as shown in Figure 4 and Figure 5 The synchronization circuit 100 further includes a bit map 50 for storing identification information of whether the storage data at the corresponding address of the cache module 10 is valid. When the identification information is valid, for example, the identification information is 1, the storage data at the corresponding address of the cache module is valid, and the storage unit 410 stores the current count corresponding to the address; when the identification information is invalid, for example, the identification information is 0, the storage data at the corresponding address of the cache module is invalid, and the storage unit 410 stores the current count corresponding to the address.
[0062] For example, the cache module 10 has N addresses, namely addr0, add1, …, addrN, and each address of the cache module 10 stores corresponding data, for example, addr0 stores data0, addr1 stores data1, and addrN stores dataN. Correspondingly, the bitmap 50 stores identification information of whether the stored data of the N addresses in the cache module 10 is valid, for example, 1 bit corresponds to identification information of whether the stored data of 1 address in the storage module 20 is valid, and the bitmap 50 includes N bits of identification information. For example, the 0th bit of the bitmap 50, namely bit0, is 0, indicating that the stored data of the address addr0 in the cache module 10 is invalid, and the current count value cnt_val0 of the address addr0 stored in the storage unit 410 is invalid; the 1st bit of the bitmap 50, namely bit1, is 1, indicating that the stored data of the address addr1 in the cache module 10 is valid, and the current count value cnt_val1 of the address addr1 stored in the storage unit 410 is valid.
[0063] The write control module 30 is further configured to write the write data corresponding to the write command into the storage module 20 when the write address information is an address in the storage module 20, and set the identification information corresponding to the write address information in the bitmap 50 as invalid. The cache module 10 and the storage module 20 have a mapping relationship between the addresses (referred to as addresses) used to store data. For example, the N addresses in the cache module 10 are addr0, add1, …, addrN, and the N addresses in the storage module 20 are correspondingly addr0, add1, …, addrN; wherein the addr0 of the cache module 10 corresponds to the addr0 of the storage module 20, the addr1 of the cache module 10 corresponds to the addr1 of the storage module 20, and so on, and the addrN of the cache module 10 corresponds to the addrN of the storage module 20. For example, when the write address information is the address addr0 in the storage module 20, the write control module 30 writes the write data corresponding to the write command into the address addr0 in the storage module 20, and sets the bit corresponding to the address addr0 in the bitmap 50 as 0.
[0064] The synchronization circuit 100 stores the identification information of whether the storage data at the corresponding address of the cache module 10 is valid in the bitmap 50, and when the write address information is the address in the storage module 20, the write control module 30 writes the write data corresponding to the write command into the storage module 20, and the write control module 30 sets the identification information corresponding to the write address information in the bitmap 50 to be invalid, that is, whether the storage data at the corresponding address of the cache module 10 is valid can be identified through the bitmap 50, and further, whether the current count value of the storage unit 410 storing the address is valid can be identified, and when the write data is written into the storage module 20 at the write address, the identification information of the corresponding bitmap 50 is set to be invalid, which is helpful for the cycle synchronization control.
[0065] In one embodiment, please refer to Figure 5 The synchronization circuit 100 further comprises a read control module 60, which is configured to determine read address information according to a received read command, and in the case that the read address information is the storage address in the cache module 10, read the identification information at the corresponding address in the bitmap 50, in the case that the identification information is valid, read the data from the read address of the cache module 10, and in the case that the identification information is invalid, read the data from the read address of the storage module 20.
[0066] If the identification information at the corresponding address in the bitmap 50 is valid, for example, the identification information is 1, it indicates that the storage data at the corresponding address of the cache module 10 is valid, in this case, the data can be read from the read address of the cache module 10 by accessing the cache module 10, which is helpful to improve the data reading efficiency. If the identification information at the corresponding address in the bitmap 50 is invalid, it indicates that the storage data at the corresponding address of the cache module 10 is invalid, in this case, the data is read from the read address of the storage module 20 by accessing the storage module, which realizes the read operation of the synchronization circuit 100.
[0067] Please refer to Figure 5 In one embodiment, the write control module 30 is further configured to write the data read from the read address of the storage module 20 into the corresponding address of the cache module 10, and set the identification information corresponding to the write address information in the bitmap 50 to be valid, which realizes the effective storage of the read data in the cache module 10, so that when the data at the corresponding address is read again, it can be directly read from the cache module 10 without accessing the storage module 20, which is helpful to improve the data access efficiency.
[0068] In one embodiment, please refer to Figure 5 The read control module 60 is further configured to generate a read response after reading the data, and the read response comprises the data read by the read control module 60, so that the data read from the synchronization circuit 100 can be fed back through the read response, which realizes the effective read operation of the data.
[0069] In one embodiment, please refer to Figure 5 The synchronization circuit 100 further comprises an access interface 70. The access interface 70 is connected with the write control module 30, the storage module 20 and the read control module 60 respectively. The access interface 70 is used to convert the write command and / or the read command into an interface signal to access the storage module 20. The access interface 70 is pre-configured, for example, a MIPI interface, a GPIO interface, or other suitable interface types. The specific access interface 70 can be selected according to the specific structure of the storage module 20, which will not be limited here. In this way, the write control module 30 and the read control module 60 can respectively transmit data between the access interface 70 and the storage module 20, which helps to improve the data access efficiency.
[0070] In one embodiment, please refer to Figure 5 The synchronization circuit 100 further comprises a decoding module 80. The decoding module 80 is used to receive and analyze the data access command. When the data access command is a write command, the decoding module 80 sends the write address information and the write data corresponding to the write command to the write control module 30. When the data access command is a read command, the decoding module 80 sends the read address information corresponding to the read command to the read control module 60. The decoding module 80 is connected with the write control module 30. For example, the decoding module 80 is also connected with the read control module 60. In this way, the synchronization circuit 100 can distinguish between read and write commands through the decoding module 80, so that the read control module 60 can implement the read operation according to the read command, and the write control module 30 can implement the write operation according to the write command.
[0071] Based on the same inventive concept, the embodiments of the present application also provide a chip for implementing the above-mentioned synchronization circuit. The implementation scheme of the chip for solving the problem is similar to the implementation scheme described in the above-mentioned synchronization circuit. Therefore, the specific limitations in one or more chip embodiments provided below can refer to the limitations of the synchronization circuit described above, which will not be repeated here.
[0072] In one embodiment, please refer to Figure 5 A chip is provided, which comprises the synchronization circuit 100. The synchronization circuit 100 can refer to the related description described above, which will not be repeated here. For example, the chip can be a DPU (Data Process Unit) or the like, which will not be limited here.
[0073] In one embodiment, please refer to Figure 3The chip provided by the embodiment of the present application is introduced. The chip comprises a synchronization circuit 100. The synchronization circuit 100 comprises a cache module 10, a storage module 20, a write control module 30, a read control module 60, a bit map 50, an access interface 70, a decoding module 80 and a synchronization control module 40. The cache module 10 is SRAM, the storage module 20 is DDR, the write control module 30 is a write controller, the read control module 60 is a read controller, the bit map 50 is a register, and the synchronization control module 40 is a synchronization controller. The synchronization controller adopts the structure as shown in the figure. Figure 3 The structure as shown in the figure is taken as an example for description.
[0074] The decoding module 80 is used for decoding the data access command to distinguish the read and write commands.
[0075] Each bit of the bit map 50 respectively corresponds to the record of whether the storage data in each address in the cache module 10 is valid, 0 is invalid, 1 is valid, and all 0 after reset. When the data returned from the storage module 20 is written into the cache module 10, the bit position of the corresponding bit map 50 is 1, and when the data is written into the storage module 20, the bit position of the corresponding bit map 50 is 0.
[0076] The write control module 30 is connected with the decoding module 80, the bit map 50, the cache module 10 and the access interface 70 respectively. The write control module 30 is used for analyzing the write command to select the cache module 10 or the storage module 20, if the write control module 30 analyzes that the storage module 20 needs to be written, the control logic of the synchronization control module 40 is not considered. And when the storage module 20 is written, the corresponding bit map is set to 0.
[0077] The read control module 60 is connected with the decoding module 80, the bit map 50, the cache module 10 and the access interface 70 respectively. The read control module 60 is used for obtaining the corresponding bit of the bit map 50 according to the read command, and selecting the cache module 10 or the storage module 20, if the corresponding bit of the bit map 50 is 1, the cache module 10 is read, if it is 0, the storage module 20 is read, the result returned when the storage module 20 is read is written into the cache module 10, and the corresponding bit position of the bit map 50 is updated to 1 when it is written.
[0078] The access interface 70 is used for converting the read and write commands into interface signals to access the storage module 20.
[0079] The synchronization control module 40 is used for recording how many times each valid data in the cache module 10 is updated. When the count value is less than the number threshold, the cache module 10 is written, and when the count value is equal to the number threshold, the storage module 20 is written. As shown in the figure, The synchronization control module 40 comprises a storage unit 410, a comparator 420, an adder 430 and a multiplexer 440.
[0080] The chip only counts in the case that the write control module 30 writes the cache module 10, without always keeping the count flip, reduces the dynamic power consumption, and only in the case that the current count value reaches the count threshold value, the write-back storage module 20 is generated once, which can obviously reduce the number of access bus, thereby improving the bandwidth utilization and data access efficiency.
[0081] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.
[0082] The technical features of the above-described embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict, it should be considered that they are within the scope of the present application.
[0083] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A synchronization circuit, characterized by The method comprises the following steps: a cache module for storing data; a storage module for storing data; a write control module for determining write address information according to a received write command, and generating a trigger signal when the write address information is an address in the cache module; a synchronization control module for determining a current count value according to the trigger signal and the write address information, and generating a first synchronization enable signal by adding one to the current count value to obtain a processed count value when the current count value is less than a count threshold value, or generating a second synchronization enable signal by resetting the current count value to obtain a processed count value when the current count value is equal to the count threshold value; the current count value is used to represent the number of times of write operation on the address in the cache module by the write control module; the write control module is further configured to write write data corresponding to the write command into a corresponding address of the cache module according to the first synchronization enable signal and the write address information, and / or write the write data corresponding to the write command into the storage module according to the second synchronization enable signal and the write address information.
2. The synchronization circuit of claim 1, wherein, The synchronization control module comprises: a storage unit for storing a current count value of cache data at a corresponding address of the cache module, and outputting the current count value according to the trigger signal; a comparator for determining whether the current count value is less than a count threshold value, and generating a first synchronization enable signal if it is less than the count threshold value, or generating a second synchronization enable signal if it is not less than the count threshold value, and resetting the current count value in the storage unit; an adder for adding one to the current count value to obtain a processed count value; a multiplexer for writing the processed count value into the corresponding address of the storage unit, or writing the reset processed count value into the corresponding address of the storage unit.
3. The synchronization circuit of claim 2, wherein, The synchronization circuit further comprises a bitmap, the bitmap is used to store identification information of whether the storage data at the corresponding address of the cache module is valid; the write control module is further configured to write write data corresponding to the write command into the storage module when the write address information is an address in the storage module; the write control module is further configured to set the identification information corresponding to the write address information in the bitmap as invalid.
4. The synchronization circuit of claim 3, wherein, The synchronization circuit further comprises a read control module, the read control module is configured to determine read address information according to a received read command, read identification information at a corresponding address in the bitmap when the read address is a storage address in the cache module, read data from the read address of the cache module when it is determined that the identification information is valid for the storage data, and read data from the read address of the storage module when it is determined that the identification information is invalid for the storage data.
5. The synchronization circuit of claim 4, wherein, the write control module is further configured to write the data read from the read address of the storage module into the corresponding address of the cache module, and set the identification information corresponding to the write address information in the bitmap as valid.
6. The synchronization circuit of claim 4, wherein, the read control module is further configured to generate a read response after reading data, the read response comprising the data read by the read control module.
7. The synchronization circuit of claim 4, wherein, the synchronization circuit further comprises a decoding module, The decoding module is configured to receive and analyze a data access command, and send write address information and write data corresponding to the write command to the write control module when the data access command is a write command, and send read address information corresponding to the read command to the read control module when the data access command is a read command.
8. The synchronization circuit of claim 4, wherein, The synchronization circuit further comprises an access interface connected to the write control module, the read control module and the storage module, and the access interface is configured to convert the write command and / or the read command into an interface signal to access the storage module.
9. The synchronization circuit of claim 1, wherein, The synchronization control module is further configured to receive and store the number threshold.
10. A chip, characterized by A synchronization circuit comprising any one of claims 1-9.
Citation Information
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