Compiling optimization method and related product

Abstract

The invention provides a compiling optimization method and a related product, the method comprises the following steps: running a first executable file, and collecting a hardware cache event, the first executable file comprises an executable program and debugging information, the executable program is obtained by compiling a program source code, and the debugging information is obtained by compiling the program source code; the debugging information comprises a corresponding relation between the program source code and an executable instruction in the executable program. Then, first configuration information is obtained according to the hardware cache event and the debugging information, and the first configuration information comprises the identifier of the program source code and the cache missing frequency corresponding to the identifier; and finally, compiling the program source code according to the first configuration information to obtain a second executable file. When the second executable file is executed, the cache optimization effect can be improved, and meanwhile the cache optimization cost can be saved.

Description

[0001] This application is a divisional application of the Chinese patent application with the application date of July 31, 2021, application number 202110876986.9, and invention name “A compilation optimization method for program source code and related products”. Technical Field

[0002] The present application relates to the field of cache technology, and in particular to a compilation optimization method and related products. Background Art

[0003] With the rapid development of cache technology, the speed at which the central processing unit (CPU) accesses memory objects (including data and instructions) is getting faster and faster. Among them, a key factor affecting the speed at which the CPU accesses memory objects is whether the cache stores objects to be accessed by the CPU. To this end, the cache needs to be optimized so that the CPU can read more objects to be accessed from the cache, reduce the number of times the CPU accesses the memory, and thus improve the speed at which the CPU accesses memory objects.

[0004] However, current cache optimization methods all have the problem of high optimization cost but low accuracy and timeliness. That is, using these cache optimization methods requires a high cost to optimize the cache, and the optimized cache may also include more redundant objects and objects with low access frequency, or the object is not moved from the memory to the cache in time before the CPU accesses the memory object.

[0005] Therefore, how to improve cache optimization effect while reducing the optimization cost of cache optimization is an urgent problem to be solved in the current cache technology field. Summary of the invention

[0006] The present application provides a compilation optimization method and related products, which can improve the accuracy and timeliness of cache optimization.

[0007] In the first aspect, the present application provides a method for compiling and optimizing a program source code, the method comprising: running a first executable file and collecting hardware cache events, wherein the first executable file comprises an executable program and debugging information, the executable program is obtained by compiling the program source code, and the debugging information comprises the correspondence between the program source code and the executable instructions in the executable program. Then, based on the hardware cache events and the debugging information, first configuration information is obtained, the first configuration information comprising an identifier of the program source code and the number of cache misses corresponding to the identifier. Finally, the program source code is compiled according to the first configuration information to obtain a second executable file.

[0008] By implementing the method described in the first aspect, a second executable file can be obtained, and when the CPU executes the second executable file, the purpose of optimizing the cache can be achieved. In addition, the method is to determine the number of cache misses corresponding to the program source code by collecting hardware cache events, and then compile the program source code in combination with the number of cache misses corresponding to the program source code, so that the compiled second executable file can more accurately and timely inform the CPU how to optimize the cache, which can not only improve the accuracy and timeliness of cache optimization, but also save the cost of cache optimization.

[0009] In a possible implementation, the first configuration information is obtained based on hardware cache events and debugging information, including: parsing hardware cache events to obtain the number of cache misses corresponding to the executable instruction, and then determining the number of cache misses corresponding to the source code associated with the executable instruction based on the number of cache misses and debugging information corresponding to the executable instruction, thereby obtaining the first configuration information.

[0010] Since the CPU can execute executable instructions, it is possible to determine which executable instructions the CPU executes when cache misses occur, thereby determining the number of cache misses corresponding to the executable instructions, and since the executable instructions are obtained by compiling the program source code, the number of cache misses corresponding to the executable instructions can be used to determine the number of cache misses corresponding to the program source code. In other words, the above implementation method can more easily and accurately determine the number of cache misses corresponding to the program source code, thereby guiding the compilation of the program source code and achieving a better compilation effect of the program source code.

[0011] In a possible implementation, the program source code is compiled according to the first configuration information to obtain the second executable file, including: parsing the first configuration information, determining the source code in the program source code that meets the first condition, wherein the first condition includes: the number of cache misses of the source code is greater than the first threshold, and the source code includes a memory access object. Then, the prefetch distance of the source code that meets the first condition is calculated, and the prefetch distance represents the advance amount of moving the memory access object from the memory to the cache. Finally, a prefetch instruction is generated according to the prefetch distance.

[0012] In the above implementation, by selecting source code that meets the first condition and performing data prefetching on the source code that meets the first condition, the workload of the CPU can be reduced, and the optimization effect of the cache can be improved overall.

[0013] In a possible implementation, the above calculation of the prefetch distance of the source code that meets the first condition includes: obtaining a control flow graph (CFG) of a first loop, the first loop is the innermost loop including the source code that meets the first condition, the CFG of the first loop includes multiple basic blocks (BBs) and multiple directed edges, the multiple directed edges are used to indicate the execution order between the multiple BBs, and then, determining the execution probability of each directed edge; calculating a single cycle time of the first loop according to the execution probability of each directed edge, and then, calculating the prefetch distance of the source code that meets the first condition according to the single cycle time of the first loop.

[0014] In the above implementation, it is considered that when the CPU executes a loop program, especially a program of the innermost loop nested in the loop, a cache miss event is most likely to occur. Therefore, by calculating the single cycle time of the innermost loop, the pre-fetch distance can be determined more accurately, thereby improving the timeliness and versatility of cache optimization. Moreover, by determining the execution probability of each directed edge, thereby calculating the single cycle time of the first cycle, the influence of the BB with a low execution probability in the first cycle on the single cycle time of the first cycle can be reduced, thereby improving the accuracy of the calculated single cycle time of the first cycle.

[0015] In a possible implementation, the above-mentioned acquisition of the CFG of the first loop includes: parsing the first configuration information, determining a function in the program source code that satisfies the second condition, wherein the second condition is that the number of cache misses of the function is greater than the second threshold, and the number of cache misses of the function is the sum of the number of cache misses of the source code included in the function. Then, determining the first loop in the function that satisfies the second condition, the first loop is the innermost loop in the function that satisfies the second condition, and the execution probability of the first loop iteration is greater than the third threshold, and then constructing the CFG of the first loop.

[0016] In the above implementation, the first loop is further determined by determining a function that satisfies the second condition, which can improve the efficiency of determining the first loop, thereby saving time for compiling the program source code and reducing the cost of compiling the program source code.

[0017] In a possible implementation, the above-mentioned calculation of the single cycle time of the first loop according to the execution probability of each directed edge includes: determining BBs and directed edges that are irrelevant to the cycle layer of the first loop, and then cutting the irrelevant BBs and directed edges to obtain a second loop. Thereafter, the execution probability of each BB in the second loop is calculated according to the execution probability of each directed edge to obtain the single cycle time of the first loop, and the single cycle time of the first loop is the sum of the products of the execution probability of each BB and the execution time of each BB.

[0018] In the above implementation, the second cycle is obtained by trimming the BBs and directed edges that are not related to the cycle layer in the first cycle, and then the single cycle time of the first cycle is calculated based on the second cycle, so that the accuracy of the calculated single cycle time of the first cycle can be improved.

[0019] In a possible implementation, before the program source code is compiled according to the first configuration information to obtain the second executable file, the method further includes: obtaining multiple structures in the program source code, and members in the multiple structures. The program source code is compiled according to the first configuration information to obtain the second executable file, including: parsing the first configuration information, determining a structure among the multiple structures that meets a third condition, the third condition including: there is no sequential dependency in the use of the members in the structure, and the number of cache misses of the structure is greater than a fourth threshold; adjusting the order of the members in the structure that meets the third condition to obtain a new structure. Afterwards, the new structure is used to replace the structure that meets the third condition.

[0020] By implementing the above implementation, the structure in the program source code can be optimized, thereby improving the cache usage rate. In addition, the method determines the number of cache misses of the structure in the program source code by collecting hardware cache events, thereby improving the accuracy of the rearrangement of the structure members.

[0021] In a possible implementation, each of the above structures includes the source code in the program source code, and the above parsing of the first configuration information to determine the structure that meets the third condition includes: parsing the first configuration information to determine the identifier of the program source code and the number of cache misses corresponding to the identifier, and then obtaining the number of cache misses of each structure according to the identifier of the program source code and the number of cache misses corresponding to the identifier, thereby determining the above structure that meets the third condition. In this way, the time for rearranging the structure members of the program source code can be saved, and the cost of rearranging the structure members of the program source code can be reduced. In addition, the screening of the structure by the third condition can also improve the accuracy of rearranging the structure members of the program source code.

[0022] In a possible implementation, the above-mentioned adjusting the order of the members in the structure satisfying the third condition includes: obtaining the number of cache misses of multiple members in the structure satisfying the third condition, and then adjusting the order of the multiple members according to the number of cache misses of the multiple members. In this way, the cache usage rate can be improved.

[0023] In a possible implementation, the above-mentioned adjusting the order of the multiple members according to the number of cache misses of the multiple members includes: obtaining the size of each member of the multiple members, and then adjusting the order of the multiple members according to the size of each member and the number of cache misses of each member. In this way, the utilization rate of the cache can be further improved.

[0024] In a second aspect, the present application provides a compilation optimization device for a program source code, the device comprising an operation unit, an event collection unit, a parsing unit and a compilation unit. The operation unit is used to run a first executable file, wherein the first executable file comprises an executable program and debugging information, the executable program is obtained by compiling the program source code, and the debugging information comprises the correspondence between the program source code and the executable instructions in the executable program. The event collection unit is used to collect hardware cache events. The parsing unit is used to obtain first configuration information based on the hardware cache event and the debugging information, the first configuration information comprising an identifier of the program source code and the number of cache misses corresponding to the identifier; the compilation unit is used to compile the program source code according to the first configuration information to obtain a second executable file.

[0025] In a possible implementation, the parsing unit is specifically used to: parse hardware cache events, obtain the number of cache misses corresponding to the executable instruction, and then determine the number of cache misses corresponding to the source code associated with the executable instruction based on the number of cache misses corresponding to the executable instruction and debugging information, thereby obtaining the first configuration information.

[0026] In a possible implementation, the compilation unit is specifically used to: parse the first configuration information, determine the source code in the program source code that meets the first condition, wherein the first condition includes: the number of cache misses of the source code is greater than the first threshold, and the source code includes a memory access object. Then, calculate the prefetch distance of the source code that meets the first condition, and the prefetch distance represents the advance amount of moving the memory access object from the memory to the cache. Finally, generate a prefetch instruction according to the prefetch distance.

[0027] In a possible implementation, the compilation unit is specifically used to: obtain a CFG of a first loop, the first loop is the innermost loop including the source code that satisfies the first condition, the CFG of the first loop includes multiple BBs and multiple directed edges, the multiple directed edges are used to indicate the execution order between the multiple BBs, and then, determine the execution probability of each directed edge; calculate a single loop time of the first loop according to the execution probability of each directed edge, and then, calculate the prefetch distance of the source code that satisfies the first condition according to the single loop time of the first loop.

[0028] In a possible implementation, the compilation unit is specifically used to: parse the first configuration information, determine the function in the program source code that meets the second condition, wherein the second condition is that the number of cache misses of the function is greater than the second threshold, and the number of cache misses of the function is the sum of the number of cache misses of the source code included in the function. Then, determine the first loop in the function that meets the second condition, the first loop is the innermost loop in the function that meets the second condition, and the execution probability of the first loop iteration is greater than the third threshold, and then construct the CFG of the first loop.

[0029] In a possible implementation, the compilation unit is specifically used to: determine BBs and directed edges that are irrelevant to the loop layer of the first loop, and then cut the irrelevant BBs and directed edges to obtain a second loop. Afterwards, the execution probability of each BB in the second loop is calculated according to the execution probability of each directed edge to obtain a single loop time of the first loop, and the single loop time of the first loop is the sum of the products of the execution probability of each BB and the execution time of each BB.

[0030] In a possible implementation, the compilation unit is further used to: obtain multiple structures in the program source code, and members in the multiple structures. The compilation unit is further used to: parse the first configuration information, determine a structure in the multiple structures that meets the third condition, the third condition including: there is no order dependency in the use of the members in the structure, and the number of cache misses of the structure is greater than a fourth threshold; adjust the order of the members in the structure that meets the third condition to obtain a new structure. Then, use the new structure to replace the structure that meets the third condition.

[0031] In a possible implementation, each of the above-mentioned structures includes the source code in the program source code, and the above-mentioned compilation unit is specifically used to: parse the first configuration information, determine the identifier of the program source code and the number of cache misses corresponding to the identifier, and then obtain the number of cache misses of each of the above-mentioned structures according to the identifier of the program source code and the number of cache misses corresponding to the identifier, thereby determining the above-mentioned structure that meets the third condition.

[0032] In a possible implementation, the compilation unit is specifically used to obtain the number of cache misses of multiple members in a structure that meets the third condition, and then adjust the order of the multiple members according to the number of cache misses of the multiple members.

[0033] In a possible implementation, the compilation unit is specifically used to: obtain the size of each member of the multiple members, and then adjust the order of the multiple members according to the size of each member and the number of cache misses of each member.

[0034] In a third aspect, the present application provides a computing device, which includes a processor and a memory, the memory stores computer instructions, and the processor executes the above-mentioned computer instructions to enable the above-mentioned computing device to perform the method provided by the first aspect or any possible implementation of the first aspect.

[0035] In a fourth aspect, the present application provides a computer-readable storage medium storing computer instructions. When the above-mentioned computer instructions are executed by a computing device, the computing device executes the method provided by the above-mentioned first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a memory access process involved in this application;

[0037] Figure 2 It is a structural diagram of a compilation optimization device provided by the present application;

[0038] Figure 3 It is a flowchart of a program source code compilation optimization method provided by the present application;

[0039] Figure 4 It is a flowchart of a compilation operation for performing data prefetching on program source code provided by the present application;

[0040] Figure 5 is a CFG of cycle 1 provided by the present application;

[0041] Figure 6 is a CFG of a loop after pruning loop 1 provided by the present application;

[0042] Figure 7 It is a flowchart of a compilation operation of performing structure member rearrangement on a program source code provided by the present application;

[0043] Figure 8 is a structural schematic diagram of a second structure provided by the present application;

[0044] Fig. 9 is a schematic diagram of storage arrangement of a second structure provided by the present application;

[0045] Fig.10 is a structural schematic diagram of a third structure provided by the present application;

[0046] Fig.11 It is a storage arrangement schematic diagram of a third structure provided by the present application;

[0047] Fig.12 is a schematic structural diagram of another third structure provided by the present application;

[0048] Fig.13 is a schematic diagram of storage arrangement of another third structure provided by the present application;

[0049] Fig.14 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0050] In order to facilitate the understanding of the technical solution provided by the present application, before describing the technical solution provided by the present application in detail, some terms involved in the present application are first introduced.

[0051] Cache is a temporary storage device located between the CPU and the memory for high-speed data exchange. Its capacity is smaller than that of the memory, but the access speed of objects (including data and instructions) is faster than that of the memory. There are usually multiple levels of cache between the CPU and the memory, such as Figure 1 The first-level cache (L1 cache), second-level cache (L2 cache) and third-level cache (L3 cache) shown in FIG. According to the cached object, the first-level cache can be divided into a data cache and an instruction cache. As the name implies, the data cache is used to cache data, and the instruction cache is used to cache instructions. Then, the CPU's access to the memory needs to go through the above-mentioned multi-level cache. Taking the case where the object accessed by the CPU is data, the CPU first accesses the first-level cache (specifically the data cache). If the data to be accessed is in the first-level cache, the data is read from the first-level cache. If the data to be accessed is not in the first-level cache, the second-level cache is accessed. If the data to be accessed is in the second-level cache, the data is read from the second-level cache. If the data to be accessed is not in the second-level cache, the third-level cache is accessed. If the data to be accessed is in the third-level cache, the data is read from the third-level cache. If the data to be accessed is not in the third-level cache, the CPU accesses the data from the memory. It should be understood that the process of the CPU accessing instructions is similar to the process of the above-mentioned data access, so it will not be described in detail here.

[0052] There are two situations in the above process: First, the object accessed by the CPU is in the cache, that is, the CPU can read the object to be accessed from the first-level cache, the second-level cache, or the third-level cache, which is called a cache hit. Second, if the object accessed by the CPU is not in the cache, that is, the CPU fails to read the object to be accessed from the first-level cache, the second-level cache, and the third-level cache, this situation is called a cache miss.

[0053] Since memory access has latency, when the object accessed by the CPU is not in the cache, the CPU needs to wait for a long time to access the data or instruction, which leads to bottlenecks in the program execution process. To this end, a variety of cache optimization methods have emerged, including but not limited to the following:

[0054] 1. Data prefetching

[0055] Data prefetching refers to the CPU transferring the data to be accessed from the memory to the cache in advance before accessing the data in the memory. There are two main ways of data prefetching: hardware prefetching and software prefetching. Among them, hardware prefetching refers to the CPU transferring the data that may be accessed in the future to the cache in advance based on the historical information of memory access. Software prefetching refers to the compiler inserting prefetch instructions into the program during the process of compiling the program source code, so that when the program is running, the prefetch instructions can be used to transfer the data that may be accessed to the cache in advance.

[0056] It is worth noting that an effective data prefetching mechanism is to transfer the memory data from the memory to the cache just before the CPU uses it, so that the CPU can access the data from the cache, thereby reducing the latency of memory access. In other words, data prefetching cannot be too early or too late. Only by moving data from the memory to the cache in a timely manner within a specific time window can cache eviction and cache pollution be minimized, and the cost of data prefetching can be avoided to be greater than the benefit of data prefetching.

[0057] 2. Structural optimization

[0058] A struct is a data structure, such as an integer or a floating point. A struct includes one or more structure members, and different structure members can be of different types. For example, a structure S includes an integer data a, a character variable b, and a double-precision variable c, where data a, variable b, and variable c are all structure members in the structure S.

[0059] The main ways to optimize structures are structure member rearrangement and structure splitting. Among them, structure member rearrangement refers to adjusting the order of members in the structure so that the frequently accessed members in the structure are located in the same cache line as much as possible, thereby improving the utilization of the cache block and achieving the purpose of cache optimization. Among them, the cache block is the unit block that makes up the cache, and each cache block includes one or more continuous memory storage units. Structure splitting refers to splitting a structure into multiple structures according to the access frequency of members in the structure, thereby improving the utilization of the cache block and achieving the purpose of cache optimization.

[0060] 3. Function Rearrangement

[0061] Function reordering refers to reordering the code within a function or between different functions so that functions with close calling relationships are arranged adjacent to each other, thereby improving the utilization of cache blocks, reducing instruction transfer waiting caused by cache misses, and improving program operation efficiency.

[0062] It is not difficult to see that the above cache optimization methods all involve the following problem: How to accurately determine which objects (data or instructions) in the memory may be frequently accessed by the CPU? After determining the objects that will be frequently accessed by the CPU, how to calculate appropriate optimization strategies based on these objects to optimize the cache. At present, cache optimization is mainly based on instrumentation technology, that is, by instrumenting and tracking the operation instructions of the CPU memory access objects (for example, load operands, store operands), the objects that the CPU needs to read from the memory are determined, so that corresponding optimization operations are performed on these objects during the compilation phase, such as data prefetching operations. However, this method requires software instrumentation to be implemented, which increases the overhead of cache optimization, and this method also has the problem of low accuracy and timeliness, that is, after the cache is optimized using the above method, the object is not moved from the memory to the cache in time before the CPU accesses the memory object.

[0063] In order to solve the above problems, the present application provides a compilation optimization method for program source code. By using this method, the program source code can be compiled to obtain a corresponding executable file. When the CPU executes the executable file, it can not only optimize the cache, but also reduce the cache optimization overhead and improve the accuracy and timeliness of cache optimization.

[0064] The program source code compilation method provided in this application can be executed by a compilation optimization device. Figure 2 FIG. 2 shows a schematic diagram of the structure of a compile optimization device. Figure 2 As shown, the compilation optimization device 100 includes an operation unit 110, an event collection unit 120, a parsing unit 130 and a compilation unit 140. The above-mentioned units are briefly introduced below.

[0065] (1) Operation unit 110

[0066] The running unit 110 is used to obtain a first executable file and run the first executable file, wherein the first executable file includes an executable program and debugging information, the executable program is compiled from a program source code, and the debugging information includes a correspondence between the program source code and executable instructions in the executable program.

[0067] (2) Event collection unit 120

[0068] The event collection unit 120 is used to collect hardware cache events when running the first executable file. Hardware cache events refer to the state data when the CPU accesses the cache. It should be understood that since there may be two situations when the CPU accesses the cache, one is a cache hit and the other is a cache miss, the above-mentioned hardware cache events may include cache hit events and cache miss events. Among them, a cache hit event refers to an event in which the CPU obtains an access object from the cache when accessing the cache; a cache miss event refers to an event in which the CPU does not obtain an access object from the cache when accessing the cache.

[0069] In the embodiment of the present application, considering that performance monitor units (PMUs) are commonly present in current CPUs, the PMUs are used to monitor the execution status events (i.e., hardware events) of various hardware in the CPU, and the hardware events on the CPU include the above-mentioned hardware cache events. Therefore, the event collection unit 120 may include a PMU 121 and a performance collection tool 122. Among them, the PMU 121 is used to monitor the hardware events on the CPU, and the performance collection tool 122 is used to sample and record the hardware cache events of the PMU 121. Optionally, the performance collection tool 122 may adopt a performance collection tool provided by Linux (e.g., perf, OProfile), or a performance collection tool provided by Windows (e.g., perfmon, VTune), etc., which is not specifically limited here.

[0070] Optionally, the PMU 121 may be configured so that the PMU 121 only monitors the hardware cache events on the CPU, thereby reducing the work of the PMU 121.

[0071] The event collection unit 120 is further configured to send the collected hardware cache events to the analysis unit 130 .

[0072] (3) Analysis unit 130

[0073] The parsing unit 130 is used to obtain the first executable file and receive the hardware cache event sent by the event collection unit 120. The parsing unit 130 is also used to parse the first executable file to obtain debugging information, and then obtain first configuration information based on the debugging information and the hardware cache event. The first configuration information includes an identifier of the program source code and the number of cache misses corresponding to the identifier. The parsing unit 130 is also used to send the first configuration information to the compiling unit 140.

[0074] (4) Compilation unit 140

[0075] The compiling unit 140 is used to obtain the program source code, receive the first configuration information sent by the parsing unit 130, and compile the program source code according to the first configuration information to obtain a second executable file.

[0076] In a specific embodiment, the compilation unit 140 includes a data prefetch module 141. The data prefetch module 141 is used to perform a compilation operation of data prefetching on the program source code according to the first configuration information. Specifically, the data prefetch module 141 parses the first configuration information, and determines the source code in the program source code that satisfies condition A, wherein condition A includes: the number of cache misses of the source code is greater than a threshold value A, and the source code includes the CPU's memory access object. Then, the data prefetch module 141 calculates the prefetch distance of the source code that satisfies condition A, and generates a prefetch instruction based on the prefetch distance, so that the CPU can read the required memory access object from the cache when executing the executable instruction corresponding to the source code.

[0077] In a specific embodiment, the compilation unit 140 also includes a structure member rearrangement module 142. The structure member rearrangement module 142 is used to perform a compilation operation of rearranging structure members on the program source code according to the first configuration information. Specifically, the structure member rearrangement module 142 obtains all structures in the program source code, as well as the members in each structure, and then determines the structure that meets condition B by parsing the above-mentioned first configuration information, wherein condition B includes: there is no sequential dependency in the use of each member in the structure, and the number of cache misses of the structure is greater than a threshold value B, and the absence of sequential dependency in the use of each member in the structure means: the members in the structure are not taken through structure pointers and offsets. Afterwards, the order of the members in the above-mentioned structure that meets condition B is adjusted to obtain a new structure, and the new structure is used to replace the original structure (i.e., the above-mentioned structure that meets condition B).

[0078] Optionally, the compilation unit 140 may further include a structure splitting module 143 or a function reordering module 144. The structure splitting module 143 is used to split the structure in the program source code where cache miss events frequently occur according to the first configuration information. The function reordering module 144 is used to perform a compilation operation of function reordering on the function in the program source code where cache miss events frequently occur according to the first configuration information.

[0079] Combine the following Figure 3 , the specific process of compiling and optimizing the program source code by the above-mentioned compiling and optimizing device 100 is described in more detail. Figure 3 As shown, Figure 3 A schematic diagram of a program source code compilation optimization method provided by the present application is shown, and the method includes but is not limited to the following steps:

[0080] S101: Obtain a first executable file.

[0081] The first executable file is a file obtained by compiling the program source code and can be loaded and executed by the CPU. The program source code refers to an uncompiled text file written in accordance with a certain programming language (for example, C language, C++ language), which is a series of human-readable computer language instructions. Optionally, the first executable file can be a binary executable file, and the executable instructions can be assembly instructions, machine instructions, etc.

[0082] In the embodiment of the present application, the first executable file includes an executable program and debugging information, the executable program refers to a program that can be loaded and executed by the CPU, the executable program includes executable instructions, and the executable instructions refer to instructions that can be loaded and executed by the CPU. The debugging information is generated during the process of the above-mentioned compiler compiling the program source code, and is used to represent the relationship between the program source code and the executable program. The debugging information includes the corresponding relationship between the program source code and the executable instructions in the executable program.

[0083] In practical applications, considering people's habit of writing program source code, the program source code can be regarded as consisting of multiple lines of source code, and after compilation, one executable instruction usually corresponds to one or more lines of source code. Then, the correspondence between the program source code and the executable instructions in the executable program included in the above debugging information can be specifically the correspondence between the identifier of each line of source code and the identifier of each executable instruction. Among them, the identifier of each line of source code can be the number of the line of source code, and the identifier of each executable instruction can be the number of the executable instruction. Optionally, the identifier of each line of source code can also be the storage address of each line of source code, and the identifier of each executable instruction can also be the storage address of the executable instruction.

[0084] S102: Run the first executable file to collect hardware cache events.

[0085] In some embodiments, the compiling and optimizing device 100 monitors the hardware events that occur during the execution of the first executable file, and samples and records the hardware cache events in the hardware events. For the specific description of the hardware events and the hardware cache events, please refer to the relevant introduction of the event acquisition unit 120 in the above content, which will not be described here for simplicity.

[0086] It should be understood that since hardware events include not only hardware cache events, in other embodiments, the compilation optimization device 100 may only monitor the hardware cache events on the CPU during the execution of the first executable file, and sample and record the monitored hardware cache events.

[0087] S103: Obtain first configuration information according to the hardware cache event and the debugging information.

[0088] The first configuration information includes an identifier of the program source code and the number of cache misses corresponding to the identifier. The identifier of the program source code may be an identifier of all source codes in the program source code (for example, an identifier of each line of source code in the program source code), or an identifier of part of the source code in the program source code, which is not specifically limited here.

[0089] In a specific embodiment, the compilation optimization device 100 obtains the first configuration information according to the hardware cache event and the debugging information, including: parsing the first executable file to obtain the debugging information. Then, the hardware cache event is parsed to obtain the number of cache misses corresponding to the executable instruction in the executable program, wherein the number of cache misses corresponding to the executable instruction refers to the number of cache miss events that occur when the CPU executes the executable instruction. Afterwards, according to the cache misses corresponding to the executable instruction and the above-mentioned debugging information, the number of cache misses corresponding to the source code associated with the executable instruction is determined, thereby obtaining the above-mentioned first configuration information.

[0090] It should be noted that the first configuration information is used to instruct the compiler to compile the program source code. Therefore, after obtaining the first configuration information, the compilation optimization device 100 needs to store the first configuration information as a file in a format that the compiler can parse. For example, the compiler used is the GCC compiler, and the GCC compiler can read and parse files in the .gcov format. Then, after obtaining the first configuration information, the compilation optimization device 100 will store the first configuration information as a file in the .gcov format, so that the GCC compiler can read and parse the first configuration information.

[0091] S104: Compile the program source code according to the first configuration information to obtain a second executable file.

[0092] Among them, similar to the first executable file, the second executable file is also a file that can be loaded and run by the CPU, but the second executable file is different from the first executable file. Compared with the first executable file, when the CPU executes the second executable file, the cache optimization effect is better, so that the time consumed in accessing the memory is less and the program runs more efficiently.

[0093] In the embodiment of the present application, after the compilation and optimization device 100 obtains the first configuration information, the program source code can be compiled according to the first configuration information in any of the following ways:

[0094] Mode 1: The compilation optimization device 100 performs a data pre-fetching compilation operation on the program source code according to the first configuration information.

[0095] Specifically, the compilation optimization device 100 parses the first configuration information to determine the source code in the program source code that meets condition A. Then, the pre-fetch distance of the source code that meets condition A is calculated, and the pre-fetch distance represents the advance amount of moving the CPU's memory access object from the memory to the cache. Finally, a pre-fetch instruction is generated according to the pre-fetch distance, so that when the CPU executes the executable instruction corresponding to the source code that meets condition A, the corresponding memory access object can be read from the cache.

[0096] In a specific embodiment, the compilation optimization device 100 determines the source code in the program source code that meets the condition A in various ways, for example:

[0097] ①. Parse the first configuration information, obtain the identifier of the program source code and the number of cache misses corresponding to the identifier, thereby obtaining the number of cache misses of multiple functions in the program source code, wherein the number of cache misses of each function is equal to the sum of the number of cache misses corresponding to the source code included in the function. Then, sort the above multiple functions in descending order according to the number of cache misses, and filter out at least one function that meets condition C (for simplicity, the function that meets condition C is referred to as the first function below), wherein condition C includes at least one of the following: the number of cache misses of the function is greater than the threshold C, and the ranking of the function is less than the threshold D. Then, determine the source code involving the CPU memory access object in each first function, and obtain the number of cache misses corresponding to the source code involving the CPU memory access object according to the identifier of the program source code and the number of cache misses corresponding to the identifier, and then sort the above source code involving the CPU memory access object in descending order according to the number of cache misses, thereby determining the source code that meets condition A, wherein condition A includes: the number of cache misses of the source code is greater than the threshold A, the ranking of the source code is less than the threshold E, and the source code includes the CPU memory access object.

[0098] It should be understood that a function may include: source code related to CPU memory access objects, source code related to arithmetic operations, source code related to logical operations, source code related to judgment and control, etc. Only the source code related to memory access objects will cause cache miss events. Therefore, in order to perform data prefetch operations more accurately, the compilation and optimization device 100 further determines the source code related to CPU memory access objects in the first function after filtering out the first function, thereby filtering out the source code that meets condition A.

[0099] One point that needs to be explained is that, in actual applications, multiple functions in the program source code may not satisfy the above-mentioned condition C, or the source code in the first function may not satisfy condition A in method ①. In this case, the compilation optimization device 100 will not perform data pre-fetching compilation optimization operations on the program source code.

[0100] ②. Parse the first configuration information to obtain the identifier of the program source code and the number of cache misses corresponding to the identifier, and then determine the source code in the program source code that involves the CPU memory access object and the number of cache misses corresponding to these source codes. Then, sort the source codes involving the CPU memory access object in descending order according to the number of cache misses, so as to determine at least one source code that meets the condition A, where the condition A includes: the number of cache misses of the source code is greater than the threshold A, the ranking of the source code is less than the threshold F, and the source code includes the CPU memory access object.

[0101] It should be noted that, in actual applications, the source codes in the program source code may not satisfy condition A in method ②. In this case, the compilation optimization device 100 will not perform the compilation optimization operation of data prefetching on the program source code.

[0102] In a specific embodiment, it is considered that when the CPU executes a loop program, especially the program of the innermost loop nested in the loop, a cache miss event is most likely to occur. Then, the compilation optimization device 100 calculates the pre-fetch distance of the source code that meets the condition A, including the following steps: obtaining the CFG of the first loop, wherein the first loop is the innermost loop including the source code that meets the condition A, the CFG of the first loop represents all the paths that the CPU will traverse during the execution of the first loop, and the CFG of the first loop includes multiple BBs and multiple directed edges, and the multiple directed edges are used to indicate the execution order between multiple BBs. Then, the execution probability of each directed edge is determined, and the single cycle time of the first loop is calculated according to the execution probability of each directed edge. Afterwards, the pre-fetch distance of the source code that meets the condition A is calculated according to the single cycle time of the first loop. For the specific process of this step, please refer to S201-S206 below.

[0103] Mode 2: The compilation optimization device 100 performs a compilation operation of rearranging structure members on the program source code according to the first configuration information.

[0104] In a specific embodiment, before the compilation optimization device 100 performs a compilation operation of rearranging structure members on the program source code, it also performs the following steps: obtaining multiple structures in the program source code, and members in the multiple structures, and then recording the type of each structure in the above multiple structures, the variables of each structure, and the members in each structure.

[0105] In a specific embodiment, the compilation optimization device 100 performs a compilation operation of rearranging structure members on the program source code according to the first configuration information, including: parsing the first configuration information, determining the identifier of the program source code and the number of cache misses corresponding to the identifier, and obtaining the number of cache misses of each of the above structures according to the identifier of the program source code and the number of cache misses corresponding to the identifier, thereby determining the structure that meets condition B, wherein condition B includes: there is no order dependency in the use of each member in the structure, and the number of cache misses of the structure is greater than threshold B, and the absence of order dependency in the use of each member in the structure means: the members in the structure are not taken through structure pointers and offsets. Afterwards, the order of the members in the structure that meets condition B is adjusted to obtain a new structure, and finally, the new structure is used to replace the structure that meets condition B. For the specific process of this step, please refer to S301-S306 below.

[0106] It should be understood that the compilation optimization device 100 can also perform compilation operations of structure splitting or function rearrangement on the program source code according to the first configuration information. Its specific concept is similar to the concept of the above-mentioned method 1 and method 2. For the sake of simplicity, this application will not elaborate on it.

[0107] By implementing the compilation method of the above-mentioned program source code, a second executable file can be obtained, and when the CPU executes the second executable file, the purpose of optimizing the cache can be achieved. In addition, according to the description above, the method is to determine the number of cache misses corresponding to the program source code by collecting hardware cache events, and then compile the program source code in combination with the number of cache misses corresponding to the program source code, so that the compiled second executable file can more accurately and timely inform the CPU how to optimize the cache. Therefore, the compilation method of the program source code provided by the present application can not only improve the accuracy and timeliness of cache optimization, but also save the cost of cache optimization.

[0108] Combine the following Figure 4 The process of calculating the pre-fetch distance of the source code satisfying the condition A by the compilation optimization device 100 in S104 is further described.

[0109] In the embodiment of the present application, considering that the at least one first function is a function in the program source code where cache miss events occur more frequently, the source code satisfying condition A is most likely to be the source code in the innermost loop of the at least one first function, that is, the first loop is most likely to be the innermost loop in the at least one first function, and therefore, the compilation optimization device 100 will execute S201-S203 to obtain the first loop. For simplicity, a first function is used as an example for description.

[0110] S201: Obtain at least one innermost loop in a first function.

[0111] It should be understood that in actual situations, the first function may include multiple innermost loops, some of which have a higher probability of being executed while others have a lower probability of being executed. Compared with the innermost loop with a lower probability of being executed, the source code that satisfies condition A is more likely to be part of the innermost loop with a higher probability of being executed. Therefore, the compilation optimization device 100 can also execute S202. It should be noted that the probability of executing the innermost loop iteration refers to the probability of iteratively running in the loop, not the probability of executing the loop in the function.

[0112] S202: Determine the innermost loop that satisfies condition D in the at least one innermost loop, and obtain a first loop and a CFG of the first loop.

[0113] The condition D includes at least one of the following: the probability of executing the loop iteration is greater than the threshold G, and the probability of executing the loop without iteration is less than the threshold H.

[0114] In a specific embodiment, the compilation optimization device 100 can calculate the probability of execution or non-execution of each innermost loop in the first function in the following manner, which is described by taking an innermost loop in the first function as an example:

[0115] First, construct the CFG of the loop. The CFG of the loop represents all the paths that the CPU will traverse during the execution of the loop. The CFG of the loop includes multiple BBs and multiple directed edges. Each directed edge indicates the execution order between two BBs in the loop. Each BB includes at least one instruction. It should be noted that the instructions in the BB are source code. Then, traverse each BB, record each BB, the number of executions of each BB, and the execution probability of each directed edge. After that, the execution probability of the loop and the probability of not executing the loop can be calculated by referring to the following formula:

[0116]

[0117] y2=1-y1

[0118] Among them, y1 represents the probability of not executing the loop, exit_edge_prob represents the probability of exiting the directed edge of the loop, exit_BB_count represents the number of executions of the BB leading to the directed edge, header_BB_count represents the number of executions of the entry BB of the loop, and y2 represents the execution probability of the loop. The above exit_edge_prob, exit_BB_count and header_BB_count can be calculated by the compilation optimization device 100 using the static analysis function of the compiler, FDO or AutoFDO and other methods. For simplicity, this application will not introduce them.

[0119] For example, assume that the first function includes loop 1, the threshold G in condition D is 0.9, and the threshold H is 0.2. Figure 5 The CFG of loop 1 is shown, wherein the execution times of BB1, BB2, BB3, BB4 and BB5 are 100, 99, 100, 99, 1 respectively, and the execution probabilities of directed edge BB1→BB2, directed edge BB1→BB3, directed edge BB2→BB3, directed edge BB3→BB4, directed edge BB3→BB5 and directed edge BB4→BB1 are 99%, 1%, 100%, 99%, 1%, 100% respectively, and BB1 is the entry BB of loop 1, and directed edge BB3→BB5 is the directed edge exiting loop 1. Therefore, using the above formula, it can be calculated that y1=(1%*100) / 100=0.01, y2=1-0.01=0.99, that is, the probability of not executing loop 1 is 0.01, and the probability of executing loop 1 is 0.99, which satisfies the above condition D, and loop 1 in the first function is a first loop.

[0120] S203: Determine BBs that are irrelevant to the loop layer of the first loop and directed edges that are irrelevant to the loop layer of the first loop, and trim the irrelevant BBs and directed edges to obtain a second loop.

[0121] Specifically, the compiling and optimizing device 100 traverses all BBs in the first loop, determines BBs and directed edges that are irrelevant to the first loop, and prunes these irrelevant BBs and directed edges to obtain a second loop. Among them, the BBs that are irrelevant to the loop layer of the first loop may be the BBs pointed to by the directed edges that exit the first loop, and the directed edges that are irrelevant to the loop layer of the first loop may be the directed edges that exit the first loop. Figure 5 Taking the loop 1 shown in the figure as an example, BB5 is a BB that is independent of the loop layer of loop 1, and the directed edge BB3→BB5 is a directed edge that is independent of the loop layer of loop 1. After cutting BB5 and the directed edge BB3→BB5, we can get the following Figure 6 The cycle shown.

[0122] S204: Calculate the execution probability of each BB in the second cycle.

[0123] Specifically, when executing the above S202, the compilation optimization device 100 constructs the CFG of each innermost loop in the first function, and records the execution probability of the BBs and directed edges included in the CFG. Therefore, the compilation optimization device 100 can obtain the execution probability of each BB and each directed edge included in the CFG of the first loop, and then calculate the execution probability of each BB in the second loop according to the execution probability of each directed edge included in the CFG of the first loop.

[0124] In a possible implementation, for the convenience of calculation, it can be assumed that the execution probability of the entry BB of the second loop is 100%, and then the execution probability of each BB in the second loop is calculated according to the execution probability of each directed edge included in the CFG of the first loop. Figure 6 Taking the loop shown as an example, assuming that the execution probability of BB1 is 100%, since the execution probabilities of directed edges BB1→BB2, BB1→BB3, BB2→BB3, BB3→BB4, and BB4→BB1 are 99%, 1%, 100%, 99%, and 100% respectively, the execution probability of BB2 is 99%, the execution probability of BB3 is 100% (1%+99%), and the execution probability of BB4 is 99%.

[0125] It should be noted here that, for loops with higher execution probabilities, after cutting out the exit branch of the loop (i.e., BBs that are not related to the loop layer of the loop), the execution probabilities of each BB in the independent loop body can still be reflected more accurately. For loops with lower execution probabilities, after cutting out the exit branch of the loop, since the execution probability of the exit branch is higher and the execution probability of the BBs in the loop layer is lower, the execution probability of each BB in the cut loop cannot represent its execution probability in the entire loop. That is to say, the compilation optimization device 100 can also improve the accuracy of data prefetching by executing the above S102.

[0126] It should also be noted that in the embodiment of the present application, by calculating the execution probability of the loop branch (that is, the execution probability of the directed edge), a more reasonable execution time of a single loop can be calculated. Figure 6BB2 may contain a large number of instructions, so it takes a long time to execute BB2. If the execution time of BB2 is not calculated based on the execution probability of the directed edge BB1→BB2, the calculated execution time of a single loop will be longer. However, in actual applications, the probability of the CPU executing BB2 is very low (1%), that is, in most cases the loop execution will jump directly from BB1 to BB3, so the calculated execution time of a single loop will be much shorter. Therefore, when calculating the execution time of a single loop, combining the execution probability of the loop branch will calculate a more reasonable value.

[0127] S205: Calculate the single cycle time of the second cycle, that is, the single cycle time of the loop layer of the first cycle (hereinafter referred to as the single cycle time of the first cycle), according to the execution probability of each BB in the second cycle and the number and type of instructions in each BB.

[0128] Specifically, the number and type of all instructions in each BB of the second loop are obtained. Since the execution time of instructions of the same type is the same, the calculation of the single cycle time of the second loop can refer to the following formula:

[0129] loop_time=sum(BB_prob*sum(inst_time))

[0130] Wherein, loop_time represents the single loop time of the second loop, BB_prob represents the execution probability of BB, inst_time represents the execution time of an instruction in BB, and sum(inst_time) represents the sum of the execution time of all instructions in BB.

[0131] S206: Calculate the pre-fetch distance of the source code satisfying condition A in the first loop according to the single loop time of the first loop and the delay time of the CPU accessing the memory.

[0132] Specifically, the compilation optimization device 100 obtains the delay time of the CPU accessing the memory, determines the first source code existing in the second loop, and then calculates the pre-fetch distance of the first source code in the second loop according to the single loop time of the second loop and the delay time of the CPU accessing the memory.

[0133] In a specific embodiment, the calculation of the pre-fetch distance of the source code that meets the condition A in the first cycle can refer to the following formula:

[0134] prefetch_dis=latency / loop_time

[0135] Among them, prefetch_dis represents the prefetch distance of the source code that meets condition A in the first loop, latency represents the delay time for the CPU to access the memory, and loop_time represents the single loop time of the second loop.

[0136] Combine the following Figure 7 The process of the compilation optimization device 100 performing the compilation operation of rearranging structure members on the program source code according to the first configuration information in S104 is further described.

[0137] S301: Determine at least one first structure among the plurality of structures, wherein members in the first structure have no sequence dependency in use.

[0138] Specifically, it is detected whether the members in each of the above structures have sequential dependency in use. If any member in the structure has sequential dependency in use, the compilation optimization device 100 does not perform the operation of reordering the structure members on the structure. If the members in the structure do not have sequential dependency in use (i.e., the first structure), the compilation optimization device 100 executes the following S302-S306.

[0139] S302: Parse the first configuration file to obtain an identifier of the program source code and a cache miss count corresponding to the identifier, thereby obtaining the cache miss count of the at least one first structure.

[0140] S303: Sort the at least one first structure according to the number of cache misses, and select a structure that meets condition E (hereinafter referred to as the second structure).

[0141] If the at least one first structure is sorted in descending order according to the number of cache misses, condition E includes at least one of the following: the number of cache misses of the structure is greater than threshold I, and the ranking of the structure is less than threshold J. If the at least one first structure is sorted in ascending order according to the number of cache misses, condition E includes at least one of the following: the number of cache misses of the structure is greater than threshold I, and the ranking of the structure is greater than threshold K. It should be understood that condition B includes: condition E and each member in the structure have no order dependency in use.

[0142] S304: Determine the number of cache misses of each member in the second structure according to the identifier of the program source code and the number of cache misses corresponding to the identifier.

[0143] S305: According to the number of cache misses of each member in the second structure, the order of the members in the second structure is adjusted to obtain a corresponding third structure.

[0144] In a specific embodiment, the compilation optimization device 100 adjusts the order of the members in the second structure according to the number of cache misses of each member in the second structure to obtain a corresponding third structure, including the following steps: according to the number of cache misses of each member in the second structure, the members with a large number of cache misses in the structure are placed in the same cache block, so that the cache utilization rate can be improved.

[0145] For example, Figure 8 As shown, the second structure includes 8 members, namely member a, member b, member c, member d, member e, member f, member g, and member h, and there is no sequential dependency in the use of these members. Fig. 9 A schematic diagram of the storage arrangement of the second structure is shown. Fig. 9 As shown, the second structure is stored as two cache blocks in the cache. Assume that when the CPU executes the program, it only needs to read the above-mentioned member a and member g from the cache. In this case, the CPU needs to read 2 cache blocks from the cache to obtain the above-mentioned member a and member g. However, if the method provided in the above embodiment is executed, that is, the order of each member in the second structure is adjusted according to the size of the number of cache misses (the members with the largest number of cache misses are: member a, member g, member b, member c, member d, member e, member f, member h), it can be obtained Fig.10 The third structure shown and Fig.11 The storage arrangement diagram of the third structure is shown in FIG. In this case, the CPU only needs to read one cache block from the cache to obtain the above members a and g. Therefore, compared with Figure 8 The second structure shown, when the cache is stored Fig.10 When the third structure is shown, the cache utilization rate can be improved.

[0146] Furthermore, the compilation optimization device 100 can also obtain the size of each member in the second structure, and adjust the order of each member in the second structure according to the number of cache misses of each member in the second structure and the size of each member in the second structure, so as to obtain a corresponding third structure. Specifically, when the number of cache misses of the members in the second structure is similar, the order of each member can be adjusted according to the size of the member, so as to obtain a corresponding third structure.

[0147] For example, Figure 8 Taking the second structure shown in FIG. 1 as an example, assuming that the number of cache misses of members b, c, d, e, f, and h in the second structure is similar, members b and e occupy less memory space than other members in the second structure. Therefore, in Fig.10Based on the third structure shown, the order of member b, member c, member d, member e, member f, and member h is further adjusted to obtain Fig.12 Another third structure shown and Fig.13 Another storage arrangement diagram of the third structure is shown in FIG. Figure 8 and Fig.10 The structures shown are all 64 bytes in size, and Fig.12 The size of the structure shown is only 56 bytes, so compared to Figure 8 and Fig.10 The structure shown is Fig.12 The structure shown occupies less storage space, that is, the cache utilization rate can be improved by using the above method.

[0148] S306: Using the third structure to replace the second structure.

[0149] The present application also provides a compilation optimization device, which is used to execute or implement the compilation optimization method of the above-mentioned program source code. The functions of the compilation optimization device can be implemented by a software system, by a hardware device, or by a combination of a software system and a hardware device.

[0150] As mentioned above Figure 2 As shown, the compilation optimization device provided by the present application may include an operation unit 110, an event collection unit 120, a parsing unit 130 and a compilation unit 140. Among them, the operation unit 110 is used to execute the steps of running the first executable file in the aforementioned S101 and S102. The event collection unit 120 is used to execute the steps of collecting hardware cache events in the aforementioned S102. The parsing unit 130 is used to execute the aforementioned S103. The compilation unit 140 is used to execute the aforementioned S104, S201-S206 and S301-S306. For the sake of simplicity, it will not be described in detail here.

[0151] The present application also provides a computing device, which is used to execute the compilation optimization method of the above-mentioned program source code, and when the above-mentioned compilation optimization device 100 is a software system, the above-mentioned compilation optimization device 100 can also be deployed on the computing device to realize the functions of the above-mentioned compilation optimization device 100.

[0152] like Fig.14 As shown, Fig.14 The schematic diagram of the structure of a computing device provided by the present application is shown. The computing device 200 includes a memory 210, a processor 220, a communication interface 230 and a bus 240. The memory 210, the processor 220 and the communication interface 230 are connected to each other through the bus 240.

[0153] The memory 210 may be a read only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 210 may store computer instructions, such as computer instructions in the execution unit 110, computer instructions in the event acquisition unit 120, computer instructions in the parsing unit 130, computer instructions in the compiling unit 140, etc. When the computer instructions stored in the memory 210 are executed by the processor 220, the processor 220 and the communication interface 230 are used to execute part or all of the methods described in the above steps S101-S104, S201-206, and S301-S306. The memory 210 may also store data, such as intermediate data or result data generated by the processor 220 during execution, such as debugging information, pre-fetch distance, structure members, a second executable file, etc.

[0154] The processor 220 may be a CPU, a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits.

[0155] The processor 220 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, some or all of the functions of the above-mentioned compilation and optimization device 100 may be completed by the hardware integrated logic circuit or software instructions in the processor 220. The processor 220 may also be a general-purpose processor, a digital signal processor (DSP), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, so as to implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc., and the steps of the method disclosed in the embodiments of the present application may be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor may be combined to be executed. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 210, and the processor 220 reads the information in the memory 210, and completes some or all of the functions of the above-mentioned compilation and optimization device 100 in combination with its hardware.

[0156] The communication interface 230 uses a method module such as, but not limited to, a transceiver to implement communication between the computing device 200 and other devices or communication networks. For example, the first executable file and program source code can be obtained through the communication interface 230, and the compiled second executable file can also be sent to other devices through the communication interface 230.

[0157] Bus 240 may include a pathway that transfers information between various components in computing device 200 (eg, memory 210 , processor 220 , communication interface 230 ).

[0158] The descriptions of the processes corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.

[0159] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, or a combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product providing the model training system includes one or more computing instructions executed by the model training system, and when these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiment diagram of the present application are generated.

[0160] The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or may be transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, twisted pair, or wireless (e.g., infrared, wireless, microwave), etc.) methods. The computer-readable storage medium stores computer program instructions for providing a model training system. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., an optical disk), or a semiconductor medium (e.g., a solid state disk (SSD)).

Claims

1. A compilation optimization method, characterized in that: include: Running a first executable file, wherein the first executable file includes an executable program and debugging information, the executable program is obtained by compiling a program source code, the executable program includes executable instructions, and the debugging information includes a correspondence between the program source code and the executable instructions; Collect hardware cache events; Obtaining first configuration information according to the hardware cache event and the debugging information, wherein the first configuration information includes an identifier of the program source code and a number of cache misses corresponding to the identifier; The program source code is compiled according to the first configuration information to obtain a second executable file.

2. The method according to claim 1, characterized in that The obtaining first configuration information according to the hardware cache event and the debugging information includes: Parsing the hardware cache event to obtain the number of cache misses corresponding to the executable instruction; The number of cache misses corresponding to the source code associated with the executable instruction is determined according to the number of cache misses corresponding to the executable instruction and the debugging information, thereby obtaining the first configuration information.

3. The method according to claim 1 or 2, wherein compiling the program source code according to the first configuration information to obtain a second executable file comprises: Parsing the first configuration information to determine source codes in the program source codes that meet a first condition, wherein the first condition includes: the number of cache misses of the source codes is greater than a first threshold, and the source codes include memory access objects; Calculating a pre-fetch distance of the source code that meets the first condition, wherein the pre-fetch distance represents an advance amount of moving the memory access object from the memory to the cache; A prefetch instruction is generated according to the prefetch distance.

4. The method according to claim 3, characterized in that The calculating the pre-fetch distance of the source code satisfying the first condition includes: Obtaining a control flow graph CFG of a first loop, where the first loop is an innermost loop including the source code that satisfies the first condition, and the CFG of the first loop includes a plurality of basic blocks BB and a plurality of directed edges, where the plurality of directed edges are used to indicate an execution order between the plurality of BBs; Determining the execution probability of each directed edge; Calculating a single cycle time of the first cycle according to the execution probability of each directed edge; The pre-fetch distance of the source code satisfying the first condition is calculated according to the single cycle time of the first cycle.

5. The method according to claim 4, characterized in that The obtaining of the CFG of the first cycle includes: Parsing the first configuration information to determine a function in the program source code that satisfies a second condition, wherein the second condition is that the number of cache misses of the function is greater than a second threshold, and the number of cache misses of the function is the sum of the number of cache misses of the source code included in the function; Determine a first loop in the function that satisfies the second condition, where the first loop is the innermost loop in the function that satisfies the second condition, and an execution probability of an iteration of the first loop is greater than a third threshold; Construct the CFG of the first loop.

6. The method according to claim 3 or 4, characterized in that: The calculating the single cycle time of the first cycle according to the execution probability of each directed edge includes: Determine BBs and directed edges that are independent of the loop layer of the first loop; The irrelevant BBs and directed edges are trimmed to obtain a second cycle; The execution probability of each BB in the second loop is calculated according to the execution probability of each directed edge to obtain a single loop time of the first loop, and the single loop time of the first loop is the sum of the products of the execution probability of each BB and the execution time of each BB.

7. The method according to claims 1-5, characterized in that: Before compiling the program source code according to the first configuration information to obtain the second executable file, the method further includes: Acquire multiple structures in the program source code, and members in the multiple structures; The program source code is compiled according to the first configuration information to obtain a second executable file, including: Parsing the first configuration information to determine a structure among the multiple structures that satisfies a third condition, wherein the third condition includes: members in the structure have no sequential dependency in use, and a cache miss count of the structure is greater than a fourth threshold; Adjusting the order of the members in the structure satisfying the third condition to obtain a new structure; The new structure is used to replace the structure satisfying the third condition.

8. The method according to claim 7, characterized in that Each of the structures includes source code in the program source code, and the parsing of the first configuration information to determine a structure that satisfies the third condition includes: Parsing the first configuration information to determine an identifier of the program source code and a number of cache misses corresponding to the identifier; The number of cache misses of each structure is obtained according to the identifier of the program source code and the number of cache misses corresponding to the identifier, thereby determining the structure that meets the third condition.

9. The method according to claim 7 or 8, characterized in that: The adjusting the order of the members in the structure satisfying the third condition includes: Obtaining the number of cache misses of multiple members in the structure that meets the third condition; The order of the multiple members is adjusted according to the magnitude of the number of cache misses of the multiple members.

10. The method according to claim 9, characterized in that The step of adjusting the order of the multiple members according to the number of cache misses of the multiple members includes: Get the size of each member in the plurality of members; The order of the multiple members is adjusted according to the size of each member and the number of cache misses of each member.

11. A compilation optimization device, characterized in that: The device comprises: An operating unit, configured to operate a first executable file, wherein the first executable file includes an executable program and debugging information, the executable program is obtained by compiling a program source code, the executable program includes executable instructions, and the debugging information includes a correspondence between the program source code and the executable instructions; An event collection unit, used for collecting hardware cache events; A parsing unit, configured to obtain first configuration information according to the hardware cache event and the debugging information, wherein the first configuration information includes an identifier of the program source code and a number of cache misses corresponding to the identifier; A compiling unit is used to compile the program source code according to the first configuration information to obtain a second executable file.

12. The device according to claim 11, characterized in that The parsing unit is specifically used for: Parsing the hardware cache event to obtain the number of cache misses corresponding to the executable instruction; The number of cache misses corresponding to the source code associated with the executable instruction is determined according to the number of cache misses corresponding to the executable instruction and the debugging information, thereby obtaining the first configuration information.

13. The apparatus according to claim 11 or 12, wherein the compilation unit is specifically configured to: Parse the first configuration information to determine source code in the program source code that meets the first condition, wherein: The first condition includes: the number of cache misses of the source code is greater than a first threshold, and the source code includes a memory access object; Calculating a pre-fetch distance of the source code that meets the first condition, wherein the pre-fetch distance represents an advance amount of moving the memory access object from the memory to the cache; A prefetch instruction is generated according to the prefetch distance.

14. The device according to claim 13, characterized in that The compilation unit is specifically used for: Obtaining a control flow graph CFG of a first loop, where the first loop is an innermost loop including the source code that satisfies the first condition, and the CFG of the first loop includes a plurality of basic blocks BB and a plurality of directed edges, where the plurality of directed edges are used to indicate an execution order between the plurality of BBs; determining an execution probability of each of the plurality of directed edges; Calculating a single cycle time of the first cycle according to the execution probability of each directed edge; The pre-fetch distance of the source code satisfying the first condition is calculated according to the single cycle time of the first cycle.

15. The device according to claim 14, characterized in that The compilation unit is specifically used for: Parsing the first configuration information to determine a function in the program source code that satisfies a second condition, wherein the second condition is that the number of cache misses of the function is greater than a second threshold, and the number of cache misses of the function is the sum of the number of cache misses of the source code included in the function; Determine a first loop in the function that satisfies the second condition, where the first loop is the innermost loop in the function that satisfies the second condition, and an execution probability of an iteration of the first loop is greater than a third threshold; Construct the CFG of the first loop.

16. The device according to claim 13 or 14, characterized in that The compilation unit is specifically used for: Determine BBs and directed edges that are independent of the loop layer of the first loop; The irrelevant BBs and directed edges are trimmed to obtain a second cycle; The execution probability of each BB in the second loop is calculated according to the execution probability of each directed edge to obtain a single loop time of the first loop, and the single loop time of the first loop is the sum of the products of the execution probability of each BB and the execution time of each BB.

17. The device according to claims 11-15, characterized in that The compilation unit is also used to: Acquire multiple structures in the program source code, and members in the multiple structures; The compilation unit is also used to: Parsing the first configuration information to determine a structure among the multiple structures that satisfies a third condition, wherein the third condition includes: members in the structure have no sequential dependency in use, and a cache miss count of the structure is greater than a fourth threshold; Adjusting the order of the members in the structure satisfying the third condition to obtain a new structure; The new structure is used to replace the structure satisfying the third condition.

18. The device according to claim 17, characterized in that Each structure includes source code in the program source code, and the compilation unit is specifically used for: Parsing the first configuration information to determine a number of cache misses corresponding to a source code associated with the executable instruction; The number of cache misses of each structure is obtained according to the number of cache misses corresponding to the source code associated with the executable instruction, thereby determining the structure that meets the third condition.

19. The device according to claim 17 or 18, characterized in that The compilation unit is specifically used for: Obtaining the number of cache misses of multiple members in the structure that meets the third condition; The order of the multiple members is adjusted according to the magnitude of the number of cache misses of the multiple members.

20. The device according to claim 19, characterized in that The compilation unit is specifically used for: Get the size of each member in the plurality of members; The order of the multiple members is adjusted according to the size of each member and the number of cache misses of each member.

21. A computing device, characterized in that The computing device comprises a processor and a memory, wherein the memory stores computer instructions, and the processor executes the computer instructions to enable the computing device to perform the method according to any one of claims 1 to 10.

22. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions. When the computer instructions are executed by a computing device, the computing device executes the method according to any one of claims 1 to 10.

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