Data Processor Bootstrapping Systems, Devices, and Clusters

Abstract

The present application provides a data processor startup system, device and cluster. The data processor startup system includes: a data processor simulates a peripheral device interconnection expansion device, and the peripheral device interconnection expansion device includes a peripheral device interconnection expansion bridge device and a peripheral device interconnection expansion terminal device. The peripheral device interconnection expansion terminal device includes multiple storage devices, and the multiple storage devices are connected to multiple operating system block devices. The operating system block device is mounted with an operating system, and the non-volatile memory includes an option read-only memory image, and the option read-only memory image guides the operation of the operating system in the corresponding operating system block device; when the processor scans the upstream port of the peripheral device interconnection expansion bridge device, the first option read-only memory image in the non-volatile memory is loaded into the memory of the processor, and the corresponding first operating system block device is matched according to the first option read-only memory image, and the first operating system in the first operating system block device is mounted.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a data processor startup system, device, and cluster. Background Art

[0002] Bare Metal Server is similar to a dedicated physical server on the cloud. It has high-performance computing capabilities on the basis of flexibility and elasticity. The computing performance is the same as that of traditional physical machines, and it has the characteristics of safe physical isolation. Before a bare metal server is put into use, it must be installed with an operating system before it can be officially used. However, in a large system, there are often thousands of bare metal servers at the same time. Therefore, installing an operating system for a bare metal server is a very labor-intensive task. Summary of the invention

[0003] The present application provides a data processor startup system, device and cluster, which can flexibly install an operating system on a server.

[0004] In a first aspect, a data processor startup system is provided, comprising:

[0005] A data processor is used to provide a peripheral device interconnection expansion device and a hardware logic of a topological relationship of the peripheral device interconnection expansion device. The data processor is also provided with a simulator. The simulator is used to provide a peripheral device interconnection expansion device and a software logic of a topological relationship of the peripheral device interconnection expansion device, and negotiate and interact with the hardware logic to realize the simulation of the peripheral device interconnection expansion device. The data processor also includes a non-volatile memory.

[0006] The peripheral device interconnection expansion device includes a peripheral device interconnection expansion bridge device and a peripheral device interconnection expansion terminal device, wherein the peripheral device interconnection expansion bridge device is used to connect the peripheral device interconnection expansion terminal device; the peripheral device interconnection expansion terminal device includes multiple storage devices, the multiple storage devices are respectively connected to multiple operating system block devices, the operating system block device is mounted with an operating system, the non-volatile memory includes one or more optional read-only memory images, and the optional read-only memory images are used to guide the operation of the operating system in the corresponding operating system block device;

[0007] A processor, for, when the processor is a first architecture processor, when scanning an upstream port of the peripheral device interconnect expansion bridge device, loading a first option read-only memory image corresponding to the first architecture processor in the non-volatile memory into the memory of the processor, matching a corresponding first operating system block device according to the first option read-only memory image, and mounting the first operating system in the first operating system block device.

[0008] In the above scheme, the required option read-only memory image can be loaded through external input as needed, and the option read-only memory image can be loaded onto the upstream port of the peripheral device interconnect expansion bridge device, so that all storage devices connected to this port can be initialized and managed without being restricted by the type and model of the storage device. Moreover, multiple read-only memory images can be loaded in batches into the non-volatile memory of the data processor, and multiple operating systems can be mounted into multiple operating system block devices respectively. When the processor scans the upstream port of the PCIE bridge device, the first option read-only memory image in the non-volatile memory is loaded into the memory of the processor, and the corresponding first operating system block device is matched according to the first option read-only memory image, and the first operating system in the first operating system block device is mounted, so that the processor can initialize and access the required option read-only memory image startup configuration more quickly without the need to load each storage device separately.

[0009] In some possible designs, the processor is further used to execute a storage device driver in the first option read-only memory image, read data of the first operating system from the first operating system block device, and thus mount the first operating system in the first operating system block device.

[0010] In some possible designs, when the first architecture processor is replaced with a second architecture processor, when the second architecture processor scans the upstream port of the peripheral device interconnect expansion bridge device, the second architecture processor loads the second option read-only memory image corresponding to the second architecture processor in the non-volatile memory into the memory of the processor, matches the corresponding second operating system block device according to the second option read-only memory image, and mounts the second operating system in the second operating system block device.

[0011] In the above solution, when replacing the hardware, you only need to replace the corresponding option read-only memory image and the operating system in the operating system block device.

[0012] In some possible designs, the first architecture processor is a processor using a complex instruction set, and the second architecture processor is a processor using a reduced instruction set; or, the first architecture processor is a processor using a unified extensible firmware interface, and the second architecture processor is a processor using a traditional basic input and output system; or, the first architecture processor is a processor using a pre-boot execution environment, and the second architecture processor is a processor using a block device.

[0013] In some possible designs, the processor is further configured to delete the first option read-only memory image from the non-volatile memory of the data processor through a remote procedure call method.

[0014] In some possible designs, the processor is further configured to add a third option read-only memory image to the non-volatile memory of the data processor through a remote procedure call method.

[0015] In the above solution, when upgrading the hardware, it is only necessary to add a corresponding third option read-only memory image in the non-volatile memory.

[0016] In some possible designs, the processor is also used to select a first option read-only memory image from multiple option read-only memory images of the non-volatile memory when scanning the upstream port of the peripheral device interconnect expansion bridge device, and load the first option read-only memory image into the memory of the processor.

[0017] In some possible designs, the processor is further configured to load the first option read-only memory image onto an upstream port of the peripheral device interconnect expansion bridge device.

[0018] In the above solution, the option read-only memory mirror can be placed on the upstream port of the peripheral device interconnect expansion bridge device, and the option read-only memory mirror can be centrally managed and controlled to avoid the problem that the option read-only memory mirror cannot be used due to a problem with a certain storage device.

[0019] In a second aspect, a computing device is provided, comprising a data processor startup system and a memory, wherein the data processor startup system and the memory can communicate with each other, and the data processor startup system is a system as described in any one of the first aspects.

[0020] According to a third aspect, a computing device cluster is provided, comprising a plurality of computing devices, at least one computing device comprising a data processor startup system and a memory, wherein the data processor startup system and the memory are capable of communicating with each other, and the data processor startup system is a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0022] Figure 1 It is a structural schematic diagram of a data processor startup system provided by the present application;

[0023] Figure 2 It is a structural diagram of a central processing unit provided by the present application;

[0024] Figure 3 It is a structural diagram of a data processor provided by the present application;

[0025] Figure 4 It is a schematic diagram of a processor loading option read-only memory image and an operating system provided by the present application;

[0026] Figure 5 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0028] See also Figure 1 , Figure 1 Schematic diagram of a data processor startup system provided by the present application. Figure 1 As shown, the data processor startup system provided in the present application includes: a central processing unit (CPU) 11 and a data processor (DPU) 12.

[0029] CPU11 is a computing core and a control core, and can handle complex situations. CPU11 can be a very large-scale integrated circuit. The main operating system and other software programs are installed in CPU11, so that CPU11 can access the memory and various PCIE devices. CPU11 can quickly access the local memory through the on-chip bus. CPU11 may include one or more processor cores. In one implementation, CPU11 may be a multi-core chip, that is, a chip containing multiple processing cores. In another implementation, CPU11 may include one or more processor cores. It can be a chip with one processing core.

[0030] See also Figure 2 , Figure 2 Schematic diagram of the structure of a central processing unit provided by this application. Figure 2 As shown, the CPU may include a memory address register 101, a memory data register 102, a program counter 103, an instruction register 104, an instruction decoder 105, a microcode read-only memory 106, an operation controller 107, a calculation unit 108, a general register group 109, an accumulator 110, a program status word register 111, a timing circuit 112, and a processor bus 120. The processor bus 120 may also be a data bus, a power bus, a control bus, or a status signal bus.

[0031] The CPU is used to process instructions and data stored in the memory 113. In some embodiments, the instructions may include one or more instruction formats. The instruction format may indicate various fields (number of bits, position of bits, etc.) to specify the operation of the data processing to be performed and the operand on which the operation will be performed. Some instruction formats may be further defined by instruction templates (or sub-formats).

[0032] In the CPU, the memory address register 101 is used to store the address of the memory that the CPU is currently accessing. The memory data register 102 is used to store the data and read or write instructions that the CPU reads or writes from the address, so as to make up for the difference in operating speed between the central processing unit and the memory.

[0033] The timing circuit 112 provides a time reference for each component through a fixed clock. The time for the central processing unit to execute an instruction is an instruction cycle. The program counter 103 is used to store the address of the next instruction. When the instructions are executed sequentially, the program counter 103 automatically adds the number of bytes of an instruction after each instruction is taken. When a transfer instruction is encountered, the program counter 103 specifies the address of the next instruction through the address code field in the transfer instruction. The instruction register 104 is used to save the instruction currently being executed. The instruction includes two fields, an operation code and an address code. The operation code part is decoded by the instruction decoder 105 to generate the control potential required by the instruction. The operation controller 107 can generate various operation control signals based on the control potential signal output by the instruction decoder and the timing signal generated by the timing circuit 112, and control the remaining components of the CPU to complete the operation of fetching and executing instructions.

[0034] A microinstruction is the smallest unit of instructions executed by a central processing unit. An instruction can be a single microinstruction or composed of several microinstructions. An instruction composed of multiple microinstructions is called a complex instruction. Various mechanisms can be used to implement the decoding of complex instructions by the instruction decoder 105. Specific decoding mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the steps of the microinstructions corresponding to the complex instructions can be stored in the microcode read-only memory 106. During the decoding process, the instruction decoder 105 can query and obtain the operation code and address code of the microinstructions constituting the complex instructions from the microcode read-only memory 106, and decode the operation code part of the microinstructions in turn to generate the control potential required by the microinstructions.

[0035] The operation controller 107 has multiple buffers, and can send the decoded instructions to their respective reservation stations for storage according to the types of instructions. After analyzing the status of the hardware circuit of the computing unit and the specific situation of whether each instruction can be executed in advance, the instructions that can be executed in advance are scheduled to the corresponding computing unit 108 for execution. During this period, the instruction stream is reordered so that the instruction pipeline can proceed and be smoothly scheduled. Exemplarily, for instructions of integer calculation, the operation controller 107 can use the integer reservation station to save instructions and assign them to the integer computing unit for calculation; for instructions of floating-point calculation, the operation controller 107 can use the floating-point reservation station to save instructions and assign them to the floating-point computing unit for calculation.

[0036] The general register group 109 is used to store the data corresponding to the address code according to the address code of the instruction. The calculation unit 108 is used to receive the operation control signal of the operation controller 107 and perform calculations on the data stored in the general register group 109, including arithmetic operations (including basic operations such as addition, subtraction, multiplication and additional operations) and logical operations (including shifting, logical testing or comparison of two values). The temporary variables generated in the calculation are stored in the accumulator 110, and the information of the generated status is stored in the program status word register 111, such as the operation result carry / borrow flag (C), the operation result overflow flag (O), the operation result zero flag (Z), the operation result negative flag (N), the operation result sign flag (S), etc. The program status word register is also used to save information such as interrupts and the working status of the computing device, so that the CPU can timely understand the machine operation status and program operation status.

[0037] The calculation unit 108 includes a variety of different circuit modules, which can be used to execute different instructions. For example, the integer calculation unit 1081 and the floating point calculation unit 1082 are used to perform arithmetic operations and logical operations on integers and floating point numbers, respectively.

[0038] It can be understood that the above-mentioned CPU is only a specific embodiment. In actual applications, it may have more or fewer components, which will not be described in detail here.

[0039] The DPU 12 includes multiple processing cores, which can process data in parallel. Therefore, the DPU 12 often has powerful computing capabilities. Figure 3, the DPU includes: multiple memories 121, multiple processing cores 122, and communication interfaces 123 and other hardware resources. For example, the processing core 122 may include a first processing core, a second processing core, ..., an Nth processing core, and the memory 121 includes a first memory, a second memory, ..., an Nth memory. In a possible embodiment, the computing power of the processing core 122 in the DPU12 is weaker than the computing power of the CPU11, and the storage capacity of the memory 121 in the DPU12 is weaker than the storage capacity of the memory in the CPU11. Therefore, the CPU11 is suitable for processing a small number of complex instructions, while the DPU12 is suitable for processing batches of simple instructions. The memory 121 may be a non-volatile memory. In a possible embodiment, the memory 121 includes a read-only memory ROM (Read-Only Memory) and a flash memory. In appropriate cases, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM) or a flash memory, or a combination of two or more of these. A slave operating system may be installed on the DPU, and the slave operating system is used to manage the hardware resources on the DPU. In a possible embodiment, the function of the slave operating system in the DPU12 is weaker than the main operating system in the CPU11. The DPU12 may be used to simulate the topological relationship between at least one peripheral device interconnection expansion device and at least one PCIE device. The hardware resources of the DPU are used to provide the hardware logic of the topological relationship of the PCIE device and the PCIE device. A simulator may be installed in the DPU12, and the simulator is used to provide the software logic of the topological relationship of the PCIE device and the PCIE device. The DPU12 implements the simulation of the PCIE device through negotiation and interaction between the software logic and the hardware logic.

[0040] The PCIE devices simulated in the DPU may include PCIE end devices and PCIE bridge devices. PCIE end devices can provide various functions. For example, the PCIE end device can be a network card that provides network data transmission functions, or a sound card that provides sound source processing. The PCIE bridge device is used to connect multiple PCIE end devices to form different topological relationships. Specifically, the PCIE bridge device includes multiple end device slots, and each end device slot is used to mount a peripheral device interconnection expansion end device. The topological relationship of the PCIE device may include one or more of a star relationship, a tree relationship, a ring relationship, a bus relationship, etc. Figure 1Taking the topological relationship of the PCIE devices as an example, the PCIE bridge device serves as the root node of the tree, and multiple PCIE end devices are respectively connected to the root node PCIE bridge device.

[0041] The processor may be a processor of various architectures including a first architecture processor and a second architecture processor. The first architecture processor is a processor using a complex instruction set, such as an x86 processor, and the second architecture processor is a processor using a reduced instruction set, such as an ARM processor. Alternatively, the first architecture processor is a processor whose interface uses a unified extensible firmware interface (UEFI), and the second architecture processor is a processor whose interface uses a legacy basic input and output system (LEGACYBIOS). Alternatively, the first architecture processor is a processor whose memory uses a preboot execution environment (Preboot Execution Environment, PXE), and the second architecture processor is a processor whose memory uses a block device (Block Device, BLK). For example, the processor may be a processor that uses PXE for storage, a complex instruction set for instruction set, and UEFI for interface; the processor may be a processor that uses BLK for storage, a complex instruction set for instruction set, and UEFI for interface; the processor may be a processor that uses PXE for storage, a reduced instruction set for instruction set, and UEFI for interface; the processor may be a processor that uses BLK for storage, a reduced instruction set for instruction set, and UEFI for interface; the processor may be a processor that uses PXE for storage, a complex instruction set for instruction set, and LEGACY for interface; the processor may be a processor that uses BLK for storage, a complex instruction set for instruction set, and LEGACY for interface; the processor may be a processor that uses PXE for storage, a reduced instruction set for instruction set, and LEGACY for interface; the processor may be a processor that uses BLK for storage, a reduced instruction set for instruction set, and LEGACY for interface. The processor may also be a processor with a new architecture developed later.

[0042] like Figure 4As shown, the non-volatile memory can store multiple option read-only memory images. Among them, the option read-only memory image is a special type of read-only memory (ROM) used to store firmware or boot code in computer hardware. When the computer starts, the option read-only memory image can contain a boot program to help the system identify and initialize the storage device, thereby guiding the operating system in the corresponding operating system block device to run. Different types of processors correspond to different option read-only memory images. Among them, the first architecture processor corresponds to the first option read-only memory image, and the second architecture processor corresponds to the second option read-only memory image. For example, the processor that uses PXE for storage, complex instruction set for instruction set, and UEFI for interface corresponds to the PXE-x86-UEFI option read-only memory image; the processor that uses BLK for storage, complex instruction set for instruction set, and UEFI for interface corresponds to the BLK-x86-UEFI option read-only memory image; the processor that uses PXE for storage, reduced instruction set for instruction set, and UEFI for interface corresponds to the PXE-ARM-UEFI option read-only memory image; the processor that uses BLK for storage, reduced instruction set for instruction set, and UEFI for interface corresponds to the BLK-ARM-UEFI option read-only memory image; the processor that uses PXE for storage XE, the processor with complex instruction set and LEGACY interface corresponds to the PXE-x86-LEGACY option read-only memory mirror; the memory uses BLK, the instruction set uses complex instruction set, and the processor with LEGACY interface corresponds to the BLK-x86-LEGACY option read-only memory mirror; the memory uses PXE, the instruction set uses reduced instruction set, and the processor with LEGACY interface corresponds to the PXE-ARM-LEGACY option read-only memory mirror; the memory uses BLK, the instruction set uses reduced instruction set, and the processor with LEGACY interface corresponds to the BLK-ARM-LEGACY option read-only memory mirror.

[0043] The PCIE end device may include multiple storage devices. Among them, the multiple storage devices are respectively connected to multiple operating system block devices, and an operating system is mounted in each operating system block device. For example, the PCIE end device may include a first storage device, a second storage device, and a third storage device, etc. Among them, the first storage device is connected to the first operating system block device, and the first operating system block device is mounted with the first operating system, and the second storage device is connected to the second operating system block device, and the second operating system block device is mounted with the second operating system. Different processors correspond to different operating systems. The first architecture processor corresponds to the first operating system, and the second architecture processor corresponds to the second operating system. Specifically, the memory adopts PXE, the instruction set adopts a complex instruction set, and the processor with UEFI interface corresponds to the PXE-x86-UEFI operating system; the memory adopts BLK, the instruction set adopts a complex instruction set, and the processor with UEFI interface corresponds to the BLK-x86-UEFI operating system; the memory adopts PXE, the instruction set adopts a reduced instruction set, and the processor with UEFI interface corresponds to the PXE-ARM-UEFI operating system; the memory adopts BLK, the instruction set adopts a reduced instruction set, and the processor with UEFI interface corresponds to the BLK-ARM-UEFI operating system; the memory adopts P XE, the processor with a complex instruction set and a LEGACY interface corresponds to the PXE-x86-LEGACY operating system; the processor with BLK as the memory, a complex instruction set and a LEGACY interface corresponds to the BLK-x86-LEGACY operating system; the processor with PXE as the memory, a reduced instruction set and a LEGACY interface corresponds to the PXE-ARM-LEGACY operating system; the processor with BLK as the memory, a reduced instruction set and a LEGACY interface corresponds to the BLK-ARM-LEGACY operating system.

[0044] It is understandable that the type and quantity of the optional read-only memory images stored in the non-volatile memory can be set as needed, and the type and data of the operating system in the storage device can also be set as needed, which is not specifically limited here.

[0045] In the case where the processor is a first-architecture processor, when the bare metal host is powered on, a PCI scanning action of the basic input and output system is performed. When the processor scans the upstream port of the PCIE bridge device, the processor selects a first-option read-only memory image corresponding to the first-architecture processor from multiple option read-only memory images of the non-volatile memory, loads the first-option read-only memory image into the memory of the processor, executes the storage device driver in the first-option read-only memory image, matches the corresponding first operating system block device according to the first-option read-only memory image, reads the data of the first operating system from the first operating system block device, and thus mounts the first operating system in the first operating system block device.

[0046] In the case where the first architecture processor is replaced with the second architecture processor, if the non-volatile memory stores a second option read-only memory image corresponding to the second architecture processor, and the storage device stores a second operating system corresponding to the second architecture processor, the bare metal host can be restarted. After the bare metal host is powered on again, when the second architecture processor scans the upstream port of the PCIE bridge device, the second option read-only memory image corresponding to the second architecture processor in the non-volatile memory is loaded into the memory of the processor, the corresponding second operating system block device is matched according to the second option read-only memory image, and the second operating system in the second operating system block device is mounted.

[0047] In the case where the first architecture processor is replaced with the third architecture processor, if the third option read-only memory image corresponding to the third architecture processor is not stored in the non-volatile memory, and the third operating system corresponding to the third architecture processor is not stored in the storage device, the processor adds the third option read-only memory image to the non-volatile memory of the data processor through the remote procedure call method, and mounts the third operating system to the third operating system block device, and then restarts the bare metal host. After the bare metal host is powered on again, when the third architecture processor scans the upstream port of the PCIE bridge device, it loads the third option read-only memory image corresponding to the third architecture processor in the non-volatile memory into the memory of the processor, matches the corresponding third operating system block device according to the third option read-only memory image, and mounts the third operating system in the third operating system block device.

[0048] Of course, if the first architecture processor is eliminated, the first option read-only memory image can be deleted from the non-volatile memory of the data processor through the remote procedure call method, and the first operating system can be uninstalled from the first operating system block device.

[0049] In the above scheme, multiple option read-only memory images can be loaded into the non-volatile memory through external input as needed. When the processor is a first architecture processor, when the processor scans the upstream port of the PCIE bridge device, the first option read-only memory image corresponding to the first architecture processor is selected from multiple option read-only memory images, and the first option read-only memory image is loaded to the upstream port of the peripheral device interconnection expansion bridge device, so that all storage devices connected to this port can be initialized and managed without being restricted by the type and model of the storage device. Then, the corresponding first operating system block device is matched according to the first option read-only memory image, and the first operating system in the first operating system block device is mounted, so that the processor can initialize and access the required option read-only memory image startup configuration faster, without the need to load each storage device separately. Multiple option read-only memory images can be stored in the non-volatile memory, and multiple operating systems can also be mounted in multiple storage devices. Therefore, even if the bare metal server includes multiple types of processors, batch loading can be adopted. It is only necessary to select the corresponding option read-only memory image to start the corresponding operating system.

[0050] See also Figure 5 , Figure 5 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410 , a communication interface 420 and a storage unit 430 .

[0051] The processing unit 410, the communication interface 420 and the storage unit 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, which is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processing unit 410 can also be used to implement some or all of the operation steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiment, such as the processing unit 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in the embodiment of the present application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-mentioned device embodiment, and the communication interface 420 can be specifically used for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be specifically used for the processing functions necessary to implement the functions of these devices and components, etc.

[0052] Figure 5The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may provide processing capabilities in a coordinated manner in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 5 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0053] The processing unit 410 may have a variety of specific implementation forms. For example, the processing unit 410 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processing unit 410 may also be a single-core processor or a multi-core processor. The processing unit 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processing unit 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0054] The storage unit 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The storage unit 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The storage unit 430 may also be used to store program codes and data, so that the processing unit 410 can call the program codes stored in the storage unit 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 5 Show more or fewer components, or have different component configurations.

[0055] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0056] The present application also provides a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0057] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one network site, computer, server or data center to another network site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or it can be a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD, etc.), or a semiconductor medium (e.g., a solid-state hard disk), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A data processor startup system, characterized in that: include: A data processor is used to provide a peripheral device interconnection expansion device and a hardware logic of a topological relationship of the peripheral device interconnection expansion device. The data processor is also provided with a simulator. The simulator is used to provide a peripheral device interconnection expansion device and a software logic of a topological relationship of the peripheral device interconnection expansion device, and negotiate and interact with the hardware logic to realize the simulation of the peripheral device interconnection expansion device. The data processor also includes a non-volatile memory. The peripheral device interconnection expansion device includes a peripheral device interconnection expansion bridge device and a peripheral device interconnection expansion terminal device, wherein the peripheral device interconnection expansion bridge device is used to connect the peripheral device interconnection expansion terminal device; the peripheral device interconnection expansion terminal device includes multiple storage devices, the multiple storage devices are respectively connected to multiple operating system block devices, the operating system block device is mounted with an operating system, the non-volatile memory includes one or more optional read-only memory images, and the optional read-only memory images are used to guide the operation of the operating system in the corresponding operating system block device; A processor, for, when the processor is a first-architecture processor, scanning an upstream port of the peripheral device interconnect expansion bridge device, loading a first-option read-only memory image corresponding to the first-architecture processor in the non-volatile memory into a memory of the processor, matching a corresponding first operating system block device according to the first-option read-only memory image, and mounting a first operating system in the first operating system block device.

2. The system according to claim 1, characterized in that The processor is further configured to execute a storage device driver in the first option read-only memory image, read data of the first operating system from the first operating system block device, and thus mount the first operating system in the first operating system block device.

3. The system according to claim 1, characterized in that When the first architecture processor is replaced with a second architecture processor, When the second architecture processor scans the upstream port of the peripheral device interconnect expansion bridge device, the second option read-only memory image corresponding to the second architecture processor in the non-volatile memory is loaded into the memory of the processor, the corresponding second operating system block device is matched according to the second option read-only memory image, and the second operating system in the second operating system block device is mounted.

4. The system according to claim 3, characterized in that The first architecture processor is a processor using a complex instruction set, and the second architecture processor is a processor using a reduced instruction set, or, the first architecture processor is a processor using a unified extensible firmware interface, and the second architecture processor is a processor using a traditional basic input and output system, or, the first architecture processor is a processor using a pre-boot execution environment, and the second architecture processor is a processor using a block device.

5. The system according to claim 4, characterized in that The processor is further configured to delete the first option read-only memory image from the non-volatile memory of the data processor through a remote procedure call method.

6. The system according to any one of claims 1 to 4, characterized in that: The processor is further configured to add a third option read-only memory image to the non-volatile memory of the data processor by using a remote procedure call method.

7. The system according to any one of claims 1 to 5, characterized in that: The processor is also used to select a first option read-only memory image from multiple option read-only memory images of the non-volatile memory when scanning the upstream port of the peripheral device interconnect expansion bridge device, and load the first option read-only memory image into the memory of the processor.

8. The system according to any one of claims 1 to 5, characterized in that: The processor is further configured to load the first option read-only memory image onto an upstream port of the peripheral device interconnect expansion bridge device.

9. A computing device, characterized in that It comprises a data processor startup system and a memory, the data processor startup system and the memory can communicate with each other, and the data processor startup system is a system as claimed in any one of claims 1 to 8.

10. A computing device cluster, characterized in that: It comprises a plurality of computing devices, at least one of which comprises a data processor startup system and a memory, the data processor startup system and the memory are capable of communicating with each other, and the data processor startup system is a system as claimed in any one of claims 1 to 8.

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