A circuit logic reconstruction and process mapping method and device based on structure selection

Abstract

The present invention discloses a circuit logic reconstruction and process mapping method and device based on structure selection, wherein the method includes the steps of: reading and analyzing target design circuit information; one-to-one mapping and node collection; node priority cutting enumeration and maximum fan-out free cone calculation; candidate equivalent node calculation; creating a hybrid structure selection network; performing logic reconstruction or process mapping. The present invention utilizes the relevant advantages and characteristics of structure selection, effectively combines the structural advantages of multiple logic representations and realizes the combination of multiple logic optimization strategies and process mapping, so as to improve the structural deviation problem in the logic synthesis stage and improve the result quality of logic reconstruction and process mapping. The present invention realizes the effective combination of logic optimization and process mapping, has excellent performance, and has obvious improvements in logic optimization and mapping results. It shows good experimental results, provides a new research idea for logic reconstruction and process mapping in logic synthesis, and has strong engineering practice significance and application value.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design automation, and in particular to a circuit logic reconstruction and process mapping method and device based on structure selection. Background Art

[0002] With the rapid development of integrated circuits, chip design cannot be separated from the support of Electronic Design Automation (EDA) tools. EDA refers to the design method that uses computer-aided design software to complete the functional design, logic synthesis, verification, physical design and other processes of the chip. Logic synthesis is a key step in the EDA workflow. It is the process of converting the circuit design using hardware description language to the circuit netlist at the logic gate level after optimizing the Boolean function under the process library input and design constraints. Among them, logic reconstruction and process mapping are the core parts of logic synthesis.

[0003] Logic reconstruction and process mapping are usually based on the methods of graph mapping and process-related mapping to perform process-independent logic optimization and process-related mapping on the target design, respectively. In the logic synthesis stage, logic optimization and process mapping are usually two separate stages. First, the process-independent logic representation is usually optimized with different optimization targets to obtain the optimized directed acyclic graph, and then the optimized directed acyclic graph is process mapped to obtain the mapping netlist. However, logic optimization is mostly based on the gain of local greedy computing nodes or levels to achieve logic optimization. The lack of guidance from process information leads to the fact that the effect of logic optimization cannot be directly reflected in the process mapping result, which is the structural deviation problem. This usually leads to resource waste caused by redundant logic optimization, and even misses the optimal mapping structure, resulting in poor mapping results. The structural deviation problem directly affects the effect of logic reconstruction and the quality of the mapping netlist, which in turn has a serious impact on the subsequent steps of EDA work. Therefore, the structural deviation problem caused by logic reconstruction and process mapping needs to be further studied and solved. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a circuit logic reconstruction and process mapping method and device based on structure selection in view of the shortcomings of the prior art, which utilizes the relevant advantages and characteristics of structure selection, effectively combines the structural advantages of multiple logic representations and realizes the combination of multiple logic optimization strategies and process mapping, so as to improve the structural deviation problem in the logic synthesis stage and improve the quality of the results of logic reconstruction and process mapping.

[0005] The technical solution adopted by the present invention to solve the above technical problem is: a circuit logic reconstruction and process mapping method based on structure selection, comprising the following steps:

[0006] Step 1: Read and analyze the target design circuit information:

[0007] Read and analyze the target design circuit information and obtain a directed acyclic graph representing the target design circuit, wherein the directed acyclic graph stores the logical function of the target design circuit;

[0008] Step 2: One-to-one mapping and node collection:

[0009] The directed acyclic Figure 1 For a directed acyclic graph mapped to different logical representations, determine the critical path nodes in the mapped directed acyclic graph and save them in a critical path node set, the nodes in the mapped directed acyclic graph other than the critical path nodes are non-critical path nodes, and the critical path nodes and the non-critical path nodes are the original nodes in the mapped directed acyclic graph;

[0010] Step 3: Node priority cutting enumeration and maximum fan-out free cone calculation:

[0011] Traverse all nodes in the mapped directed acyclic graph, perform priority cutting enumeration on the nodes, and save the cutting information of the nodes; traverse the non-critical path nodes in the mapped directed acyclic graph, calculate the maximum fan-out free cone of the nodes, and save the maximum fan-out free cone information of the nodes;

[0012] Step 4: Calculation of candidate equivalent nodes:

[0013] Step 4.1, traverse all nodes and their cuts in the critical path node set, perform hierarchical logic rewrite optimization on the node cuts, obtain a candidate structure with hierarchical advantages that is equivalent to the original node in logical function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node;

[0014] Step 4.2, traverse the non-critical path nodes and their cuts in the mapped directed acyclic graph, perform area-oriented logic rewrite optimization on the node cuts, obtain a candidate structure with area advantage that is equivalent to the original node in logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; traverse the maximum fan-out free cone of the non-critical path nodes in the mapped directed acyclic graph, perform area-oriented logic rewrite optimization on the maximum fan-out free cone of the node, obtain a candidate structure with area advantage that is equivalent to the original node in logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node;

[0015] Step 5: Create a hybrid structure selection network:

[0016] Based on the original node and its corresponding candidate equivalent node information, a hybrid structure selection network is created, where the hybrid structure selection network is a heterogeneous directed acyclic graph that stores the logic function of the target design circuit and stores the candidate structures as different logic representations;

[0017] Step 6: Perform logic reconstruction or process mapping:

[0018] For the hybrid structure selection network, a logic reconstruction optimization based on graph mapping is performed to obtain an optimized directed acyclic graph, or a process mapping is performed to obtain a mapped netlist, wherein the optimized directed acyclic graph is a directed acyclic graph obtained after remapping the hybrid structure selection network, which is equivalent to the original node logical function and has an optimized number of nodes or levels, and the mapped netlist is a process gate-level netlist obtained by mapping the hybrid structure selection network based on process library information.

[0019] Preferably, the specific process of step 1 is: reading an aig file or a register transfer level Verilog file containing target design circuit information, and obtaining a directed acyclic graph that stores the logical functions of the target design circuit, wherein the directed acyclic graph contains the node type, node connection relationship, and input information and output information of the target design circuit.

[0020] Preferably, the specific process of step 2 is as follows: traverse all nodes in the directed acyclic graph obtained in step 1, create corresponding nodes for all nodes in different logical representations in a one-to-one mapping manner, generate a new directed acyclic graph after mapping, and the mapped directed acyclic graph retains the logical functions and structural characteristics of the directed acyclic graph before mapping; traverse the main output nodes of the mapped directed acyclic graph, and mark the main output nodes whose node levels are greater than the set level range; perform depth-first traversal based on the marked main output nodes until the main input node of the mapped directed acyclic graph, and save all nodes accessed by the depth-first traversal as key path nodes in a hash table, so as to obtain a set of key path nodes.

[0021] Preferably, the specific process of step 4.1 is as follows: traverse all nodes and their cuts in the critical path node set, obtain the truth table corresponding to the cut of the node, match the truth table corresponding to the cut of the node with the optimal logic expression library of accurate comprehensive calculation, perform hierarchical logic rewrite optimization, obtain the optimized circuit structure for the successfully matched cut, use the optimized circuit structure as a candidate structure with hierarchical advantages that is equivalent to the original node logical function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node;

[0022] The specific process of step 4.2 is as follows: traverse the non-critical path nodes and their cuts in the mapped directed acyclic graph, obtain the truth table corresponding to the cut of the node, match the truth table corresponding to the cut of the node with the optimal logic expression library of the precise comprehensive calculation, perform area-oriented logic rewrite optimization, obtain the optimized circuit structure for the successfully matched cut, use the optimized circuit structure as a candidate structure with area advantage that is equivalent to the original node logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; traverse the maximum fan-out free cone of the non-critical path nodes in the mapped directed acyclic graph, calculate the truth table of the maximum fan-out free cone of the node, perform area-oriented logic rewrite optimization on the maximum fan-out free cone based on the truth table of the maximum fan-out free cone and the input signal of the maximum fan-out free cone, obtain the candidate structure with area advantage that is equivalent to the original node logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node.

[0023] Preferably, the optimal logical expression library is a pre-calculated area or level optimal negation, permutation, and negation equivalence classification database, that is, an NPN equivalence classification database, wherein N, P, and N represent the complement operation on the input, the permutation operation on the input, and the complement operation on the output, respectively.

[0024] Preferably, the area-oriented logic rewrite optimization performed on the maximum fan-out free cone adopts a comprehensive optimization strategy based on the sum of products and disjoint support decomposition optimization method.

[0025] Preferably, the specific process of step 5 is as follows:

[0026] Step 5.1, traverse the input nodes of the directed acyclic graph obtained in step 4, and create corresponding input nodes in the hybrid structure selection network;

[0027] Step 5.2, traverse the original nodes and create representative nodes in the hybrid structure selection network;

[0028] Step 5.3, based on the candidate equivalent nodes corresponding to the original nodes, create a selection node in the hybrid structure selection network, and create an equivalence relationship between the representative node and the selection node;

[0029] Step 5.4, traverse the output nodes of the directed acyclic graph obtained in step 4, create corresponding output nodes in the hybrid structure selection network, and finally obtain the hybrid structure selection network.

[0030] Preferably, the specific process of step 6 is:

[0031] Step 6.1, traverse all nodes in the hybrid structure selection network, perform priority cutting enumeration on the nodes, identify representative nodes and selection nodes, and obtain the cutting set of the selection nodes and the cutting set of the representative nodes;

[0032] Step 6.2: Insert the cut of the selected node into the cut set of the representative node. The process is:

[0033] Traverse the nodes of the hybrid structure selection network and determine whether the node is a representative node. If the node is not a representative node, skip the node; if the node is a representative node, obtain the cut set of the selection node corresponding to the representative node, traverse the cut set of the corresponding selection node, determine whether the phases of the representative node and the selection node are the same, if the phases are the same, insert the cut of the selection node into the cut set of the representative node; if the phases are different, invert the phase of the cut of the selection node and insert it into the cut set of the representative node;

[0034] Step 6.3: Perform logic reconstruction optimization based on graph mapping to obtain an optimized directed acyclic graph, or perform process mapping to obtain a mapped netlist, where:

[0035] The process of obtaining the optimized directed acyclic graph is as follows: performing logic reconstruction optimization based on graph mapping based on the hybrid structure selection network, that is, sorting the cut set representing the nodes according to the graph mapping conditions and selecting the cut with the lowest cost for graph mapping, and finally outputting the optimized directed acyclic graph;

[0036] The process of obtaining the mapped netlist is as follows: selecting a network based on a hybrid structure to perform process mapping, that is, sorting the cut set representing the nodes according to the process information and selecting the cut with the lowest cost for Boolean matching and mapping, and finally outputting the process gate-level netlist.

[0037] A circuit logic reconstruction and process mapping device based on structure selection for implementing the above method comprises:

[0038] An input reading module is used to read and parse the target design circuit information and obtain a directed acyclic graph representing the target design circuit;

[0039] Mapping and node collection module for converting a directed acyclic loop representing the target design circuit Figure 1 For a directed acyclic graph mapped to different logical representations, determining the key path nodes in the mapped directed acyclic graph and saving them to the key path node set;

[0040] A candidate equivalent information processing module is used to perform logical optimization on the candidate structure and save it as a candidate equivalent node;

[0041] A hybrid structure selection network creation module is used to create a hybrid structure selection network based on the original node and candidate equivalent node information;

[0042] A logic reconstruction module or a process mapping module, wherein the logic reconstruction module is used to perform logic reconstruction optimization on the hybrid structure selection network to obtain an optimized directed acyclic graph, and the process mapping module is used to perform process mapping on the hybrid structure selection network to obtain a mapped process gate-level netlist.

[0043] Compared with the prior art, the present invention has the following advantages:

[0044] (1) The circuit logic reconstruction and process mapping method based on structure selection proposed in the present invention is a universal logic reconstruction and process mapping method in the logic synthesis stage, which can support multiple logic representation forms, such as AND-Inverter graph (AIG), majority logic graph (MIG), XOR-AND graph (XAG), XOR-Majority graph (XMG), etc.

[0045] (2) The hybrid structure selection network proposed in the present invention supports the simultaneous evaluation of multiple logical representations and uses the characteristics of structure selection to realize the combination of multiple logical representations. For example, the hybrid structure selection network obtained by combining AIG and MIG fully utilizes the expression advantages of multiple logical representations.

[0046] (3) The hybrid structure selection network proposed by the method of the present invention can be widely used in a variety of mapping algorithms and optimization algorithms, such as logic reconstruction based on graph mapping, application specific integrated circuit (ASIC) process mapping algorithm, field programmable gate array (FPGA) process mapping algorithm, etc., and has wide scalability and strong practical significance;

[0047] (4) Compared with the traditional method for creating a structure selection network, the present invention has significant innovation. Compared with the traditional method for creating a structure selection network, the present invention avoids calling the SAT solver to find equivalent nodes. The present invention adopts a comprehensive strategy with different objectives to optimize the node cutting and maximum fan-out free cone, and saves the optimized candidate structure and uses it to create a hybrid structure selection network. Finally, the optimal candidate structure is calculated through specific mapping information, which effectively solves the problem of result deviation, significantly improves the logic optimization effect, and improves the quality of process mapping.

[0048] (5) Compared with the traditional logic reconstruction optimization method and process mapping method, the method of the present invention realizes the effective combination of logic optimization and process mapping. The method of the present invention has excellent performance and has obvious improvements in logic optimization and mapping results. In terms of circuit logic reconstruction optimization, the test results based on EPFL benchmarks show that the method of the present invention can optimize the network area by about 2% and optimize the network level by about 67%; in terms of ASIC process mapping, the test results based on the sky130_fd_sc_hd__tt_025C_1v80.genlib process library show that compared with the process mapping algorithm in Mockturtle (https: / / github.com / lsils / mockturtle.git), the mapping area of ​​the method of the present invention can be reduced by 4% and the delay can be reduced by 15.4%; therefore, the present invention provides a new research idea for logic reconstruction and process mapping in logic synthesis, and at the same time shows good experimental results, which has strong engineering practice significance and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of a directed acyclic graph is obtained by reading the circuit information of the analytical target and mapping it one-to-one;

[0050] Figure 2 A schematic diagram of obtaining candidate equivalent nodes after collecting nodes of the AIG obtained by one-to-one mapping;

[0051] Figure 3 Schematic diagram of creating a hybrid structure selection network based on original nodes and their corresponding candidate equivalent node information;

[0052] Figure 4 This is the main workflow of the circuit logic reconstruction and process mapping method based on structure selection in this embodiment;

[0053] Figure 5 It is a part of the procedure of the circuit logic reconstruction and process mapping method based on structure selection of this embodiment;

[0054] Figure 1~Figure 4 In the figure, a, b, c, d, and e represent the input of the target design circuit respectively, res represents the output of the target design circuit, the solid line represents the connection relationship of the nodes, the dotted line represents the logical negation, the blue circle represents the logical AND node (i.e., AND node), the green square represents the logical OR node (i.e., OR node), and the orange oval represents the majority voter with three inputs (i.e., MAJ node). DETAILED DESCRIPTION

[0055] The present invention is further described in detail below with reference to the accompanying drawings.

[0056] Example: For Figure 1The target design circuit shown in is subjected to circuit logic reconstruction and process mapping by the method of the present invention, and the steps are as follows:

[0057] Step 1: Read and analyze the target design circuit information:

[0058] Figure 1 The target design circuit shown in is represented by a register transfer level Verilog file containing the target design circuit information. The Verilog file is read and parsed to obtain a directed acyclic graph (AIG) storing the logical functions of the target design circuit. The AIG contains the node type, node connection relationship, and input and output information of the target design circuit.

[0059] Step 2: One-to-one mapping and node collection:

[0060] Traverse all nodes in the AIG obtained in step 1, create corresponding nodes for all nodes in different logical representations, and generate a new directed acyclic graph, namely, MIG, after mapping. Figure 1 As shown, the MIG retains the logical functions and structural characteristics of the AIG before mapping; traverses the main output nodes of the MIG, and marks the main output nodes whose node levels are greater than the set level range; performs depth-first traversal based on the marked main output nodes until the main input node of the MIG, and saves all nodes accessed by the depth-first traversal as key path nodes in the hash table, thereby obtaining a set of key path nodes.

[0061] Step 3: Node priority cutting enumeration and maximum fan-out free cone calculation:

[0062] Traverse all nodes in MIG, perform priority cutting enumeration on the nodes, and save the cutting information of the nodes; traverse non-critical path nodes in MIG, calculate the maximum fan-out free cone of the nodes, and save the maximum fan-out free cone information of the nodes.

[0063] Step 4: Calculation of candidate equivalent nodes:

[0064] Step 4.1, traverse all nodes and their cuts in the critical path node set, obtain the truth table corresponding to the node cut, match the truth table corresponding to the node cut with the optimal logic expression library of precise comprehensive calculation, perform hierarchical logic rewrite optimization, obtain the optimized circuit structure for the successfully matched cut, use the optimized circuit structure as a candidate structure with hierarchical advantages that is equivalent to the original node logical function but different in structure, and save the candidate structure in the MIG in the form of a candidate equivalent node;

[0065] Step 4.2, traverse the non-critical path nodes and their cuts in MIG, obtain the truth table corresponding to the node cut, match the truth table corresponding to the node cut with the optimal logic expression library of precise comprehensive calculation, perform area-oriented logic rewrite optimization, obtain the optimized circuit structure for the successfully matched cut, use the optimized circuit structure as a candidate structure with area advantage that is equivalent to the original node in logic function but different in structure, and save the candidate structure in the form of a candidate equivalent node in MIG; traverse the maximum fan-out free cone of the non-critical path nodes in MIG, calculate the truth table of the maximum fan-out free cone of the node, perform area-oriented logic rewrite optimization on the maximum fan-out free cone based on the truth table of the maximum fan-out free cone and the input signal of the maximum fan-out free cone, obtain the candidate structure with area advantage that is equivalent to the original node in logic function but different in structure, and save the candidate structure in the form of a candidate equivalent node in MIG.

[0066] In step 4, the optimal logic expression library is a pre-calculated area or level optimal negation, permutation, and negation equivalence classification database, that is, an NPN equivalence classification database, where N, P, and N represent the complement operation on the input, the permutation operation on the input, and the complement operation on the output, respectively; the area-oriented logic rewrite optimization performed on the maximum fan-out free cone adopts a comprehensive optimization strategy based on the sum of products and disjoint support decomposition optimization method.

[0067] Figure 2 A schematic diagram of obtaining candidate equivalent nodes after collecting nodes of the AIG obtained by one-to-one mapping.

[0068] Step 5: Create a hybrid structure selection network:

[0069] Step 5.1, traverse the input nodes of the directed acyclic graph obtained in step 4, and create corresponding input nodes in the hybrid structure selection network;

[0070] Step 5.2, traverse the original nodes and create representative nodes in the hybrid structure selection network;

[0071] Step 5.3, based on the candidate equivalent nodes corresponding to the original nodes, create a selection node in the hybrid structure selection network, and create an equivalence relationship between the representative node and the selection node;

[0072] Step 5.4, traverse the output nodes of the directed acyclic graph obtained in step 4, create corresponding output nodes in the hybrid structure selection network, and finally obtain the hybrid structure selection network, which is a heterogeneous directed acyclic graph that saves the logical function of the target design circuit and simultaneously saves the candidate structures as different logical representations.

[0073] Step 6: Perform logic reconstruction or process mapping:

[0074] Step 6.1, traverse all nodes in the hybrid structure selection network, perform priority cutting enumeration on the nodes, identify representative nodes and selection nodes, and obtain the cutting set of the selection nodes and the cutting set of the representative nodes;

[0075] Step 6.2: Insert the cut of the selected node into the cut set of the representative node. The process is:

[0076] Traverse the nodes of the hybrid structure selection network and determine whether the node is a representative node. If the node is not a representative node, skip the node; if the node is a representative node, obtain the cut set of the selection node corresponding to the representative node, traverse the cut set of the corresponding selection node, determine whether the phases of the representative node and the selection node are the same, if the phases are the same, insert the cut of the selection node into the cut set of the representative node; if the phases are different, invert the phase of the cut of the selection node and insert it into the cut set of the representative node;

[0077] Step 6.3: Perform logic reconstruction optimization based on graph mapping to obtain an optimized directed acyclic graph, or perform process mapping to obtain a mapped netlist, where:

[0078] The process of obtaining the optimized directed acyclic graph is as follows: performing logic reconstruction optimization based on graph mapping based on the hybrid structure selection network, that is, sorting the cut set representing the nodes according to the graph mapping conditions and selecting the cut with the lowest cost for graph mapping, and finally outputting the optimized directed acyclic graph;

[0079] The process of obtaining the mapped netlist is as follows: selecting a network based on a hybrid structure to perform process mapping, that is, sorting the cut set representing the nodes according to the process information and selecting the cut with the lowest cost for Boolean matching and mapping, and finally outputting the process gate-level netlist.

[0080] In the above steps 3 and 6, the priority cutting enumeration adopts the existing technology, that is, it is implemented based on the existing priority cutting enumeration algorithm open sourced in the known Mockturtle (https: / / github.com / lsils / mockturtle).

[0081] Figure 3 The schematic diagram of creating a hybrid structure selection network based on the original node and its corresponding candidate equivalent node information. The original node is the MIG obtained by one-to-one mapping of AIG, and the candidate equivalent node information is the newly created candidate MIG after optimization. The hybrid structure selection network can effectively combine the structural characteristics of different logical representations. It saves the original node as a representative node, the candidate structure as a selection node and establishes an equivalent relationship. It achieves the structural advantages of other logical representations while retaining the advantages of the original directed acyclic graph structure. Finally, the mapping-related information is used to guide the mapper to select the best structure.

[0082] The method of the above embodiment can be implemented by a circuit logic reconstruction and process mapping device based on structure selection, the device comprising: an input reading module for reading and parsing target design circuit information and obtaining a directed acyclic graph representing the target design circuit; a mapping and node collection module for converting the directed acyclic graph representing the target design circuit into a node-based circuit logic reconstruction and process mapping device; Figure 1 For a directed acyclic graph mapped to different logical representations, the critical path nodes in the mapped directed acyclic graph are determined and saved in a critical path node set; a candidate equivalent information processing module is used to perform logical optimization on the candidate structure and save it as a candidate equivalent node; a hybrid structure selection network creation module is used to create a hybrid structure selection network based on the original node and candidate equivalent node information; a logic reconstruction module or a process mapping module, wherein the logic reconstruction module is used to perform logic reconstruction optimization on the hybrid structure selection network to obtain an optimized directed acyclic graph, and the process mapping module is used to perform process mapping on the hybrid structure selection network to obtain a mapped process gate-level netlist.

[0083] Figure 4 This is the main workflow of the circuit logic reconstruction and process mapping method based on structure selection in this embodiment. The hybrid structure selection network stores a variety of candidate structures for subsequent logic reconstruction and process mapping operations. These candidate structures are candidates that are different from the structure of the original directed acyclic graph but have equivalent logical functions; that is, Figure 4 The hybrid structure selection network shown is equivalent to the original structure, candidate structure 1 and candidate structure 2, which are logically equivalent to each other; the logic reconstruction or process mapping operation is based on the cutting and cost function calculation to calculate the best structure from the three structures for matching, and obtain the optimized directed acyclic graph or the mapped process gate-level netlist. The relevant cost of the cost function calculation is based on the cost function calculation in the known open source logic reconstruction and process mapping algorithm in Mockturtle (https: / / github.com / lsils / mockturtle). Figure 4 In the mapped process gate-level netlist shown, O21BAI_1 represents the NAND or OR unit in the process library, NAND2_1 represents the two-input NAND unit in the process library, NOR2_1 represents the two-input NOR unit in the process library, and INV represents the inverter unit in the process library, wherein the process library adopts the sky130_fd_sc_hd__tt_025C_1v80.genlib process library.

[0084] Figure 5This is a partial program of the circuit logic reconstruction and process mapping method based on structure selection of this embodiment. Circuit logic reconstruction based on structure selection requires input of the target design circuit, and execution of relevant program instructions to iteratively optimize the input circuit to achieve optimization of the logic level and number of nodes. Process mapping based on structure selection requires input of the target design circuit and relevant process library, and execution of relevant program instructions to process map the input circuit, obtain mapping information and output the mapped process gate-level netlist.

[0085] The circuit logic reconstruction and process mapping method based on structural selection proposed in the present invention has obvious advantages and excellent performance. It has obvious improvements in logic optimization and mapping results, effectively improves the structural deviation problem of the mapper, and greatly improves the mapping quality. At the same time, the present invention has good scalability, supports multiple mainstream logic representations such as AIG, MIG, XAG and XMG, and proposes a hybrid selection network to support the combination of multiple logic representations. After experimental testing, compared with the logic reconstruction method in Mockturtle, the present invention is not easy to fall into local optimality in the logic optimization experiment, and improves the effect of logic optimization. The results of the logic optimization experiment are shown in Table 1. In the process mapping experiment, based on the sky130_fd_sc_hd__tt_025C_1v80.genlib process library test, the present invention effectively improves the structural deviation problem in process mapping and improves the result quality of process mapping. The results of the process mapping experiment are shown in Table 2.

[0086] In terms of circuit logic reconstruction optimization, the test results based on EPFL benchmarks show that the method of the present invention can optimize the network area by about 2% and optimize the network level by about 67%; in terms of ASIC process mapping, the test results based on the sky130_fd_sc_hd__tt_025C_1v80.genlib process library show that compared with the process mapping algorithm in Mockturtle, the mapping area of ​​the method of the present invention can be reduced by 4% and the latency can be reduced by 15.4%.

[0087] Table 1. Logic optimization experimental results:

[0088]

[0089] Table 2. Process mapping experimental results:

[0090]

[0091] In summary, compared with the existing methods, the result quality of the circuit logic reconstruction and process mapping method based on structure selection proposed in the present invention has been greatly improved. The present invention proposes a new hybrid structure selection network creation method, which uses candidates of multiple logic optimization algorithms to create a hybrid structure selection network to achieve the combination of logic optimization and process mapping. The candidates of logic optimization provide more candidate mapping structures for the mapper, and the process mapping provides process information guidance for the selection of logic optimization and uses the mapper to calculate the optimal structure for mapping, which effectively improves the structural deviation problem in the mapping. In addition, the present invention also has the characteristics of strong expansibility and can support multiple logic representations. The present invention provides a new research idea for logic reconstruction and process mapping in logic synthesis, and at the same time shows good experimental results, which has strong engineering practice significance and application value.

Claims

1. A circuit logic reconstruction and process mapping method based on structure selection, characterized in that: The following steps are involved: Step 1: Read and analyze the target design circuit information: Read and analyze the target design circuit information and obtain a directed acyclic graph representing the target design circuit, wherein the directed acyclic graph stores the logical function of the target design circuit; Step 2: One-to-one mapping and node collection: Map the directed acyclic graph obtained in step 1 to directed acyclic graphs of different logical representations one-to-one, determine the critical path nodes in the mapped directed acyclic graph and save them to the critical path node set, and the nodes other than the critical path nodes in the mapped directed acyclic graph are non-critical path nodes, and the critical path nodes and non-critical path nodes are the original nodes in the mapped directed acyclic graph; Step 3: Node priority cutting enumeration and maximum fan-out free cone calculation: Traverse all nodes in the mapped directed acyclic graph, perform priority cutting enumeration on the nodes, and save the cutting information of the nodes; traverse the non-critical path nodes in the mapped directed acyclic graph, calculate the maximum fan-out free cone of the nodes, and save the maximum fan-out free cone information of the nodes; Step 4: Calculation of candidate equivalent nodes: Step 4.1, traverse all nodes and their cuts in the critical path node set, perform hierarchical logic rewrite optimization on the node cuts, obtain a candidate structure with hierarchical advantages that is equivalent to the original node in logical function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; Step 4.2, traverse the non-critical path nodes and their cuts in the mapped directed acyclic graph, perform area-oriented logic rewrite optimization on the node cuts, obtain a candidate structure with area advantage that is equivalent to the original node in logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; traverse the maximum fan-out free cone of the non-critical path nodes in the mapped directed acyclic graph, perform area-oriented logic rewrite optimization on the maximum fan-out free cone of the node, obtain a candidate structure with area advantage that is equivalent to the original node in logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; Step 5: Create a hybrid structure selection network: Based on the original node and its corresponding candidate equivalent node information, a hybrid structure selection network is created, where the hybrid structure selection network is a heterogeneous directed acyclic graph that stores the logic function of the target design circuit and stores the candidate structures as different logic representations; Step 6: Perform logic reconstruction or process mapping: For the hybrid structure selection network, a logic reconstruction optimization based on graph mapping is performed to obtain an optimized directed acyclic graph, or a process mapping is performed to obtain a mapped netlist, wherein the optimized directed acyclic graph is a directed acyclic graph obtained after remapping the hybrid structure selection network, which is equivalent to the original node logical function and has an optimized number of nodes or levels, and the mapped netlist is a process gate-level netlist obtained by mapping the hybrid structure selection network based on process library information.

2. A circuit logic reconstruction and process mapping method based on structure selection according to claim 1, characterized in that: The specific process of step 1 is: reading the aig file or register transfer level Verilog file containing the target design circuit information, obtaining a directed acyclic graph that stores the logical functions of the target design circuit, and the directed acyclic graph contains the node type, node connection relationship, and input information and output information of the target design circuit.

3. The circuit logic reconstruction and process mapping method based on structure selection according to claim 1, characterized in that: The specific process of step 2 is as follows: traverse all nodes in the directed acyclic graph obtained in step 1, create corresponding nodes for all nodes in one-to-one mapping in different logical representation forms, generate a new directed acyclic graph after mapping, and the directed acyclic graph after mapping retains the logical functions and structural characteristics of the directed acyclic graph before mapping; traverse the main output nodes of the directed acyclic graph after mapping, and mark the main output nodes whose node levels are greater than the set level range; perform depth-first traversal based on the marked main output nodes until the main input node of the directed acyclic graph after mapping, and save all nodes accessed by the depth-first traversal as key path nodes in a hash table, so as to obtain a set of key path nodes.

4. The circuit logic reconstruction and process mapping method based on structure selection according to claim 1, characterized in that: The specific process of step 4.1 is as follows: traverse all nodes and their cuts in the critical path node set, obtain the truth table corresponding to the cut of the node, match the truth table corresponding to the cut of the node with the optimal logic expression library of accurate comprehensive calculation, perform hierarchical logic rewrite optimization, obtain the optimized circuit structure for the successfully matched cut, use the optimized circuit structure as a candidate structure with hierarchical advantages that is equivalent to the original node logical function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; The specific process of step 4.2 is as follows: traverse the non-critical path nodes and their cuts in the mapped directed acyclic graph, obtain the truth table corresponding to the cut of the node, match the truth table corresponding to the cut of the node with the optimal logic expression library of the precise comprehensive calculation, perform area-oriented logic rewrite optimization, obtain the optimized circuit structure for the successfully matched cut, use the optimized circuit structure as a candidate structure with area advantage that is equivalent to the original node logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node; traverse the maximum fan-out free cone of the non-critical path nodes in the mapped directed acyclic graph, calculate the truth table of the maximum fan-out free cone of the node, perform area-oriented logic rewrite optimization on the maximum fan-out free cone based on the truth table of the maximum fan-out free cone and the input signal of the maximum fan-out free cone, obtain the candidate structure with area advantage that is equivalent to the original node logic function but different in structure, and save the candidate structure in the mapped directed acyclic graph in the form of a candidate equivalent node.

5. The circuit logic reconstruction and process mapping method based on structure selection according to claim 4, characterized in that: The optimal logic expression library is a pre-calculated area or level optimal negation, permutation, and negation equivalence classification database, that is, an NPN equivalence classification database, where N, P, and N represent the complement operation on the input, the permutation operation on the input, and the complement operation on the output, respectively.

6. The circuit logic reconstruction and process mapping method based on structure selection according to claim 4, characterized in that: The area-oriented logic rewrite optimization performed on the maximum fan-out free cone adopts a comprehensive optimization strategy based on sum-of-products and disjoint support decomposition optimization methods.

7. The circuit logic reconstruction and process mapping method based on structure selection according to claim 1, characterized in that: The specific process of step 5 is as follows: Step 5.1, traverse the input nodes of the directed acyclic graph obtained in step 4, and create corresponding input nodes in the hybrid structure selection network; Step 5.2, traverse the original nodes and create representative nodes in the hybrid structure selection network; Step 5.3, based on the candidate equivalent nodes corresponding to the original nodes, create a selection node in the hybrid structure selection network, and create an equivalence relationship between the representative node and the selection node; Step 5.4, traverse the output nodes of the directed acyclic graph obtained in step 4, create corresponding output nodes in the hybrid structure selection network, and finally obtain the hybrid structure selection network.

8. The circuit logic reconstruction and process mapping method based on structure selection according to claim 7, characterized in that: The specific process of step 6 is as follows: Step 6.1, traverse all nodes in the hybrid structure selection network, perform priority cutting enumeration on the nodes, identify representative nodes and selection nodes, and obtain the cutting set of the selection nodes and the cutting set of the representative nodes; Step 6.2: Insert the cut of the selected node into the cut set of the representative node. The process is: Traverse the hybrid structure to select the nodes of the network and determine whether the node is a representative node. If the node is not a representative node, skip the node; If the node is a representative node, obtain the cut set of the selection node corresponding to the representative node, traverse the cut set of the corresponding selection node, and determine whether the phases of the representative node and the selection node are the same. If the phases are the same, insert the cut of the selection node into the cut set of the representative node; If the phases are different, the phase of the cut that selected the node is inverted and inserted into the set of cuts representing the node; Step 6.3: Perform logic reconstruction optimization based on graph mapping to obtain an optimized directed acyclic graph, or perform process mapping to obtain a mapped netlist, where: The process of obtaining the optimized directed acyclic graph is as follows: performing logic reconstruction optimization based on graph mapping based on the hybrid structure selection network, that is, sorting the cut set representing the nodes according to the graph mapping conditions and selecting the cut with the lowest cost for graph mapping, and finally outputting the optimized directed acyclic graph; The process of obtaining the mapped netlist is as follows: selecting a network based on a hybrid structure to perform process mapping, that is, sorting the cut set representing the nodes according to process information and selecting the cut with the lowest cost for Boolean matching and mapping, and finally outputting the process gate-level netlist.

9. A circuit logic reconstruction and process mapping device based on structure selection for implementing the method according to any one of claims 1 to 8, characterized in that: include: An input reading module is used to read and parse the target design circuit information and obtain a directed acyclic graph representing the target design circuit; A mapping and node collection module, for mapping a directed acyclic graph representing a target design circuit one-to-one to a directed acyclic graph of a different logical representation, determining key path nodes in the mapped directed acyclic graph and saving them to a key path node set; A candidate equivalent information processing module is used to perform logical optimization on the candidate structure and save it as a candidate equivalent node; A hybrid structure selection network creation module is used to create a hybrid structure selection network based on the original node and candidate equivalent node information; A logic reconstruction module or a process mapping module, wherein the logic reconstruction module is used to perform logic reconstruction optimization on the hybrid structure selection network to obtain an optimized directed acyclic graph, and the process mapping module is used to perform process mapping on the hybrid structure selection network to obtain a mapped process gate-level netlist.

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