Simulation method and device of chip system and related equipment

Abstract

Embodiments of the present application provide a chip system simulation method and device and related equipment, wherein the method comprises: obtaining connection data of a chip system; the connection data comprises physical connection data, which is formed based on the physical connection relationship between each chip in the chip system; performing chip system power network simulation node extraction on the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes; and simulating the chip system based on the power network structure. The technical solution provided by the embodiments of the present application can improve the reliability of the pressure drop electromigration simulation result.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer, in particular to a chip system simulation method and device and related equipment. BACKGROUND

[0002] With the increase of the design integration of chip system, the wire resistance becomes more dominant, increasing the electromigration and voltage drop problems, which play an important role in shortening the service life of electronic equipment. By performing voltage drop electromigration simulation on the chip system, the voltage drop electromigration simulation result can predict and analyze these problems, so as to take corresponding design measures to improve the circuit reliability of the chip system. Therefore, under this background, how to provide a technical solution to improve the reliability of the voltage drop electromigration simulation result has become a technical problem that the person skilled in the art needs to solve. SUMMARY

[0003] Therefore, the embodiments of the present application provide a chip system simulation method, device and related equipment to improve the reliability of the voltage drop electromigration simulation result.

[0004] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0005] In a first aspect, the embodiments of the present application provide a chip system simulation method, comprising:

[0006] obtaining connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system;

[0007] performing power network simulation node extraction on the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes;

[0008] performing voltage drop electromigration simulation on the chip system based on the power network structure.

[0009] In a second aspect, the embodiments of the present application provide a chip system simulation device, comprising:

[0010] a data acquisition module configured to obtain connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system;

[0011] a power network structure construction module configured to perform power network simulation node extraction on the physical connection data, and construct a power network structure of the chip system based on the extracted power network simulation nodes;

[0012] simulate the chip system based on the power network structure.

[0013] In a third aspect, an electronic device is provided, which includes a memory and a processor. The memory stores a program. The processor invokes the program stored in the memory to execute the simulation method of the chip system according to the first aspect.

[0014] In a fourth aspect, a storage medium is provided, which stores a program. The program, when executed, implements the simulation method of the chip system according to the first aspect.

[0015] In a fifth aspect, a computer program product is provided, which includes a computer program. The computer program, when executed by a processor, implements the simulation method of the chip system according to the first aspect.

[0016] The simulation method of the chip system provided by the embodiments of the present application includes: obtaining connection data of a chip system; the connection data includes physical connection data formed based on physical connection relationships between chips in the chip system; performing power network simulation node extraction on the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes; and performing voltage drop electromigration simulation on the chip system based on the power network structure.

[0017] It can be seen that, in the simulation method of the chip system provided by the embodiments of the present application, the connection data of the chip system includes the physical connection data formed based on the physical connection relationships between the chips in the chip system; therefore, when the power network simulation nodes are extracted based on the physical connection data, the power network simulation nodes can reflect the physical connection relationships between the chips; and then, the power network structure constructed based on the extracted power network simulation nodes can be close to the power network distribution in the real physical structure of the chip system, so that the simulation result obtained based on the power network structure can more reliably reflect the power network distribution of the chip system, facilitating adjustment of the power network distribution of the chip system and prolonging the service life of the chip system. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings.

[0019] Figure 1is a flowchart of a simulation method of a chip system provided by an embodiment of the present application;

[0020] Figure 2 is a structural diagram of a chip system formed by a plurality of chips provided by an embodiment of the present application;

[0021] Figure 3 is an implementation process diagram of a chip system simulation provided by an embodiment of the present application, in which chips are isolated from each other to build a power network structure;

[0022] Figure 4 is Figure 3 is a flowchart corresponding to the implementation process shown in the figure;

[0023] Figure 5 is another flowchart of a simulation method of a chip system provided by an embodiment of the present application;

[0024] Figure 6 is a schematic diagram of a chip and a connection structure between chips provided by an embodiment of the present application;

[0025] Figure 7 is Figure 6 is a schematic diagram of a connection structure in the structure shown in the figure;

[0026] Figure 8 is an implementation process diagram of obtaining connection data in a simulation method of a chip system provided by an embodiment of the present application;

[0027] Figure 9 is a structural diagram of a simulation device of a chip system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0029] The use of 2.5D / 3D integrated circuit packaging technology has injected new vitality into the microchip industry, especially in high-end fields such as central processing units (CPUs), graphics processing units (GPUs), and system on chips (SoCs), avoiding the diminishing returns problem caused by progress in ultra-deep submicron process nodes.

[0030] But with the continuous development of process nodes, the packaging technology of integrated circuits is also more and more complex. As an important item of chip sign kernel, the solution of joint simulation of pressure drop electromigration among multiple chips (dies) is particularly important.

[0031] The current pressure drop electromigration simulation solution can support the joint simulation of 2.5D chip system. For the connection structure: TSV (Through-Silicon Via), micro-bump (mbump) RLC (Resistance Inductance Capacitance) parameters are directly provided by the process factory and the packaging factory, wherein the connection structure is a structure used to connect the chips when the stacked level is combined according to the design requirements of the chip system.

[0032] The simulation tool (pressure drop electromigration simulation tool) separately extracts the power network nodes of each die. In the case of not being able to see the connection structure, the simulation tool connects the RLC circuit model nodes of the connection components such as mbump to the metal wires of the corresponding chip, constructs the circuit path from the solder bump at the packaging level to the power network nodes of all chips, and obtains the power network structure of the chip system. Thus, the next step of multi-chip (multi-die) joint simulation analysis can be performed. Such simulation is crucial for optimizing the power integrity (PI) and signal integrity (SI) of the chip system.

[0033] However, in the above solution, the dies in the chip system are isolated from each other, and the power network nodes of each die are independently extracted. The connection structure between the chips cannot be utilized, so that the connection nodes generated by the coupling of the connection structure cannot be considered, and the corresponding RLC circuit structure generated by the coupling cannot be considered. As a result, when the chip system performs pressure drop electromigration simulation, the power network structure cannot accurately reflect the real power network distribution of the chip system, which affects the authenticity and reliability of the pressure drop electromigration simulation result.

[0034] To solve the above problems, the embodiments of the present application provide a simulation method of a chip system to improve the reliability of the pressure drop electromigration simulation result.

[0035] Please refer to Figure 1 , Figure 1 is a flowchart of the simulation method of the chip system provided by the embodiments of the present application.

[0036] As shown in Figure 1 , the method comprises the following steps:

[0037] In step S101, connection data of the chip system is acquired; the connection data includes physical connection data, and the physical connection data is formed based on physical connection relationships among chips in the chip system.

[0038] The connection data is data reflecting the connection relationships of the chip system, and in addition to the physical connection data, can also include logical connection data. The logical connection data can refer to the electrical connection relationships among various logic gates or circuit elements in the circuit of the chip system. The logical connection data defines the path of the current, including how the current flows through various logic gates and circuit elements, and the interaction therebetween.

[0039] The physical connection data is formed based on the physical connection relationships of the chip system, and thus can reflect the physical implementation form of the chip system. That is, the physical connection relationships correspond to the physical implementation form of the chip system, and thus the physical connection relationships can refer to the combined connection relationships of the chips in the chip system. Then, the physical connection data can be regarded as data describing the three-dimensional structure of the chip system in a two-dimensional plane.

[0040] In step S102, the physical connection data is subjected to power network simulation node extraction of the chip system, and a power network structure of the chip system is constructed based on the extracted power network simulation nodes.

[0041] Since the physical connection data is formed based on the physical connection relationships, it can reflect the combined connection relationships of the chips in the chip system. Therefore, when the power network simulation node extraction is performed based on the physical connection data, each node in the complete power network structure of the chip system can be reflected, and the circuit nodes and RLC circuit parameters generated by the coupling of the connection structures between chips can also be considered, so that an accurate power network structure of the chip system is finally obtained.

[0042] In step S103, voltage drop electro-migration simulation is performed on the chip system based on the power network structure.

[0043] After the power network simulation nodes are extracted, the coupling parasitic can be considered according to the process file, the power network RLC parasitic parameter circuit of the chip system is extracted, the various power network simulation nodes are connected to the connection positions of the resistance-inductance-capacitance model formed by the power network RLC parasitic parameter circuit, and the power network structure of the chip system is formed.

[0044] The power network structure formed in the embodiment of the present application can consider the RLC circuit structure generated by the coupling of the connection structures. It is ensured that when the voltage drop electro-migration simulation is performed, the path impedance effect can be more accurately reflected, the power network distribution (such as the current distribution and direction) is more accurate, and the reliability of the voltage drop electro-migration simulation result is improved.

[0045] The simulation method of the chip system provided by the embodiments of the present application can improve the reliability of the simulation result of the electromigration under voltage drop, and the following will be described by taking a common simulation scheme of electromigration under voltage drop as a comparative example.

[0046] Please refer to Figure 2 and Figure 3 , Figure 2 is a structural schematic diagram of a chip system formed by a plurality of chips provided by the embodiments of the present application, Figure 3 is an implementation process schematic diagram of a chip system simulation by constructing a power network structure for chip isolation provided by the embodiments of the present application.

[0047] As shown in Figure 2 , the chip system formed by a plurality of dies mainly includes the following parts:

[0048] The si_interposer (silicon interposer) includes an interposer bottom die (ibotdie).

[0049] The memory die includes an instruction memory (imem).

[0050] The asic die is a generic (GENERIC) chip, including an application-specific integrated circuit (ASIC) of a specific type.

[0051] Among them, the memory die and the asic die are connected through an AP layer (Access Point, interconnection layer) -> mbump -> AP layer -> wiring layer -> TSV -> BMET layer (Bottom Metal Layer, bottom metal layer) connected with the bump -> bump (bump) structure, and the si_interposer to realize 2.5D interconnection. The memory die, the asic die and the si_interposer can be formed by different processes.

[0052] For the structure of the chip system shown in Figure 2 , when simulating the electromigration under voltage drop, the method adopted is as shown in Figure 3 :

[0053] Forming a power network node of the memory die;

[0054] Forming a power network node of the asic die;

[0055] Constructing the RLC circuit model of the connection structure.

[0056] Then, connecting the power network nodes of the memory die and the power network nodes of the asic die to the RLC model to form the power network structure of the chip system.

[0057] The process of constructing the power network structure of the chip system based on the power network nodes of each chip can refer to Figure 4 , Figure 4 The implementation process corresponding to the flowchart is shown in Figure 3 .

[0058] As shown in Figure 4 , the process includes:

[0059] 1.1, obtaining the DEF file or chip power consumption model of each chip.

[0060] The DEF (Design Exchange Format) file of the chip contains the TSV graphic position and the graphic position information of mbump and bump.

[0061] The chip power consumption model is a full-chip power ground network model with spice (simulation program with integrated circuit emphasis) precision, which simulates the entire power distribution network of the port on the chip power supply point, accurately reflects the instantaneous power consumption distribution of a chip and the entire chip RC network structure, so that the chip power consumption model as input is helpful for voltage drop electrical migration simulation analysis.

[0062] 1.2, obtaining the power ground or signal bump coordinate information.

[0063] The coordinate information of the bump can be obtained from the design file and the data manual, or it can also be obtained from the GDS (Graphic Data System) file, which is used to store and transmit IC layout information, including the position and hierarchical information of the bump.

[0064] 2, creating a virtual position alignment for multiple chips and relative coverage areas through the relative coordinates of the chips.

[0065] 3, obtaining the RLC parameter information of the mbump of the packaging and inter-chip connection components.

[0066] 4, extracting the PG nodes of each chip to form the power network nodes of each chip.

[0067] Modeling and parameter extraction of power grid nodes of each chip to obtain the power grid nodes of each chip.

[0068] 5. Connecting the PG nodes of each chip to the corresponding positions of the RLC model to form the power grid structure of the chip system.

[0069] The RLC model is a resistance-inductance-capacitance model formed by RLC parameters, and realizes the connection of the PG nodes of each chip.

[0070] 6. Voltage drop electro-migration simulation of the power grid structure of the chip system.

[0071] As can be seen in the flow shown in FIG. 5, when the complete power grid structure is created in step 5, the die-to-die isolation is performed for single-die power grid node extraction, and the nodes generated by the coupling and the RLC parameters generated by the coupling cannot be considered according to the physical structure of the chip-to-chip connection. Figure 4 In addition, the flow shown in FIG. 5 requires a fixed format process file that can be read by a simulation tool provided by each die corresponding fab (fabrication, semiconductor product manufacturing factory) and a fixed format process file that can be read by a parasitic parameter extraction tool provided by each die corresponding fab.

[0072] Figure 4 On the other hand, since the backside power supply technology involves transferring the power supply network to the backside of the chip system, it is necessary to add a metal layer to the wafer backside and to process the ability to electrically connect the device wafer backside to the nanosilicon through hole on the front side. This backside power supply technology requires a special wafer thinning process and complex physical and electrical simulation and design, which may be beyond the capability of traditional voltage drop electro-migration simulation tools, and therefore cannot support the simulation requirements of backside power supply design.

[0073] In the simulation method of the chip system provided by the embodiment of the present application, since the physical connection data in the connection data of the chip system can be formed based on the physical connection relationship between each chip in the chip system, that is, the connection data of the chip system can be the connection data of the chip system of the backside power supply design.

[0074] Therefore, even if the chip system adopts a backside power supply design, the physical connection data can be formed according to the physical connection relationship of the chip system generated by the backside power supply design, and therefore the embodiment of the present application can support the voltage drop electro-migration simulation of the chip system obtained by the backside power supply design.

[0075] Therefore, even if the chip system adopts a backside power supply design, the physical connection data can be formed according to the physical connection relationship of the chip system generated by the backside power supply design, and therefore the embodiment of the present application can support the voltage drop electro-migration simulation of the chip system obtained by the backside power supply design.

[0076] ​It can be seen that the technical scheme provided by the embodiment of the present application, when the voltage drop electromigration simulation of the chip system is performed, the connection data of the chip system comprises: physical connection data formed based on the physical connection relationship between each chip in the chip system; therefore, when the power network simulation node is extracted based on the physical connection data, the power network simulation node can reflect the node of the physical connection relationship between each chip; and the power network structure constructed based on the extracted power network simulation node can be close to the power network distribution in the real physical structure of the chip system, so that when the simulation is performed based on the power network structure, the simulation result can more reliably reflect the power network distribution of the chip system, facilitating the adjustment of the power network distribution of the chip system and prolonging the service life of the chip system.

[0077] In order to form accurate and reliable physical connection data, in an embodiment, the physical connection data can be formed with reference to the combined connection relationship of each chip in the real chip system.

[0078] Please refer to Figure 5 , Figure 5 is another flowchart of the simulation method of the chip system provided by the embodiment of the present application.

[0079] As Figure 5 indicated, the method can further comprise:

[0080] Step S200, redefining the names of each chip in the chip system and the sub-modules constituting each chip to obtain the renamed each chip and sub-module; and redefining the name of the connection structure connecting each chip to obtain the renamed connection structure.

[0081] The names of the chips and the sub-modules constituting the chips are redefined so that different chips and sub-modules have different names.

[0082] The stack hierarchy is a hierarchy formed after each chip in the chip system is arranged at the corresponding hierarchical position according to the design requirements of the chip system.

[0083] For the convenience of description of the hierarchical position of the connection structure and each chip, please refer to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of the chip and the connection structure between the chips provided by the embodiment of the present application, Figure 7 is Figure 6 a schematic diagram of the connection structure in the structure shown in

[0084] For the convenience of description, Figure 6 a hybrid bonded 3DIC stack structure design is taken as an example for display.

[0085] AsFigure 6 As shown in the figure, the structure of the chip system includes a main die at a lower layer level, a top die connected with the main die and corresponding to a top layer level, and a connection structure connecting the two chips.

[0086] The connection structure mainly refers to: TSV -> HBM layer -> HBV hole.

[0087] The HBV hole is a hole connecting the HBM layer and the metal layer of the top die, and the TSV is connected with the HBV hole through the HBM layer. The TSV is in contact with the high-layer metal side of the main die, such as Figure 7 The TSV landing layer is usually a certain thick metal layer above the RDL layer on the chip.

[0088] As shown in the figure, the bonding plane of the hybrid bonding stack structure is shown. Figure 4 As shown in the figure, the bonding plane of the hybrid bonding stack structure is shown.

[0089] The TSV is connected with the HBV through the HBM, realizing the interconnection of the upper chip and the lower chip.

[0090] In step S201, the renamed chips, sub-modules of each chip and connection structures are sorted in the vertical direction of the stacked level of the chip system, and the physical connection relationship of the chip system is formed.

[0091] The simulation input file can be Original process metal layer naming As shown in the figure, the simulation input file used in the flowchart, but since the connection data of the embodiment of the present application needs to include the physical connection data. Therefore, in order to obtain accurate physical connection data, the name of the chip and its sub-module in the simulation input file and the name of the connection structure are modified and replaced to obtain an updated simulation input file, so that the simulation input files of different chips are obviously different, which is convenient for the simulation equipment to identify, and then the updated simulation input file is obtained. Connection data including accurate physical connection data.

[0092] In the process of reestablishing the physical connection relationship, all relevant process metal layers (including metal layers in the chip and metal layers in the connection structure) and via layers can be first renamed and sorted according to the stacking level of the chip system (3D-IC). In order to facilitate the distinction of the definition of the metal layers in different dies, the name of the metal layers included in the die can be named according to the name of the die, or can be named according to the inter-chip interconnection relationship (for example, according to the stacking relationship from bottom to top). Different dies can be different processes or the same process, and finally ensure that the naming of all layer layers is not repeated.

[0093] For example, the names of each chip and its sub-modules and the connection structure are named in the manner of inter-die interconnection relationship, which can be shown in the following table:

[0094] Renaming metal1 itop_m1 HBM iconn_HBM Figure 5 M1 m1

[0095] In the above table, "itop" represents the renaming of the upper chip located at the upper hierarchical position, "iconn_HBM" represents the renaming of the HBM layer in the connection structure, and "m1" can represent the renaming of the lower chip.

[0096] Since it is only necessary to distinguish each chip and the connection structure, in the case that the renaming of the upper chip has been updated, the renaming of the lower chip can also remain unchanged, that is, still the original name.

[0097] After redefining the names of each chip and its sub-modules and the connection structure in the chip system, in the vertical direction of the stacking level of the chip system, starting from the lowest metal layer of the imain die at the bottom and going up layer by layer according to the connection structure, "iconn_TSV, iconn_HBM and iconn_HBV" represent the metal and via of the intermediate connection part, and the finally formed physical connection relationship is as follows:

[0098] itop_m1

[0099] itop_v1

[0100] itop_m2

[0101] itop_v2

[0102] itop_m3

[0103] itop_v3

[0104] itop_m4

[0105] itop_v4

[0106] itop_ap

[0107] iconn_HBV

[0108] iconn_HBM

[0109] iconn_TSV

[0110] m1

[0111] v1

[0112] m2

[0113] v2

[0114] m3

[0115] v3

[0116] m4

[0117] v4

[0118] ap.

[0119] Wherein, "itop_m1" represents the first layer of metal layer of the upper chip, "itop_v1" represents the first connection hole of the upper chip, and so on. The "i_top" indicates that it is a submodule of the upper chip, and the number indicates how many layers the upper chip has. The above-mentioned upper chip with 4 layers of metal layers is taken as an example for illustration.

[0120] Similarly, "mi (i = 1, 2, 3, 4)" represents the number of layers of the lower chip.

[0121] The above-mentioned representation takes updating the name of the upper chip and its submodule as an example, and keeps the name of the lower chip and its submodule unchanged.

[0122] The renaming of each chip and its submodule and the connection structure in the physical connection relationship is taken as the basis for subsequent updating of each simulation input file, so that each chip and the connection structure in the modified simulation input file can be distinguished, which is convenient to reflect the physical connection relationship of the chip system and facilitate the simulation tool to identify different levels of chips and connection structures.

[0123] Please continue to refer to Figure 4 , the method further comprises:

[0124] Step S202, based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the simulation input file of the chip system.

[0125] According to the foregoing Figure 6The simulation input file used in the shown flow can be seen to contain different types, and different types of simulation input files contain different information, so the update of the specific type of simulation input file can be carried out according to the specific type.

[0126] In step S203, connection data of the chip system is obtained based on the updated simulation input file.

[0127] The different levels of chips and connection structures in the updated simulation input file can be clearly distinguished, which facilitates the fine description of the physical connection relationship, so as to form accurate physical connection data.

[0128] In an embodiment, the simulation input file is a group of files containing circuit design, process parameters, device characteristics and working conditions; step S202 can include:

[0129] Based on the renaming of each chip and the sub-modules of each chip in the physical connection relationship, and the renaming of the connection structure, the first simulation input file containing the circuit design is updated to obtain the updated first simulation input file;

[0130] Based on the renaming of each chip and the sub-modules of each chip in the physical connection relationship, and the renaming of the connection structure, the second simulation input file containing the device characteristics and working conditions is updated to obtain the updated second simulation input file;

[0131] And, based on the renaming of each chip and the sub-modules of each chip in the physical connection relationship, and the renaming of the connection structure, the third simulation input file containing the process parameters is updated to obtain the updated third simulation input file.

[0132] Since the simulation input file is a group of files, when performing the voltage drop electromigration simulation of the chip system, the input files include multiple files, and this group of files contains circuit design, process parameters, device characteristics and working conditions, so that each file provides necessary data for the simulation tool to predict and analyze the voltage drop and electromigration problem of the power network structure of the chip system under actual working conditions.

[0133] Step S203 can include:

[0134] Based on the updated first simulation input file, the updated second simulation input file and the updated third simulation input file, the connection data of the chip system is obtained.

[0135] The updated simulation input files can reflect each chip in the chip system and the connection structure between the chips, so that the formed connection data can fully reflect the complete power network structure of the chip system, the power network structure is close to the real physical structure of the chip system, and the reliability and authenticity of the voltage drop electromigration simulation analysis are improved.

[0136] In step S204, based on the updated simulation input files, the renaming of each chip and the sub-modules of each chip, and the connection structure, internal data describing the physical connection relationship of each chip and connection structure data describing the physical connection relationship between the chips are determined in the physical connection data.

[0137] The simulation input files are updated according to the renaming of each chip and the sub-modules of each chip in the physical connection relationship, and the renaming of the connection structure, so that each chip in the chip system and the connection structure between the chips can be clearly distinguished in the updated simulation input files, so that the internal data of each chip and the connection structure data can be determined in the physical connection data obtained based on the updated simulation input files.

[0138] In step S205, internal simulation nodes of each chip are generated according to the internal data, and simulation nodes of the connection structure for connecting the chips are generated according to the connection structure data.

[0139] The internal data is used to form each simulation node in the chip, and the connection structure data is used to form the simulation node of the connection structure. Since the simulation node is finally connected with the resistance-inductance-capacitance model to form the final power network structure, in the embodiment of the application, the connection structure simulation node of the connection structure is considered in the process of connecting with the resistance-inductance-capacitance model, so that when the power network structure is constructed, the RLC generated by the connection structure coupling can be considered, and the finally established power network structure is ensured to fit the actual physical structure of the chip system.

[0140] In step S206, based on the generated internal simulation nodes of each chip and the simulation nodes of the connection structure, the power network simulation nodes of the chip system are formed.

[0141] The internal simulation nodes and the simulation nodes of the connection structure are both used to form the power network structure, and are collectively referred to as the power network simulation nodes of the chip system.

[0142] In one embodiment, step S205 can include:

[0143] The connection structure simulation node is abstractly generated according to the data describing the metal layer of the connection structure in the connection structure data, and the relative position relationship of the connection holes connecting the metal layers.

[0144] Based on Figure 8 As can be seen from the structure, the connection structure mainly refers to: through silicon via -> HBM layer -> HBV hole; therefore, in the connection structure data for describing the connection structure, data for describing the metal layer (i.e. HBM layer), data for describing the connection hole (i.e. through silicon via and HBV hole), and data for describing the relative position relationship of the connection hole are included, so that the connection structure simulation node can be accurately abstracted and generated.

[0145] In step S207, the internal simulation node of the chip and the simulation node of the connection structure are added to the corresponding connection position of the resistance-inductance-capacitance model of the chip system, so as to construct the power network structure of the chip system.

[0146] The resistance-inductance-capacitance model is used to describe and simulate the circuit connection between the internal simulation node of the chip and the simulation node of the connection structure.

[0147] After the internal simulation node of the chip and the simulation node of the connection structure are obtained, the resistance-inductance-capacitance model can be used to describe and simulate the circuit connection between these nodes. That is, each connection position of the resistance-inductance-capacitance model has its corresponding resistance, inductance and capacitance values, which will affect the performance of the circuit, such as signal transmission delay, power integrity and electromagnetic compatibility, etc.

[0148] Therefore, based on the internal simulation node and the simulation node of the connection structure, after the connection of the corresponding position in the resistance-inductance-capacitance model is completed, the power network structure of the chip system obtained is approximately expressed as the real power network of the chip system.

[0149] In step S208, the chip system is simulated based on the power network structure.

[0150] In order to facilitate the update of the simulation input file containing different contents, in an embodiment, the first simulation input file is a design file; the design file is a design exchange format file, which contains circuit design and is used to describe the layout, circuit and physical information of the chip system;

[0151] The first simulation input file containing the circuit design is updated based on the renaming of each chip and each sub-module of the chip and the renaming of the connection structure, to obtain an updated first simulation input file, which includes:

[0152] Based on the renaming of each chip and each sub-module of the chip, the names of each chip and each sub-module of the chip in the design exchange format file are updated, and based on the renaming of the connection structure, the name of the connection structure in the design exchange format file is updated, to obtain an updated design exchange format file.

[0153] Design exchange format file is an ASCII format file, which describes the actual design of chip system, lists the library cells and the location and connection relationship of the library cells, and is used to transfer the design between different design systems while keeping the content of the design unchanged. The design exchange format file is different from GDSII which only transfers geometric information. It can transfer the logical information and physical information of the design to the layout and routing tool. The logical information includes logical connection relationship (represented by netlist), grouping information and physical constraint. The physical information includes layout planning, layout location and direction, and routing geometry data.

[0154] The library cell refers to a predefined circuit module used in integrated circuit design, which is usually used in automatic layout and routing (P&R) tools. The library cell can be a standard cell such as a logic gate, a flip-flop, etc., or a larger module such as a memory block, a processor core, etc. hard macro.

[0155] The physical connection relationship includes the renaming of the chips, the sub-modules in the chips and the connection structures in the chip system; that is, the physical connection relationship redefines the chips at different levels, the sub-modules in the chips at different levels, and the metal layers and vias in the metal structures connecting the chips at different levels according to the stacking hierarchy of the chip system. Thus, the physical connection relationship (i.e. the combined connection relationship of the chips) of the chip system can be reflected by renaming. The stacking hierarchy of the chip system can be regarded as the structural hierarchy in the vertical direction of the actual structure of the chip system, so the three-dimensional structure of the chip system can be reflected in the two-dimensional plane (the plane formed in the vertical direction) by the renaming method.

[0156] Since the design exchange format file reflects the actual physical structure of the chip system, it includes the name definition of the chips, the sub-modules of each chip and the connection structures of the chip system. Therefore, the names of the chips, the sub-modules of each chip and the connection structures in the design exchange format file can be updated according to the renaming of the chips and the sub-modules of each chip and the connection structures in the physical connection relationship.

[0157] To update the design exchange format file, please refer to Figure 8 , Figure 8 is an implementation process diagram for obtaining connection data in the simulation method of the chip system provided by the embodiment of the application.

[0158] As Figure 8In the case that the first simulation input file is a design exchange format file, the chip can include: an upper layer chip at an upper layer level position in a chip system according to a stacking hierarchy of the chip system, and a lower layer chip relative to the upper layer chip; a renaming of the chip to add a level position identifier; a renaming of the sub-module to add a level position identifier for the chip; and the design exchange format file includes: a design exchange format file of the upper layer chip, a design exchange format file of each first sub-module in the upper layer chip, and a design exchange format file of the connection structure; a design exchange format file of the lower layer chip and a design exchange format file of each second sub-module in the lower layer chip.

[0159] The renaming of each chip and each chip sub-module is used to update the name of each chip and each chip sub-module in the design exchange format file, including:

[0160] Step 2.1: The renaming of each chip and each chip sub-module is used to update the name of each chip and each chip sub-module in the design exchange format file, and the renaming of the connection structure is used to update the name of the connection structure in the design exchange format file, to obtain an updated design exchange format file.

[0161] In the updating of the design exchange format file, the design exchange format file of the upper layer chip, the design exchange format file of the lower layer chip, and the design exchange format file of the connection structure can all be updated. Alternatively, one of the design exchange format file of the upper layer chip and the design exchange format file of the lower layer chip can be updated, and of course, the design exchange format file of the connection structure is updated.

[0162] The updating of the design exchange format file of the upper layer chip and / or the lower layer chip in step 2.1 can be:

[0163] The updating of the design exchange format file of the upper layer chip can be: based on the renaming of each chip and each chip sub-module, adding the level position identifier of the upper layer to the name of the chip and its sub-module in the design exchange format file of the upper layer chip, and adding the level position identifier of the upper layer to the name of the first sub-module in the first sub-module exchange design format file.

[0164] The updating of the design exchange format file of the lower layer chip can be: based on the renaming of each chip and each chip sub-module, adding the level position identifier of the lower layer to the name of the chip and its sub-module in the design exchange format file of the lower layer chip, and adding the level position identifier of the lower layer to the name of the second sub-module in the second sub-module exchange design format file.

[0165] The hierarchical position identifier represents the hierarchical position of the chip, such as the aforementioned top die is a chip in the upper hierarchical position, and the main die is a chip in the lower hierarchical position relative to the top die, so that each chip can be distinguished based on the hierarchical position, and of course, the chips can also be distinguished by name or numbered.

[0166] When distinguishing each chip and each submodule within the chip by the hierarchical position identifier, the submodule of the upper chip in the upper hierarchical position is referred to as the first submodule, and the submodule of the lower chip is referred to as the second submodule.

[0167] Since the renaming of the chip is mainly used to distinguish each chip and the submodule inside when forming the physical connection relationship, the chip in the upper hierarchical position can be renamed, and the name of the chip in the lower hierarchical position remains unchanged (for example, the aforementioned first submodule in the upper hierarchical position is renamed to "itop_m3", and the name of the lower chip remains unchanged: "m3"); the chip in the lower hierarchical position can also be renamed, and the name of the chip in the upper hierarchical position remains unchanged, so that each chip can be distinguished. Of course, the upper chip and the lower chip can also be renamed, which is convenient for the simulation tool to identify different chips.

[0168] Therefore, when updating the design exchange format file, the chip and the submodule can be updated according to the renaming in the physical connection relationship. For example, the aforementioned renaming of the chip and the submodule in the physical connection relationship, when updating the design exchange format file, the name of the chip and the submodule and the connection structure in the DEF file of the top die and the DEF file of the submodule included in the top die and the DEF file of the connection can be replaced with the renaming in the physical connection relationship. That is, the name of each metal layer and hole of the top die is replaced, the name of each metal layer and hole in each submodule constituting the top die is replaced, and the name of the metal layer and hole of the connection structure is replaced.

[0169] In some other embodiments, the second simulation input file can be a library file; the library file includes: a library exchange format file, a timing library file (.lib library file), and a current model file; wherein the library exchange format file contains device characteristics for describing various standard cell modules and integrated circuit design modules that constitute a chip system; the timing library file contains device characteristics and process conditions for describing timing and power consumption information of various standard cell modules and integrated circuit design modules in the chip system; and the current model file contains device characteristics for describing the switching current of the standard cell module and the analog integrated circuit design module under different output states.

[0170] Of course, the current model file can also contain information such as equivalent resistance, capacitance, and leakage current, which can accurately reflect the instantaneous power consumption of the module.

[0171] Please continue to refer to Figure 8 As shown in Figure 8 When the second simulation input file is a library file, the renaming of each chip and each chip submodule in the physical connection relationship and the renaming of the connection structure are used to update the second simulation input file containing device characteristics and process conditions to obtain an updated second simulation input file, including:

[0172] Step 3.1: Based on the renaming of each chip and each chip submodule, for the library exchange format file used to constitute a chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added in the naming of the submodule to obtain an updated library exchange format file with a hierarchical position identifier.

[0173] Step 3.2: Based on the renaming of each chip and each chip submodule, for the timing library file used to constitute a chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added in the name of the submodule to obtain an updated timing library file with a hierarchical position identifier.

[0174] Step 3.3: Based on the renaming of each chip and each chip submodule, for the current model file used to constitute a chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added in the name of the submodule to obtain an updated current model file with a hierarchical position identifier.

[0175] When processing library type files, the LEF file is processed first because it contains physical information of the standard cell library, such as the size, shape, hierarchy, pin position, etc. of the cell. These information must be known by the layout tool (such as layout routing tool) when placing the cell.

[0176] The LEF file also contains information about the process layers, which is necessary for subsequent routing and verification steps.

[0177] After the LEF file is read, the next step is to process the ".lib library files". The ".lib library files" contain timing information for standard cell modules, such as cell delays, fanouts, loads, etc. This information is crucial for timing analysis and optimization. Timing analysis tools use the data in the ".lib library files" to calculate the timing characteristics of the circuit, ensuring that the circuit meets performance requirements.

[0178] When the layout and timing analysis are complete, current model files are processed. These files contain current characteristics of various parts of the circuit for signal integrity (SI) and power integrity (PI) analysis.

[0179] Current model files are typically extracted after the layout design is complete, as they require detailed information about the layout to accurately simulate the behavior of the circuit under actual working conditions.

[0180] Ensuring that the physical and electrical characteristics of the chip system design are properly considered and analyzed, resulting in a high-performance, high-reliability chip system design.

[0181] Therefore, when updating the library type files based on the physical connection relationship between the chip and the sub-module, the same processing sequence is followed, and the updates are made in sequence.

[0182] For example, the LEF file of the first sub-module instantiated in the top die is replaced with the metal layer name and a new LEF file is created. The updated LEF file can handle the instantiation of sub-modules in the case where the main die and the top die use the same logic cell library and IP library. For example, the same IP "macro" is instantiated in both the top die and the main die. Since the updated LEF file is based on the renaming of the chip and sub-module in the physical connection information, the metal layer description of the pin in the original LEF file "macro.lef" of this IP is replaced with the name "itop_macro", resulting in a new LEF file "itop_macro.lef". At the same time, the name of the IP used in common is modified "macro" -> "itop_macro", resulting in two LEF files with the same graph, which are used for instantiation in the main die and the top die, respectively.

[0183] After the LEF file is updated, the lib library files and current model files are also updated with the same renaming, resulting in new lib library files and current model files, ensuring that the names of the created logic cells and simulation module cells are consistent in different library files.

[0184] In other embodiments, the third simulation input file is a process file; the process file includes: a layout and routing process library exchange format file (layout and routing process library LEF file), the layout and routing process library exchange format file contains process parameters, which are used to describe the process layer and standard unit module of the chip system and the layout information of the integrated circuit design module.

[0185] Please continue to refer to Figure 8 ,like Figure 8 As shown, when the third simulation input file is a layout and routing process library exchange format file, the renaming of each chip and the sub-module of each chip based on the physical connection relationship, and the renaming of the connection structure, update the third simulation input file containing the process parameters to obtain the updated third simulation input file, including:

[0186] Step 4.1: Based on the renaming of each chip, submodule and connection structure, the names of each chip, submodule and connection structure in the layout and routing process library exchange format file are updated to obtain an updated layout and routing process library exchange format file.

[0187] Step 4.2: Merge the updated layout and routing process library exchange format file of the upper chip, the layout and routing process library exchange format file of the lower chip, and the layout and routing process library exchange format file of the connection structure connecting the upper chip and the lower chip.

[0188] First, based on the renaming of chips, submodules and connection structures in the physical connection relationship, the names of chips, submodules and connection structures in the layout and routing process LEF file provided by each fab are replaced to generate a new layout and routing process LEF file.

[0189] Then, the updated layout and routing process library exchange format files are merged: the layout and routing process library exchange format file for the upper-layer chip, the layout and routing process library exchange format file for the lower-layer chip, and the layout and routing process library exchange format file for the connection structure connecting the upper and lower chips. In other words, the updated layout and routing process library exchange format file for the upper-layer chip, the layout and routing process library exchange format file for the lower-layer chip, and the layout and routing process library exchange format file for the connection structure are "merged" to ultimately generate a LEF file containing all the merged information. This file will be used in the subsequent physical design and verification process. The "merge" step is a key step in ensuring that all design elements can be correctly integrated and interacted during the physical design phase. This process ensures design consistency and manufacturability.

[0190] The merged layout routing process library exchange format file is mainly used for the voltage drop electromigration analysis simulation tool to identify the width information of the routing layer. Since the technical scheme is to perform voltage drop electromigration analysis on the power network, the power and ground network routing line width comes from the DEF file description, the layout routing process LEF file does not affect the tool to restore the power and ground network routing pattern, and is only used as a necessary file for the simulation tool.

[0191] In some other embodiments, the process file further includes: a voltage drop electromigration process file containing process parameters, a set of process parameters and rules for describing and controlling the problems of electromigration and voltage drop.

[0192] Please continue to refer to Figure 8 As Figure 8 shown, when the third simulation input file is a voltage drop electromigration process file, the third simulation input file containing process parameters is updated based on the renaming of each chip and the sub-module of each chip in the physical connection relationship and the renaming of the connection structure, to obtain an updated third simulation input file, including:

[0193] Step 5.1: Based on the renaming of each chip, sub-module and connection structure, the names of each chip, sub-module and connection structure in the voltage drop electromigration process file are updated to obtain an updated voltage drop electromigration process file.

[0194] Step 5.2: The voltage drop electromigration process files of the upper chip, the lower chip and the connection structure connecting the upper chip and the lower chip in the updated voltage drop electromigration process file are merged.

[0195] Firstly, based on the renaming of the chip, the sub-module and the connection structure in the physical connection relationship, the names of the chip, the sub-module and the connection structure in the voltage drop electromigration process file provided by each fab for voltage drop electromigration analysis are replaced to generate a new voltage drop electromigration process file.

[0196] Then, the updated voltage drop electromigration process files of the upper chip, the lower chip and the connection structure are merged to finally generate a voltage drop electromigration process file containing all the merged information.

[0197] Among them, in the process of merging the above updated voltage drop electromigration process files, the description of the relationship between die and connection in different hierarchical positions is mainly processed, and the connection relationship can be clearly described in a fixed format. The metal width, thickness, etching line width process table, square resistance, dielectric layer definition and other information do not need to be modified.

[0198] For example, the upper metal of the TSV is connected to the HBM layer of the connection, and the lower metal is connected to the thick metal side of the main die. The upper metal of the HBV is connected to the AP layer of the top die, and the lower metal is connected to the HBM layer of the connection.

[0199] After the update processing of the simulation input file based on the physical connection relationship is completed, the physical connection data of the chip system can be obtained. The updated lib library file, current model file, DEF file, LEF file, layout routing process LEF file, voltage drop electromigration process file, and all library files used in the original design (such as the aforementioned SPEF file and timing file that do not need to be modified) are read into the simulation tool (voltage drop electromigration simulation tool), the physical connection data of the chip system is obtained, the conversion of the stacking structure of the multi-die chip system to a 2D graph is completed, and the logical connection and physical connection of the chip system are completed.

[0200] After updating each file in the simulation input file, please continue to refer to Figure 8 , based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file, the connection data of the chip system is obtained, including:

[0201] Step 2.2: Determine the update file condition of the design exchange format file, instantiate each exchange design format file based on the update file condition, and extract the data of the instantiated design exchange format file to obtain the first connection data.

[0202] The main purpose of updating the simulation input file is to distinguish each chip and connection structure in the chip system, and the design exchange format file includes different files for the upper chip, the lower chip, and the connection structure. Therefore, after updating the design exchange format file, the instantiation processing of each subsequent design exchange format file can be performed based on the specific updated file (i.e., the update file condition of the design exchange format file).

[0203] In one embodiment, step 2.2 can include:

[0204] When it is determined that the update file condition is that the design exchange format file of the upper chip and the design exchange format file of the lower chip and the design exchange format file of the connection structure are all updated, the updated design exchange format file of the lower chip is instantiated; the updated design exchange format file of the upper chip and the design exchange format file of the connection structure are instantiated.

[0205] The data of the instantiated design exchange format file is extracted to obtain the first connection data.

[0206] In the case of determining that the design exchange format files of the upper chip and the connection structure are updated, but the design exchange format file of the lower chip is not updated, the updated design exchange format file of the lower chip is instantiated; the updated design exchange format file of the upper chip and the updated design exchange format file of the connection structure are instantiated.

[0207] The data of the instantiated design exchange format file is extracted to obtain first connection data.

[0208] In the case of determining that the design exchange format files of the upper chip and the connection structure are updated, but the design exchange format file of the lower chip is not updated, the updated design exchange format file of the lower chip is instantiated; the updated design exchange format file of the upper chip and the updated design exchange format file of the connection structure are instantiated.

[0209] The data of the instantiated design exchange format file is extracted to obtain first connection data.

[0210] The updated design exchange format file is instantiated, so that the logical connection relationship and the physical connection relationship of the chip system are reflected in the same updated design exchange format file.

[0211] Based on the update selection of different design exchange format files, accurate instantiation processing of each design exchange format file is realized to obtain first connection data which can accurately describe the physical structure of the chip system.

[0212] Please continue to refer to Figure 8 , the method can further include:

[0213] Step 3.4: Extracting the data of the updated library exchange format file, the updated timing library file and the updated current model file to obtain second connection data.

[0214] Step 4.3: Extracting the data of the merged layout routing technology library exchange format file to obtain third connection data.

[0215] Step 5.3: Extracting the data of the merged voltage drop electromigration process file to obtain fourth connection data.

[0216] Step 6: Based on the first connection data, the second connection data, the third connection data and the fourth connection data, the connection data of the chip system is obtained.

[0217] Since the content of each file is different, after the update, the connection data of each updated file is extracted respectively, and finally the connection data of the chip system is formed.

[0218] In the case that the first simulation input file is a design exchange format file, after the design exchange format file of the chip and its sub-modules and the connection structure is updated, a new design exchange format file is generated. In order to ensure the design correctness of the chip system, optimize the performance and subsequent preparation for manufacturing, after the new design exchange format file is obtained, the design exchange format file is instantiated.

[0219] In an embodiment, when it is determined that the update file condition is that the design exchange format file of the upper chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower chip is not updated, the design exchange format file of the lower chip which is not updated is instantiated, including:

[0220] In the design exchange format file of the lower chip which is not updated, the updated design exchange format file of the upper chip and the updated design exchange format file of the connection structure are instantiated;

[0221] In the design exchange format file of the lower chip which is not updated, the power supply ground network definition which has a power connection with the updated upper chip is logically connected and redefined;

[0222] The instantiation processing of the design exchange format file of the lower chip which is not updated is completed.

[0223] The DEF files of the top die and the connection are instantiated in the DEF file of the main die. When the DEF files of the top die and the connection are instantiated, the top die and the connection can be regarded as secondary modules and added to the DEF of the main die according to the definition of the instantiation of a module, and the following two definitions are added to the “COMPONENT” in the DEF of the main die through the description of the physical position and the instantiation name:

[0224] -itop topdie+FIXED(500 50000)N;

[0225] -iconn connection+FIXED(500 50000)N;

[0226] The instantiation processing of the DEF of the main die is completed.

[0227] When the original coordinates are not aligned, the coordinate information needs to be converted based on the reserved TSV center position of the main die and the displacement of the relative position of the TSV to the HBV hole center in the connection.

[0228] The TSV is instantiated in the DEF of the main die using the LEF (Library Exchange Format) of an IP, and has specific coordinate information, so coordinate conversion can be performed.

[0229] After the DEF of the top die and the DEF of the connection are instantiated into the DEF of the main die, the power ground network definition that has a power connection with the top die is further logically connected and redefined in the DEF file of the main die. For example, power supply from VDD1 of the main die to VDD of the top die and VDD CON of the connection is performed by supplementing the logical connection relationship of VDD1 in the DEF file of the main die according to the DEF syntax:

[0230] -VDD1

[0231] (PIN VDD1)

[0232] (*VDD1)

[0233] (itop VDD)

[0234] (iconn VDD CON).

[0235] Of course, the design type simulation input file can also include a SPEF (Standard Parasitic Extraction Format) file and a timing file, but due to the characteristics of the recorded content of the SPEF file and the timing file themselves, they do not need to be updated, so the timing file and the SPEF file can be used directly.

[0236] In an embodiment, when it is determined that the update file is updated, the design exchange format file of the upper chip and the design exchange format file of the connection structure are updated, but the design exchange format file of the lower chip is not updated, and the instantiation processing of the updated design exchange format file of the upper chip includes:

[0237] In the updated design exchange format file of the upper layer chip, the hierarchical position identifier of the upper layer is added in the naming of the instantiated standard cell module, and the hierarchical position identifier of the upper layer is added in the name of the instantiated integrated circuit design module; the standard cell module and the integrated circuit design module are first sub-modules that constitute the upper layer chip.

[0238] The instantiation processing of the design exchange format file of the upper layer chip refers to modifying the name of the instantiated IP (integrated circuit design module) or standard cell module in the DEF file of the top die. For example, a prefix "itop_" is added to the name of the IP and standard cell module appearing in the DEF of the top die, to ensure that the design exchange format file of the upper layer chip can be normally used.

[0239] For example, when instantiating the DEF file of the top die, the following updates can be made:

[0240] " -aaa inv1+FIXED(10000 10000)N ";

[0241] is modified to:

[0242] " -aaa itop_inv1+FIXED(10000 10000)N ";

[0243] Wherein, the above represents instantiation information of a library cell.

[0244] " -aaa " is used to specify that the component has certain properties.

[0245] " inv1 " is the name of the library cell, indicating that this is a standard cell or macro cell named inv1.

[0246] " +FIXED " is a placement state marker, indicating that the position of the library cell is fixed and cannot be changed. In layout design, the FIXED state is usually used for cells whose positions have been determined, such as macro cells or certain standard cells.

[0247] " (10000 10000) " is the coordinate position of the library cell in the overall layout of the chip system, indicating that the lower left corner of the library cell is located at the coordinate (10000, 10000). The coordinate unit depends on the unit defined in the DEF file (such as microns, nanometers, etc.).

[0248] " N " represents the placement direction of the library cell. In the DEF file, N represents North, i.e. 0 degree direction, indicating that the library cell is placed according to its original direction without rotation.

[0249] Of course, in other update file cases, the instantiation processing of the design exchange format file of the upper chip, the design exchange format file of the lower chip and the design exchange format file of the connection structure is the same as the above execution process, except that the un-updated design exchange format file of the upper chip or the design exchange format file of the lower chip is used.

[0250] Please continue to refer to Figure 9 , can also include:

[0251] Step 7: Chip system power network simulation node extraction is performed on the physical connection data, and a power network structure of the chip system is constructed based on the extracted power network simulation nodes.

[0252] Step 8: Voltage drop electro-migration simulation is performed on the chip system based on the power network structure.

[0253] Embodiments of the present application also provide a chip system simulation device for implementing the chip system simulation method described in the foregoing embodiments.

[0254] Please refer to Figure 9 , Figure 9 is a structural schematic diagram of a chip system simulation device provided by an embodiment of the present application.

[0255] As Figure 9 indicated, the device comprises:

[0256] A data acquisition module 91 is configured to acquire connection data of a chip system; the connection data comprises physical connection data, and the physical connection data is formed based on physical connection relationships among chips in the chip system.

[0257] A power network structure construction module 92 is configured to perform chip system power network simulation node extraction on the physical connection data, and construct a power network structure of the chip system based on the extracted power network simulation nodes.

[0258] A simulation module 93 is configured to perform voltage drop electro-migration simulation on the chip system based on the power network structure.

[0259] As ​ indicated, optionally, the device further comprises:

[0260] The physical connection relationship forming module 90 is configured to redefine names of each chip and sub-modules of each chip in the chip system, to obtain renamed names of each chip and sub-modules, so that different chips have different names; redefine names of connection structures connecting the chips, to obtain renamed names of the connection structures; and sort the renamed chips, sub-modules of each chip and connection structures in a vertical direction of a stack level of the chip system, to form a physical connection relationship of the chip system.

[0261] The data obtaining module 91 is configured to obtain connection data of the chip system, including:

[0262] Based on the renamed names of each chip and sub-modules of each chip and the renamed names of the connection structures in the physical connection relationship, and according to a type of the simulation input file of the chip system, the simulation input file of the corresponding type is updated.

[0263] The connection data of the chip system is obtained based on the updated simulation input file.

[0264] Optionally, the type of the simulation input file includes a design type; and the simulation input file of the design type is a design exchange format file, which is used to describe layout, circuit and physical information of the chip system.

[0265] The data obtaining module 91 is configured to update the simulation input file of the corresponding type based on the renamed names of each chip and sub-modules of each chip and the renamed names of the connection structures in the physical connection relationship, including:

[0266] Based on the renamed names of each chip and sub-modules of each chip, the names of each chip and sub-modules of each chip in the design exchange format file are updated, and based on the renamed names of the connection structures, the names of the connection structures in the design exchange format file are updated.

[0267] The data obtaining module 91 is configured to obtain the connection data of the chip system based on the updated simulation input file, including:

[0268] The updated design exchange format file is instantiated.

[0269] Data of the instantiated design exchange format file is extracted to form the connection data of the chip system.

[0270] Optionally, the type of the simulation input file comprises: a library type; the simulation input file of the library type comprises: a library exchange format file, a timing library file and a current model file; wherein the library exchange format file is used to describe each standard cell module and integrated circuit design module constituting a chip system; the timing library file is used to describe timing and power consumption information of each standard cell module and integrated circuit design module in the chip system; and the current model file is used to describe flip current conditions of the standard cell module and the analog integrated circuit design module in different output states.

[0271] The data acquisition module 91 is configured to update the simulation input file of the corresponding type according to the type of the simulation input file of the chip system based on the renaming of each chip and the sub-module of each chip of the physical connection relationship and the renaming of the connection structure, and comprises the following steps:

[0272] Based on the renaming of each chip and the sub-module of each chip, for the library exchange format file of each sub-module used to constitute a chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added in the naming of the sub-module to form the library exchange format file of the sub-module with the hierarchical position identifier.

[0273] Based on the renaming of each chip and the sub-module of each chip, for the timing library file of each sub-module used to constitute a chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added in the name of the sub-module to form the timing library file of the sub-module with the hierarchical position identifier.

[0274] In addition, based on the renaming of each chip and the sub-module of each chip, for the current model file of each sub-module used to constitute a chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added in the name of the sub-module to form the current model file of the sub-module with the hierarchical position identifier.

[0275] The data acquisition module 91 is configured to acquire the connection data of the chip system based on the updated simulation input file, and comprises the following steps:

[0276] The data of the updated library exchange format file, the updated timing library file and the updated current model file are extracted to form the connection data of the chip system.

[0277] Optionally, the type of the simulation input file comprises: a process type; the simulation input file of the process type comprises: a layout and routing process library exchange format file, and the layout and routing process library exchange format file is used to describe the process layer and the layout information of the standard cell module and the integrated circuit design module of the chip system.

[0278] The data acquisition module 91 is configured to update the simulation input file of a corresponding type according to the type of the simulation input file of the chip system based on the renaming of each chip and the sub-module of each chip and the renaming of the connection structure, including:

[0279] updating the names of each chip, the sub-module, and the connection structure in the layout and routing technology library exchange format file based on the renaming of each chip, the sub-module, and the connection structure;

[0280] merging the layout and routing technology library exchange format file of the upper chip, the layout and routing technology library exchange format file of the lower chip, and the layout and routing technology library exchange format file of the connection structure connecting the upper chip and the lower chip in the updated layout and routing technology library exchange format file;

[0281] The data acquisition module 91 is configured to acquire the connection data of the chip system based on the updated simulation input file, including:

[0282] extracting the data of the merged layout and routing technology library exchange format file to form the connection data of the chip system.

[0283] It can be seen that the technical scheme provided by the embodiment of the application, when performing the voltage drop electromigration simulation of the chip system, the connection data of the chip system includes: the physical connection data formed based on the physical connection relationship between each chip in the chip system; therefore, when extracting the power network simulation node based on the physical connection data, the power network simulation node can reflect the node of the physical connection relationship between each chip; and the power network structure constructed based on the extracted power network simulation node can be close to the power network distribution in the real physical structure of the chip system, so that when performing the simulation based on the power network structure, the simulation result obtained can more reliably reflect the power network distribution of the chip system, facilitating the adjustment of the power network distribution of the chip system and prolonging the service life of the chip system.

[0284] The embodiment of the application provides an electronic device, such as a terminal device, a server device, and the like computer device, including a memory and a processor, the memory stores a program, the processor calls the program stored in the memory, and executes the simulation method of the chip system as described in any one of the preceding embodiments.

[0285] The embodiment of the application provides a storage medium, the storage medium stores a program, and the program is executed to implement the simulation method of the chip system as described in any one of the preceding embodiments.

[0286] The embodiment of the present application provides a computer program product, comprising a computer program, which realizes the simulation method of the chip system according to any one of the foregoing embodiments when executed by a processor.

[0287] The above describes a plurality of embodiment schemes provided by the embodiment of the present application, and each optional mode introduced by each embodiment scheme can be combined and cross-referenced in the case of no conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiment schemes disclosed and published by the embodiment of the present application.

[0288] Although the embodiment of the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A chip system simulation method, characterized in that: include: Acquire connection data of the chip system; the connection data includes physical connection data, and the physical connection data is formed based on the physical connection relationship between each chip in the chip system; Extracting power network simulation nodes of the chip system from the physical connection data, and constructing a power network structure of the chip system based on the extracted power network simulation nodes; Performing voltage drop and electromigration simulation on the chip system based on the power network structure; The obtaining of the connection data of the chip system includes: Based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, the simulation input file of the chip system is updated; the simulation input file includes a first simulation input file including a circuit design; including: Based on the renaming of each chip and each chip's submodule in the physical connection relationship, and the renaming of the connection structure, the first simulation input file is updated to obtain an updated first simulation input file; the first simulation input file is a design file, the design file includes a design exchange format file, the design exchange format file includes a circuit design, and is used to describe the layout, circuit, and physical information of the chip system; including: Based on the renaming of each chip and the submodule of each chip, updating the name of each chip and the submodule of each chip in the design exchange format file; including: Based on the renaming of each chip and each chip's submodule, in the design exchange format file of the upper chip, the name of the chip and its submodule is added with the upper layer's hierarchical position identifier, and the name of the first submodule in the exchange design format file of the first submodule is added with the upper layer's hierarchical position identifier; and / or, based on the renaming of each chip and the submodule of each chip, adding the hierarchical position identifier of the lower layer to the name of the chip and its submodule in the design exchange format file of the lower chip, and adding the hierarchical position identifier of the lower layer to the name of the second submodule in the exchange design format file of the second submodule; The chip includes: an upper chip that is in an upper hierarchical position in the chip system according to the stacking hierarchy of the chip system, and a lower chip relative to the upper chip; the renaming of the chip is a renaming that adds a hierarchical position identifier, and the renaming of the sub-module is a renaming that adds a hierarchical position identifier for the chip; the design exchange format file includes: a design exchange format file of the upper chip, a design exchange format file of each first sub-module in the upper chip, and a design exchange format file of the connection structure; a design exchange format file of the lower chip and a design exchange format file of each second sub-module in the lower chip.

2. The chip system simulation method according to claim 1, wherein: Before the step of obtaining the connection data of the chip system, the method further includes: Redefine the names of the chips in the chip system and the submodules constituting the chips, thereby renaming the chips and submodules so that different chips and submodules have different names; and redefine the names of the connection structures connecting the chips, thereby renaming the connection structures; In a vertical direction of the stacking layer of the chip system, the renamed chips, submodules of the chips, and connection structures are sorted to form a physical connection relationship of the chip system; The obtaining of the connection data of the chip system further includes: The connection data of the chip system is obtained based on the updated simulation input file.

3. The chip system simulation method according to claim 2, wherein: The simulation input file also includes a set of files containing process parameters, device characteristics and operating conditions; the renaming of each chip and each chip's submodule in the physical connection relationship, as well as the renaming of the connection structure, updating the simulation input file of the chip system, further includes: Based on the renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the second simulation input file containing device characteristics and operating conditions to obtain an updated second simulation input file; and, based on the renaming of the chips and the submodules of each chip in the physical connection relationship, and the renaming of the connection structure, updating a third simulation input file containing process parameters to obtain an updated third simulation input file; The obtaining the connection data of the chip system based on the updated simulation input file includes: Connection data of the chip system is acquired based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file.

4. The chip system simulation method according to claim 3, wherein: The renaming of each chip and the submodule of each chip in the physical connection relationship and the renaming of the connection structure, updating the first simulation input file to obtain an updated first simulation input file, further includes: Based on the renaming of the connection structure, the name of the connection structure in the design exchange format file is updated to obtain an updated design exchange format file.

5. The chip system simulation method according to claim 4, wherein: The second simulation input file is a library file, and the library file includes: a library exchange format file, a timing library file, and a current model file; wherein the library exchange format file contains device characteristics, which are used to describe the various standard cell modules and integrated circuit design modules that constitute the chip system; the timing library file contains device characteristics and process conditions, which are used to describe the timing and power consumption information of the various standard cell modules and integrated circuit design modules in the chip system; the current model file contains device characteristics, which are used to describe the flip current conditions of the standard cell modules and the analog integrated circuit design modules under different output states; The renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the second simulation input file containing device characteristics and process conditions to obtain an updated second simulation input file, includes: Based on the renaming of each chip and the submodule of each chip, for the library exchange format file of the submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to obtain an updated library exchange format file with the hierarchical position identifier; Based on the renaming of each chip and each chip's submodule, for the timing library file of the submodule that is used to constitute the chip and is instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the submodule to obtain an updated timing library file with the hierarchical position identifier; In addition, based on the renaming of each chip and the sub-module of each chip, for the current model file of the sub-module used to constitute the chip and instantiated in the constituted chip, the hierarchical position identifier of the corresponding chip is added to the name of the sub-module to obtain an updated current model file with a hierarchical position identifier.

6. The chip system simulation method according to claim 5, wherein: The third simulation input file is a process file, which includes: a layout and routing process library exchange format file, the layout and routing process library exchange format file containing process parameters for describing the process layer and standard unit module of the chip system and the layout information of the integrated circuit design module; The renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the third simulation input file containing the process parameters to obtain the updated third simulation input file, includes: Based on the renaming of each chip, submodule, and connection structure, the names of each chip, submodule, and connection structure in the layout and routing process library exchange format file are updated to obtain an updated layout and routing process library exchange format file; The method further comprises: The updated layout and routing process library exchange format file includes the layout and routing process library exchange format file of the upper chip, the layout and routing process library exchange format file of the lower chip, and the layout and routing process library exchange format file of the connection structure connecting the upper chip and the lower chip.

7. The chip system simulation method according to claim 6, wherein: The process file also includes: a voltage drop electromigration process file, wherein the voltage drop electromigration process file includes process parameters, a set of process parameters and rules for describing and controlling electromigration and voltage drop problems; The renaming of each chip and the submodule of each chip in the physical connection relationship, and the renaming of the connection structure, updating the third simulation input file containing the process parameters to obtain the updated third simulation input file, includes: Based on the renaming of each chip, submodule, and connection structure, updating the name of each chip, submodule, and connection structure in the voltage drop electromigration process file to obtain an updated voltage drop electromigration process file; The method further comprises: The updated voltage drop electromigration process file includes the voltage drop electromigration process file of the upper chip, the voltage drop electromigration process file of the lower chip, and the voltage drop electromigration process file of the connection structure connecting the upper chip and the lower chip.

8. The chip system simulation method according to claim 7, wherein: The acquiring the connection data of the chip system based on the updated first simulation input file, the updated second simulation input file, and the updated third simulation input file includes: Determining an update status of a design exchange format file, instantiating each exchange design format file based on the update status, and extracting data of the instantiated design exchange format file to obtain first connection data; Extracting data of an updated library exchange format file, an updated timing library file, and an updated current model file to obtain second connection data; and extracting data from the merged layout and routing process library exchange format file to obtain third connection data, and extracting data from the merged voltage drop electromigration process file to obtain fourth connection data; Connection data of the chip system is obtained based on the first connection data, the second connection data, the third connection data, and the fourth connection data.

9. The chip system simulation method according to claim 8, wherein: The determining of the updated file status of the design exchange format file, instantiating each exchange design format file based on the updated file status, and extracting data of the instantiated design exchange format file to obtain the first connection data includes: When it is determined that the updated file situation is that the design exchange format file of the upper layer chip, the design exchange format file of the lower layer chip, and the design exchange format file of the connection structure are all updated, instantiating the updated design exchange format file of the lower layer chip; and instantiating the updated design exchange format file of the upper layer chip and the design exchange format file of the connection structure; Extracting data of the instantiated design exchange format file to obtain first connection data; When it is determined that the updated file situation is that the design exchange format file of the upper layer chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower layer chip is not updated, instantiating the design exchange format file of the lower layer chip that has not been updated; and instantiating the updated design exchange format file of the upper layer chip and the design exchange format file of the connection structure; Extracting data of the instantiated design exchange format file to obtain first connection data; When it is determined that the updated file situation is that the design exchange format file of the lower layer chip and the design exchange format file of the connection structure are updated, but the design exchange format file of the upper layer chip is not updated, instantiating the updated design exchange format file of the lower layer chip; and instantiating the unupdated design exchange format file of the upper layer chip and the updated design exchange format file of the connection structure; The data of the instantiated design exchange format file is extracted to obtain first connection data.

10. The chip system simulation method according to claim 9, wherein: When it is determined that the updated file situation is that the design exchange format file of the upper layer chip and the design exchange format file of the connection structure are both updated, but the design exchange format file of the lower layer chip is not updated, instantiating the design exchange format file of the lower layer chip that has not been updated includes: Instantiating the updated design exchange format file of the upper layer chip and the updated design exchange format file of the connection structure in the design exchange format file of the lower layer chip that has not been updated; In the design exchange format file of the lower layer chip that has not been updated, the power ground network definition that has power connection with the updated upper layer chip is logically redefined; Complete the instantiation process of the design exchange format file of the lower-level chip that has not been updated.

11. The chip system simulation method according to claim 10, wherein: The instantiation processing of the updated design exchange format file of the upper chip includes: In the updated design exchange format file of the upper-layer chip, the hierarchical position identifier of the upper layer is added to the name of the instantiated standard cell module, and the hierarchical position identifier of the upper layer is added to the name of the instantiated integrated circuit design module; The standard cell module and the integrated circuit design module are the first submodules constituting the upper chip.

12. The chip system simulation method according to any one of claims 2 to 11, wherein: The extracting the power supply network simulation nodes of the chip system from the physical connection data includes: Based on the renaming of the chips and submodules of each chip, and the connection structure in the updated simulation input file, determining internal data describing the physical connection relationship of each chip and connection structure data describing the physical connection relationship between chips in the physical connection data; Abstractly generating an internal simulation node of each chip based on the internal data, and abstractly generating a simulation node of a connection structure for connecting chips based on the connection structure data; Based on the generated internal simulation nodes of each chip and the simulation nodes of the connection structure, a power supply network simulation node of the chip system is formed.

13. The chip system simulation method according to claim 12, wherein: The abstraction and generation of simulation nodes for connecting the chip-to-chip connection structure according to the connection structure data includes: Based on the data describing the metal layers of the connection structure and the data on the relative positional relationship of the connection holes connecting the metal layers in the connection structure data, a connection structure simulation node is abstractly generated.

14. The chip system simulation method according to claim 12, wherein: The step of constructing the power supply network structure of the chip system based on the extracted power supply network simulation nodes includes: Adding the internal simulation nodes of the chip and the simulation nodes of the connection structure to corresponding connection positions in the resistance, inductance and capacitance model of the chip system to construct a power network structure of the chip system; The RL model is used to describe and simulate the circuit connections between the internal simulation nodes of the chip and the simulation nodes of the connection structure.

15. The chip system simulation method according to any one of claims 1 to 11, characterized in that: The connection data of the chip system is the connection data of the chip system designed with back side power supply.

16. A chip system simulation device, characterized in that: include: A data acquisition module, configured to acquire connection data of the chip system; the connection data includes physical connection data, which is formed based on the physical connection relationship between the chips in the chip system; A power network structure construction module, configured to extract power network simulation nodes of a chip system from the physical connection data, and construct a power network structure of the chip system based on the extracted power network simulation nodes; A simulation module, configured to perform voltage drop and electromigration simulation on the chip system based on the power network structure; The data acquisition module includes: a simulation input file update module; the simulation input file update module is used to update the simulation input file of the chip system based on the renaming of each chip and the sub-module of each chip in the physical connection relationship, and the renaming of the connection structure; the simulation input file includes a first simulation input file containing a circuit design; including: based on the renaming of each chip and the sub-module of each chip in the physical connection relationship, and the renaming of the connection structure, updating the first simulation input file to obtain an updated first simulation input file; the first simulation input file is a design file, the design file includes a design exchange format file, the design exchange format file contains the circuit design, and is used to describe the layout, line and physical information of the chip system ; including: based on the renaming of each chip and the sub-module of each chip, updating the name of each chip and the sub-module of each chip in the design exchange format file; including: based on the renaming of each chip and the sub-module of each chip, adding the upper-level hierarchical position identifier to the name of the chip and its sub-module in the design exchange format file of the upper-level chip, and adding the upper-level hierarchical position identifier to the name of the first sub-module in the exchange design format file of the first sub-module; and / or, based on the renaming of each chip and the sub-module of each chip, adding the lower-level hierarchical position identifier to the name of the chip and its sub-module in the design exchange format file of the lower-level chip, and adding the lower-level hierarchical position identifier to the name of the second sub-module in the exchange design format file of the second sub-module; The chip includes: an upper chip that is in an upper hierarchical position in the chip system according to the stacking hierarchy of the chip system, and a lower chip relative to the upper chip; the renaming of the chip is a renaming that adds a hierarchical position identifier, and the renaming of the sub-module is a renaming that adds a hierarchical position identifier for the chip; the design exchange format file includes: a design exchange format file of the upper chip, a design exchange format file of each first sub-module in the upper chip, and a design exchange format file of the connection structure; a design exchange format file of the lower chip and a design exchange format file of each second sub-module in the lower chip.

17. An electronic device, characterized in that: It includes a memory and a processor, the memory stores a program, and the processor calls the program stored in the memory to execute the simulation method of the chip system according to any one of claims 1 to 15.

18. A storage medium, characterized in that The storage medium stores a program, and when the program is executed, the simulation method of the chip system according to any one of claims 1 to 15 is implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the simulation method of the chip system according to any one of claims 1 to 15 is implemented.

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