A line rewiring method, device and rewiring processing system

Abstract

A line rewiring method, device and rewiring processing system, based on an original drawing, obtains the initial position information of the first feature point group of a bare crystal in the original drawing and the initial position information of the second feature point group of connecting lines connected to the leads of the bare crystal to be processed; according to the deflection information of the bare crystal, obtains the actual position information of the bare crystal, the actual position information of the first feature point group and the actual position information of the second feature point group to construct a basic grid map; obtains the actual coordinate information of the first feature point of each lead of the bare crystal to be processed in the basic grid and the coordinate information set of the connecting lines to be connected corresponding to the first feature point, and determines whether there is an intersection between the actual coordinate information of the first feature point and the coordinate information set of the corresponding connecting line; if there is no intersection, connects the first feature point and the second feature point of the corresponding connecting line to obtain a rewiring line; restores the marking points of the grid and the rewiring line to a graphic to obtain a rewiring drawing.

Description

Technical Field

[0001] The present invention relates to the field of advanced packaging, and in particular to a line rewiring method, device and rewiring processing system. Background Art

[0002] Integrated circuit chips need to form circuits on wafers and be applied to circuit boards through processing steps such as packaging. Packaging integrated circuits has the functions of protecting chips, electrical connections, and facilitating assembly. Traditional packaging usually involves cutting wafers into individual chips before packaging. With the demand for miniaturization, thinning, and density of integrated circuit chips, more and more wafer-level packaging (WLP) is being used. Unlike traditional packaging, most of the process in the packaging process is to operate on the wafer, that is, the entire package is packaged on the wafer, and then the chips are cut and sliced ​​after the packaging is completed. For chips with small chip area and a small number of pins, fan-in packaging (FIWLP) is usually used. For chips with small chip area and a large number of pins, the chip area cannot accommodate enough pins, so fan-out packaging (FOWLP) is derived. In order to achieve more pins outside the chip area, a redistribution layer (RDL) is usually used to connect the internal solder joints and external solder joints of the chip. For fan-out packaging, in actual operation, it is necessary to first slice and divide the bare die wafer, and then reconfigure the independent bare die into the wafer or carrier, and based on this, through batch processing and metallization wiring interconnection, the final packaged chip is formed.

[0003] When placing the bare crystal, due to the influence of equipment accuracy, the bare crystal may shift, rotate, and other changes during the placement process. The bare crystal shift may cause the bare crystal to be disconnected from the wiring, thereby affecting data transmission. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a line rewiring method, device and rewiring processing system for accurately connecting bare crystals.

[0005] In order to solve the above technical problems, the present invention provides a line rewiring method, comprising:

[0006] S1. Based on the original drawing, initial position information of a first feature point group of a bare die to be processed and initial position information of a second feature point group of connecting lines connected to the leads of the bare die to be processed in the original drawing are obtained;

[0007] S2, obtaining deflection information of the bare crystal, and obtaining actual position information of the bare crystal, actual position information of the first feature point group, and actual position information of the second feature point group according to the deflection information of the bare crystal;

[0008] S3, constructing a basic grid map according to the actual position information of the bare die, the actual position information of the first feature point group, and the actual position information of the second feature point group;

[0009] S4, obtaining the actual coordinate information of the first feature point of each lead of the bare crystal to be processed in the basic grid and the coordinate information set of the connected line to be connected corresponding to the first feature point, and determining whether there is an intersection between the actual coordinate information of the first feature point and the coordinate information set of the corresponding connected line;

[0010] S5, when the actual coordinates of the first feature point and the coordinate set of the corresponding connected line do not have an intersection, connecting the first feature point and the second feature point of the corresponding connected line to obtain a rerouted line;

[0011] S6. Repeat steps S4 and S5 until all leads and connecting lines are connected, and the marking points of the grid and the rewiring lines are restored to graphics to obtain a rewiring drawing file.

[0012] In one embodiment, the first feature point in the first feature point group and the second feature point in the second feature point group are center points of intersection areas of leads of the bare die to be processed and corresponding connected connecting lines.

[0013] In one embodiment, a graphic intersection method is used to determine whether the connecting line and the lead graphic of the bare crystal to be processed intersect, obtain the graphic intersection area of ​​the lead of the bare crystal to be processed and the connecting line, and obtain the position information of the center point of the graphic intersection area.

[0014] In one embodiment, when step S3 constructs the basic grid map, the grid map is marked according to the actual position information of the bare die and the connecting lines. The marked position in the grid map is the non-routable area, and the unmarked area is the routable area. Each square represents a coordinate point.

[0015] In one embodiment, in step S5, the shortest path connection between the first feature point and the corresponding second feature point is selected to obtain the rerouted line. When performing the shortest path connection, it is also determined whether the adjacent squares are marked when the shortest path is extended to the lead width. If marked, it is determined whether the mark is the corresponding connecting line. If it is not a connecting line, the line is corrected to connect to the second feature point.

[0016] In one embodiment, according to the connection path between the first characteristic point and the second characteristic point, a wiring connection of the lead width is performed to obtain a redistribution line.

[0017] In one embodiment, after obtaining the basic grid map, the basic grid map is divided into a plurality of unit grid maps according to the connection relationship of the bare crystals, and the unit grid maps are subjected to parallel processing of rewiring.

[0018] A line rewiring device using any of the above-mentioned line rewiring methods, the line rewiring device comprising an information acquisition unit, a graphics processing unit, a grid map construction unit, a rewiring processing unit and an image restoration unit; the information acquisition unit is used to acquire and receive the original drawing file and the deflection information of the bare crystal; the graphics processing unit obtains information including the actual position information of the bare crystal, the initial position information of the first feature point and the initial position information of the second feature point according to the original drawing file and the deflection information of the bare crystal; the grid construction unit obtains a basic grid map according to the information of the graphics processing unit; the rewiring processing unit obtains the actual coordinate information of the first feature point of each lead of the bare crystal in the basic grid and the coordinate information set of the connecting lines to be connected corresponding to the first feature point based on the basic grid map, and determines whether the actual coordinate information of the first feature point and the coordinate information set of the corresponding connecting line have an intersection; when the actual coordinate of the first feature point and the coordinate set of the corresponding connecting line do not have an intersection, the first feature point and the corresponding second feature point are connected to obtain a rewiring line; the image restoration unit restores the marking points of the grid and the rewiring line into a graphic to obtain a rewiring drawing file.

[0019] In one embodiment, the line rewiring device also includes a unit grid map acquisition unit, which is used to divide a plurality of unit grid maps according to the actual positions between the bare crystal to be processed and other bare crystals in the basic grid map, so that the rewiring processing unit can process the unit grid maps in parallel.

[0020] A rewiring processing system comprises a pattern acquisition device, a pattern exposure device and the above-mentioned line rewiring device.

[0021] In one embodiment, the graphic acquisition device acquires actual position information of the bare crystal and outputs it to a circuit rewiring device. The circuit rewiring device obtains a rewiring drawing based on the actual position information of the bare crystal and the design drawing of the bare crystal and the connecting line and outputs it to the graphic exposure device. The graphic exposure device performs exposure operation based on the rewiring drawing to realize the graphic transfer of the rerouted circuit.

[0022] Compared with the prior art, the line rewiring method, device and rewiring processing system of the present invention can restore the connection between bare crystals and bare crystals, or between bare crystals and connecting lines after offset, ensure the communication of bare crystals, and improve chip yield; at the same time, a basic grid diagram is used to determine whether the bare crystal leads are connected to the connecting lines, and the unconnected leads and connecting lines are routed in the shortest path. The method is simple and the rewiring effect is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 (a) is a schematic diagram of the design of an embodiment of bare die packaging wiring.

[0024] Figure 1(b) is a schematic diagram of another embodiment of the bare die packaging wiring design.

[0025] Figure 2 (a) is a schematic diagram of bare die offset in an embodiment of bare die packaging wiring.

[0026] Figure 2 (b) is a schematic diagram of bare die offset in another embodiment of bare die package connection.

[0027] Figure 3 (a) is a schematic diagram of an embodiment of the intersection area of ​​the connecting line and the pattern of the bare die lead to be processed.

[0028] Figure 3 (b) is a schematic diagram of the initial positions of the first feature point and the second feature point.

[0029] Figure 4 It is a schematic diagram of an embodiment of a basic grid diagram rerouting line.

[0030] Figure 5 It is a block diagram of an embodiment of a line rewiring method.

[0031] Figure 6 is the unit grid Figure 1 Schematic diagram of an embodiment.

[0032] Figure 7 It is a schematic diagram of another embodiment of a unit grid diagram.

[0033] Figure 8 It is a schematic diagram of an embodiment of a line rewiring device.

[0034] Fig. 9 is a schematic diagram of an embodiment of a rewiring processing system. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described below by means of specific embodiments shown in the accompanying drawings.

[0036] like Figure 1 (a) and Figure 1 (b) is a schematic diagram of bare die packaging wiring design. The bare die connection relationship includes both the connection with the routing and the connection with the adjacent bare die. The pins of the bare die are connected to the routing through the leads, and then connected to the external solder joints, or connected to the leads of other adjacent bare die through the leads, so as to connect two adjacent bare die. Figure 2 (a) and Figure 2As shown in (b), due to the problem of equipment accuracy, when placing the bare crystal, the position of the bare crystal is offset relative to the design drawing, causing the pins and leads of the bare crystal to be offset as a whole, disconnecting from the routing or adjacent bare crystals, and cutting off the circuit. In order to restore the circuit routing of the bare crystal, the present invention provides a line rewiring method for the bare crystal offset to restore the circuit connection.

[0037] The wiring method constructs a basic grid map based on the original drawing file and the offset information of the bare crystal, and searches for the shortest path to disconnect the line connection through the basic grid map.

[0038] First, the original drawing and the offset information of the die are obtained, wherein the original drawing includes the initial position information of the first circuit group related to the offset die and the initial position information of the second circuit group connected to the offset die; the actual position information of the first feature point group of the first circuit group and the actual position information of the second feature point group of the second circuit group are obtained according to the initial position information and the offset information of the die, and if the position of the second circuit group is not offset, the actual position information of the second feature point group is consistent with the initial position information; a basic grid map is constructed according to the original drawing, the actual position information of the first feature point group, the actual position information of the second feature point group and the offset information of the die, and the non-routable area is marked in the basic grid map, and the non-routable area includes the corresponding area of ​​the components related to the offset die and the related component area connected to the offset die; it is judged in turn whether each first feature point of the first feature point group in the basic grid map is connected to the corresponding circuit, and if the first feature point is not connected to the corresponding circuit, a rewiring connection is performed between the first feature point and the second feature point corresponding to the first feature point according to the wiring width through the shortest connection path of the routable area, and the rewiring of the current offset die is completed after all feature points are processed.

[0039] The connection between the leads of the bare crystal to be processed and the connecting lines is taken as an example to specifically illustrate the method of rewiring the bare crystal offset. The connecting lines can be fixed-position routing lines and / or the leads of the bare crystal connected to the leads of the bare crystal to be processed. The positions of the leads of the bare crystal to be processed and the leads of the adjacent bare crystal will change due to the offset of the placement position.

[0040] like Figure 3-7 As shown, the rewiring method comprises the following steps:

[0041] S1. Based on the original drawing, the initial position information of the first feature point group of the bare crystal to be processed and the initial position information of the second feature point group of the connecting line connected to the bare crystal to be processed in the original drawing are obtained. The bare crystal to be processed and the connecting line in the original drawing are accurately connected and located on the same layer, and the bare crystal to be processed in the original drawing is in an ideal design position. If the initial design drawing contains multiple layers, the multiple layers are merged to obtain the original drawing of a single layer, and the information of the bare crystal to be processed and the connecting line information are mapped to the merged layer, and the graphics of the bare crystal and the connecting line are marked.

[0042] The initial position information of the first feature point group of the bare crystal to be processed includes the initial position information of the first feature point of each lead of the bare crystal to be processed, and the initial position information of the second feature point group of the connecting lines includes the initial position information of the second feature point of each connecting line corresponding to the lead of the bare crystal to be processed.

[0043] The first characteristic point of the lead and the second characteristic point of the connecting line in the original drawing are the center point of the intersection area where the lead and the connecting line are connected. The graphic intersection area of ​​the connecting line and the lead can be obtained by constructing the graphic topological relationship of the original drawing. The method for obtaining the graphic intersection area of ​​the connecting line and the lead can adopt a graphic intersection method, that is, the graphic intersection method is used to determine whether the connecting line and the lead graphic of the bare crystal to be processed intersect, and the graphic intersection area of ​​the lead of the bare crystal to be processed and the connecting line is found. Then, the position information of the center point of the graphic intersection area is obtained, that is, the initial position information corresponding to the first characteristic point of the lead and the initial position information corresponding to the second characteristic point of the connecting line.

[0044] S2. Obtain the deflection information of the bare crystal, and obtain the actual position information of the bare crystal, the actual position information of the first feature point group, and the actual position information of the second feature point group according to the deflection information of the bare crystal. The deflection information of the bare crystal includes the deflection information of the bare crystal to be processed and the deflection information of the adjacent bare crystal connected to the lead of the bare crystal to be processed. The deflection information of the bare crystal includes offset information, rotation information, and scaling information. According to the offset information, rotation information, and scaling information of the bare crystal, the actual position information of the bare crystal and the actual position information of the first feature point of the bare crystal lead can be calculated.

[0045] The actual position information of the die includes the actual position information of the die to be processed and the actual position information of the adjacent die connected to the die to be processed.

[0046] The routing line connected to the bare crystal to be processed will not move due to the position offset of the bare crystal to be processed. Therefore, when the connecting line is a routing line, the actual position information of the second feature point group is consistent with the initial position information.

[0047] If an adjacent die connected to the die to be processed is offset, actual position information of the second feature point group is obtained according to deflection information of the adjacent die.

[0048] S3. Construct a basic grid map according to the actual position information of the bare crystal, the actual position information of the first feature point group, and the actual position information of the second feature point group.

[0049] According to the actual position information of the bare die and the connecting line, the marked position in the grid map is the non-routable area, and the unmarked area is the routable area. Each square represents a coordinate point. The marking can be in various forms, such as marking the position of the routing line and the bare die. The marking can be selected in various forms such as × or Δ symbol marking, or digital marking, etc.

[0050] The actual position information of the die includes the actual position information of the die to be processed and the actual position information of the adjacent die connected to the die to be processed.

[0051] S4. Obtain the actual coordinate information of the first feature point of each lead of the bare crystal to be processed in the basic grid diagram and the coordinate information set of the connecting lines corresponding to the leads, and determine whether there is an intersection between the actual coordinate information of the feature point of the lead and the coordinate information set of the corresponding connecting lines.

[0052] If the actual position coordinates of the first feature point and the coordinate set of the corresponding connected lines have an intersection, it means that the leads of the bare crystal to be processed are correctly connected to the corresponding connected lines and no rewiring is required; if the actual position coordinates of the first feature point of the bare crystal to be processed and the coordinate set of the corresponding connected lines do not have an intersection, the leads of the bare crystal to be processed and the connecting lines are reconnected.

[0053] S5. When there is no intersection between the actual position coordinates of the first feature point and the coordinate set of the corresponding connected line, the first feature point and the second feature point of the corresponding connected line are connected to obtain a rerouted line.

[0054] In the case of avoiding marked cells, the shortest path connection between the first feature point and the corresponding second feature point is selected to obtain the re-routing line. When performing the shortest path connection, it is also determined whether the adjacent squares are marked when the shortest path is extended to the lead width. If marked, it is determined whether the mark is the corresponding connected line. If not, the line is corrected to connect to the second feature point. According to the connection path of the first feature point and the second feature point, the lead width wiring connection is performed to obtain the re-routing line.

[0055] The shortest path between the first feature point and the second feature point can be obtained by taking the first feature point as the starting point and the second feature point as the end point, selecting adjacent grids in the wiring area to move closer to the second feature point, and judging whether the width of the connecting line extended to both sides with the adjacent grid as the midpoint is connected to the marked grid, and if the marked grid is not the connecting line to be connected, then replacing the adjacent grid to continue searching for the shortest connection path until the shortest connection path between the first feature point and the second feature point in the wiring area is obtained.

[0056] When obtaining the shortest path, a grid maze algorithm may be used, such as a method of traversing all feasible paths between the first feature point and the second feature point to find the shortest path.

[0057] S6. Repeat steps S4 and S5 until all leads and connecting lines are connected, restore the marking points of the grid and the rewiring lines to graphics, obtain a rewiring drawing, and the bare crystal to be processed and the connecting lines in the rewiring drawing are restored to a fully connected state.

[0058] In order to improve the processing speed, it is preferred that after constructing the basic grid map according to the actual position information of the bare crystal, the actual position information of the first feature point group and the actual position information of the second feature point group, the unit grid map in the basic grid map is first divided. According to the connection relationship of the bare crystal, the basic grid map is divided into multiple unit grid maps, and each grid map contains the offset bare crystal to be processed and the routing connected to the offset bare crystal to be processed; or the bare crystal to be processed and the adjacent bare crystal connected to the offset bare crystal to be processed, which can constitute an independent unit and have no overlapping relationship with other bare crystals. Figure 7 In the example shown, the area surrounded by the bare die without offset forms a unit grid diagram, so that there is no overlapping relationship between the unit grid diagrams; Figure 8 In the example shown, the area surrounded by the bare crystal by the routing forms a unit grid diagram, and there is no overlapping relationship between the unit grid diagrams. The unit grid diagrams are rewired in parallel, that is, multiple unit grid diagrams are processed simultaneously. For each unit grid diagram, the actual coordinate information of the first feature point of each lead of the bare crystal in the unit grid diagram and the coordinate information set of the connecting line to be connected corresponding to the first feature point are obtained respectively, and it is determined whether there is an intersection between the actual coordinate information of the first feature point of the lead and the coordinate information set of the corresponding connecting line. For the first feature point of the lead that does not have an intersection with the coordinate set of the corresponding connecting line, the actual position coordinates of the first feature point of the lead and the actual position coordinates of the second feature point of the corresponding connecting line are obtained, and the shortest path between the first feature point and the second feature point is selected to connect the first feature point of the lead and the corresponding second feature point of the connecting line while avoiding the marked squares.

[0059] like Figure 8The line rewiring device shown includes an information acquisition unit, a graphics processing unit, a grid map construction unit, a rewiring processing unit and an image restoration unit.

[0060] The information acquisition unit is used to acquire and receive the original image file and the deflection information of the bare crystal.

[0061] The graphics processing unit obtains actual position information of the bare die, initial position information of the first feature point, and initial position information of the second feature point according to the original image file and the deflection information of the bare die.

[0062] The grid construction unit obtains a basic grid map according to the information of the graphics processing unit. The grid map is marked according to the actual position information of the bare die and the connection line. The marked position in the grid map is the non-routable area, and the unmarked area is the routable area. Each square represents a coordinate point.

[0063] The rewiring processing unit obtains the actual coordinate information of the first feature point of each lead of the bare crystal in the basic grid and the coordinate information set of the connecting lines to be connected corresponding to the first feature point based on the basic grid diagram, and determines whether there is an intersection between the actual coordinate information of the first feature point and the coordinate information set of the corresponding connecting line; when there is no intersection between the actual coordinate of the first feature point and the coordinate set of the corresponding connecting line, the first feature point and the corresponding second feature point are connected to obtain the rewiring line.

[0064] The image restoration unit restores the marking points of the grid and the rewiring lines into graphics to obtain a rewiring drawing file.

[0065] The line rewiring device comprises a unit grid map acquisition unit, which is used to divide a plurality of unit grid maps according to the actual positions between the bare crystal to be processed and other bare crystals in the basic grid map, so as to perform parallel processing on the unit grid maps.

[0066] like Fig. 9 As shown, a rewiring processing system includes a pattern acquisition device, a routing rewiring device, and a pattern exposure device.

[0067] The graphic acquisition device acquires the actual position information of the bare crystal and outputs it to the routing rewiring device. The routing rewiring device obtains the rewiring drawing based on the actual position information of the bare crystal and the design drawing of the bare crystal and the connecting line and outputs it to the graphic exposure device. The graphic exposure device performs exposure operation according to the rewiring drawing to realize the graphic transfer of the rerouted line.

Claims

1. A line rewiring method, characterized in that: S1. Based on the original drawing, initial position information of a first feature point group of a bare die to be processed and initial position information of a second feature point group of connecting lines connected to the leads of the bare die to be processed in the original drawing are obtained; S2, obtaining deflection information of the bare crystal, and obtaining actual position information of the bare crystal, actual position information of the first feature point group, and actual position information of the second feature point group according to the deflection information of the bare crystal; S3, constructing a basic grid map according to the actual position information of the bare die, the actual position information of the first feature point group, and the actual position information of the second feature point group; S4, obtaining the actual coordinate information of the first feature point of each lead of the bare crystal to be processed in the basic grid and the coordinate information set of the connected line to be connected corresponding to the first feature point, and determining whether there is an intersection between the actual coordinate information of the first feature point and the coordinate information set of the corresponding connected line; S5. When there is no intersection between the actual coordinates of the first feature point and the coordinate set of the corresponding connecting line, the shortest path between the first feature point and the corresponding second feature point is selected to connect and obtain the re-routing line. When performing the shortest path connection, it is also determined whether the adjacent squares are marked when the shortest path is extended to the lead width. If it is marked, it is determined whether the mark is the corresponding connecting line. If it is not a connecting line, the line is corrected to connect to the second feature point. According to the connection path between the first feature point and the second feature point, the wiring connection of the lead width is performed to obtain the re-routing line. S6. Repeat steps S4 and S5 until all leads and connecting lines are connected, and the marking points of the grid and the rewiring lines are restored to graphics to obtain a rewiring drawing file.

2. The line rewiring method according to claim 1, characterized in that: The first feature point in the first feature point group and the second feature point in the second feature point group are center points of intersection areas of the leads of the bare die to be processed and the corresponding connected connecting lines.

3. The line rewiring method according to claim 2, characterized in that: The connecting line and the lead pattern of the bare crystal to be processed are judged whether they intersect by a graphic intersection method, the graphic intersection area of ​​the lead of the bare crystal to be processed and the connecting line is obtained, and the position information of the center point of the graphic intersection area is obtained.

4. The line rewiring method according to claim 1, characterized in that: When constructing the basic grid map in step S3, the actual position information of the bare die and the connecting lines is marked in the grid map. The marked position in the grid map is the non-routable area, and the unmarked area is the routable area. Each square represents a coordinate point.

5. The line rewiring method according to claim 1, characterized in that: After the basic grid map is obtained, the basic grid map is divided into a plurality of unit grid maps according to the connection relationship of the bare crystals, and the unit grid maps are rewired in parallel.

6. A line rewiring device using any line rewiring method as claimed in any one of claims 1 to 5, characterized in that: The line rewiring device comprises an information acquisition unit, a graphics processing unit, a grid map construction unit, a rewiring processing unit and an image restoration unit; The information acquisition unit is used to acquire and receive the original image file and the deflection information of the bare crystal; The graphics processing unit obtains the actual position information of the bare die, the initial position information of the first feature point and the initial position information of the second feature point according to the original image file and the deflection information of the bare die; The grid construction unit obtains a basic grid map according to information of the graphics processing unit; The rewiring processing unit obtains the actual coordinate information of the first feature point of each lead of the bare crystal in the basic grid and the coordinate information set of the connecting line to be connected corresponding to the first feature point according to the basic grid diagram, and determines whether there is an intersection between the actual coordinate information of the first feature point and the coordinate information set of the corresponding connecting line; when there is no intersection between the actual coordinate of the first feature point and the coordinate set of the corresponding connecting line, the first feature point and the corresponding second feature point are connected to obtain the rewiring line; The image restoration unit restores the marking points of the grid and the rewiring lines into graphics to obtain a rewiring drawing file.

7. The line rewiring device according to claim 6, characterized in that: It includes a unit grid map acquisition unit, which is used to divide a plurality of unit grid maps according to the actual positions between the bare crystal to be processed and other bare crystals in the basic grid map, so that the rewiring processing unit can process the unit grid maps in parallel.

8. A rewiring processing system, characterized in that: The rewiring processing system comprises a pattern acquisition device, a line rewiring device, and a pattern exposure device. The line rewiring device is any one of the line rewiring devices described in claims 6-7.

9. The rewiring processing system according to claim 8, characterized in that: The graphic acquisition device acquires the actual position information of the bare crystal and outputs it to the line rewiring device. The line rewiring device obtains the rewiring drawing based on the actual position information of the bare crystal and the design drawing of the bare crystal and the connecting line and outputs it to the graphic exposure device. The graphic exposure device performs exposure operation according to the rewiring drawing to realize the graphic transfer of the rerouted line.

Images