A control circuit for avoiding RAM read-write conflicts in display drivers

Abstract

The present invention belongs to the field of communication technology, and in particular, relates to a control circuit for avoiding RAM read-write conflicts for display driving. It comprises: N groups of RAM signal lines, respectively connected to the RAM signal preprocessing module; wherein each group of the RAM signal lines comprises a clock, an address and a group of input and / or output data buses; each clock signal represents an action with its effective edge; a RAM signal preprocessing module, through which each action signal is captured and released to the RAM module in sequence according to its order or priority; a RAM module, connected to the RAM signal preprocessing module through a RAM interface. The present invention solves the problem of conflict between RAM external read-write and internal display read without increasing the area.

Description

Technical Field

[0001] The invention belongs to the field of communication technology, and in particular relates to a control circuit for avoiding RAM read-write conflicts for display driving. Background Art

[0002] In recent years, with the rapid development of industries such as communications, computers, and consumer electronics, people's channels for obtaining information are gradually increasing, people's demand for electronic products is increasing, and the demand for large dot matrix displays as information interaction windows for various electronic devices is also increasing.

[0003] Generally speaking, the display data of the dot matrix screen is stored in the RAM built into or external to the driver chip. Due to the requirement of high refresh rate, it is required to simultaneously write the display data externally and read the display data internally to drive the display screen. If the display driver chip clock is built-in and independent of the communication clock, the conflict between these two RAM read and write tasks is inevitable. The solutions commonly adopted in the prior art are: 1) RAM does not use the standard six-tube unit, and the RAM itself has an additional set of independent read-out terminals for display, such as Figure 1 As shown in the figure, an additional read-out end is added to the standard six-tube RAM structure for display; 2) A dual RAM solution is used to make the data being displayed and the RAM being displayed independent of each other. Two RAMs are used to store two frames of images. When the current frame is displayed, the written data is stored in another RAM. After entering the next frame, the functions of the two RAMs are interchanged.

[0004] However, both of the above solutions will lead to a proportional increase in RAM area. Since the RAM area required by a large dot matrix is ​​very large, the chip area will increase significantly. Therefore, a control circuit for avoiding RAM read-write conflicts for display drive is proposed to solve the problem of RAM external read-write and internal display read conflicts without increasing the area. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a control circuit for avoiding RAM read-write conflicts for display driving, so as to solve the conflict problem between RAM external read-write and internal display read without increasing the area.

[0006] In order to solve the above technical problems, the present invention provides a control circuit for avoiding RAM read-write conflicts for display driving, comprising:

[0007] N groups of RAM signal lines are respectively connected to the RAM signal preprocessing module; each group of RAM signal lines includes a clock, an address and a group of input and / or output data buses; each clock signal represents an action with its effective edge;

[0008] A RAM signal preprocessing module, through which each action signal is captured and released to the RAM module in sequence according to the order or priority thereof;

[0009] The RAM module is connected to the RAM signal preprocessing module via a RAM interface.

[0010] Preferably, the RAM signal preprocessing module includes N clock units, one of the clock units is allocated to each group of RAM signal lines, and the clock units include: a capture trigger D1, a blocking trigger D2, a release trigger D3, a NOT gate T1, a delay unit X1, an AND gate AND1, an OR gate OR1, a delay unit X2, an AND gate AND2 and a delay unit X3; the D end of the capture trigger D1 is connected to a power supply, the CLK end of the capture trigger D1 is connected to an input clock, the R end of the capture trigger D1 is connected to the R end of the blocking trigger D2, the input end of the delay unit X3 and the output end of the AND gate AND2, and the Q end of the capture trigger D1 is connected to a capture flag, the input end of the delay unit X1 and the blocking trigger The CLK end of the blocking trigger D2 is connected to the blocking flag, the Q end of the blocking trigger D2 is connected to the input end of the NOT gate T1 and the D end of the release trigger D3, the CLK end of the release trigger D3 is connected to the release clock, the R end of the release trigger D3 is connected to the output end of the delay unit X3, the output end of the NOT gate T1 and the output end of the delay unit X1 are respectively connected to the two input ends of the AND gate AND1, the output end of the AND gate AND1 and the Q end of the release trigger D3 are respectively connected to the two input ends of the OR gate OR1, the output end of the OR gate OR1 is connected to the action pulse and the input end of the delay unit X2, and the input end and output end of the delay unit X2 are respectively connected to the two input ends of the AND gate AND2.

[0011] Preferably, the delay unit X2 is a configurable delay unit.

[0012] Preferably, the logic process of the clock unit includes: first capturing the action pulse of the input clock, and then determining whether the current pulse signal is being blocked; if not, directly providing an action signal to the processing of the RAM module; otherwise, waiting for the blockage to be released before providing an action signal to the processing of the RAM module; finally, when the action is completed, it can be automatically reset after a delay.

[0013] Preferably, for one group of the RAM signal lines, the capture flag and action pulse output by the clock unit corresponding to the remaining N-1 groups of RAM signal lines can be used to generate a blocking flag and a release clock of the clock unit in the group through combinational logic; and the signal lines other than the clock signal in each group of RAM signal lines are selected to be connected to the RAM module when the action pulse of the RAM signal line in the group is valid.

[0014] Preferably, when there are two groups of the RAM signal lines, the display driving functions of display output and communication reading and writing are realized respectively, and the logic of the display driving function includes: clock unit one, clock unit two, RAM signal line one and RAM signal line two; the input clock of the clock unit one is connected to the clock one in the RAM signal line one, the capture flag and the action pulse output by the clock unit one are connected to the two input ends of the OR gate OR2, the output end of the OR gate OR2 generates the blocking flag input by the clock unit two, the action pulse output by the clock unit one is connected to the NOT gate T2 and the delay unit X5 in sequence to generate the release clock input by the clock unit two; the input clock of the clock unit two is connected to the clock two in the RAM signal line two, the capture flag output by the clock unit two is connected to the two input ends of the OR gate OR2, and the blocking flag is generated by the output end of the OR gate OR2. The flag and action pulse are connected to the two input ends of the OR gate OR3, the output end of the OR gate OR3 generates the blocking flag input by the clock unit one, and the action pulse output by the clock unit two is connected to the NOT gate T3 and the delay unit X4 in sequence to generate the release clock input by the clock unit one; the action pulses output by the clock unit one and the clock unit two are connected to the two input ends of the OR gate OR4, and the output end of the OR gate OR4 outputs the clock to the RAM module; the RAM signal line one and the RAM signal line two are respectively connected to the two input ends of the selector MUX, the output end of the selector MUX is connected to the RAM module, and the two control ends of the selector MUX are respectively connected to the action pulses output corresponding to the clock unit one and the clock unit two.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The RAM signal preprocessing module in the front of the present invention will capture each action signal and release it to the RAM module in the back stage in sequence according to its order or priority. In this way, it is only necessary to ensure that the read and write frequency of each group of signal lines does not exceed the maximum read and write frequency of the RAM divided by N to ensure the conflict-free nature of the entire RAM as a whole, so as to solve the RAM read and write conflict problem without increasing the chip area; the present invention does not expose the timing details to the outside (the timing details are encapsulated externally), which reduces the application cost; the present invention is universal, has no requirements for the RAM itself, and can use the RAM array optimized by the process factory or the external RAM; the present invention is implemented using pure digital logic and has no special process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A RAM structure diagram with an additional read port added in the prior art of the present invention.

[0018] Figure 2 This is a structural block diagram of a control circuit for avoiding RAM read-write conflicts according to the present invention.

[0019] Figure 3 A logic circuit diagram of a clock unit provided by the present invention.

[0020] Figure 4 A logic processing flow chart of the clock unit provided by the present invention.

[0021] Figure 5 A logic circuit diagram of two groups of RAM signal lines provided by the present invention to realize the display driving function. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0023] like Figure 2 As shown, the embodiment of the present invention provides a control circuit for avoiding RAM read-write conflicts for display driving. Considering that the latter stage is a common RAM module, the RAM module is only required to have basic read-write functions, no additional functions are required, and no specific interface is required. However, only one read-write operation can be performed at the same time, so various designs of on-chip and off-chip RAM modules can be used; including:

[0024] N groups of RAM signal lines are respectively connected to the RAM signal preprocessing module; each group of RAM signal lines includes a clock, an address and a group of input and / or output data buses; each clock signal represents an action with its effective edge;

[0025] A RAM signal preprocessing module, through which each action signal is captured and released to the RAM module in sequence according to the order or priority thereof;

[0026] The RAM module is connected to the RAM signal preprocessing module via a RAM interface.

[0027] like Figure 3As shown, the RAM signal preprocessing module includes N clock units, each group of RAM signal lines is correspondingly allocated with one clock unit, and the clock unit includes: a capture trigger D1, a blocking trigger D2, a release trigger D3, a NOT gate T1, a delay unit X1, an AND gate AND1, an OR gate OR1, a delay unit X2, an AND gate AND2 and a delay unit X3; the D end of the capture trigger D1 is connected to a power supply, the CLK end of the capture trigger D1 is connected to an input clock, the R end of the capture trigger D1 is connected to the R end of the blocking trigger D2, the input end of the delay unit X3 and the output end of the AND gate AND2, and the Q end of the capture trigger D1 is connected to a capture flag, the input end of the delay unit X1 and the output end of the blocking trigger D 2, the D end of the blocking trigger D2 is connected to the blocking flag, the Q end of the blocking trigger D2 is connected to the input end of the NOT gate T1 and the D end of the release trigger D3, the CLK end of the release trigger D3 is connected to the release clock, the R end of the release trigger D3 is connected to the output end of the delay unit X3, the output end of the NOT gate T1 and the output end of the delay unit X1 are respectively connected to the two input ends of the AND gate AND1, the output end of the AND gate AND1 and the Q end of the release trigger D3 are respectively connected to the two input ends of the OR gate OR1, the output end of the OR gate OR1 is connected to the action pulse and the input end of the delay unit X2, and the input end and output end of the delay unit X2 are respectively connected to the two input ends of the AND gate AND2.

[0028] Among them, D1 is a capture trigger, which is used to mark whether a signal is captured; D2 is a blocking trigger, which is used to mark whether the signal is blocked; D3 is a release trigger, which is used to provide a release signal. The NOT gate T1, the delay unit X1, the AND gate AND1, and the OR gate OR1 form an action structure, which is used to provide an action signal to the subsequent RAM. The delay unit X2, the AND gate AND2, and the delay unit X3 form a reset structure, which is used to automatically reset after the action is completed.

[0029] The external clock enters from the input clock port, and the capture trigger D1 is commanded to act after the effective edge of the signal line input clock; then, if there is no blocking flag, the action will be generated directly after the delay of the delay unit X1, otherwise, the blocking trigger D2 is set to 1 to prevent the action from occurring; then, wait for the release signal, when the release signal appears, the Q end of the release trigger D3 generates a high level, and the action occurs; finally, when the action occurs, the reset structure will automatically reset the structure after a delay time, which is generated by the delay unit X2 and should not be less than the processing time of the subsequent RAM. In addition, the delay unit X3 is used to avoid glitches when the action signal is turned off, and its delay should ensure that the reset of the release trigger D3 is later than the blocking trigger D2. Reset causes the action pulse to be quiet.

[0030] Furthermore, the delay unit X2 is a configurable delay unit, which is used to estimate the execution time to improve the yield rate, speed grade the chip or adapt to a variety of external RAMs.

[0031] like Figure 4 As shown, the logical process of the clock unit includes: first capturing the action pulse of the input clock, and then determining whether the current pulse signal is being blocked; if not, directly providing an action signal to the processing of the RAM module; otherwise, waiting for the blockage to be released before providing an action signal to the processing of the RAM module; finally, when the action is completed, it can be automatically reset after a delay.

[0032] Furthermore, for one group of the RAM signal lines, the capture flag and action pulse output by the clock unit corresponding to the remaining N-1 groups of RAM signal lines can be used to generate a blocking flag and a release clock of the clock unit in the group through combinational logic; and the signal lines other than the clock signal in each group of RAM signal lines are selected to be connected to the RAM module when the action pulse of the group is valid.

[0033] like Figure 5 As shown, when there are two groups of RAM signal lines, the display driving functions of display output and communication reading and writing are realized respectively, and the logic of the display driving function includes: clock unit 1, clock unit 2, RAM signal line 1 and RAM signal line 2; the input clock of the clock unit 1 is connected to the clock 1 in the RAM signal line 1, the capture flag and the action pulse output by the clock unit 1 are connected to the two input ends of the OR gate OR2, the output end of the OR gate OR2 generates the blocking flag input by the clock unit 2, the action pulse output by the clock unit 1 is connected to the NOT gate T2 and the delay unit X5 in sequence to generate the release clock input by the clock unit 2; the input clock of the clock unit 2 is connected to the clock 2 in the RAM signal line 2, the capture flag output by the clock unit 2 is connected to the two input ends of the OR gate OR2, and the blocking flag is generated by the output end of the OR gate OR2. The flag and action pulse are connected to the two input ends of the OR gate OR3, the output end of the OR gate OR3 generates the blocking flag input by the clock unit one, and the action pulse output by the clock unit two is connected to the NOT gate T3 and the delay unit X4 in sequence to generate the release clock input by the clock unit one; the action pulses output by the clock unit one and the clock unit two are connected to the two input ends of the OR gate OR4, and the output end of the OR gate OR4 outputs the clock to the RAM module; the RAM signal line one and the RAM signal line two are respectively connected to the two input ends of the selector MUX, the output end of the selector MUX is connected to the RAM module, and the two control ends of the selector MUX are respectively connected to the action pulses output corresponding to the clock unit one and the clock unit two.

[0034] In the application scenario of display driver, there are two groups of RAM signal lines, display output and communication reading and writing. In this case, the blocking flag of each group is the sum of the capture flag and action pulse of the other group; the release clock is the end of the action pulse of the other group plus a certain delay, and the delay is used to ensure that the release clock appears after the end of the blocking flag. Avoid the situation where the release clock appears before the end of the blocking flag at the end of one group of actions, and the signal of the other group of clocks is received between the release clock and the end of the blocking flag, resulting in the other group of clocks being unable to release after being captured.

[0035] In summary, the present invention focuses on designing a RAM multi-clock conflict avoidance mechanism, which solves the conflict problem while significantly reducing the area compared to previous solutions. The timing details are encapsulated externally, reducing the application cost. It is also versatile and can use on-chip or off-chip RAM.

[0036] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A control circuit for avoiding RAM read-write conflicts for display driving, characterized in that: include: N groups of RAM signal lines are respectively connected to the RAM signal preprocessing modules; Each group of RAM signal lines includes a clock, an address and a group of input and / or output data buses; each clock signal represents an action with its effective edge; A RAM signal preprocessing module, through which each action signal is captured and released to the RAM module in sequence according to the order or priority thereof; A RAM module connected to the RAM signal preprocessing module via a RAM interface; The RAM signal preprocessing module includes N clock units, and each group of RAM signal lines is allocated with one clock unit. The clock units include: a capture trigger D1, a blocking trigger D2, a release trigger D3, a NOT gate T1, a delay unit X1, an AND gate AND1, an OR gate OR1, a delay unit X2, an AND gate AND2 and a delay unit X3; the D end of the capture trigger D1 is connected to a power supply, the CLK end of the capture trigger D1 is connected to an input clock, the R end of the capture trigger D1 is connected to the R end of the blocking trigger D2, the input end of the delay unit X3 and the output end of the AND gate AND2, the Q end of the capture trigger D1 is connected to a capture flag, the input end of the delay unit X1 and the CLK end of the blocking trigger D2, and the blocking trigger D1 is connected to the capture flag. The D end of the device D2 is connected to the blocking flag, the Q end of the blocking trigger D2 is connected to the input end of the NOT gate T1 and the D end of the release trigger D3, the CLK end of the release trigger D3 is connected to the release clock, the R end of the release trigger D3 is connected to the output end of the delay unit X3, the output end of the NOT gate T1 and the output end of the delay unit X1 are respectively connected to the two input ends of the AND gate AND1, the output end of the AND gate AND1 and the Q end of the release trigger D3 are respectively connected to the two input ends of the OR gate OR1, the output end of the OR gate OR1 outputs an action pulse, the action pulse is respectively connected to the input end of the delay unit X2 and one input end of the AND gate AND2, and the output end of the delay unit X2 is connected to the other input end of the AND gate AND2.

2. A control circuit for avoiding RAM read-write conflicts for display driving as claimed in claim 1, characterized in that: The delay unit X2 is a configurable delay unit.

3. A control circuit for avoiding RAM read-write conflicts for display driving as claimed in claim 1, characterized in that: The logic process of the clock unit includes: first capturing the action pulse of the input clock, and then determining whether the current pulse signal is being blocked; if not, directly providing an action signal to the processing of the RAM module; otherwise, waiting for the blockage to be released before providing an action signal to the processing of the RAM module; finally, when the action is completed, it can be automatically reset after a delay.

4. A control circuit for avoiding RAM read-write conflicts for display driving as claimed in claim 1, characterized in that: For one group of the RAM signal lines, the capture flag and action pulse output by the clock unit corresponding to the remaining N-1 groups of RAM signal lines can be used to generate the blocking flag and release clock of the clock unit in the group of RAM signal lines through combinational logic; and the signal lines other than the clock signal in each group of RAM signal lines are selected to be connected to the RAM module when the action pulse of the group of RAM signal lines is valid.

5. A control circuit for avoiding RAM read-write conflicts for display driving as claimed in claim 4, characterized in that: When there are two groups of RAM signal lines, the display driving functions of display output and communication reading and writing are realized respectively, and the logic of the display driving function includes: clock unit 1, clock unit 2, RAM signal line 1 and RAM signal line 2; the input clock of the clock unit 1 is connected to the clock 1 in the RAM signal line 1, the capture flag and the action pulse output by the clock unit 1 are connected to the two input ends of the OR gate OR2, the output end of the OR gate OR2 generates the blocking flag input by the clock unit 2, the action pulse output by the clock unit 1 is connected to the NOT gate T2 and the delay unit X5 in turn to generate the release clock input by the clock unit 2; the input clock of the clock unit 2 is connected to the clock 2 in the RAM signal line 2, the capture flag and the action pulse output by the clock unit 2 are connected to the two input ends of the OR gate OR2, the output end of the OR gate OR2 generates the blocking flag input by the clock unit 2, and the action pulse output by the clock unit 1 is connected to the NOT gate T2 and the delay unit X5 in turn to generate the release clock input by the clock unit 2; the input clock of the clock unit 2 is connected to the clock 2 in the RAM signal line 2, and the capture flag and the action pulse output by the clock unit 2 are connected to the two input ends of the OR gate OR2. The action pulse is connected to the two input ends of the OR gate OR3, and the output end of the OR gate OR3 generates a blocking flag input by the clock unit one. The action pulse output by the clock unit two is sequentially connected to the NOT gate T3 and the delay unit X4 to generate a release clock input by the clock unit one; the action pulses output by the clock unit one and the clock unit two are connected to the two input ends of the OR gate OR4, and the output end of the OR gate OR4 outputs the clock to the RAM module; the RAM signal line one and the RAM signal line two are respectively connected to the two input ends of the selector MUX, and the output end of the selector MUX is connected to the RAM module, and the two control ends of the selector MUX are respectively connected to the action pulses output corresponding to the clock unit one and the clock unit two.

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