Signal processing circuits, memory

Abstract

An embodiment of the present disclosure proposes a signal processing circuit and a memory, including: an instruction decoding circuit; wherein the instruction decoding circuit includes: a preprocessing circuit, used to receive a first chip select signal corresponding to the previous cycle of a current chip select signal, and a first instruction signal corresponding to the previous cycle of the current chip select signal, and perform a logical operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal; an operation circuit, connected to the preprocessing circuit, used to receive the first chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to but not limited to a signal processing circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memory that can transmit data at double the data rate (DDR) have emerged.

[0003] In dynamic random access memory (DRAM), a command address (CMD / ADD) or CA signal can be sampled as an address and decoded as an instruction.

[0004] However, there are still many problems that need to be solved in the current decoding process. Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure provide a signal processing circuit and a memory. In one aspect, the embodiments of the present disclosure provide a signal processing circuit, the signal processing circuit comprising: an instruction decoding circuit; wherein,

[0006] The instruction decoding circuit comprises:

[0007] a preprocessing circuit, configured to receive a first chip select signal corresponding to a previous cycle of a current chip select signal and a first instruction signal corresponding to a previous cycle of the current chip select signal, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal;

[0008] An operation circuit is connected to the preprocessing circuit, and is used to receive the first chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state.

[0009] In the above solution, the preprocessing circuit is specifically configured to receive a first chip select signal and a second chip select signal corresponding to a previous cycle and two previous cycles of a current chip select signal, respectively, and a first instruction signal and a second instruction signal corresponding to a previous cycle and two previous cycles of the current chip select signal, respectively, and perform a logical operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal, and perform a logical operation on the second chip select signal and the second instruction signal to generate a second chip select identification signal;

[0010] The operation circuit is specifically used to receive the first chip select identification signal, the second chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and at least one of the first chip select identification signal and the second chip select identification signal is in a disabled state.

[0011] In the above solution, in the first mode, the period of the current chip select signal is equal to one preset clock period; in the second mode, the period of the current chip select signal is equal to two preset clock periods.

[0012] In the above solution, the pre-processing circuit includes:

[0013] a first preprocessing circuit, configured to receive the first chip select signal and the first instruction signal in the first mode and the first chip select signal and the first instruction signal in the second mode, and generate first chip select identification signals corresponding to the first mode and the second mode respectively;

[0014] The second preprocessing circuit is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate a second chip select identification signal corresponding to the first mode and the second mode respectively.

[0015] In the above solution, the first preprocessing circuit includes:

[0016] a first chip select flag generating circuit, configured to receive the first chip select signal and the first command signal in the first mode and the first chip select signal and the first command signal in the second mode, and generate first intermediate chip select flag signals corresponding to the first mode and the second mode respectively;

[0017] a first selection circuit connected to the first chip select flag generation circuit, configured to output a first intermediate chip select flag signal corresponding to the first mode in the first mode; and output a first intermediate chip select flag signal corresponding to the second mode in the second mode;

[0018] A first sampling circuit is connected to the first selection circuit, and is used to sample the first intermediate chip select identification signal output by the first selection circuit once to obtain the first chip select identification signal corresponding to the first mode, and to sample the first intermediate chip select identification signal output by the first selection circuit twice to obtain the first chip select identification signal corresponding to the second mode.

[0019] In the above solution, the second pre-processing circuit includes:

[0020] a second chip select flag generating circuit, configured to receive the second chip select signal and the second command signal in the first mode and the second chip select signal and the second command signal in the second mode, and generate second intermediate chip select flag signals corresponding to the first mode and the second mode respectively;

[0021] a second selection circuit connected to the second chip select identification generating circuit, configured to output a second intermediate chip select identification signal corresponding to the first mode in the first mode; and output a second intermediate chip select identification signal corresponding to the second mode in the second mode;

[0022] A second sampling circuit is connected to the second selection circuit, and is used to sample the second intermediate chip select identification signal output by the second selection circuit once to obtain the second chip select identification signal corresponding to the first mode, and sample the second intermediate chip select identification signal output by the second selection circuit twice to obtain the second chip select identification signal corresponding to the second mode.

[0023] In the above solution, the second chip select flag generating circuit includes:

[0024] a first NOR gate, configured to perform a NOR logic operation on the second instruction signal and the second chip select signal in the first mode;

[0025] a first NOT gate, configured to perform a NOT logic operation on a logic operation result of the first NOR gate, and output a corresponding second intermediate chip select identification signal in the first mode;

[0026] The second NOR gate is used to perform a NOR logic operation on the second instruction signal and the second chip select signal in the second mode, and output a corresponding second intermediate chip select identification signal in the second mode.

[0027] In the above solution, the second chip select signal in the first mode overlaps with the first chip select signal in the second mode; the second command signal in the first mode overlaps with the first command signal in the second mode;

[0028] The first chip select flag generating circuit includes:

[0029] a third NOR gate, configured to perform a NOR logic operation on the first command signal in the first mode and the first chip select signal;

[0030] a second NOT gate, configured to perform a NOT logic operation on a logic operation result of the third NOR gate, and output a first intermediate chip select identification signal corresponding to the first mode;

[0031] The third sampling circuit is used to perform a sampling process on the inverse signal of the second intermediate chip select identification signal generated by the second chip select identification generation circuit in the first mode to obtain the first intermediate chip select identification signal corresponding to the second mode.

[0032] In the above solution, the first chip select flag generation circuit / the second chip select flag generation circuit includes:

[0033] The third selection circuit is connected to the input end of the corresponding NOR gate and is used to output the first command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the first layout is laid out; and to output the second command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the second layout is laid out.

[0034] In the above solution, the operation circuit includes:

[0035] a first arithmetic circuit, connected to both the first pre-processing circuit and the second pre-processing circuit, configured to receive a first chip select identification signal and a second chip select identification signal corresponding to the first mode, a first mode flag signal, the current chip select signal, and a current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, wherein the first mode flag signal indicates that the signal processing circuit is in the first mode;

[0036] The second operation circuit is connected to both the first preprocessing circuit and the second preprocessing circuit, and is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the second mode, the second mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal. The second mode flag signal indicates that the signal processing circuit is in the second mode.

[0037] In the above solution, the first operation circuit / the second operation circuit includes: an OR gate, a first NAND gate, a second NAND gate and a fourth NOR gate, wherein:

[0038] The input end of the OR gate is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the first mode / second mode, and the output end is connected to one input end of the first NAND gate;

[0039] Another input end of the first NAND gate is used to receive the first mode flag signal / the second mode flag signal, and an output end is connected to the first input end of the fourth NOR gate;

[0040] The input end of the second NAND gate is used to receive the current chip select signal and the current command signal, and the output end is connected to the second input end of the fourth NOR gate;

[0041] The output end of the fourth NOR gate is used to output the decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal.

[0042] In the above solution, the signal processing circuit further includes: a clock processing circuit; wherein,

[0043] The clock processing circuit is used to receive a source clock signal and output an initial clock signal and an initial complementary clock signal; wherein, the clock period of the source clock signal is the same as the preset clock period, the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

[0044] In the above solution, the signal processing circuit further includes:

[0045] a first receiving circuit, configured to receive the initial clock signal and the initial complementary clock signal, and output a first clock signal and a first complementary clock signal, wherein a clock period of each of the first clock signal and the first complementary clock signal is twice a clock period of the source clock signal;

[0046] a second receiving circuit, configured to receive a source command address signal and output the initial command address signal;

[0047] The third receiving circuit is used to receive the source chip select signal and output the initial chip select signal.

[0048] In the above solution, the signal processing circuit further includes:

[0049] a chip select processing circuit, connected to the first receiving circuit and the third receiving circuit, configured to receive the initial chip select signal, sample the initial chip select signal once using the first clock signal / first complementary clock signal to obtain the second chip select signal; sample the second chip select signal once using the first clock signal / first complementary clock signal to obtain the first chip select signal; and sample the first chip select signal once using the first clock signal / first complementary clock signal to obtain the current chip select signal;

[0050] The command address processing circuit is connected to the first receiving circuit and the second receiving circuit, and is used to receive the initial command address signal, sample the initial command address once using the first clock signal / first complementary clock signal to obtain the second instruction signal; sample the second instruction number once using the first clock signal / first complementary clock signal to obtain the first instruction signal; and sample the first instruction signal once using the first clock signal / first complementary clock signal to obtain the current instruction signal.

[0051] Another aspect of the embodiments of the present disclosure further provides a memory, which includes the signal processing circuit as described in any of the above solutions.

[0052] In the above solution, the memory includes: the fifth generation double data rate synchronous dynamic random access memory DDR5.

[0053] In the disclosed embodiment, the preprocessing circuit receives the first chip select signal and the first instruction signal corresponding to the previous cycle of the current chip select signal, and obtains the first chip select identification signal after a logical operation. The operation circuit jointly determines whether to generate a decoding command corresponding to the current chip select signal based on the state of the first chip select identification signal and the state of the current chip select signal. That is to say, the decoding command corresponding to the current chip select signal is at least jointly determined based on the current chip select signal and the chip select signal and instruction signal corresponding to the previous cycle of the current chip select signal. This can improve the problem of the second cycle of the non-target on-chip terminal resistance command being incorrectly decoded, thereby improving the success rate of decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of the structure of a signal processing circuit provided in an embodiment of the present disclosure;

[0055] Figure 2 A schematic diagram of the structure of an instruction decoding circuit provided in an embodiment of the present disclosure;

[0056] Figure 3 A signal timing diagram provided in an embodiment of the present disclosure Figure 1 ;

[0057] Figure 4 A signal timing diagram provided in an embodiment of the present disclosure Figure 2 ;

[0058] Figure 5 A signal timing diagram provided in an embodiment of the present disclosure Figure 3 ;

[0059] Figure 6 A signal timing diagram provided in an embodiment of the present disclosure Figure 4 ;

[0060] Figure 7 A schematic diagram of the framework structure of a signal processing circuit provided in an embodiment of the present disclosure;

[0061] Figure 8 A signal timing diagram provided in an embodiment of the present disclosure Figure 5 ;

[0062] Figure 9 A signal timing diagram provided in an embodiment of the present disclosure Figure 6 ;

[0063] Figure 10a A schematic structural diagram of a signal processing circuit provided in an embodiment of the present disclosure;

[0064] Figure 10b A detailed structural diagram of an instruction decoding circuit provided in an embodiment of the present disclosure;

[0065] Figure 11 A signal timing diagram provided in an embodiment of the present disclosure Figure 7 ;

[0066] Figure 12 A signal timing diagram provided in an embodiment of the present disclosure Figure 8 ;

[0067] Figure 13 A signal timing diagram provided in an embodiment of the present disclosure Figure 9 ;

[0068] Figure 14 10 is a signal timing diagram provided in an embodiment of the present disclosure;

[0069] Figure 15 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] To make the technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0071] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0072] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0073] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0074] In the embodiments of the present disclosure, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0075] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0076] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0077] The memory involved in the embodiments of the present disclosure includes but is not limited to a dynamic random access memory, and the dynamic random access memory will be used as an example for exemplary description hereinafter.

[0078] Taking the fifth generation DDR (DDR5, 5th DDR) DRAM as an example, the CA signal can be used as both address sampling and instruction sampling and decoding. The CA signal here is a general term for various command address signals of DRAM, which may include command signals such as row address strobe (RAS), column address strobe (CAS), write command (WE, Write), activate command (ACT, Active), and may also include address signals such as A13 to A0. In addition, in actual applications, the number of bits of the address signal included in the command address signal may be determined according to the specifications of the DRAM, and the embodiments of the present disclosure do not impose any limitations.

[0079] For example, Figure 1 , which shows a schematic diagram of the structure of a signal processing circuit, which includes: a clock processing circuit 101, a first receiving circuit 102, a second receiving circuit 103, a third receiving circuit 104, a fourth sampling circuit 105, a fifth sampling circuit 106, a sixth sampling circuit 107, a seventh sampling circuit 108, an eighth sampling circuit 109, a ninth sampling circuit 110, a first AND gate 111, a second AND gate 112, a third AND gate 113, and an instruction decoding circuit 114. Among them, the fourth sampling circuit 105, the fifth sampling circuit 106, the eighth sampling circuit 109, and the ninth sampling circuit 110 can be composed of D-type flip-flops, and the sixth sampling circuit 107 and the seventh sampling circuit 108 can be composed of D-type flip-flops and inverters. In addition, as for the instruction decoding circuit 114, it can be composed of logic components such as a three-input NAND gate and a two-input NOR gate, see for details. Figure 2 shown.

[0080] exist Figure 1In the embodiment, the input signal of the clock processing circuit 101 is the source clock signal CLK, and the output signals are the initial clock signal CK_t and the initial complementary clock signal CK_c. The input signals of the first receiving circuit 102 are the initial clock signal CK_t and the initial complementary clock signal CK_c, and the output signals are the first clock signal PCLK_E and the first complementary clock signal PCLK_O. The input signals of the second receiving circuit 103 are the source command address signal CA[13:0] and the reference signal VREFCA, and the output signal is the initial command address signal CA. The input signals of the third receiving circuit 104 are the source chip select signal CS_n and the reference signal VREFCA, and the output signal is the initial chip select signal CS. The chip select processing circuit includes a sixth sampling circuit 107, a seventh sampling circuit 108, an eighth sampling circuit 109, and a ninth sampling circuit 110. The chip select processing circuit receives the initial chip select signal CS, and samples the initial chip select signal CS once by using the first clock signal PCLK_E and the first complementary clock signal PCLK_O through the sixth sampling circuit 107 and the seventh sampling circuit 108 to obtain the first chip select even signal PCS_E and the first chip select odd signal PCS_O; samples the first chip select even signal PCS_E and the first chip select odd signal PCS_O by using the first clock signal PCLK_E and the first complementary clock signal PCLK_O respectively through the eighth sampling circuit 109 and the ninth sampling circuit 110 to obtain the second chip select even signal PCS_ED and the second chip select odd signal PCS_OD; and uses the first AND gate 111 to convert the first clock signal PCLK_E and the first complementary clock signal PCLK_O into the first chip select even signal PCS_ED and the second chip select odd signal PCS_OD; The first chip select even signal PCS_ED is logically operated on the first complementary clock signal PCLK_E to obtain the third chip select even signal CS_CLK_E, and the first chip select odd signal PCS_OD is logically operated on the first complementary clock signal PCLK_O by the second AND gate 112 to obtain the third chip select odd signal CS_CLK_O; the first clock signal PCLK_E is used to sample the initial command address signal CA through the fourth sampling circuit 105 to obtain the initial instruction even signal CA[4:0]_1T_E; the first complementary clock signal PCLK_O is used to sample the initial command address signal CA through the fifth sampling circuit 106 to obtain the initial instruction odd signal CA[4:0]_1T_O.

[0081] Then, the instruction decoding circuit 114 decodes CA[4:0]_1T_E, CA[4:0]_1T_O, PCS_ED, PCS_OD, CS_CLK_O, and CS_CLK_E to obtain the instruction even signal CMD_E and the instruction odd signal CMD_O. Finally, the third AND gate 113 of the logic gate circuit performs a logical operation on CMD_E and CMD_O to obtain the target instruction signal CMD. It should be noted that CA[13:0] here represents a group of signals, collectively referred to as CA[0], CA[1], ..., CA

[13] . Accordingly, the second receiving circuit 103 actually includes 14 receiving circuits and output lines, and even the subsequent sampling circuits are 14, which correspond one-to-one to CA[0], CA[1], ..., CA

[13] .

[0082] based on Figure 1 The signal processing circuit shown in FIG. 1 has a corresponding signal timing diagram as shown in FIG. Figure 3 as well as Figure 4 As shown, Figure 3 The figure shows the timing diagram of each signal when the effective pulse width of the CS signal is the width of one preset clock cycle. It should be noted that in the embodiment of the present disclosure, the signal processing circuit here can be applied to a command signal of one preset clock cycle (represented by 1N Mode), indicating that the target command signal CMD only includes a valid command of one preset clock cycle. Figure 3 The timing diagram in 1NMode is shown; the signal processing circuit here can also be applied to the command signal of two preset clock cycles (indicated by 2NMode), indicating that the target command signal CMD includes a valid command of 2 preset clock cycles. Figure 4 The figure below shows the timing diagram in 2N Mode.

[0083] exist Figure 3In the embodiment, the initial clock signal is represented by CK_t, the first clock signal is represented by PCLK_E, the first complementary clock signal is represented by PCLK_O, and the clock period of the CK_t signal is equal to the preset clock period, and the clock periods of the PCLK_E signal and the PCLK_O signal are both twice the preset clock period; the initial command address signal is represented by CA, and CA may include Cy, Cz, C0, C1, C2 and C3; the initial chip select signal is represented by CS, the first chip select even signal is represented by PCS_E, and the first chip select odd signal is represented by PCS_O The CS signal is sampled on the rising edge of the PCLK_E signal to produce the first chip select even signal, represented by PCS_E. This signal is an active-high pulse with a pulse width twice the preset clock period. The CS signal is sampled on the rising edge of the PCLK_O signal to produce the first chip select odd signal, represented by PCS_O, a low-level signal. The CA signal is sampled on the rising edge of the PCLK_E signal to produce the initial instruction even signal, represented by CA[4:0]_1T_E. The PCS_ODD signal is the delayed output of the PCS_OD signal and is used to perform a logical AND operation with the PCS_OD signal and the PCLK_O clock signal to produce two valid pulses of the CS_CLK_O clock. Figure 4 The diagram shows the timing of each signal when the effective pulse width of the CS signal is 2 preset clock cycles, that is, in the 2N Mode, which will not be described in detail here.

[0084] In the above embodiment, the initial clock signal CK_t and the initial complementary clock signal CK_c are divided into the first clock signal PCLK_E and the first complementary clock signal PCLK_O after the first receiving circuit 102, thereby sampling the initial command address signal CA. The normal command (normal CMD) and the non-target on-chip termination resistance command (NT ODT CMD, NotTarget On Die Termination Command) in DDR5 use the first cycle of its CA signal as the instruction and address, and the second cycle as the remaining address. Therefore, the DDR5 design requires two-stage D-type flip-flop sampling, and then uses them as the address information of the two cycles respectively. For instructions, it is necessary to use the first-stage CA signal for combinational logic decoding, and then perform second-stage sampling of the decoded CMD signal to align with the sampling address of the second cycle. The normal CMD here can be understood as normal read and write instructions, and NT ODT CMD can be understood as non-target related instructions.

[0085] In the above embodiment, a pulsed CMD signal is generated by applying simple PCS_ED / PCS_OD and PCLK_E / PCLK_O combinational logic to generate the CS_CLK_O / CS_CLK_E sampling instructions, which are then ANDed with PCS_OD / PCS_ED. For normal CMD, decoding occurs when the CS signal is low. Regardless of 1N or 2N Mode, the CS signal is low only during the first cycle. Figure 5 It shows that in 1N Mode, the CS signal is at a low level in two consecutive preset clock cycles under NT ODT CMD. Since the CS signal is at a low level in two consecutive cycles under NT ODT CMD, according to the signal processing circuit provided in the above embodiment, the CS signal in the second cycle under NT ODT CMD will be incorrectly decoded as an instruction. Figure 6 For NT ODT CMD, the CS signal is low for two consecutive cycles, which is used as a mark to distinguish the secondary signal as NT ODT CMD. However, during the second cycle when the CS signal is low, it will be mistakenly decoded as a decoding signal, resulting in incorrect decoding.

[0086] Based on the above problems, a signal processing circuit is proposed in the embodiment of the present disclosure, such as Figure 7 As shown, including:

[0087] Instruction decoding circuit 114; wherein the instruction decoding circuit 114 includes:

[0088] The preprocessing circuit 115 is configured to receive a first chip select signal corresponding to a previous cycle of the current chip select signal and a first instruction signal corresponding to a previous cycle of the current chip select signal, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal;

[0089] The operation circuit 116 is connected to the preprocessing circuit 115, and is used to receive the first chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state.

[0090] Here, if only the state of the current chip select signal and the first chip select signal corresponding to the cycle before the current cycle is used to determine whether to decode, a decoding error may also occur. Specifically, when the current chip select signal is at a low level, if the first chip select signal corresponding to the cycle before the current chip select signal is also at a low level, then the decoding command is canceled, which may also lead to a judgment error. Figure 8 A signal timing diagram in 1N Mode is shown in FIG. Figure 8The figure shows the situation of two consecutive normal CMDs. When determining whether to decode based only on the current chip select signal and the state of the first chip select signal corresponding to the previous cycle of the current cycle, the decoding command in the second cycle of the normal CMD will be canceled, resulting in incorrect decoding.

[0091] It should be noted that the enabled state here can be a high-level state, and the disabled state can be a low-level state; alternatively, the enabled state can be a low-level state, and the disabled state can be a high-level state. This is not limited in the embodiments of the present disclosure. The following will be exemplified by taking the enabled state as a low-level state and the disabled state as a high-level state as an example.

[0092] It is understood that the CA1 signal in the CA signal can be used to distinguish between normal CMD and NT ODT CMD. Specifically, when the CA1 signal is at a high level, it is a normal CMD, and when the CA1 signal is at a low level, it is an NT ODT CMD. In the disclosed embodiment, the preprocessing circuit receives the first chip select signal and the first command signal corresponding to the previous cycle of the current chip select signal, and obtains the first chip select identification signal after performing a logical operation. The operation circuit determines whether to generate a decoding command corresponding to the current chip select signal based on the state of the first chip select identification signal and the state of the current chip select signal. In other words, the decoding command corresponding to the current chip select signal is determined based on the current chip select signal and the chip select signal and command signal corresponding to the previous cycle of the current chip select signal. Therefore, the problem of incorrect decoding of the second cycle of NT ODT CMD can be effectively improved.

[0093] However, in the scheme of jointly judging whether to generate the decoding instruction corresponding to the current chip select signal by the first instruction signal corresponding to the previous cycle of the current cycle, the first chip select signal and the chip select signal corresponding to the current cycle, if Figure 9 In the 1N Mode shown, if an NT ODT CMD is followed by a normal CMD, the current cycle may be interpreted as the second cycle of the NT ODT CMD, thereby canceling the decoding command corresponding to the current chip select signal and causing a decoding error. How to eliminate the incorrect decoding of the second cycle of the NT ODT CMD while ensuring that the normal command is decoded, and further improve the decoding success rate, has become an urgent problem to be solved.

[0094] Based on the above problems, the embodiments of the present disclosure also provide the following solutions.

[0095] In some embodiments, the pre-processing circuit 115 is specifically configured to receive a first chip select signal and a second chip select signal corresponding to a previous cycle and two previous cycles of a current chip select signal, respectively, and a first instruction signal and a second instruction signal corresponding to a previous cycle and two previous cycles of the current chip select signal, respectively, and perform a logical operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal, and perform a logical operation on the second chip select signal and the second instruction signal to generate a second chip select identification signal;

[0096] The operation circuit 116 is specifically used to receive the first chip select identification signal, the second chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and at least one of the first chip select identification signal and the second chip select identification signal is in a disabled state.

[0097] It can be understood that in the above embodiment, by utilizing the current chip select signal, the first instruction signal and the first chip select signal corresponding to the previous cycle of the current cycle, the second instruction signal and the second chip select signal corresponding to the previous two cycles of the current cycle, it is jointly determined whether to generate a decoding command corresponding to the current chip select signal. While ensuring that the normal CMD is decoded, the second cycle of the NT ODT CMD is avoided from being erroneously decoded, thereby further improving the decoding success rate.

[0098] In some embodiments, as Figure 10a As shown, the signal processing circuit further includes: a clock processing circuit 201; wherein,

[0099] The clock processing circuit 201 is used to receive a source clock signal and output an initial clock signal and an initial complementary clock signal; wherein, the clock period of the source clock signal is the same as the preset clock period, the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

[0100] In some embodiments, as Figure 10a As shown, the signal processing circuit further includes:

[0101] A first receiving circuit 202 is configured to receive an initial clock signal and an initial complementary clock signal, and output a first clock signal and a first complementary clock signal, wherein the clock periods of the first clock signal and the first complementary clock signal are both twice the clock period of the source clock signal;

[0102] The second receiving circuit 203 is used to receive the source command address signal and output the initial command address signal;

[0103] The third receiving circuit 204 is configured to receive a source chip select signal and output an initial chip select signal.

[0104] It should be noted that, in the embodiment of the present disclosure, whether it is the first receiving circuit 202, the second receiving circuit 203 or the third receiving circuit 204, they can all be receivers (represented by "Receiver") or buffers (represented by "Buffer").

[0105] It should be noted that the source command address signal here can be represented by CA[13:0], and the initial command address signal is represented by CA; the source chip select signal can be represented by CS_n, and the initial chip select signal is represented by CS; the initial clock signal and the initial complementary clock signal are represented by CK_t and CK_c, respectively, and the first clock signal and the first complementary clock signal are represented by PCLK_E and PCLK_O, respectively. The clock periods of the first clock signal and the first complementary clock signal are both twice the clock period of the source clock signal, and the phase difference between the first clock signal and the first complementary clock signal is 180 degrees; the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

[0106] It should also be noted that, in the embodiment of the present disclosure, whether it is a source command address signal or an initial command address signal, it is not a single signal, but represents a group of command address signals, namely CA[0] to CA

[13] . Therefore, for the second receiving circuit, there may be 14 receiving circuits for receiving 14 signals such as CA[0], CA[1], ..., CA

[13] . Figure 1 Only one receiving circuit is shown as an example.

[0107] In some embodiments, as Figure 10a As shown, the signal processing circuit further includes:

[0108] The chip select processing circuit 206 is connected to the first receiving circuit 202 and the third receiving circuit 204, and is configured to receive an initial chip select signal, sample the initial chip select signal once using the first clock signal / the first complementary clock signal to obtain a second chip select signal; sample the second chip select signal once using the first clock signal / the first complementary clock signal to obtain a first chip select signal; and sample the first chip select signal once using the first clock signal / the first complementary clock signal to obtain a current chip select signal.

[0109] The command address processing circuit 205 is connected to the first receiving circuit 202 and the second receiving circuit 203, and is used to receive the initial command address signal, sample the initial command address once using the first clock signal / first complementary clock signal to obtain the second instruction signal; sample the second instruction number once using the first clock signal / first complementary clock signal to obtain the first instruction signal; and sample the first instruction signal once using the first clock signal / first complementary clock signal to obtain the current instruction signal.

[0110] It should be noted that Figure 10a The clock signals received by the command address processing circuit 205 and the chip select processing circuit 206 are merely exemplary and are not intended to limit the present disclosure.

[0111] In some embodiments, in a first mode, a period of the current chip select signal is equal to one preset clock period; and in a second mode, a period of the current chip select signal is equal to two preset clock periods.

[0112] The signal processing circuit in the embodiment of the present disclosure can be used in a first mode or a second mode. In the first mode, the target command signal CMD includes only one valid command for a preset clock cycle, while in the second mode, the target command signal CMD includes two valid commands for a preset clock cycle. In the second mode, the period of the current chip select signal is twice the period of the current chip select signal in the first mode.

[0113] Here, in the first mode, the current chip select signal is represented by CS_E, the first chip select signal is represented by ODD_CS_1B, the first chip select identification signal is represented by CS_EVEN_P_B, the second chip select signal is represented by EVEN_CS_1B, and the second chip select identification signal is represented by CS_EVEN_PP_T; in the second mode, the current chip select signal is represented by CS_2T_E, the first chip select signal is represented by EVEN_CS_1B, the first chip select identification signal is represented by CS_EVEN_P_B_2N, the second chip select signal is represented by EVEN_CS_0B, and the second chip select identification signal is represented by CS_EVEN_PP_T_2N.

[0114] In some embodiments, as Figure 10b As shown, the first chip select flag generation circuit 119 / the second chip select flag generation circuit 122 includes:

[0115] The third selection circuit 131 is connected to the input end of the corresponding NOR gate and is used to output the first command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first command signal / second command signal when the first layout is in progress; and to output the second command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first command signal / second command signal when the second layout is in progress.

[0116] It is understood that, depending on the layout, CA0, one of the 14 signals included in the source command address signal CA[13:0], can be sampled and logically operated to output the first / second command signal. Alternatively, CA1, one of the 14 signals included in the source command address signal CA[13:0], can be sampled and logically operated to output the first / second command signal. When CA1 is selected as the first command address signal, in the first mode, the first command signal is represented by ODD_CA1_1B, and the second command signal is represented by EVEN_CA1_1B. In the second mode, the first command signal is represented by EVEN_CA1_1B, and the second command signal is represented by EVEN_CA1_0B. When CA0 is selected as the first command address signal, in the first mode, the first command signal is represented by ODD_CA0_1B, and the second command signal is represented by EVEN_CA0_1B. In the second mode, the first command signal is represented by EVEN_CA0_1B, and the second command signal is represented by EVEN_CA0_0B. It should be noted that the above only exemplifies CA0 or CA1 as the first command address signal, but is not limited thereto. In actual application, a specific selection can be made according to different layout designs.

[0117] In the following, CA1 is used as the first command address signal as an example to specifically describe how to implement decoding using the signal processing circuit provided in the embodiment of the present disclosure in the first mode and the second mode, respectively.

[0118] In some embodiments, as Figure 7 as well as Figure 10b As shown, the pre-processing circuit 115 includes:

[0119] The first preprocessing circuit 117 is configured to receive the first chip select signal and the first instruction signal in the first mode and the first chip select signal and the first instruction signal in the second mode, and generate first chip select identification signals corresponding to the first mode and the second mode respectively;

[0120] The second preprocessing circuit 118 is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second chip select identification signals corresponding to the first mode and the second mode respectively.

[0121] Here, the first preprocessing circuit 117 mainly processes the first chip select signal and the first instruction signal in the first mode and the second mode accordingly, thereby generating a first chip select identification signal, and the second preprocessing circuit 118 mainly processes the second chip select signal and the second instruction signal in the first mode and the second mode accordingly, thereby generating a second chip select identification signal.

[0122] In some embodiments, as Figure 10b As shown, the second pre-processing circuit 118 includes:

[0123] The second chip select flag generating circuit 122 is configured to receive the second chip select signal and the second command signal in the first mode and the second chip select signal and the second command signal in the second mode, and generate second intermediate chip select flag signals corresponding to the first mode and the second mode respectively;

[0124] The second selection circuit 123 is connected to the second chip select identification generation circuit 122, and is used to output the second intermediate chip select identification signal corresponding to the first mode in the first mode; and output the second intermediate chip select identification signal corresponding to the second mode in the second mode;

[0125] The second sampling circuit 124 is connected to the second selection circuit 123, and is used to sample the second intermediate chip select identification signal output by the second selection circuit 123 once to obtain the second chip select identification signal corresponding to the first mode, and sample the second intermediate chip select identification signal output by the second selection circuit 123 twice to obtain the second chip select identification signal corresponding to the second mode.

[0126] Here, the corresponding second intermediate chip select identification signal in the first mode is represented by EVEN_CHK2.

[0127] Here, the second selection circuit 123 is also connected to the first mode flag signal EN_1N and the second mode flag signal EN_2N. The first mode flag signal indicates that the signal processing circuit is in the first mode, and the second mode flag signal indicates that the signal processing circuit is in the second mode. The second selection circuit 123 outputs the second intermediate chip select identification signal corresponding to the first mode through the first mode flag signal, and the second selection circuit 123 outputs the second intermediate chip select identification signal corresponding to the second mode through the second mode flag signal.

[0128] Here, the second sampling circuit 124 may include a first flip-flop 138, a second flip-flop 139, and a first buffer 142. Here, both the first flip-flop 138 and the second flip-flop 139 comprise D-type flip-flops. The input of the first flip-flop 138 is connected to the output of the second selection circuit 123 to receive the second intermediate chip select identification signal output by the second selection circuit 123. The clock terminal of the first flip-flop 138 is connected to the first receiving circuit to receive the first clock signal PCLK_E and generate the second chip select identification signal CS_EVEN_PP_T corresponding to the first mode. The output of the first flip-flop 138 is connected to the input of the first buffer 142 to enhance signal driving capability. The input of the second flip-flop 139 is connected to the output of the first buffer 142. The clock terminal of the second flip-flop 139 is connected to the first receiving circuit to receive the first clock signal PCLK_E and generate the second chip select identification signal CS_EVEN_PP_T_2N corresponding to the second mode.

[0129] The following will be combined Figure 10b The composition of the second chip select flag generating circuit 122 is described in detail.

[0130] In some embodiments, the second chip select flag generation circuit 122 includes:

[0131] A first NOR gate 125 is used to perform a NOR logic operation on the second command signal and the second chip select signal in the first mode;

[0132] A first NOT gate 126 is configured to perform a NOT logic operation on the logic operation result of the first NOR gate 125 and output a second intermediate chip select identification signal corresponding to the first mode;

[0133] The second NOR gate 127 is used to perform a NOR logic operation on the second instruction signal and the second chip select signal in the second mode, and output a corresponding second intermediate chip select identification signal in the second mode.

[0134] In some specific examples, the first input end of the first NOR gate 125 is connected to the output end of the third selection circuit 131, the second input end of the first NOR gate 125 is connected to the chip select processing circuit, the output end of the first NOR gate 125 is connected to the input end of the second buffer 143, and the signal coming out of the second buffer 143 is divided into two paths, one path is connected to the first NOR gate 126, and the other path is connected to the first chip select identification generation circuit 119.

[0135] In some embodiments, as Figure 10b As shown, the first pre-processing circuit 117 includes:

[0136] A first chip select flag generating circuit 119 is configured to receive the first chip select signal and the first command signal in the first mode and the first chip select signal and the first command signal in the second mode, and generate first intermediate chip select flag signals corresponding to the first mode and the second mode respectively;

[0137] The first selection circuit 120 is connected to the first chip select identification generation circuit 119 and is used to output the first intermediate chip select identification signal corresponding to the first mode in the first mode; and output the first intermediate chip select identification signal corresponding to the second mode in the second mode;

[0138] The first sampling circuit 121 is connected to the first selection circuit 120, and is used to sample the first intermediate chip select identification signal output by the first selection circuit 120 once to obtain the first chip select identification signal corresponding to the first mode, and sample the first intermediate chip select identification signal output by the first selection circuit 120 twice to obtain the first chip select identification signal corresponding to the second mode.

[0139] Here, the first intermediate chip selection identification signal corresponding to the second mode is represented by EVEN_CHK1.

[0140] Here, the first selection circuit 120 is also connected to the first mode flag signal EN_1N and the second mode flag signal EN_2N. The first selection circuit 120 outputs the first intermediate chip select identification signal corresponding to the first mode through the first mode flag signal, and the first selection circuit 120 outputs the first intermediate chip select identification signal corresponding to the second mode through the second mode flag signal.

[0141] Here, the first sampling circuit 121 may include a half latch 141, a third buffer 144, and a third flip-flop 140. Here, the third flip-flop 140 comprises a D-type flip-flop. The input of the half latch 141 is connected to the output of the first selection circuit 120 to receive the first intermediate chip select identification signal output by the first selection circuit 120. The clock terminal of the half latch 141 is connected to the first receiving circuit to receive the first clock signal PCLK_E and generate the first chip select identification signal CS_EVEN_P_B corresponding to the second mode. The output of the half latch 141 is connected to the input of the third buffer 144 to enhance signal driving capability. The input of the third flip-flop 140 is connected to the output of the third buffer 144. The clock terminal of the third flip-flop 140 is connected to the first receiving circuit to receive the first clock signal PCLK_E and generate the first chip select identification signal CS_EVEN_P_B_2N corresponding to the first mode.

[0142] In some embodiments, the second chip select signal in the first mode overlaps with the first chip select signal in the second mode; the second command signal in the first mode overlaps with the first command signal in the second mode;

[0143] The first chip select flag generating circuit 119 includes:

[0144] A third NOR gate 128 is used to perform a NOR logic operation on the first command signal and the first chip select signal in the first mode;

[0145] The second NOT gate 129 is used to perform a NOT logic operation on the logic operation result of the third NOR gate 128 and output a first intermediate chip select identification signal corresponding to the first mode;

[0146] The third sampling circuit 130 is configured to perform a sampling process on the inverted signal of the second intermediate chip select identification signal generated by the second chip select identification generation circuit 122 in the first mode to obtain a corresponding first intermediate chip select identification signal in the second mode.

[0147] In some specific examples, the third sampling circuit 130 includes a D-type flip-flop. The third sampling circuit 130 can use the first complementary clock signal PCLK_O to sample the inverted signal of the second intermediate chip select identification signal in the first mode.

[0148] Figure 11 A timing diagram of a first mode provided in an embodiment of the present disclosure is provided. Figure 12 A timing diagram of a second mode provided in an embodiment of the present disclosure.

[0149] like Figure 11 As shown, in the first mode, when the current chip select signal CS(1st) is low, it is sampled by PCLK_E and output as CS_E, which is sent to the instruction decoder circuit. Therefore, the CS signals of the two preceding cycles must be checked separately. The previous cycle, CS(1pre), is sampled by PCLK_O and output as ODD_CS_1B. This signal is then logically operated with the previous cycle's CA1 sampling signal, ODD_CA1_1B. Next, a flip-flop is added after this logical output signal, which is then sampled by PCLK_E and output as CS_EVEN_P_B. Similarly, the previous two cycles, CS(2pre), are sampled by PCLK_E and output as EVEN_CS_1B. This signal is logically operated with the previous cycle's CA1 sampling signal, EVEN_CA1_1B, to produce EVEN_CHK2. This trigger is then added after PCLK_E and output as CS_EVEN_PP_T. CS_EVEN_P_B and CS_EVEN_PP_T are used to overwrite the current cycle decoding command through logical operation, thereby avoiding incorrect decoding of the second cycle of NT ODT CMD.

[0150] like Figure 12As shown, in the second mode, when the current chip select signal CS(1st) is low, it is sampled by PCLK_E and output as CS_E, which is sent to the instruction decoding circuit. Therefore, it is necessary to check the CS of the first two cycles of the cycle. CS(1pre) of the previous cycle is sampled by PCLK_E and output as EVEN_CS_1B. This is logically operated with the CA1 sampling information EVEN_CA1_1B of the previous cycle, and the output is EVEN_CHK1. Two-stage flip-flops are added and sampled by PCLK_E to output CS_EVEN_P_B_2N. Similarly, CS(2pre) of the first two cycles of the cycle is sampled by PCLK_E and output as EVEN_CS_0B. This is logically operated with the CA1 sampling information EVEN_CA1_0B of the first two cycles of the cycle, and two-stage flip-flops are sampled by PCLK_E to output CS_EVEN_PP_T_2N. CS_EVEN_P_B_2N and CS_EVEN_PP_T_2N are used to overwrite the current cycle decoding command through logical operation, thereby avoiding incorrect decoding of the second cycle of NT ODT CMD.

[0151] In some embodiments, as Figure 10b As shown, the operation circuit includes:

[0152] The first operation circuit 132 is connected to both the first pre-processing circuit 117 and the second pre-processing circuit 118, and is configured to receive the first chip select identification signal and the second chip select identification signal corresponding to the first mode, the first mode flag signal, the current chip select signal, and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, wherein the first mode flag signal indicates that the signal processing circuit is in the first mode;

[0153] The second operation circuit 133 is connected to both the first preprocessing circuit 117 and the second preprocessing circuit 118, and is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the second mode, the second mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal. The second mode flag signal indicates that the signal processing circuit is in the second mode.

[0154] In some embodiments, the first operation circuit 132 / the second operation circuit 133 includes an OR gate 134 , a first NAND gate 135 , a second NAND gate 136 , and a fourth NOR gate 137 , wherein:

[0155] The input end of the OR gate 134 is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the first mode / the second mode, and the output end is connected to one input end of the first NAND gate 135;

[0156] Another input terminal of the first NAND gate 135 is used to receive the first mode flag signal / the second mode flag signal, and the output terminal is connected to the first input terminal of the fourth NOR gate 137;

[0157] The input end of the second NAND gate 136 is used to receive the current chip select signal and the current command signal, and the output end is connected to the second input end of the fourth NOR gate 137;

[0158] The output terminal of the fourth NOR gate 137 is used to output a decoding signal corresponding to the current chip select signal or to disable the decoding signal corresponding to the current chip select signal.

[0159] It should be noted that Figure 10b The various logic gates in the instruction decoding circuit shown in FIG are only exemplary demonstrations, but are not limited to Figure 10b As shown in Figure 10b There are other combinations of logic gates in that have the same effect.

[0160] In some specific examples, the first operation circuit 132 includes two second NAND gates 136, and the second operation circuit 133 includes two second NAND gates 136. The second NAND gates 136 in the first operation circuit 132 are used to receive the current chip select signal CS_E corresponding to the first mode, and the command address signals CA0_E, CA1_E, CA2_E, CA3_E, and CA4_E corresponding to the first mode. The second NAND gates 136 in the second operation circuit 133 are used to receive the current chip select signal CS_2T_E corresponding to the second mode, and the command address signals CA0_2T_E, CA1_2T_E, CA2_2T_E, CA3_2T_E, and CA4_2T_E corresponding to the first mode.

[0161] For the cycle corresponding to the current chip select signal, when the chip select signal corresponding to the current cycle is at a high level, it indicates that a decoding signal corresponding to the chip select signal corresponding to the current cycle needs to be generated to disable it. When the chip select signal corresponding to the current cycle is at a low level, it indicates that a decoding signal corresponding to the chip select signal corresponding to the current cycle may need to be generated. However, whether it is necessary to generate a decoding signal corresponding to the chip select signal corresponding to the current cycle needs to be determined in combination with the first chip select signal and the first command signal of the previous cycle (1pre) of the current chip select signal.

[0162] When the first chip select signal is high, it indicates that the current cycle is the first cycle of NT ODT CMD or normal CMD, and a decoding signal needs to be generated. When the first chip select signal is low, and the first command signal is high, it indicates that the previous cycle of the current chip select signal was normal CMD and the current cycle is the first cycle of normal CMD or NT ODT CMD, and a decoding signal needs to be generated. When both the first chip select signal and the first command signal are low, a comprehensive judgment is made based on the second command signal and the second chip select signal from the two cycles before the current chip select signal (2pre).

[0163] When the first chip select signal and the first instruction signal are both low, when the second chip select signal and the second instruction signal are also in a low state, it means that 1pre and 2pre are two cycles of NT ODT CMD. When the first chip select signal and the first instruction signal are both low, when the second chip select signal is in a high state, or the second chip select signal is in a low state and the second instruction signal is a high signal, it means that the current cycle is the second cycle of NT ODT CMD, and it is necessary to generate a decoding signal corresponding to disabling the current chip select signal.

[0164] Therefore, the OR logic operation can be used to select the case where the first chip select signal in 1pre is at a high level or the first instruction signal is at a high level, so that the result of the logic operation of the first chip select signal and the first instruction signal is a high level state (disabled state). Alternatively, the NOR logic operation can be used to select the case where the second chip select signal and the second instruction signal in 2pre are both at a low level, so that the result of the logic operation of the second chip select signal and the second instruction signal is a high level state (disabled state).

[0165] The following combination Figure 10b How to generate a decoding signal corresponding to the current chip select signal or disable a decoding signal corresponding to the current chip select signal in the first mode is introduced in detail.

[0166] In the first mode, the corresponding first command signal is ODD_CA1_1B, and the first chip select signal is ODD_CS_1B. After a logic operation through the third NOR gate 128 and the second NOT gate 129, CS_EVEN_P_B is obtained. When either ODD_CA1_1B or ODD_CS_1B is high, CS_EVEN_P_B is high; otherwise, CS_EVEN_P_B is low. The second command signal is EVEN_CA1_1B, and the second chip select signal is EVEN_CS_1B. After a logic operation through the first NOR gate 125 and the first NOT gate 126, CS_EVEN_PP_T is obtained. When either EVEN_CA1_1B or EVEN_CS_1B is high, CS_EVEN_PP_T is high; otherwise, CS_EVEN_PP_T is low. CS_EVEN_PP_T and CS_EVEN_P_B are logically operated via an OR gate 134. A high level is output when either CS_EVEN_PP_T or CS_EVEN_P_B is high. This is then logically ANDed with the current chip select signal CS_E. A decoding signal is generated only when either CS_EVEN_PP_T or CS_EVEN_P_B is high and the current chip select signal CS_E is low. Otherwise, a decoding signal corresponding to the disabled chip select signal is generated.

[0167] It can be understood that the embodiment of the present disclosure checks the initial command address signal CA and the initial chip select signal CS of the first two cycles of the current chip select signal when the current chip select signal is in a low level state. If the CS signals of the first two cycles are both low levels, and the CA1 signal sampling information of the cycle is low level, the current CS signal is allowed to be transmitted to the instruction decoding circuit for instruction decoding and output, and the fourth NOR gate 137 outputs the decoding signal corresponding to the current chip select signal; if the CS signal of the previous cycle is high level, or the CA1 signal sampling information of the cycle is high level, the current CS signal is also allowed to be transmitted to the instruction decoding circuit 114 for instruction decoding and output, and the fourth NOR gate 137 outputs the decoding signal corresponding to the current chip select signal. In the first mode, the current CS signal is sampled by the PCLK_E signal and output to the instruction decoding circuit 114. The CS signals corresponding to the first two cycles are sampled and output by the PCLK_E signal and the PCLK_O signal, respectively. A first-level sampling circuit is added for each. The CS signals are sampled and output by the PCLK_E signal as the second chip select identification signal CS_EVEN_PP_T and the first chip select identification signal CS_EVEN_P_B, which are sent to the operation circuit. The decoding instruction is overwritten through logical operation. In the second mode, the current CS signal is sampled and output to the operation circuit by the PCLK_E signal. The CS signals corresponding to the first two cycles are sampled and output by the PCLK_E signal. Two-level sampling circuits are added for each. The CS signals are sampled and output by the PCLK_E signal as the second chip select identification signal CS_EVEN_PP_T_2N and the first chip select identification signal CS_EVEN_P_B_2N, which are sent to the operation circuit. The decoding instruction is overwritten through logical operation and treated as one decoding signal, thereby avoiding erroneous decoding of the second cycle of NT ODT CMD.

[0168] Figure 13 is a timing diagram of the corresponding signal in the first mode, Figure 14 Schematic diagram of the timing of the corresponding signals in the second mode. In some embodiments, the second chip select identification signal CS_EVEN_PP_T of the two cycles before the current chip select signal CS and the first chip select identification signal CS_EVEN_P_B of the previous cycle are used to perform a logical operation when the current chip select signal CS is collected to complete the CS check of the two cycles before the current chip select signal CS; Figure 13 as well as Figure 14 The first chip select flag signal and the second chip select flag signal are shown by dotted lines. In the first mode, the CS CHECK flag signal of the previous cycle and the current sample CS_n are sampled by PCLK_E and PCLK_OT respectively. Since the judgment result is obtained after the first chip select flag signal and the second chip select flag signal are logically operated, and then compared with the current CS_n, there is a difference of one preset clock cycle, which makes the trigger instruction sampling margin in the instruction decoding circuit smaller.

[0169] In the embodiment of the present disclosure, Figure 13 as well as Figure 14 The first chip select flag signal and the second chip select identification signal, shown by the solid line in the figure, transmit the CS_EVEN_PP_T signal and the CS_EVEN_P_B signal to the operation circuit. The instruction decode input terminal checks the instruction signal and the chip select signal of the previous two cycles of the current chip select signal. Because the current chip select signal and the CS_EVEN_PP_T and CS_EVEN_P_B signals are simultaneously sampled by PCLK_E / PCLK_O and output to the instruction decode terminal, in the embodiment of the present disclosure, the result of the logical operation of the first chip select identification signal and the second chip select identification signal is used as a decoding instruction and directly sent to the decoding circuit, thereby increasing the instruction sampling margin of the next-level trigger.

[0170] An embodiment of the present disclosure proposes a signal processing circuit, including: an instruction decoding circuit; wherein the instruction decoding circuit includes: a preprocessing circuit, used to receive a first chip select signal corresponding to the previous cycle of a current chip select signal, a first instruction signal corresponding to the previous cycle of the current chip select signal, and perform a logical operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal; an operation circuit, connected to the preprocessing circuit, used to receive the first chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state. In the disclosed embodiment, the preprocessing circuit receives the first chip select signal and the first instruction signal corresponding to the previous cycle of the current chip select signal, and obtains the first chip select identification signal after a logical operation. The operation circuit jointly determines whether to generate a decoding command corresponding to the current chip select signal based on the state of the first chip select identification signal and the state of the current chip select signal. That is to say, the decoding command corresponding to the current chip select signal is at least jointly determined based on the current chip select signal and the chip select signal and instruction signal corresponding to the previous cycle of the current chip select signal. This can improve the problem of the second cycle of the non-target on-chip terminal resistance command being incorrectly decoded, thereby improving the success rate of decoding.

[0171] Another aspect of the present disclosure further provides a memory, such as Figure 15 As shown, the memory 145 includes a signal processing circuit 146 as in any of the above embodiments.

[0172] In some embodiments, the memory 145 includes: fifth generation double data rate synchronous dynamic random access memory DDR5.

[0173] It should be noted that the embodiments of the present disclosure can be applied to the control circuit of CA signal sampling and decoding in DRAM chips, but are not limited to this scope. Other circuits related to input signal sampling and instruction decoding can also adopt this design.

[0174] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not implemented. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0175] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0176] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0177] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A signal processing circuit, characterized in that: The signal processing circuit includes: an instruction decoding circuit; wherein, The instruction decoding circuit comprises: a preprocessing circuit, configured to receive a first chip select signal and a second chip select signal corresponding to a previous cycle and two previous cycles of a current chip select signal, respectively, and a first instruction signal and a second instruction signal corresponding to a previous cycle and two previous cycles of the current chip select signal, respectively, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal, and perform a logic operation on the second chip select signal and the second instruction signal to generate a second chip select identification signal; An operation circuit is connected to the preprocessing circuit, and is used to receive the first chip select identification signal, the second chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and at least one of the first chip select identification signal and the second chip select identification signal is in a disabled state.

2. The signal processing circuit according to claim 1, wherein: In the first mode, the period of the current chip select signal is equal to one preset clock period; in the second mode, the period of the current chip select signal is equal to two preset clock periods.

3. The signal processing circuit according to claim 2, wherein: The preprocessing circuit includes: a first preprocessing circuit, configured to receive the first chip select signal and the first instruction signal in the first mode and the first chip select signal and the first instruction signal in the second mode, and generate first chip select identification signals corresponding to the first mode and the second mode respectively; The second preprocessing circuit is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate a second chip select identification signal corresponding to the first mode and the second mode respectively.

4. The signal processing circuit according to claim 3, wherein: The first pre-processing circuit includes: a first chip select flag generating circuit, configured to receive the first chip select signal and the first command signal in the first mode and the first chip select signal and the first command signal in the second mode, and generate first intermediate chip select flag signals corresponding to the first mode and the second mode respectively; a first selection circuit connected to the first chip select flag generation circuit, configured to output a first intermediate chip select flag signal corresponding to the first mode in the first mode; and output a first intermediate chip select flag signal corresponding to the second mode in the second mode; A first sampling circuit is connected to the first selection circuit, and is used to sample the first intermediate chip select identification signal output by the first selection circuit once to obtain the first chip select identification signal corresponding to the first mode, and to sample the first intermediate chip select identification signal output by the first selection circuit twice to obtain the first chip select identification signal corresponding to the second mode.

5. The signal processing circuit according to claim 4, wherein: The second pre-processing circuit includes: a second chip select flag generating circuit, configured to receive the second chip select signal and the second command signal in the first mode and the second chip select signal and the second command signal in the second mode, and generate second intermediate chip select flag signals corresponding to the first mode and the second mode respectively; a second selection circuit connected to the second chip select identification generating circuit, configured to output a second intermediate chip select identification signal corresponding to the first mode in the first mode; and output a second intermediate chip select identification signal corresponding to the second mode in the second mode; A second sampling circuit is connected to the second selection circuit, and is used to sample the second intermediate chip select identification signal output by the second selection circuit once to obtain the second chip select identification signal corresponding to the first mode, and sample the second intermediate chip select identification signal output by the second selection circuit twice to obtain the second chip select identification signal corresponding to the second mode.

6. The signal processing circuit according to claim 5, wherein: The second chip select flag generating circuit includes: a first NOR gate, configured to perform a NOR logic operation on the second instruction signal and the second chip select signal in the first mode; a first NOT gate, configured to perform a NOT logic operation on a logic operation result of the first NOR gate, and output a corresponding second intermediate chip select identification signal in the first mode; The second NOR gate is used to perform a NOR logic operation on the second instruction signal and the second chip select signal in the second mode, and output a corresponding second intermediate chip select identification signal in the second mode.

7. The signal processing circuit according to claim 5, wherein: The second chip select signal in the first mode overlaps with the first chip select signal in the second mode; The second command signal in the first mode overlaps with the first command signal in the second mode; The first chip select flag generating circuit includes: a third NOR gate, configured to perform a NOR logic operation on the first command signal in the first mode and the first chip select signal; a second NOT gate, configured to perform a NOT logic operation on a logic operation result of the third NOR gate, and output a first intermediate chip select identification signal corresponding to the first mode; The third sampling circuit is used to perform a sampling process on the inverse signal of the second intermediate chip select identification signal generated by the second chip select identification generation circuit in the first mode to obtain the first intermediate chip select identification signal corresponding to the second mode.

8. The signal processing circuit according to claim 5, wherein: The first chip select flag generation circuit / the second chip select flag generation circuit includes: The third selection circuit is connected to the input end of the corresponding NOR gate and is used to output the first command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the first layout is laid out; and to output the second command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the second layout is laid out.

9. The signal processing circuit according to claim 3, wherein: The operation circuit includes: a first arithmetic circuit, connected to both the first pre-processing circuit and the second pre-processing circuit, configured to receive a first chip select identification signal and a second chip select identification signal corresponding to the first mode, a first mode flag signal, the current chip select signal, and a current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, wherein the first mode flag signal indicates that the signal processing circuit is in the first mode; The second operation circuit is connected to both the first preprocessing circuit and the second preprocessing circuit, and is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the second mode, the second mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal. The second mode flag signal indicates that the signal processing circuit is in the second mode.

10. The signal processing circuit according to claim 9, wherein: The first operation circuit / the second operation circuit includes: an OR gate, a first NAND gate, a second NAND gate and a fourth NOR gate, wherein: The input end of the OR gate is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the first mode / second mode, and the output end is connected to one input end of the first NAND gate; Another input end of the first NAND gate is used to receive the first mode flag signal / the second mode flag signal, and an output end is connected to the first input end of the fourth NOR gate; The input end of the second NAND gate is used to receive the current chip select signal and the current command signal, and the output end is connected to the second input end of the fourth NOR gate; The output end of the fourth NOR gate is used to output the decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal.

11. The signal processing circuit according to claim 2, wherein: The signal processing circuit further includes: a clock processing circuit; wherein, The clock processing circuit is used to receive a source clock signal and output an initial clock signal and an initial complementary clock signal; wherein, the clock period of the source clock signal is the same as the preset clock period, the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

12. The signal processing circuit according to claim 11, wherein: The signal processing circuit further includes: a first receiving circuit, configured to receive the initial clock signal and the initial complementary clock signal, and output a first clock signal and a first complementary clock signal, wherein a clock period of each of the first clock signal and the first complementary clock signal is twice a clock period of the source clock signal; a second receiving circuit, configured to receive a source command address signal and output an initial command address signal; The third receiving circuit is used to receive the source chip select signal and output the initial chip select signal.

13. The signal processing circuit according to claim 12, wherein: The signal processing circuit further includes: a chip select processing circuit, connected to the first receiving circuit and the third receiving circuit, configured to receive the initial chip select signal, sample the initial chip select signal once using the first clock signal / first complementary clock signal to obtain the second chip select signal; sample the second chip select signal once using the first clock signal / first complementary clock signal to obtain the first chip select signal; and sample the first chip select signal once using the first clock signal / first complementary clock signal to obtain the current chip select signal; The command address processing circuit is connected to the first receiving circuit and the second receiving circuit, and is used to receive the initial command address signal, sample the initial command address once using the first clock signal / first complementary clock signal to obtain the second instruction signal; sample the second instruction signal once using the first clock signal / first complementary clock signal to obtain the first instruction signal; and sample the first instruction signal once using the first clock signal / first complementary clock signal to obtain the current instruction signal.

14. A memory, characterized in that: The memory includes the signal processing circuit according to any one of claims 1 to 13.

15. The memory according to claim 14, wherein: The memory includes: the fifth generation double data rate synchronous dynamic random access memory DDR5.

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