Method and System for Suppressing DC-Link Capacitor Current Ripple of Coupled-Type Three-Level Inverters

Abstract

The present invention belongs to the field of power electronic power conversion, and provides a method and system for suppressing the DC-side capacitor current ripple of a coupled three-level inverter. According to the value range of the duty ratio distribution factor of the virtual voltage vector, a method for dividing the space vector diagram region of the coupled three-level inverter is determined; according to the amplitude, phase angle and three-phase output current of the reference voltage vector, the sector and region where the reference voltage vector is located are judged; according to the sector and region where the reference voltage vector is located, the duty ratios of a virtual voltage vector and two basic voltage vectors closest to it are calculated respectively; according to the sector and region where the reference voltage vector is located, the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation, a controller is designed based on the deadbeat control method to update the duty ratio distribution factor of the small vector, so as to realize the independent control of the capacitor voltage; based on the updated duty ratio of the small vector and the sector and region where the reference voltage vector is located, a switching sequence is designed.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and particularly relates to a method and a system for suppressing the DC-side capacitor current ripple of a coupled three-level inverter. Background Technique

[0002] The statements in this part only provide background technical information related to the present invention, and do not necessarily constitute prior art.

[0003] Three-level inverters are widely used in new energy power generation, motor drive, and energy storage systems due to their advantages such as simple structure, good output current waveform quality, and high efficiency. The T-Type three-level inverter is a commonly used circuit topology, but it contains a relatively large number of power switching tubes. The coupled three-level inverter only contains ten power switching tubes, further reducing the number of power switching tubes while maintaining the multi-level output characteristics, and has broad application prospects.

[0004] Electrolytic capacitors are components that are prone to failure, and their stability directly determines the output waveform quality of the inverter. The DC-side capacitor current ripple is defined as the root mean square value of the neutral line current. When the DC-side capacitor current ripple is very high, the service life of the capacitor will be shortened, and even the inverter will be directly damaged. Larger capacitors will extend the service life of the inverter, but increase the system volume and cost.

[0005] The inventors found that the existing methods for suppressing the DC-side capacitor current ripple mainly target the T-Type or Hybrid Active Neutral-Point-Clamped (HANPC) three-level inverter topologies. When the coupled three-level inverter operates under the condition of unequal DC-side capacitor voltages, the harmonic content of its output current will increase. In addition, the output states of this topology are limited and cannot generate medium vectors. Therefore, the existing control methods cannot be directly applied. Therefore, a method for suppressing the DC-side capacitor current ripple of a coupled three-level inverter under unbalanced conditions needs to be studied urgently. Summary of the Invention

[0006] To solve the above problems, the present invention proposes a method and a system for suppressing the DC-side capacitor current ripple of a coupled three-level inverter. The present invention can effectively suppress the DC-side capacitor current ripple of the coupled three-level inverter, while maintaining good output current waveform quality, and is applicable to the conditions of balanced and unbalanced DC-side capacitor voltages.

[0007] According to some embodiments, the first solution of the present invention provides a method for suppressing the DC-side capacitor current ripple of a coupled three-level inverter, adopting the following technical solution:

[0008] The method for suppressing the DC-side capacitor current ripple of a coupled three-level inverter includes:

[0009] According to the value range of the duty cycle distribution factor of the virtual voltage vector, determine the method for dividing the space vector diagram region of the coupled three-level inverter;

[0010] Based on the amplitude, phase angle and three-phase output current of the reference voltage vector, determine the sector and region where the reference voltage vector is located;

[0011] Based on the sector and region where the reference voltage vector is located, select the virtual voltage vector closest to it and two basic voltage vectors, and calculate their duty cycles respectively;

[0012] Based on the sector and region where the reference voltage vector is located, the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation, design a controller based on the deadbeat control method, update the duty cycle distribution factor of the small vector, and achieve independent control of the capacitor voltage;

[0013] Based on the updated duty cycle of the small vector and the sector and region where the reference voltage vector is located, design a switching sequence, convert the switching sequence into the PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0014] According to some embodiments, the second solution of the present invention provides a system for suppressing the DC-side capacitor current ripple of a coupled three-level inverter, and adopts the following technical solutions:

[0015] The system for suppressing the DC-side capacitor current ripple of a coupled three-level inverter includes:

[0016] A sector division module configured to determine the method for dividing the space vector diagram region of the coupled three-level inverter according to the value range of the duty cycle distribution factor of the virtual voltage vector;

[0017] A sector judgment module configured to determine the sector and region where the reference voltage vector is located based on the amplitude, phase angle and three-phase output current of the reference voltage vector;

[0018] A basic voltage vector selection module configured to select the virtual voltage vector closest to it and two basic voltage vectors according to the sector and region where the reference voltage vector is located, and calculate their duty cycles respectively;

[0019] A capacitor voltage independent control module configured to design a controller based on the deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation, update the duty cycle distribution factor of the small vector, and achieve independent control of the capacitor voltage;

[0020] A driving signal generation module is configured to design a switching sequence based on the updated duty ratio of small vectors and the sector and region where the reference voltage vector is located, convert the switching sequence into a PWM driving signal for a power switch tube, and control the operation of a coupled three-level inverter.

[0021] According to some embodiments, a third aspect of the present invention provides a computer-readable storage medium.

[0022] A computer-readable storage medium stores a computer program thereon, and when the program is executed by a processor, it implements the steps in the method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter as described in the first aspect above.

[0023] According to some embodiments, a fourth aspect of the present invention provides a computer device.

[0024] A computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in the method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter as described in the first aspect above.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] Compared with the traditional space vector modulation method, the DC-side capacitor current ripple of the present invention is significantly reduced, and the service life of the DC-side capacitor can be extended. Under the conditions of balanced and unbalanced DC-side capacitor voltages, the method of the present invention reduces the total harmonic distortion rate of the three-phase output current of the coupled three-level inverter, improves the efficiency and stability of the system. The present invention corrects the duty ratios of P-type small vectors and N-type small vectors according to different sectors, regions, the given value of the DC-side capacitor voltage deviation, and the actual value of the DC-side capacitor voltage to achieve independent control of the capacitor voltage. Compared with the traditional space vector method, the present invention only uses three voltage vectors to synthesize the reference voltage vector and does not need to use an indirect method to calculate the voltage vector duty ratio, which reduces the calculation burden. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The specification drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0028] Figure 1 It is a circuit topology diagram of a coupled three-level inverter;

[0029] Figure 2 It is a space vector diagram of a coupled three-level inverter when the DC-side unbalance factor is greater than 0;

[0030] Figure 3It is the space vector diagram of the coupled three-level inverter when the DC-side unbalance factor is less than 0;

[0031] Figure 4 It is the value range of the duty ratio distribution factor β of the virtual vector when the system adopts the traditional space vector modulation method;

[0032] Figure 5 is the region division method of Embodiment 1 of the present invention;

[0033] Figure 6 It is the schematic diagram of the switching sequence when the system adopts the traditional space vector modulation method, the reference voltage is in Sector 1 and the outer region;

[0034] Figure 7 It is the schematic diagram of the switching sequence when the system adopts the control method of Embodiment 1 of the present invention, the reference voltage is in Sector 1 and Region A1;

[0035] Figure 8 It is the schematic diagram of the principle of the DC-side capacitor current ripple suppression method of Embodiment 1 of the present invention;

[0036] Figure 9(a) is the simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC-side unbalance factor is 0.2, and the modulation degree is 0.8;

[0037] Figure 9(b) is the simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC-side unbalance factor is -0.2, and the modulation degree is 0.8;

[0038] Figure 9(c) is the simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC-side unbalance factor is 0, and the modulation degree is 0.8;

[0039] Figure 10(a) is the simulation waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC-side unbalance factor is 0.2, and the modulation degree is 0.8;

[0040] Figure 10(b) is the simulation waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC-side unbalance factor is -0.2, and the modulation degree is 0.8;

[0041] Figure 10(c) is the simulation waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC-side unbalance factor is 0, and the modulation degree is 0.8;

[0042] Figure 11(a) is the simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC-side unbalance factor is 0.2, and the modulation degree is 0.4;

[0043] Figure 11(b) is the simulation waveform diagram when the system adopts the traditional space vector modulation method, the DC-side unbalance factor is -0.2, and the modulation degree is 0.4;

[0044] Figure 11(c) is the simulation waveform diagram of the system when using the traditional space vector modulation method, the DC-side unbalance factor is 0, and the modulation index is 0.4;

[0045] Figure 12(a) is the simulation waveform diagram of the system when using the control method of Embodiment 1 of the present invention, the DC-side unbalance factor is 0.2, and the modulation index is 0.4;

[0046] Figure 12(b) is the simulation waveform diagram of the system when using the control method of Embodiment 1 of the present invention, the DC-side unbalance factor is -0.2, and the modulation index is 0.4;

[0047] Figure 12(c) is the simulation waveform diagram of the system when using the control method of Embodiment 1 of the present invention, the DC-side unbalance factor is 0, and the modulation index is 0.4;

[0048] Figure 13(a) is the simulation waveform diagram of the system when using the control method of Embodiment 1 of the present invention, the modulation index is set to 0.8, and the DC-side capacitor voltage deviation given value has a unit step;

[0049] Figure 13(b) is the simulation waveform diagram of the system when using the control method of Embodiment 1 of the present invention, the modulation index is set to 0.4, and the DC-side capacitor voltage deviation given value has a unit step. Detailed implementation manners

[0050] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0051] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further descriptions of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0052] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or their combinations.

[0053] Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0054] Embodiment 1

[0055] This embodiment provides a method for suppressing the DC-side capacitor current ripple of a coupled three-level inverter. In this embodiment, the method includes the following steps:

[0056] Determine the method for dividing the space vector diagram region of the coupled three-level inverter according to the value range of the duty ratio distribution factor of the virtual voltage vector;

[0057] Judge the sector and region where the reference voltage vector is located according to the amplitude, phase angle and three-phase output current of the reference voltage vector;

[0058] Select a virtual voltage vector and two basic voltage vectors with the closest distance respectively according to the sector and region where the reference voltage vector is located, and calculate their duty ratios;

[0059] Design a controller based on the deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation, update the duty ratio distribution factor of the small vector, and realize the independent control of the capacitor voltage;

[0060] Design a switching sequence based on the updated duty ratio of the small vector and the sector and region where the reference voltage vector is located, convert the switching sequence into the PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0061] Figure 1 For the system topology of the coupled three-level inverter, it includes two groups of photovoltaic arrays, two DC-side electrolytic capacitors, a coupled three-level inverter and a three-phase load. Each group of photovoltaic arrays is connected to an electrolytic capacitor, and further design a control strategy to realize the independent maximum power point tracking (MPPT) function of the photovoltaic array, thereby improving the system efficiency.

[0062] Among them, the power switch tube refers to an Insulated-Gate Bipolar Transistor (IGBT); the power switch tube can also be implemented by other forms of transistors, and can be specifically selected according to the actual needs of those skilled in the art.

[0063] The switching states of the coupled three-level inverter include three types: P, O, and N. Select the DC-side neutral point O (see Figure 1 ) as the reference. When the switching state is P, the output voltage of the bridge arm is +VP; when the switching state is O, the output voltage of the bridge arm is 0; when the switching state is N, the output voltage of the bridge arm is –VN.

[0064] For the convenience of analysis, define the DC-side imbalance factor μ as:

[0065]

[0066] Among them, V P and V N are the voltages across the upper and lower capacitors respectively, Vdiff is the difference between the voltages of the two capacitors on the DC side (i.e., V diff = V P - V N ), and V dc is the sum of the voltages of the two capacitors on the DC side.

[0067] Based on Equation (1), the expressions for the upper and lower capacitor voltages on the DC side can be obtained as follows:

[0068]

[0069] Figure 2 and Figure 3 are the space vector diagrams of the coupled three-level inverter when the DC side unbalance factor is greater than and less than 0, respectively. The entire space vector diagram is divided into 6 sectors (i.e., the first sector - the sixth sector, which can also be expressed as sector 1 - sector 6). It can be seen that under the condition of DC side midpoint voltage unbalance, the positions of the large vectors and zero vectors remain unchanged, i.e., the same as in the case of midpoint voltage balance; the positions of the small vectors shift, and the small vectors no longer maintain the redundancy characteristic, thus making the implementation process of the space vector modulation method extremely complex.

[0070] The influence of all basic voltage vectors on the neutral line current (i np ) is shown in Table 1. It is not difficult to find that only the small vectors affect the neutral line current. In addition, the magnitudes of the neutral line currents generated by each pair of P-type small vectors and N-type small vectors are equal and the directions are opposite.

[0071] Without loss of generality, taking sector 1 as an example, the specific implementation process is described in detail.

[0072] According to the value range of the duty cycle distribution factor of the virtual voltage vector, the method for dividing the space vector diagram region of the coupled three-level inverter is determined, specifically:

[0073] Based on the two pairs of small vectors in the first sector of the space vector diagram of the coupled three-level inverter, the first virtual voltage vector and the second virtual voltage vector are synthesized respectively;

[0074] Based on the two virtual voltage vectors and the two large vectors, the duty cycles of the two virtual voltage vectors are determined by the indirect method;

[0075] The duty cycle distribution factor of the virtual voltage vector is calculated according to the duty cycles of the two virtual voltage vectors;

[0076] Considering the value range of the large vector, the duty cycle distribution factor of the small vector, and when the DC side unbalance factor is zero, the value range of the duty cycle distribution factor of the two virtual voltage vectors is determined;

[0077] Determine two straight lines passing through the first sector based on the maximum and minimum values of the duty cycle distribution factor of the virtual voltage vector, which respectively represent the connection line of a virtual voltage vector and a large vector;

[0078] Use the two straight lines as the region division conditions to divide the first sector of the space vector diagram of the coupled three-level inverter. Specifically as follows:

[0079] The small vectors in sector 1 include the first pair of small vectors [POO](V S1p ) and [ONN](V S1n ), the second pair of small vectors [PPO](V S2p ) and [OON](V S2n ). Their amplitudes are no longer equal and it is difficult to synthesize the reference voltage vector. Therefore, each pair of small vectors synthesizes a virtual voltage vector, and their expressions are respectively:

[0080]

[0081] Among them, V v1 and V v2 respectively represent two virtual vectors of the first virtual voltage vector and the second virtual voltage vector, and α is the duty cycle distribution factor of the small vector.

[0082] Therefore, all the basic voltage vectors in sector 1 are respectively expressed as:

[0083]

[0084] Among them, V L1 , V L2 and V Z respectively represent the large vector [PNN], the large vector [PPN] and the zero vector [OOO].

[0085] Relationship between line current (i np ) and basic voltage vector in Table 1

[0086]

[0087]

[0088] 1. Calculation of virtual vector duty cycle distribution factor

[0089] When the reference voltage vector (Vref) is located in the outer region of sector 1, use two virtual voltage vectors and two large vectors to synthesize the reference voltage, and its volt-second balance equation is:

[0090]

[0091] Among them, d L1 , d L2, d v1 and d v2 respectively represent the duty cycles of V L1 , V L2 , V v1 and V v2 .

[0092] After simplification, the sum of the duty cycles of the virtual vectors (d v12 ) is:

[0093]

[0094] Among them, m is the modulation index, and its expression is:

[0095]

[0096] Let the duty cycle distribution factor of the virtual voltage vector be β, and the duty cycles (d v1 and d v2 ) of each virtual voltage vector can be respectively expressed as:

[0097]

[0098] Therefore, the duty cycles of the two large vectors are:

[0099]

[0100] Considering that d L1 and d L2 should be greater than 0, and 0 ≤ β ≤ 1, the maximum value β max and the minimum value β min are respectively:

[0101]

[0102] 2. Analysis of the Duty Cycle Distribution Factor of the Virtual Voltage Vector

[0103] When the duty cycle distribution factor α of the small vector and the DC side imbalance factor μ are equal to 0, β max and β min under different modulation indices are as Figure 4 shown. It is not difficult to find that β max and β min can take 0 or 1 within a certain range. In addition, as the modulation index increases, the maximum and minimum values of β can take 0 or 1 in a larger interval.

[0104] When β max is equal to 1, Equation (11) can be expressed as:

[0105]

[0106] Similarly, when βmin When it is equal to 0, Equation (12) can be expressed as:

[0107]

[0108] It can be seen that Equation (13) and Equation (14) respectively represent two straight lines passing through Sector 1. At this time, the two straight lines respectively pass through a small vector and a large vector, and its space vector diagram is shown in Figure 5. Taking the above two straight lines as the region division conditions, only three voltage vectors are used to synthesize the reference voltage vector, which reduces the calculation burden.

[0109] When the reference voltage vector is located in Sector 1, the small vectors [POO], [ONN], [PPO] and [OON] determine the neutral line current, that is, the output currents i a and i c directly determine the DC-side capacitor current ripple. Therefore, the DC-side capacitor current ripple can be suppressed by discarding the virtual voltage vector with a larger neutral line current amplitude. Specifically, when |i a | ≤ |i c |, β should be equal to 1; when |i a | > |i c |, β should be 0. When the reference voltage vector is located in other sectors outside Sector 1, the values of the duty ratio distribution factors of the virtual voltage vectors can be obtained using the above principle, which will not be elaborated here.

[0110] When |i a | ≤ |i c |, Figure 6 and Figure 7 are the neutral point current and output voltage waveforms of the traditional method and the method of the present invention. Since the small vectors [POO] and [ONN] with higher neutral line current amplitude are discarded, the method of the present invention can effectively reduce the DC-side capacitor current ripple.

[0111] 3. Independent control of capacitor voltage

[0112] As mentioned above, in a large-capacity centralized photovoltaic power generation system, by connecting a set of photovoltaic arrays to both ends of each DC-side capacitor respectively, the voltages at both ends of the two capacitors C1 and C2 of the DC-side capacitor are controlled respectively to achieve the independent MPPT function and improve the system efficiency. For this purpose, a controller is designed based on the deadbeat control method to accurately adjust the neutral line current, obtain the duty ratio distribution factors of the P-type small vector and the N-type small vector, and update the duty ratios of each basic voltage vector to achieve independent control of the capacitor voltage.

[0113] According to Kirchhoff's Current Law (KCL), the mathematical model of the neutral line current can be expressed as:

[0114]

[0115] Among them, C dc is the DC-side capacitor, and C dc = C1 = C2.

[0116] Assume that a sampling period is T s , and the discrete model of the neutral line current can be expressed as:

[0117]

[0118] Among them, V diff (k) and V diff (k + 1) respectively represent the difference in capacitor voltages at the kth and (k + 1)th sampling periods, and i np (k) is the neutral line current value at the kth sampling period.

[0119] Let V diff (k + 1) be the given value of the capacitor voltage deviation Then the reference value of the neutral line current can be expressed as:

[0120]

[0121] Specifically, when the reference voltage vector is in sector 1 (regions A1 and B1), that is, in the first region of the first sector, the relationship between the neutral line current and the duty cycle is:

[0122] i np = i a d S1n + i b d S1p + i c d S1p (18);

[0123] Among them, d S1p and d S1n respectively represent the duty cycles of the first pair of small vectors [POO] and [ONN], and i a , i b and i c are the three-phase output currents of the inverter respectively.

[0124] To achieve independent control of the capacitor voltage, the duty cycles of d S1p and d S1n are corrected as:

[0125]

[0126] Among them, y np is an intermediate variable, and the relationship between y np and the small vector duty cycle allocation factor α is:

[0127]

[0128] Combining equations (17), (18) and (19), we can obtain the optimal value of y np as follows:

[0129]

[0130] When the reference voltage vector is located in other sectors and regions, the optimal value of y np can be solved according to the above method. When the reference voltage vector is located in Sector 1, Regions A2 and B2, the optimal value of y np is as follows:

[0131]

[0132] When the reference voltage vector is located in Sector 2, Regions A1 and B1, the optimal value of y np is as follows:

[0133]

[0134] When the reference voltage vector is located in Sector 2, Regions A2 and B2, the optimal value of y np is as follows:

[0135]

[0136] When the reference voltage vector is located in Sector 3, Regions A1 and B1, the optimal value of y np is as follows:

[0137]

[0138] When the reference voltage vector is located in Sector 3, Regions A2 and B2, the optimal value of y np is as follows:

[0139]

[0140] When the reference voltage vector is located in Sector 4, Regions A1 and B1, the optimal value of y np is as follows:

[0141]

[0142] When the reference voltage vector is located in Sector 4, Regions A2 and B2, the optimal value of y np is as follows:

[0143]

[0144] When the reference voltage vector is located in Sector 5, Regions A1 and B1, the optimal value of y np is as follows:

[0145]

[0146] When the reference voltage vector is located in Sector 5, Region A2 and B2, the optimal value of y np is:

[0147]

[0148] When the reference voltage vector is located in Sector 6, Region A1 and B1, the optimal value of y np is:

[0149]

[0150] When the reference voltage vector is located in Sector 6, Region A2 and B2, the optimal value of y np is:

[0151]

[0152] 4. Switching Sequence Design

[0153] Considering factors such as low harmonic content in the output of the coupled three-level inverter, small influence of dead time, and few switching times of power switches, the switching sequence is designed.

[0154] When the reference voltage vector is located in Region A1 within Sector 1, the five-segment switching sequence is designed as follows: [PNN]-[POO]-[PPN]-[ONN]-[PNN];

[0155] When the reference voltage vector is located in Region A2 within Sector 1, the five-segment switching sequence is designed as follows: [PNN]-[PPO]-[PPN]-[OON]-[PNN];

[0156] When the reference voltage vector is located in Region B1 within Sector 1, the five-segment switching sequence is designed as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN];

[0157] When the reference voltage vector is located in Region B2 within Sector 1, the five-segment switching sequence is designed as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN];

[0158] When the reference voltage vector is located in Region A1 within Sector 2, the five-segment switching sequence is designed as follows: [PPN]-[PPO]-[NPN]-[OON]-[PPN];

[0159] When the reference voltage vector is located in Region A2 within Sector 2, the five-segment switching sequence is designed as follows: [PPN]-[OPO]-[NPN]-[NON]-[PPN];

[0160] When the reference voltage vector is in region B1 within sector 2, the five-segment switching sequence is designed as follows: [NPN]-[PPO]-[OOO]-[OON]-[NPN];

[0161] When the reference voltage vector is in region B2 within sector 2, the five-segment switching sequence is designed as follows: [PPN]-[OPO]-[OOO]-[NON]-[PPN];

[0162] When the reference voltage vector is in region A1 within sector 3, the five-segment switching sequence is designed as follows: [NPN]-[OPO]-[NPP]-[NON]-[NPN];

[0163] When the reference voltage vector is in region A2 within sector 3, the five-segment switching sequence is designed as follows: [NPN]-[OPP]-[NPP]-[NOO]-[NPN];

[0164] When the reference voltage vector is in region B1 within sector 3, the five-segment switching sequence is designed as follows: [NPP]-[OPO]-[OOO]-[NON]-[NPP];

[0165] When the reference voltage vector is in region B2 within sector 3, the five-segment switching sequence is designed as follows: [NPN]-[OPP]-[OOO]-[NOO]-[NPN];

[0166] When the reference voltage vector is in region A1 within sector 4, the five-segment switching sequence is designed as follows: [NPP]-[OPP]-[NNP]-[NOO]-[NPP];

[0167] When the reference voltage vector is in region A2 within sector 4, the five-segment switching sequence is designed as follows: [NPP]-[OOP]-[NNP]-[NNO]-[NPP];

[0168] When the reference voltage vector is in region B1 within sector 4, the five-segment switching sequence is designed as follows: [NNP]-[OPP]-[OOO]-[NOO]-[NNP];

[0169] When the reference voltage vector is in region B2 within sector 4, the five-segment switching sequence is designed as follows: [NPP]-[OOP]-[OOO]-[NNO]-[NPP];

[0170] When the reference voltage vector is in region A1 within sector 5, the five-segment switching sequence is designed as follows: [NNP]-[OOP]-[PNP]-[NNO]-[NNP];

[0171] When the reference voltage vector is in region A2 within sector 5, the five-segment switching sequence is designed as follows: [NNP]-[POP]-[PNP]-[ONO]-[NNP];

[0172] When the reference voltage vector is in region B1 within sector 5, the five-segment switching sequence is designed as follows: [PNP]-[OOP]-[OOO]-[NNO]-[PNP];

[0173] When the reference voltage vector is in region B2 within sector 5, the five-segment switching sequence is designed as follows: [NNP]-[POP]-[OOO]-[ONO]-[NNP];

[0174] When the reference voltage vector is in region A1 within sector 6, the five-segment switching sequence is designed as follows: [PNP]-[POP]-[PNN]-[ONO]-[PNP];

[0175] When the reference voltage vector is in region A2 within sector 6, the five-segment switching sequence is designed as follows: [PNP]-[POO]-[PNN]-[ONN]-[PNP];

[0176] When the reference voltage vector is in region B1 within sector 6, the five-segment switching sequence is designed as follows: [PNN]-[POP]-[OOO]-[ONO]-[PNN];

[0177] When the reference voltage vector is in region B2 within sector 6, the five-segment switching sequence is designed as follows: [PNP]-[POO]-[OOO]-[ONN]-[PNP].

[0178] The switching sequence is converted into the driving signals of the power switching tubes, thereby controlling the operation of the coupled three-level inverter system.

[0179] Figure 8 This is the schematic diagram of the method for suppressing the DC-side capacitor current ripple in the first embodiment of the present invention.

[0180] Figure 9 is the simulation waveform diagram of the system using the traditional space vector modulation method with a modulation index of 0.8, including the DC-side capacitor voltages (V P and V N ), line voltages (V ab ), phase-A output voltage (i a ), and neutral line current (i np) Among them, the imbalance coefficient of Fig. 9(a) is set to 0.2, the imbalance coefficient of Fig. 9(b) is set to -0.2, and the imbalance coefficient of Fig. 9(c) is set to 0. At this time, the DC-side input voltage is 100V. It can be seen that the DC-side current ripple of the system is very high, and the effective values of the DC-side capacitor current ripple are as high as 2.621A, 2.622A, and 2.621A respectively.

[0181] Fig. 10 is the simulation waveform diagram of the system when using the control method of Embodiment 1 of the present invention and the modulation degree is 0.8. Among them, the imbalance coefficient of Fig. 10(a) is set to 0.2, the imbalance coefficient of Fig. 10(b) is set to -0.2, and the imbalance coefficient of Fig. 10(c) is set to 0. At this time, the line voltage of the system is a five-level waveform, and the output current is a sine waveform. The effective values of the DC-side capacitor current ripple of the system are respectively reduced to 1.715A, 1.709A, and 1.711A. It can be seen that the DC-side capacitor current ripple of the system is 65.43%, 65.18%, and 65.28% of the traditional space vector modulation method respectively, and maintains good output current quality, with obvious advantages.

[0182] Fig. 11 is the simulation waveform diagram of the system when using the traditional space vector modulation method and the modulation degree is 0.4. Among them, the imbalance coefficient of Fig. 11(a) is set to 0.2, the imbalance coefficient of Fig. 11(b) is set to -0.2, and the imbalance coefficient of Fig. 11(c) is set to 0. It can be seen that the line voltage (V ab ) is reduced to a three-level waveform, and the output current quality of the system has decreased. The total harmonic distortion rate (THD i ) of its output current is 1.82%, 1.82%, and 1.76% respectively. The DC-side capacitor current ripple of the system is very high, and the DC-side capacitor current ripple is as high as 1.718A, 1.718A, and 1.718A respectively.

[0183] Fig. 12 is the simulation when the system uses the control method of Embodiment 1 of the present invention and the modulation degree is 0.4. Among them, the imbalance coefficient of Fig. 12(a) is set to 0.2, the imbalance coefficient of Fig. 12(b) is set to -0.2, and the imbalance coefficient of Fig. 12(c) is set to 0. At this time, the line voltage is a five-level waveform, and the output current is a sine waveform. The DC-side capacitor current ripple of the system is reduced by 54.83%, 55.30%, and 55.15% respectively compared with the traditional space vector modulation method, with obvious advantages.

[0184] FIG. 13 is a simulation waveform diagram of the system using the control method of Embodiment 1 of the present invention when the given value of the capacitor voltage deviation undergoes a step change. It can be seen that the control method of Embodiment 1 of the present invention can independently control the capacitor voltages of the two DC sides. In addition, while suppressing the capacitor current ripple on the DC side under dynamic conditions, the control method of Embodiment 1 of the present invention maintains good output current waveform quality.

[0185] Embodiment 2

[0186] This embodiment provides a system for suppressing the capacitor current ripple on the DC side of a coupled three-level inverter, including:

[0187] A sector division module, configured to determine the method for dividing the space vector diagram region of the coupled three-level inverter according to the value range of the duty ratio distribution factor of the virtual voltage vector;

[0188] A sector judgment module, configured to judge the sector and region where the reference voltage vector is located according to the amplitude, phase angle of the reference voltage vector, and the three-phase output current;

[0189] A basic voltage vector selection module, configured to select the nearest virtual voltage vector and two basic voltage vectors according to the sector and region where the reference voltage vector is located, and calculate their duty ratios respectively;

[0190] A capacitor voltage independent control module, configured to design a controller based on the deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation, and the actual value of the DC side capacitor voltage deviation, update the duty ratio distribution factor of the small vector, and realize independent control of the capacitor voltage;

[0191] A drive signal generation module, configured to design a switching sequence based on the updated duty ratio of the small vector and the sector and region where the reference voltage vector is located, convert the switching sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0192] The examples and application scenarios implemented by the above modules and the corresponding steps are the same, but are not limited to the content disclosed in the above Embodiment 1. It should be noted that the above modules, as part of the system, can be executed in a computer system such as a set of computer-executable instructions.

[0193] In the above embodiments, the descriptions of each embodiment have their own focuses. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0194] The proposed system can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the above modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0195] Embodiment III

[0196] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the steps in the method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter as described in Embodiment I above.

[0197] Embodiment IV

[0198] This embodiment provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in the method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter as described in Embodiment I above.

[0199] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can adopt the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories and optical memories, etc.) containing computer-usable program code.

[0200] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the specified functions in Figure 1 one or more flows or multiple flows and / or blocks Figure 1 one or more blocks or multiple blocks.

[0201] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the specified functions in the flow Figure 1One or more processes and / or blocks Figure 1 The functions specified in one or more blocks.

[0202] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one Figure 1 One or more processes and / or blocks Figure 1 The steps of the functions specified in one or more blocks.

[0203] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), or a random access memory (RAM), etc.

[0204] Although the specific implementation manners of the present invention have been described above in conjunction with the accompanying drawings, it is not a limitation on the protection scope of the present invention. Those skilled in the art should understand that, based on the technical solutions of the present invention, various modifications or deformations that can be made by those skilled in the art without creative efforts are still within the protection scope of the present invention.

Claims

1. A method for suppressing the DC-side capacitor current ripple of a coupled three-level inverter, characterized in that Including: Determine the region division method of the space vector diagram of the coupled three-level inverter according to the value range of the duty ratio distribution factor of the virtual voltage vector; Specifically: synthesize the first virtual voltage vector and the second virtual voltage vector from two pairs of small vectors in the first sector of the space vector diagram of the coupled three-level inverter respectively; determine the duty ratios of the two virtual voltage vectors based on the indirect method according to the two virtual voltage vectors and the two large vectors; calculate the duty ratio distribution factor of the virtual voltage vector according to the duty ratios of the two virtual voltage vectors; consider the value range of the large vector, the duty ratio distribution factor of the small vector, and when the DC-side unbalance factor is zero, determine the value range of the duty ratio distribution factor of the two virtual voltage vectors; determine two straight lines passing through the first sector based on the maximum and minimum values of the duty ratio distribution factor of the virtual voltage vector, which respectively represent the connection line of a virtual voltage vector and a large vector; use the two straight lines as the region division conditions to divide the first sector of the space vector diagram of the coupled three-level inverter; when the maximum value of the duty ratio distribution factor of the virtual voltage vector is 1, it is obtained that: When the minimum value of the duty ratio distribution factor of the virtual voltage vector is 0, it is obtained that: Among them, μ is the DC side unbalance factor, α is the small vector duty cycle allocation factor, V ref is the reference voltage vector, V dc is the sum of the voltages of the two capacitors on the DC side; Judge the sector and region where the reference voltage vector is located according to the amplitude, phase angle and three-phase output current of the reference voltage vector; Select a virtual voltage vector and two basic voltage vectors closest in distance according to the sector and region where the reference voltage vector is located, and calculate their duty ratios respectively; Design a controller based on the deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation, update the duty ratio distribution factor of the small vector, and realize the independent control of the capacitor voltage; Design a switching sequence based on the updated duty ratio of the small vector and the sector and region where the reference voltage vector is located, convert the switching sequence into the PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

2. The method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter according to claim 1, characterized in that, The specific operation of selecting a virtual voltage vector and two basic voltage vectors closest in distance and calculating their duty ratios respectively is as follows: Synthesize the first virtual voltage vector and the second virtual voltage vector from two pairs of small vectors in the first sector of the space vector diagram of the coupled three-level inverter respectively; Based on the two virtual voltage vectors and the two large vectors, determine the duty ratios of the two virtual voltage vectors and the two large vectors based on the indirect method; Discard the virtual voltage vector with a large assigned midline current, and select the other virtual voltage vector and two basic voltage vectors to calculate their duty ratios respectively.

3. The method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter according to claim 1, characterized in that, The specific operation of designing a controller based on the deadbeat control method according to the sector and region where the reference voltage vector is located, the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation, updating the duty ratio distribution factor of the small vector, and realizing the independent control of the capacitor voltage is as follows: Determine the discrete model of the midline current according to the given value of the DC-side capacitor voltage deviation and the actual value of the DC-side capacitor voltage deviation; Design a controller based on the deadbeat control method according to the discrete model of the midline current to adjust the midpoint voltage; Determine the relationship between the neutral current and the duty ratio distribution factor of the small vectors in the first sector based on the sector and region where the reference voltage vector is located; Update the duty ratio of the small vectors based on the neutral current to achieve independent control of the capacitor voltage.

4. The method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter according to claim 1, wherein Based on the updated duty ratio of the small vectors and the sector and region where the reference voltage vector is located, design the switching sequence. Specifically: Determine the expression for the optimal value of the intermediate variable in the first sector according to the relationship between the neutral current and the duty ratio of the selected small vectors in the first sector and the reference value of the neutral current; Determine the optimal value of the intermediate variable when the reference voltage vector is in other sectors and regions according to the expression for the optimal value of the intermediate variable in the first sector; Determine the duty ratio distribution factor of the small vectors according to the magnitude of the neutral current; Design different switching sequences based on the optimal values of the intermediate variables when the reference voltage is in different sectors and regions.

5. The method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter according to claim 1, wherein The design of the switching sequence is specifically as follows: When the reference voltage vector is in region A1 of sector 1, design a five-segment switching sequence as follows: [PNN]-[POO]-[PPN]-[ONN]-[PNN]; When the reference voltage vector is in region A2 of sector 1, design a five-segment switching sequence as follows: [PNN]-[PPO]-[PPN]-[OON]-[PNN]; When the reference voltage vector is in region B1 of sector 1, design a five-segment switching sequence as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN]; When the reference voltage vector is in region B2 of sector 1, design a five-segment switching sequence as follows: [PPN]-[POO]-[OOO]-[ONN]-[PPN]; When the reference voltage vector is in region A1 of sector 2, design a five-segment switching sequence as follows: [PPN]-[PPO]-[NPN]-[OON]-[PPN]; When the reference voltage vector is in region A2 of sector 2, design a five-segment switching sequence as follows: [PPN]-[OPO]-[NPN]-[NON]-[PPN]; When the reference voltage vector is in region B1 of sector 2, design a five-segment switching sequence as follows: [NPN]-[PPO]-[OOO]-[OON]-[NPN]; When the reference voltage vector is in region B2 of sector 2, design a five-segment switching sequence as follows: [PPN]-[OPO]-[OOO]-[NON]-[PPN]; When the reference voltage vector is in region A1 of sector 3, design a five-segment switching sequence as follows: [NPN]-[OPO]-[NPP]-[NON]-[NPN]; When the reference voltage vector is in region A2 of sector 3, design a five-segment switching sequence as follows: [NPN]-[OPP]-[NPP]-[NOO]-[NPN]; When the reference voltage vector is in region B1 of sector 3, design a five-segment switching sequence as follows: [NPP]-[OPO]-[OOO]-[NON]-[NPP]; When the reference voltage vector is in region B2 of sector 3, the five-segment switching sequence is designed as follows: [NPN]-[OPP]-[OOO]-[NOO]-[NPN]; When the reference voltage vector is in region A1 of sector 4, the five-segment switching sequence is designed as follows: [NPP]-[OPP]-[NNP]-[NOO]-[NPP]; When the reference voltage vector is in region A2 of sector 4, the five-segment switching sequence is designed as follows: [NPP]-[OOP]-[NNP]-[NNO]-[NPP]; When the reference voltage vector is in region B1 of sector 4, the five-segment switching sequence is designed as follows: [NNP]-[OPP]-[OOO]-[NOO]-[NNP]; When the reference voltage vector is in region B2 of sector 4, the five-segment switching sequence is designed as follows: [NPP]-[OOP]-[OOO]-[NNO]-[NPP]; When the reference voltage vector is in region A1 of sector 5, the five-segment switching sequence is designed as follows: [NNP]-[OOP]-[PNP]-[NNO]-[NNP]; When the reference voltage vector is in region A2 of sector 5, the five-segment switching sequence is designed as follows: [NNP]-[POP]-[PNP]-[ONO]-[NNP]; When the reference voltage vector is in region B1 of sector 5, the five-segment switching sequence is designed as follows: [PNP]-[OOP]-[OOO]-[NNO]-[PNP]; When the reference voltage vector is in region B2 of sector 5, the five-segment switching sequence is designed as follows: [NNP]-[POP]-[OOO]-[ONO]-[NNP]; When the reference voltage vector is in region A1 of sector 6, the five-segment switching sequence is designed as follows: [PNP]-[POP]-[PNN]-[ONO]-[PNP]; When the reference voltage vector is in region A2 of sector 6, the five-segment switching sequence is designed as follows: [PNP]-[POO]-[PNN]-[ONN]-[PNP]; When the reference voltage vector is in region B1 of sector 6, the five-segment switching sequence is designed as follows: [PNN]-[POP]-[OOO]-[ONO]-[PNN]; When the reference voltage vector is in region B2 of sector 6, the five-segment switching sequence is designed as follows: [PNP]-[POO]-[OOO]-[ONN]-[PNP].

6. A DC-side capacitor current ripple suppression system for a coupled three-level inverter, characterized in that Including: A sector division module configured to determine a method for dividing the space vector diagram region of a coupled three-level inverter according to the value range of the virtual voltage vector duty ratio distribution factor; Specifically: Synthesize the first virtual voltage vector and the second virtual voltage vector according to two pairs of small vectors in the first sector of the space vector diagram of the coupled three-level inverter; Determine the duty cycles of the two virtual voltage vectors based on the indirect method according to the two virtual voltage vectors and two large vectors; Calculate the duty cycle distribution factor of the virtual voltage vector according to the duty cycles of the two virtual voltage vectors; Considering the value range of the large vector, the duty cycle distribution factor of the small vector, and when the DC-side unbalance factor is zero, determine the value range of the duty cycle distribution factors of the two virtual voltage vectors; Determine two straight lines passing through the first sector based on the maximum and minimum values of the duty cycle distribution factor of the virtual voltage vector, which respectively represent the connection line between a virtual voltage vector and a large vector; Use the two straight lines as the region division conditions to divide the first sector of the space vector diagram of the coupled three-level inverter; When the maximum value of the duty cycle distribution factor of the virtual voltage vector is 1, it is obtained that: When the minimum value of the duty cycle distribution factor of the virtual voltage vector is 0, it is obtained that: Among them, μ is the DC-side imbalance factor, α is the duty ratio distribution factor of the small vector, and V ref is the reference voltage vector, and V dc is the sum of the voltages of the two capacitors on the DC side; A sector judgment module, configured to judge the sector and region where the reference voltage vector is located according to the amplitude, phase angle, and three-phase output current of the reference voltage vector; A basic voltage vector selection module, configured to select the nearest virtual voltage vector and two basic voltage vectors according to the sector and region where the reference voltage vector is located, and calculate their duty cycles respectively; A capacitor voltage independent control module, configured to design a controller based on the deadbeat control method according to the sector and region where the reference voltage vector is located, the DC-side capacitor voltage deviation given value, and the actual DC-side capacitor voltage deviation, update the duty cycle distribution factor of the small vector, and achieve independent control of the capacitor voltage; A drive signal generation module, configured to design a switching sequence based on the updated duty cycle of the small vector and the sector and region where the reference voltage vector is located, convert the switching sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter according to any one of claims 1-5.

8. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the method for suppressing the DC-side capacitor current ripple of the coupled three-level inverter according to any one of claims 1-5.

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