Radio frequency circuit, control method thereof and electronic equipment

Abstract

The embodiment of the invention provides a radio frequency circuit, a control method thereof and electronic equipment, the radio frequency circuit comprises a digital front-end processor, a signal converter and a plurality of first radio frequency transceivers, and the digital front-end processor comprises a first interface circuit; the signal converter is connected with the first interface circuit and the plurality of first radio frequency transceivers, obtains a plurality of first control signals based on a first request signal sent by the first interface circuit, and respectively sends the plurality of first control signals to the plurality of first radio frequency transceivers; based on a plurality of second request signals sent by a plurality of first radio frequency transceivers, a second control signal is obtained, and the second control signal is sent to the first interface circuit; the plurality of first radio frequency transceivers are connected with the first interface circuit, and each first radio frequency transceiver responds to the first control signal and sends input data to the first interface circuit; the first interface circuit transmits output data to each of the first radio frequency transceivers in response to the second control signal.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a radio frequency circuit and a control method thereof, and an electronic device. Background Art

[0002] The Remote Radio Unit (RRU) is a device that converts baseband optical signals into RF signals, amplifies them, and transmits them at a location far away from the Base band Unit (BBU). The main hardware requirements of the Remote Radio Unit include Digital Front End (DFE), RF Transceiver, power amplifier, etc. Low-cost hardware can enable the Remote Radio Unit to support dual transmit channels, dual receive channels (i.e. 2T2R) and four transmit channels, four receive channels (i.e. 4T4R). When 6T6R or 8T8R needs to be implemented, expensive or even imported RF transceiver chips that support 4T4R or 8T8R need to be used, which leads to a sharp increase in costs and is not conducive to the localization of the Remote Radio Unit. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a radio frequency circuit and a control method thereof, and an electronic device.

[0004] According to a first aspect of the present disclosure, there is provided a radio frequency circuit, comprising:

[0005] A digital front-end processor, a signal converter and a plurality of first radio frequency transceivers, wherein the digital front-end processor includes a first interface circuit;

[0006] The signal converter is connected to the first interface circuit and the plurality of first RF transceivers. The signal converter obtains a plurality of first control signals based on a first request signal sent by the first interface circuit, and sends the first control signals to the plurality of first RF transceivers respectively; and obtains a second control signal based on a plurality of second request signals sent by the plurality of first RF transceivers, and sends the second control signal to the first interface circuit.

[0007] The plurality of first radio frequency transceivers are connected to the first interface circuit, and each of the first radio frequency transceivers sends input data to the first interface circuit in response to the first control signal;

[0008] The first interface circuit sends output data to each of the first radio frequency transceivers in response to the second control signal.

[0009] In some embodiments, the signal converter comprises:

[0010] A first signal processing unit, connected to a signal output interface of the first interface circuit and a signal input interface of each of the first radio frequency transceivers, wherein the first signal conversion unit obtains a plurality of synchronized first control signals based on the first request signal;

[0011] A second signal conversion unit is connected to a signal input end of the first interface circuit and a signal output port of each of the first radio frequency transceivers, and the second signal conversion unit obtains the second control signal based on a plurality of the second request signals.

[0012] In some embodiments, the first signal processing unit includes: a splitter, which splits the first request signal from one path into multiple paths to obtain the multiple synchronized first control signals.

[0013] In some embodiments, the first request signal is a first differential request signal in the form of a differential signal, and the first control signal is a first differential control signal in the form of a differential signal;

[0014] The splitter is a differential clock splitter.

[0015] In some embodiments, the second signal conversion unit includes: an AND gate logic circuit, and the AND gate logic circuit sends the second control signal after receiving a plurality of the second request signals sent by a plurality of the first RF transceivers.

[0016] In some embodiments, the second request signal is a second differential request signal in the form of a differential signal, and the second control signal is a second differential control signal in the form of a differential signal; and the AND gate logic circuit includes:

[0017] a plurality of differential-to-single-ended circuits, wherein a differential input end of each of the differential-to-single-ended circuits is connected to a signal output interface of the first radio frequency transceiver, and each of the differential-to-single-ended circuits converts the second differential request signal into a single-ended request signal;

[0018] A single-ended AND gate, wherein a plurality of input ends of the single-ended AND gate are connected to the single-ended output ends of the plurality of differential-to-single-ended circuits, and the single-ended AND gate issues the single-ended control signal after receiving a plurality of the single-ended request signals issued by the plurality of differential-to-single-ended circuits;

[0019] A single-ended to differential circuit, wherein the single-ended input end of the single-ended to differential circuit is connected to the output end of the single-ended AND gate, and the differential output end of the single-ended to differential circuit is connected to the signal input interface of the first interface circuit; the single-ended to differential circuit converts the single-ended control signal into a second differential control signal and sends it to the first interface circuit.

[0020] In some embodiments, the digital front-end processor further comprises: a second interface circuit;

[0021] The radio frequency circuit further includes a second radio frequency transceiver connected to the second interface circuit;

[0022] The second RF transceiver sends input data to the second interface circuit in response to a third request signal sent by the second interface circuit; and after sending a fourth request signal to the second interface circuit, receives output data sent by the second interface circuit.

[0023] According to a second aspect of the present disclosure, an electronic device is provided, comprising the radio frequency circuit as claimed in any one of claims 1 to 7.

[0024] According to a second aspect of the present disclosure, a control method for a radio frequency circuit is provided, wherein the radio frequency circuit includes a digital front-end processor, a signal converter, and a plurality of first radio frequency transceivers, and the digital front-end processor includes a first interface circuit; the control method includes:

[0025] The signal converter obtains a plurality of first control signals based on the first request signal sent by the first interface circuit, and sends the first control signals to the plurality of first RF transceivers respectively; each of the first RF transceivers sends input data to the first interface circuit in response to the first control signal;

[0026] The signal converter receives a second request signal sent by each of the plurality of first RF transceivers, obtains a second control signal based on the plurality of second request signals and sends the second control signal to the first interface circuit, and the first interface circuit sends output data to each of the first RF transceivers in response to the second control signal.

[0027] In some embodiments, the digital front-end processor further includes a second interface circuit, the radio frequency circuit further includes a second radio frequency transceiver; and the control method further includes:

[0028] The second RF transceiver sends input data to the second interface circuit in response to a third request signal sent by the second interface circuit, and receives output data sent by the second interface circuit after sending a fourth request signal to the second interface circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of an RRU including a digital front-end chip and a radio frequency transceiver chip provided in an embodiment of the present disclosure Figure 1 ;

[0030] Figure 2 Schematic diagram of an RRU including a digital front-end chip and a radio frequency transceiver chip provided in an embodiment of the present disclosure Figure 2 ;

[0031] Figure 3 Schematic diagram of an RRU including a digital front-end chip and a radio frequency transceiver chip provided in an embodiment of the present disclosure Figure 3 ;

[0032] Figure 4 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 1 ;

[0033] Figure 5 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 2 ;

[0034] Figure 6 A schematic diagram of a splitter provided in an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of an AND gate logic circuit provided in an embodiment of the present disclosure;

[0036] Figure 8 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 3 ;

[0037] Fig. 9 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 4 ;

[0038] Fig.10 A schematic diagram of a signal synchronization operation between a receiver and a transmitter provided in an embodiment of the present disclosure;

[0039] Fig.11 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 5 ;

[0040] Fig.12 A flowchart of a method for controlling a radio frequency circuit provided in an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0042] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0046] Figure 1 Schematic diagram of an RRU including a digital front-end chip and a radio frequency transceiver chip provided in an embodiment of the present disclosure Figure 1 .like Figure 1 As shown, a low-cost or domestically produced digital front-end chip DFE usually includes only two JESD204B interface circuits P0 and P1. Each JESD204B interface circuit includes a group of signal interfaces and four groups of data interfaces. A group of signal interfaces includes a signal input interface JESD SYNC_IN and a signal output interface JESD SYNC_OUT. Each group of data interfaces includes a data input interface SERDES IN and a data output interface SERDES OUT. Figure 1 SERDES OUT*2 in the figure indicates two SERDES OUT interfaces, and similarly, SERDES IN*2 indicates two SERDES IN interfaces. Since each JESD204B interface circuit includes only one set of signal interfaces, each JESD204B interface circuit can normally only be connected to one RF transceiver chip.

[0047] Continue to see Figure 1Each RF transceiver chip TRX includes a set of signal interfaces JESD SYNC_IN, JESDSYNC_OUT and two sets of data interfaces SERDES IN*2, SERDES OUT*2. Each RF transceiver chip supports 2T2R through two sets of data interfaces. The two JESD204B interface circuits P0 and P1 of the digital front-end chip are connected to the two RF transceiver chips TRX1 and TRX2 respectively. Therefore, Figure 1 The RRU shown can support up to 4T4R.

[0048] Figure 2 Schematic diagram of an RRU including a digital front-end chip and a radio frequency transceiver chip provided in an embodiment of the present disclosure Figure 2 .like Figure 2 As shown, when it is required to use low-cost or domestic digital front-end chip DFE to drive more RF transceiver chips TRX to improve signal transmission efficiency, for example, Figure 2 The digital front-end chip DFE is required to drive three RF transceiver chips to achieve 6T6R. The signal interface and data interface of the first RF transceiver chip TRX1 are respectively connected to the signal interface and data interface of the P0 interface circuit of the digital front-end chip DFE, and the signal interface and data interface of the third RF transceiver chip TRX are respectively connected to the signal interface and data interface of the P1 interface circuit of the digital front-end chip DFE. Since the number of data interfaces of an interface circuit in the digital front-end chip DFE is greater than the number of data interfaces of the RF transceiver chip TRX, the data interface of the second RF transceiver chip TRX2 can be connected to the P0 interface circuit, but the signal interface of the second RF transceiver chip TRX cannot be connected to the digital front-end chip, resulting in the inability to be driven, that is, the inability to achieve 6T6R.

[0049] In one embodiment, an expensive 8T8R radio frequency transceiver chip or two 4T4R radio frequency transceiver chips can be used to meet the requirements of 6T6R and 8T8R. However, these two chips are expensive and are usually not domestically designed.

[0050] Figure 3 Schematic diagram of an RRU including a digital front-end chip and a radio frequency transceiver chip provided in an embodiment of the present disclosure Figure 3 .like Figure 3As shown, in other embodiments, the above-mentioned low-cost or domestically produced digital front-end chip DFE can be used to connect two RF transceiver chips TRX1 and TRX2 that support 2T2R to achieve 4T4R. At the same time, an additional small-scale FPGA (Field-Programmable Gate Array) is added. The FPGA is connected to the third RF transceiver chip TRX3 that supports 2T2R, and is connected to the digital front-end chip DFE. Specifically, a GTX (Gigabit Transceiver, high-speed serial) interface of the FPGA is connected to the optical port of the baseband processing unit BBU, and the GTX interface of the FPGA and the optical port communicate based on the CPRI (Common Public Radio Interface) protocol. Another GTX interface of the FPGA is connected to the digital front-end chip DFE, and communicates with the digital front-end chip DFE based on the CPRI protocol.

[0051] On the one hand, FPGA can achieve the same functions as the digital front-end chip DFE, filter the data of the third RF transceiver chip TRX3, perform data pre-distortion processing, etc., and communicate based on LVDS (Low-Voltage DifferentialSignaling). On the other hand, FPGA can aggregate and distribute data. Specifically, FPGA can combine the data transmitted from the digital front-end chip DFE and the data transmitted from the third RF transceiver chip TRX3 and transmit them to the optical port. It can also distribute part of the data from the optical port to the digital front-end chip DFE, and process the other part by itself and send it to the third RF transceiver chip TRX3, thereby realizing 6T6R. However, since FPGA is included in the circuit design, the design power consumption is large, and the cost and design complexity of FPGA are high.

[0052] If FPGA is used instead of digital front-end chips to implement 6T6R or 8T8R, the cost will be higher and the logic resource requirements will be very large, making it difficult to implement.

[0053] In view of this, an embodiment of the present disclosure provides a radio frequency circuit. Figure 4 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 1 ,like Figure 4 As shown, the radio frequency circuit includes: a digital front-end processor 100 , a signal converter 200 and a plurality of first radio frequency transceivers 300 , wherein the digital front-end processor 100 includes a first interface circuit 110 .

[0054] The signal converter 200 is connected to the first interface circuit 110 and multiple first RF transceivers 300. The signal converter 200 obtains multiple first control signals based on the first request signal sent by the first interface circuit 110, and sends them to the multiple first RF transceivers 300 respectively; and obtains a second control signal based on multiple second request signals sent by the multiple first RF transceivers 300, and sends it to the first interface circuit 110.

[0055] A plurality of first RF transceivers 300 are connected to the first interface circuit 110. Each first RF transceiver 300 sends input data to the first interface circuit 110 in response to a first control signal. The first interface circuit 110 sends output data to each first RF transceiver 300 in response to a second control signal.

[0056] In this embodiment, the signal converter 200 sends the plurality of first control signals to the plurality of first RF transceivers 300 respectively, which means that the signal converter 200 sends each of the plurality of first control signals to one of the first RF transceivers 300, and each first RF transceiver 300 receives a first control signal. The signal converter 200 obtains a second control signal based on the plurality of second request signals sent by the plurality of first RF transceivers 300, which means that each of the plurality of first RF transceivers 300 sends a second request signal, and the signal converter 200 obtains the second control signal after receiving the plurality of second request signals, and sends the second control signal to the first interface circuit 110.

[0057] The input data of the first RF transceiver 300 may come from the terminal. The input data sent by each first RF transceiver 300 to the first interface circuit 110 is the input data received from the terminal. The input data sent by different first RF transceivers 300 to the first interface circuit 110 may be the same or different.

[0058] The first interface circuit 110 sends output data to each first RF transceiver 300 in response to the second control signal, and each first RF transceiver 300 can send the received output data to the terminal. Here, the output data sent by the first interface circuit 110 to different first RF transceivers 300 may be the same or different.

[0059] The first interface circuit 110 includes a signal interface and multiple groups of data interfaces, and each first RF transceiver 300 includes a signal interface and a data interface. It is understandable that the data interface and signal interface of each first RF transceiver 300 should be connected to the data interface and signal interface of the first interface circuit 110 accordingly in order to communicate with the first interface circuit 110. In some embodiments, the number of data interfaces of the first interface circuit 110 is large, while the number of signal interfaces is small. This will result in multiple groups of data interfaces of the first interface circuit 110 being connected to the data interfaces of multiple first RF transceivers 300, but the number of signal interfaces cannot meet the connection with the signal interface of each first RF transceiver 300.

[0060] The embodiment of the present disclosure proposes that when the total number of signal interfaces of the plurality of first RF transceivers 300 is greater than the number of signal interfaces of the first interface circuit 110, in order to realize the communication between the first interface circuit 110 and the plurality of first RF transceivers 300, a signal converter 200 may be provided. The signal converter 200 connects the signal interface of the first interface circuit 110 and the signal interface of the plurality of first RF transceiver chips. The signal converter 200 may convert the first request signal sent by the first interface circuit 110 into a plurality of first control signals, and send them to the plurality of first RF transceivers 300 respectively. After receiving the first control signal, each first RF transceiver 300 sends the input data to the data interface of the first interface circuit 110 through its data interface in response to the first control signal. The signal converter 200 may also convert the plurality of second request signals sent by the plurality of first RF transceivers 300 into a second control signal, and send it to the first interface circuit 110. The first interface circuit 110 sends the output data to each first RF transceiver 300 in response to the second control signal. In this way, the first interface circuit 110 can perform signal interaction with the plurality of first RF transceivers 300 through the signal converter 200 to control the data interaction between the plurality of first RF transceivers 300 and the digital front-end processor 100, thereby increasing the number of data transceiver channels of the remote RF unit, enabling the remote RF unit to implement 6T6R and 8T8R communication, and improving data transmission efficiency. Moreover, compared with FPGA, the newly added signal converter has simple hardware design, low cost, and high reliability.

[0061] In some embodiments, the signal converter 200 obtains multiple synchronous first control signals based on the first request signal. In this way, the multiple first RF transceivers 300 can synchronously send input data to the digital front-end processor 100 to increase the amount of data transmission per unit time, that is, to improve data transmission efficiency.

[0062] Figure 5 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 2 In some embodiments, Figure 5 As shown, the signal interface of the first interface circuit 110 includes a signal input interface JESD SYNC_IN and a signal output interface JESD SYNC_OUT, and the signal interface of the first RF transceiver 300 includes a signal input interface JESD SYNC_IN and a signal output interface JESDSYNC_OUT. The signal converter 200 includes: a first signal conversion unit 210 and a second signal conversion unit 220. The first signal conversion unit 210 connects the signal output interface JESD SYNC_OUT of the first interface circuit 110 and the signal input interface JESD SYNC_IN of each first RF transceiver 300, and the first signal conversion unit 210 obtains a plurality of synchronized first control signals based on the first request signal. The second signal conversion unit 220 connects the signal input interface JESD SYNC_IN of the first interface circuit 110 and the signal output interface JESD SYNC_OUT of each first RF transceiver 300, and the second signal conversion unit 220 obtains a second control signal based on a plurality of second request signals.

[0063] In this embodiment, a first signal conversion unit 210 is provided between the signal output interface of the first interface circuit 110 and the signal input interfaces of the plurality of first RF transceivers 300, and a second signal conversion unit is provided between the signal input interface of the first interface circuit 110 and the signal output interfaces of the plurality of first RF transceivers 300, so that the first signal conversion unit 210 and the second signal conversion unit can perform signal conversion operations simultaneously, so that the first interface circuit 110 can receive input data and send output data simultaneously, thereby improving the signal transmission efficiency of the RRU.

[0064] In some embodiments, the first signal conversion unit 210 includes: a splitter, the input end of the splitter is connected to the signal output interface JESD SYNC_OUT of the first interface circuit 110, and the multiple output ends of the splitter are respectively connected to the signal input interfaces JESD SYNC_IN of multiple first RF transceivers 300; the splitter is used to split the first request signal from one path to multiple paths to obtain multiple synchronized first control signals.

[0065] The splitter can split a single input signal into multiple synchronous output signals. The present disclosure does not limit the specific circuit of the splitter, which can be any splitter commonly used in the art. In this embodiment, the splitter is used to split the first request signal into multiple paths, and multiple synchronized first control signals can be obtained to control multiple first RF transceivers to send input data to the first interface circuit at the same time, thereby improving data transmission efficiency. In addition, the circuit design of the splitter is relatively mature, and the direct use of the splitter can shorten the product verification cycle and ensure high reliability.

[0066] Figure 6A schematic diagram of a splitter provided in an embodiment of the present disclosure. In some embodiments, the first request signal is a first differential request signal in the form of a differential signal, and the first control signal is a first differential control signal in the form of a differential signal. Figure 6 As shown, the signal output interface of the first interface circuit 110 includes differential signal output interfaces JESDSYNC_OUT+ and JESD SYNC_OUT-, which are used to output the first differential request signal. The signal input interface of each first RF transceiver 300 includes differential signal input interfaces JESD SYNC_IN+ and JESD SYNC_IN-, which are used to receive the first differential control signal.

[0067] In some embodiments, the splitter may be a differential clock splitter, which includes a pair of differential input terminals and multiple pairs of differential output terminals, wherein the pair of differential input terminals is connected to the differential signal output interface of the first interface circuit, and each pair of differential output terminals is connected to a differential signal input interface of the first RF transceiver. Figure 6 As shown, the differential clock splitter 211 includes differential input terminals IN+, IN-, and multiple pairs of differential output terminals Q0+, Q0- and Q1+, Q1-. The differential input terminals IN+, IN- are respectively connected to JESD SYNC_OUT+ and JESD SYNC_OUT- of the first interface circuit 110, the differential output terminals Q0+, Q0- are respectively connected to JESD SYNC_IN+ and JESD SYNC_IN- of the first first RF transceiver 300, and the differential output terminals Q1+, Q1- are respectively connected to JESD SYNC_IN+ and JESD SYNC_IN- of the second first RF transceiver 300.

[0068] The differential clock splitter 211 is used to split the first differential request signal into multiple pairs of first differential control signals, and send them to multiple first RF transceivers 300 respectively. Each first RF transceiver 300 is interfaced with a pair of first differential control signals.

[0069] The present disclosure does not limit the specific circuit of the differential clock splitter 211, which can be any differential clock splitter commonly used in the art. For example, it can be a low-jitter 1:2 differential clock splitter. The use of a differential clock splitter in this embodiment can meet the requirement that the first interface circuit 110 and the first RF transceiver 300 use differential signals for signal transmission, and directly using the differential clock splitter 211 can simplify the circuit design of the first signal conversion unit 210, reduce the occupied area, and facilitate the reliability and miniaturization of the product.

[0070] It should be understood that, in another embodiment, the first signal conversion unit 210 may also include a differential-to-single-ended circuit, a single-ended splitter, and a plurality of single-ended-to-differential circuits. The differential input end of the differential-to-single-ended circuit is connected to the differential signal output interface of the first interface circuit, and is used to convert the first differential request signal into a first single-ended request signal. The input end of the single-ended splitter is connected to the single-ended output end of the differential-to-single-ended circuit, and is used to convert the first single-ended request signal into a plurality of synchronized first single-ended control signals. The single-ended input end of each single-ended-to-differential circuit is connected to a single-ended output end of the single-ended splitter, and the differential output end of each single-ended-to-differential circuit is connected to a differential signal input interface of a first RF transceiver, and each single-ended-to-differential circuit is used to convert the first single-ended control signal into a first differential control signal and send it to the first RF transceiver. In practical applications, any of the above two schemes can be adopted according to the specific situation, and the present disclosure does not limit this.

[0071] In another embodiment, the first request signal can also be a first single-ended request signal in the form of a single-ended signal, and the first control signal is a first single-ended control signal in a single-ended form, then the splitter can use a single-ended splitter to convert the first single-ended request signal into multiple synchronized first single-ended control signals.

[0072] In some embodiments, the second signal conversion unit 220 includes: an AND gate logic circuit, wherein multiple input ends of the AND gate logic circuit are respectively connected to the signal output interfaces of multiple first RF transceivers 300, and the output end of the AND gate logic circuit is connected to the signal input interface of the first interface circuit 110, and the AND gate logic circuit is used to issue a second control signal after receiving multiple second request signals issued by multiple first RF transceivers 300.

[0073] The second request signals sent by the multiple first RF transceivers 300 may be completely synchronized, or there may be a time difference between them, that is, they are not completely synchronized. In this embodiment, the AND gate logic circuit sends the second control signal only after receiving the multiple second request signals, so that the timing of different second request signals can be adjusted, so that the first interface circuit 110 can send output data to different first RF transceivers 300 at the same time, thereby improving signal transmission efficiency.

[0074] Figure 7 A schematic diagram of an AND gate logic circuit provided in an embodiment of the present disclosure. In some embodiments, the second request signal is a second differential request signal in the form of a differential signal, and the second control signal is a second differential control signal in the form of a differential signal. Figure 7As shown, the signal input interface of the first interface circuit 110 includes differential signal input interfaces JESD SYNC_IN+ and JESD SYNC_IN- for receiving the second differential control signal. The signal output interface of each first RF transceiver 300 includes differential signal output interfaces JESD SYNC_OUT+ and JESD SYNC_OUT- for outputting the second differential request signal.

[0075] In some embodiments, the AND gate logic circuit includes: a plurality of differential-to-single-ended circuits 221 , a single-ended AND gate 222 , and a single-ended-to-differential circuit 223 .

[0076] The differential input end of each differential-to-single-ended circuit 221 is connected to a differential signal output interface JESD SYNC_OUT+, JESD SYNC_OUT- of a first RF transceiver 300, and each differential-to-single-ended circuit 221 converts the second differential request signal into a single-ended request signal. Here, to distinguish from the first single-ended request signal mentioned above, the single-ended request signal here can also be referred to as the second single-ended request signal.

[0077] Multiple input ends of the single-ended AND gate 222 are connected to the single-ended output ends of the multiple differential-to-single-ended circuits 221. The single-ended AND gate 222 sends a single-ended control signal after receiving multiple single-ended request signals sent by the multiple differential-to-single-ended circuits 221. Here, in order to distinguish it from the first single-ended control signal mentioned above, the single-ended control signal here can also be called a second single-ended control signal.

[0078] The single-ended input end of the single-ended to differential circuit 223 is connected to the output end of the single-ended AND gate 222, and the differential output end of the single-ended to differential circuit 223 is connected to the differential signal input interface JESD SYNC_IN+, JESD SYNC_IN- of the first interface circuit 110; the single-ended to differential circuit 223 converts the single-ended control signal into a second differential control signal and sends it to the first interface circuit 110.

[0079] In this embodiment, the cost can be reduced by using low-cost differential-to-single-ended circuit 221, single-ended AND gate 222 and single-ended-to-differential circuit 223. It should be understood that in other embodiments, differential AND gates may also be directly used.

[0080] In another embodiment, the second request signal can also be a second single-ended request signal in the form of a single-ended signal, and the second control signal is a second single-ended control signal in a single-ended form. Then the AND gate logic circuit can directly use a single-ended AND gate to obtain the second single-ended control signal based on multiple second single-ended request signals.

[0081] In some embodiments, there may be a plurality of first interface circuits 110 , and each first interface circuit 110 corresponds to a signal converter 200 and a plurality of first RF transceivers 300 . Figure 8 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 3 ,like Figure 8 As shown, the digital front-end processor 100 includes two first interface circuits 110 , and each first interface circuit 110 performs signal exchange with two first RF transceivers 300 through a signal converter 200 .

[0082] It should be noted that the numbers of transceiver channels supported by the first RF transceivers 300 connected to different first interface circuits 110 may be the same or may not be completely the same. Figure 8 In the illustrated embodiment, each first interface circuit 110 is connected to two first RF transceivers 300 supporting 2T2R, that is, each first interface circuit 110 supports 4T4R, so the digital front-end processor 100 can support 8T8R at most.

[0083] In other embodiments, the first first interface circuit 110 may be connected to two first RF transceivers 300 supporting 2T2R, and the second first interface circuit 110 may be connected to two first RF transceivers 300 supporting 1T1R, so that the digital front-end processor 100 can support 6T6R at most.

[0084] Fig. 9 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 4 In some embodiments, Fig. 9 As shown, the digital front-end processor 100 may further include: a second interface circuit 120. The RF circuit also includes a second RF transceiver 400 connected to the second interface circuit 120; the second RF transceiver 400 sends input data to the second interface circuit 120 in response to a third request signal sent by the second interface circuit 120; and, after sending a fourth request signal to the second interface circuit 120, receives output data sent by the second interface circuit 120.

[0085] The second interface circuit 120 has the same interface as the first interface circuit 110. The above descriptions of the interface of the first interface circuit 110 are all applicable to the second interface circuit 120, so the interface of the second interface circuit is not described in detail in this application. The number of data transceiver channels supported by the second RF transceiver 400 may be the same as or different from the number of data channels supported by the first RF transceiver 300.

[0086] like Fig. 9As shown, the first interface circuit 110 and the second interface circuit 120 each include a group of signal interfaces and four groups of data interfaces. The signal interface of the first interface circuit 110 is connected to the signal interfaces of two first RF transceivers 300 supporting 2T2R through the signal converter 200. Every two groups of the four groups of data interfaces of the first interface circuit 110 are connected to the two groups of data interfaces of a first RF transceiver 300, so the first interface circuit 110 and the two first RF transceivers 300 can support 4T4R. The signal interface of the second interface circuit 120 is directly connected to the signal interface of a second RF transceiver 400 supporting 2T2R, and the two groups of data interfaces in the second interface circuit 120 are correspondingly connected to the two groups of data interfaces of the second RF transceiver 400, so the second interface circuit 120 and the second RF transceiver 400 can support 2T2R. With this arrangement, the digital front-end processor 100 can support 6T6R at most.

[0087] In the embodiment of the present disclosure, two connection modes between the interface circuit of the digital front-end processor 100 and the RF transceiver are provided, one is that the first interface circuit 110 performs signal interaction with multiple first RF transceivers 300 through the signal converter 200, and the other is that the second interface circuit 120 directly performs signal interaction with the second RF transceiver 400. In practical applications, when the digital front-end processor 100 includes multiple interface circuits, different interface circuits can adopt the connection mode of the first interface circuit 110, or the connection mode of the second interface circuit 120, which can be specifically set according to the number of data transceiver channels required. The mode provided by the embodiment of the present disclosure that the first interface circuit 110 performs signal interaction with multiple first RF transceivers 300 through the signal converter 200 can enable the digital front-end processor 100 to implement richer data transceiver modes, such as Fig. 9 The digital front-end processor 100 shown can implement 2T2R, 4T4R, 6T6R and 8T8R, and has simple hardware design and low cost.

[0088] In addition, each interface circuit of the digital front-end processor 100 provided in the above embodiment of the present disclosure includes two groups of data interfaces (such as Figure 5 ) or four groups of data interfaces (such as Figure 8 ) is only an example. In actual applications, each interface circuit of the digital front-end processor 100 may include more groups of data interfaces, such as six groups, eight groups, etc. It can be understood that the present application is applicable to the case where the number of signal interfaces in the interface circuit of the digital front-end processor 100 is less than the total number of signal interfaces of the multiple RF transceivers, and does not limit the number of data interfaces in the interface circuit. The number of data interfaces of the interface circuit can be more than, equal to, or less than the total number of data interfaces of the multiple RF transceivers.

[0089] In some embodiments, the first interface circuit 110 and the second interface circuit are both interface circuits that meet the JESD204B interface protocol. The JESD204B interface protocol defines a SYNC signal, i.e., a synchronization signal. For example, the SYNC signal is a low-level valid signal. The SYNC signal can be in the form of a single-ended signal or a differential signal. However, when using a differential signal, its effective level should also be a low level.

[0090] The SYNC signal controls the data transmission timing between the receiver and the transmitter. Fig.10 A schematic diagram of a signal synchronization operation between a receiver and a transmitter provided in an embodiment of the present disclosure. Fig.10 The process of synchronous operation of JESD204B subclass 1 and subclass 2 is shown. Fig.10 As shown, the SYNC signal is sent from the receiver to the transmitter. The receiver sends a synchronization request (sync_request) to the transmitter by pulling the level of the SYNC interface (also known as the synchronization interface) low. After the transmitter detects the synchronization request, it sends a / K / = / K28.5 / symbol stream to the receiver. The receiver waits for at least four consecutive / K / symbols to be correctly received, confirms that synchronization is established (synchronized), and then pulls the level of the SYNC interface high to stop the synchronization request.

[0091] Once the transmitter detects that the receiver has stopped its synchronization request, the transmitter will continue to send / K / symbols until the next LMFC (Local MultiFrame Clock) boundary (that is, the valid edge). On the first frame after the selected LMFC boundary, the transmitter sends the initial lane alignment sequence (ILAS) to the receiver for verification. The receiver can decode the sequence and verify the synchronization establishment. After that, the transmitter can send the collected data, that is, the application data.

[0092] In the embodiment of the present disclosure, when the digital front-end processor 100 requests the RF transceiver to send input data, the digital front-end processor 100 is a receiver and the RF transceiver is a transmitter. When the RF transceiver requests the digital front-end processor 100 to send output data, the RF transceiver is a receiver and the digital front-end processor 100 is a transmitter. The input data and output data in the embodiment of the present disclosure may be application data.

[0093] The synchronization signal sent by the digital front-end processor 100 to the radio frequency transceiver is defined as a receiving synchronization signal (Rx_sync signal), and the synchronization signal sent by the radio frequency transceiver to the digital front-end processor 100 is defined as a transmitting synchronization signal (Tx_sync signal). The first request signal and the third request signal in the embodiment of the present disclosure are both Rx_sync signals. The second request signal and the fourth request signal are both Tx_sync signals.

[0094] Fig.11 Schematic diagram of a radio frequency circuit provided in an embodiment of the present disclosure Figure 5 The following combination Fig.11 , taking the digital front-end processor 100 as a receiver and the first RF transceiver 300 as a transmitter as an example, the synchronization operation process is described in detail.

[0095] First, the first interface circuit 110 of the digital front-end processor 100 pulls down the level of its JESD SYNC_OUT+ interface and pulls up the level of its JESD SYNC_OUT- interface to send out a first differential request signal (i.e., Rx_sync signal). The differential clock divider 211 detects that the level of its IN+ terminal is pulled down and the level of its IN- terminal is pulled up, and then pulls down the levels of Q0+ and Q1+ terminals, and pulls up the levels of Q0- and Q1- terminals to send out a first differential control signal to each first RF transceiver 300. The first RF transceiver 300 detects that the level of its JESD SYNC_IN+ interface is pulled down and the level of its JESD SYNC_IN- interface is pulled up, which indicates that the synchronization request sent by the digital front-end processor 100 has been received.

[0096] Next, each first RF transceiver 300 sends a / K / = / K28.5 / symbol stream to the first interface circuit 110 via the SERDES OUT interface. Since the multiple first control signals are synchronous, each first RF transceiver 300 sends a / K / = / K28.5 / symbol stream to the first interface circuit 110 substantially synchronously.

[0097] After the first interface circuit 110 waits for its SERDES IN interface to correctly receive at least four consecutive / K / symbols, it pulls up the level of its JESD SYNC_OUT+ interface and pulls down the level of its JESD SYNC_OUT- interface to stop sending the first request signal (Rx_sync signal). After detecting that the level of its IN+ terminal is pulled up and the level of its IN- terminal is pulled down, the differential clock splitter 211 pulls up the levels of Q0+ and Q1+ terminals and pulls down the levels of Q0- and Q1- terminals to stop sending the first control signal to each first RF transceiver 300. The first RF transceiver 300 detects that the level of its JESD SYNC_IN+ interface is pulled up and the level of its JESD SYNC_IN- interface is pulled down, and learns that the digital front-end processor 100 stops the synchronization request. The first RF transceiver 300 will continue to transmit / K / symbols until the next LMFC boundary. In the first frame after the selected LMFC boundary, the first RF transceiver 300 sends an initial lane alignment sequence (ILAS) to the digital front-end processor 100 for verification. Afterwards, the first RF transmitter 300 can send input data.

[0098] As shown above, the differential clock splitter 211 can accurately transmit the level state of the signal output interface in the digital front-end processor 100 to the signal input interface of each first RF transceiver 300 to achieve signal interaction between the digital front-end processor 100 and multiple first RF transceivers 300.

[0099] The synchronization operation process is described in detail below by taking the digital front-end processor 100 as a transmitter and the first RF transceiver 300 as a receiver as an example.

[0100] First, each first RF transceiver 300 pulls down the level of its JESD SYNC_OUT+ interface and pulls up the level of its JESD SYNC_OUT+ interface to send out a second request signal (i.e., Tx_sync signal). After the differential input end of each differential-to-single-ended circuit 221 detects the above-mentioned level change, it pulls down the level of its single-ended output end to send out a single-ended request signal. After detecting that the level of each input end is pulled down, the single-ended AND gate 222 pulls down the level of its output end to send out a single-ended control signal. After detecting that the level of its single-ended input end is pulled down, the single-ended-to-differential circuit 223 pulls down the level of one end connected to the JESD SYNC_IN+ of the first interface circuit 110 and pulls up the level of one end connected to the JESD SYNC_IN- of the first interface circuit 110.

[0101] The first interface circuit 110 of the digital front-end processor 100 detects that the level of its JESD SYNC_IN+ interface is pulled low, and the level of its JESD SYNC_IN- interface is pulled high, which represents the reception of the synchronization request sent by each first RF transceiver 300. Then, the first interface circuit 110 sends a / K / = / K28.5 / symbol stream to each first RF transceiver through multiple SERDES OUT interfaces.

[0102] After each first RF transceiver 300 waits for its SERDES IN interface to correctly receive at least four consecutive / K / symbols, it pulls the level of its JESD SYNC_OUT+ interface high and pulls the level of its JESD SYNC_OUT- interface low to stop sending the second request signal.

[0103] After the differential input of each differential-to-single-ended circuit 221 detects the level change, the level of its single-ended output is pulled high to stop sending the single-ended request signal. After detecting that the level of one of the inputs is pulled high, the single-ended AND gate 222 pulls the level of its output high to stop sending the single-ended control signal. After detecting that the level of its single-ended input is pulled high, the single-ended-to-differential circuit 223 pulls the level of one end connected to the JESD SYNC_IN+ of the first interface circuit 110 high and pulls the level of one end connected to the JESD SYNC_IN- of the first interface circuit 110 low.

[0104] Next, the first interface circuit 110 detects that the level of its JESD SYNC_IN+ interface is pulled high, and the level of the JESDSYNC_IN- interface is pulled low, and learns that all first RF transceivers 300 have stopped synchronization requests. The first interface circuit 110 will continue to transmit / K / symbols until the next LMFC boundary. In the first frame after the selected LMFC boundary, the first interface circuit 110 sends an initial lane alignment sequence (ILAS) to each first RF transceiver 300 for verification. Afterwards, the first interface circuit sends output data to each first RF transceiver.

[0105] In this embodiment, the second signal conversion unit uses an AND gate, so that the first interface circuit 110 can detect the synchronization requests of all the first RF transceivers 300. In addition, although the AND gate will inform the first interface circuit of stopping sending the synchronization request after detecting that one first RF transceiver 300 stops sending the synchronization request, since multiple first RF transceivers stop sending the synchronization request at substantially the same time, the use of the AND gate does not affect the synchronization operation between the multiple first RF transceivers and the first interface circuit.

[0106] In summary, the AND gate can accurately transmit the level state of the signal output interface of each first RF transceiver 300 to the signal input interface of the digital front-end chip, so as to accurately control the timing between the digital front-end processor 100 and the plurality of first RF transceivers 300. In the disclosed embodiment, since the transmission frequency of the SYNC signal of the 204B interface is relatively low, only a few megahertz, the hardware design of the signal converter is easier and has lower cost, and the data transceiver channel of the RRU can be expanded at low cost.

[0107] The synchronous operation when the second interface circuit is a receiver and the second RF transceiver is a transmitter, or the synchronous operation when the second interface circuit is a transmitter and the second RF transceiver is a receiver can refer to the synchronous operation process of the above-mentioned receiver and transmitter, which will not be repeated here.

[0108] In some embodiments, the digital front-end processor 100 further includes a front-end interface circuit, a filtering circuit, and a data pre-distortion (DPD) circuit. The front-end interface circuit is used to connect to the optical port, the DPD circuit connects the first interface circuit 110 and the second interface circuit, and the DPD circuit can poll the first interface circuit 110 and the second interface circuit. In other words, the first interface circuit and the second interface circuit each independently send a synchronization request, that is, the first request signal and the third request signal may be asynchronous. The first interface circuit and the second interface circuit each independently send or receive data.

[0109] For example, the digital front-end processor 100 in the embodiment of the present disclosure may be a digital front-end chip DFE. The first RF transceiver and the second RF transceiver may be RF transceiver chips. The single-ended to differential circuit may be a single-ended to differential device, and the differential to single-ended circuit may be a differential to single-ended device. Both the single-ended to differential device and the differential to single-ended device may use low-cost devices.

[0110] An embodiment of the present disclosure further provides an electronic device, which includes the radio frequency circuit as described in any of the above embodiments.

[0111] The description of the embodiment of the electronic device of the present application is similar to the description of the above-mentioned RF circuit embodiment, and has similar beneficial effects as the RF circuit embodiment. For technical details not disclosed in the embodiment of the electronic device of the present application, please refer to the description of the RF circuit embodiment of the present application for understanding.

[0112] By way of example, the electronic device may be an RRU product.

[0113] An embodiment of the present disclosure also provides a control method for a radio frequency circuit, wherein the radio frequency circuit includes a digital front-end processor, a signal converter, and a plurality of first radio frequency transceivers, and the digital front-end processor includes a first interface circuit. Fig.12A flow chart of a method for controlling a radio frequency circuit provided in an embodiment of the present disclosure is shown in FIG. Fig.12 As shown, the control method includes:

[0114] S100: The signal converter obtains a plurality of first control signals based on a first request signal sent by the first interface circuit, and sends the signals to a plurality of first radio frequency transceivers respectively; each first radio frequency transceiver sends input data to the first interface circuit in response to the first control signal;

[0115] S200: The signal converter receives a second request signal sent by each of the multiple first RF transceivers, obtains a second control signal based on the multiple second request signals and sends it to the first interface circuit, and the first interface circuit sends output data to each first RF transceiver in response to the second control signal.

[0116] In some embodiments, the signal converter obtains a plurality of synchronized first control signals based on a first request signal sent by the first interface circuit.

[0117] In some embodiments, the signal converter includes a splitter. In step S100, the signal converter obtains multiple synchronous first control signals based on the first request signal sent by the first interface circuit, specifically including: the splitter splits the first request signal from one path into multiple paths to obtain multiple synchronous first control signals.

[0118] In some embodiments, the signal conversion unit includes an AND gate logic circuit. In step S200, the signal converter obtains the second control signal based on multiple second request signals, including: the AND gate logic circuit sends the second control signal after receiving multiple second request signals sent by multiple first RF transceivers.

[0119] In some embodiments, the digital front-end processor further includes a second interface circuit, and the radio frequency circuit further includes a second radio frequency transceiver; the control method further includes:

[0120] The second RF transceiver sends input data to the second interface circuit in response to the third request signal sent by the second interface circuit, and receives output data sent by the second interface circuit after sending a fourth request signal to the second interface circuit.

[0121] Here, after receiving the fourth request signal, the second interface circuit sends the output data to the second radio frequency transceiver.

[0122] The description of the embodiment of the control method of the radio frequency circuit of the present application is similar to the description of the embodiment of the radio frequency circuit described above, and has similar beneficial effects as the embodiment of the radio frequency circuit. For technical details not disclosed in the embodiment of the method of the present application, please refer to the description of the embodiment of the radio frequency circuit of the present application for understanding.

[0123] In summary, the embodiments of the present disclosure provide a radio frequency circuit, an electronic device including the radio frequency circuit, and a control method for the radio frequency circuit, wherein the radio frequency circuit includes a digital front-end processor and a plurality of first radio frequency transceivers, and the digital front-end processor includes a first interface circuit. In the embodiments of the present disclosure, when the total number of signal interfaces of the plurality of first radio frequency transceivers is greater than the number of signal interfaces of the first interface circuit, a signal converter may be provided to realize communication between the first interface circuit and the plurality of first radio frequency transceivers. The signal converter connects the signal interface of the first interface circuit and the signal interface of the plurality of first radio frequency transceiver chips. The signal converter may convert a first request signal issued by the first interface circuit into a plurality of first control signals, and send them to the plurality of first radio frequency transceivers respectively. After each first radio frequency transceiver receives the first control signal, it sends input data to the first interface circuit in response to the first control signal. The signal converter may also convert a plurality of second request signals issued by the plurality of first radio frequency transceivers into a second control signal, and send it to the first interface circuit. The first interface circuit sends output data to each first radio frequency transceiver in response to the second control signal. In this way, the first interface circuit can communicate with multiple first RF transceivers through the signal converter to control the data interaction between the multiple first RF transceivers and the digital front-end processor, increase the number of data transceiver channels of the remote RF unit, enable the remote RF unit to achieve 6T6R, 8T8R communication, and improve data transmission efficiency. In addition, compared with FPGA, the newly added signal converter has simple hardware design, low cost, and high reliability.

[0124] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A radio frequency circuit, comprising: A digital front-end processor, a signal converter and a plurality of first radio frequency transceivers, wherein the digital front-end processor includes a first interface circuit; The signal converter is connected to the first interface circuit and the plurality of first RF transceivers. The signal converter obtains a plurality of first control signals based on a first request signal sent by the first interface circuit, and sends the first control signals to the plurality of first RF transceivers respectively; and obtains a second control signal based on a plurality of second request signals sent by the plurality of first RF transceivers, and sends the second control signal to the first interface circuit. The plurality of first radio frequency transceivers are connected to the first interface circuit, and each of the first radio frequency transceivers sends input data to the first interface circuit in response to the first control signal; The first interface circuit sends output data to each of the first radio frequency transceivers in response to the second control signal.

2. The radio frequency circuit according to claim 1, wherein the signal converter comprises: A first signal conversion unit, connected to a signal output interface of the first interface circuit and a signal input interface of each of the first radio frequency transceivers, wherein the first signal conversion unit obtains a plurality of synchronized first control signals based on the first request signal; A second signal conversion unit is connected to the signal input interface of the first interface circuit and the signal output interface of each of the first radio frequency transceivers, and the second signal conversion unit obtains the second control signal based on a plurality of the second request signals.

3. The radio frequency circuit according to claim 2, wherein the first signal conversion unit comprises: A splitter is used to split the first request signal from one path into multiple paths to obtain the multiple synchronous first control signals.

4. The radio frequency circuit according to claim 3, wherein the first request signal is a first differential request signal in the form of a differential signal, and the first control signal is a first differential control signal in the form of a differential signal; The splitter is a differential clock splitter.

5. The radio frequency circuit according to claim 2, wherein the second signal conversion unit comprises: An AND gate logic circuit, wherein the AND gate logic circuit sends out the second control signal after receiving a plurality of the second request signals sent by a plurality of the first radio frequency transceivers.

6. The radio frequency circuit according to claim 5, wherein the second request signal is a second differential request signal in the form of a differential signal, and the second control signal is a second differential control signal in the form of a differential signal; and the AND gate logic circuit comprises: a plurality of differential-to-single-ended circuits, wherein a differential input end of each of the differential-to-single-ended circuits is connected to a signal output interface of the first radio frequency transceiver, and each of the differential-to-single-ended circuits converts the second differential request signal into a single-ended request signal; A single-ended AND gate, wherein a plurality of input ends of the single-ended AND gate are connected to the single-ended output ends of the plurality of differential-to-single-ended circuits, and the single-ended AND gate issues the single-ended control signal after receiving a plurality of the single-ended request signals issued by the plurality of differential-to-single-ended circuits; A single-ended to differential circuit, wherein the single-ended input end of the single-ended to differential circuit is connected to the output end of the single-ended AND gate, and the differential output end of the single-ended to differential circuit is connected to the signal input interface of the first interface circuit; the single-ended to differential circuit converts the single-ended control signal into a second differential control signal and sends it to the first interface circuit.

7. The radio frequency circuit according to claim 1, wherein the digital front-end processor further comprises: A second interface circuit; The radio frequency circuit further includes a second radio frequency transceiver connected to the second interface circuit; The second RF transceiver sends input data to the second interface circuit in response to a third request signal sent by the second interface circuit; and after sending a fourth request signal to the second interface circuit, receives output data sent by the second interface circuit.

8. An electronic device comprising the radio frequency circuit according to any one of claims 1 to 7.

9. A control method for a radio frequency circuit, the radio frequency circuit comprising a digital front-end processor, a signal converter and a plurality of first radio frequency transceivers, the digital front-end processor comprising a first interface circuit; the control method comprising: The signal converter obtains a plurality of first control signals based on the first request signal sent by the first interface circuit, and sends the first control signals to the plurality of first RF transceivers respectively; Each of the first radio frequency transceivers sends input data to the first interface circuit in response to the first control signal; The signal converter receives a second request signal sent by each of the plurality of first RF transceivers, obtains a second control signal based on the plurality of second request signals and sends the second control signal to the first interface circuit, and the first interface circuit sends output data to each of the first RF transceivers in response to the second control signal.

10. The control method according to claim 9, wherein the digital front-end processor further comprises a second interface circuit, and the radio frequency circuit further comprises a second radio frequency transceiver; and the control method further comprises: The second RF transceiver sends input data to the second interface circuit in response to a third request signal sent by the second interface circuit, and receives output data sent by the second interface circuit after sending a fourth request signal to the second interface circuit.

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