Method of realizing LVDS communication based on FPGA

Abstract

The present application discloses a high-speed backplane system and method for implementing LVDS communication based on FPGA, wherein the high-speed backplane system includes a controller and a communication component, the communication component includes multiple communication modules, and the communication component specifically includes a master module and at least one slave module. The controller is connected to the master module, and both the master module and the slave module are provided with an FPGA chip, and the FPGA chip in the master module is also electrically connected to an MCU; the master module and the slave module each include at least a sending interface and a receiving interface, and the master module and the slave module exchange data frames through an interface component composed of the sending interface and the receiving interface. The master module and the slave module of the present application exchange data through the interface component, so that the master module controls the slave module and obtains information from the slave module. The structure is simple, so that the connection between the modules is stable and reliable, which improves the efficiency of the system in the field and reduces the cost.

Description

Technical Field

[0001] The present application relates to the field of industrial automation control, and in particular to a high-speed backplane system and method for implementing LVDS communication based on FPGA. Background Art

[0002] Currently, 485 and CAN are two commonly used communication protocols in gateway communications. However, these protocols suffer from slow communication speeds, which limits data exchange between master and slave stations and cannot meet the growing demand for high-speed data transmission. 485 or CAN protocols are often used in expansion modules of gateway products. To achieve data transmission, terminal resistors may be installed on the end modules to ensure signal stability. However, this method is not only cumbersome to install and debug, but any problem with a node can also affect the stability and reliability of the entire communication system.

[0003] Clearly, traditional communication technologies, due to limited communication speeds and the cumbersome installation and commissioning of modules during field use, are no longer able to meet the demands for high-speed data transmission in modern industries, vehicles, and other fields. Therefore, how to increase the data exchange speed of gateway expansion modules, simplify the installation and commissioning process, and improve work efficiency and system stability are urgent challenges facing those skilled in the art. Summary of the Invention

[0004] In order to solve the above problems, the present application provides a high-speed backplane system and method for implementing LVDS communication based on FPGA, which realizes high-speed full-duplex communication, reduces the system data exchange cycle, and improves operating efficiency.

[0005] In the first aspect, the present application provides a high-speed backplane system for implementing LVDS communication based on FPGA, which adopts the following technical solutions:

[0006] A high-speed backplane system for implementing LVDS communication based on an FPGA, comprising a controller and a communication component, wherein the communication component comprises multiple communication modules, specifically comprising a master module and at least one slave module, the controller being connected to the master module, the master module and the slave module each being provided with an FPGA chip, and the FPGA chip in the master module being further electrically connected to an MCU;

[0007] The master station module and the slave station module each include at least one sending interface and one receiving interface, and the master station module and the slave station module interact with each other via an interface component composed of the sending interface and the receiving interface.

[0008] By adopting the above technical means, the master module and the slave module realize data exchange through the interface component, so that the master module controls the slave module and obtains the information of the slave module. The structure is simple, and the connection between the modules is stable and reliable, which improves the efficiency of the system on site and reduces costs.

[0009] Preferably, all the communication modules are connected in series, each of the communication modules has at least one corresponding lower-level module or one upper-level module, and the communication modules send and receive the data frames through the interface component, and the data frames include continuous data frames and non-continuous data frames;

[0010] When the master station module continues to send the continuous data frames to all the slave station modules, all the slave station modules enter a continuous receiving and sending state. When a slave station module has a subordinate module, the slave station module establishes a hardware-triggered forwarding channel to forward the continuous data frames to its own subordinate module without delay.

[0011] By adopting the above-mentioned technical means, this system establishes a hardware-triggered forwarding channel when the communication module communicates continuous data frames, realizing the delay-free forwarding of continuous data frames, and the sending and receiving of all modules are independent of each other, realizing high-speed full-duplex communication of this system, reducing the data exchange cycle and improving operation efficiency.

[0012] In a second aspect, the present application provides a method for implementing LVDS communication based on FPGA, which adopts the following technical solutions:

[0013] A method for implementing LVDS communication based on FPGA, based on the above-mentioned high-speed backplane system for implementing LVDS communication based on FPGA, includes the following steps:

[0014] All communication modules are started, and all lower-level modules continuously send their own existence data frames to the corresponding upper-level modules, and each communication module determines whether it exists in the lower-level module based on the own existence data frames;

[0015] Determining all existing slave modules according to all existing lower-level modules, and performing module scanning on all existing slave modules by the master module to obtain attribute setting data of all the slave modules;

[0016] The master station module obtains configuration setting data from the controller of the high-speed backplane system, performs data comparison between the configuration setting data and the attribute setting data and obtains a comparison result;

[0017] When the data comparison of all the lower-level modules is completed, the master station module sends continuous data frames to all the slave station modules based on the comparison results for data communication.

[0018] By adopting the above technical means, the master station module confirms, connects and scans the slave station module by sending data frames to the slave station module, exchanges data with the slave station module, and achieves the purpose of controlling the slave station module and obtaining slave module information through the master station module.

[0019] Preferably, each of the communication modules determines whether it has the lower-level module according to the data frame it has, specifically comprising the following steps:

[0020] After each upper-level module receives the self-existence data frame sent by the corresponding lower-level module, the upper-level module generates a lower-level module existence flag based on the self-existence data frame and stores it in its own FPGA chip;

[0021] When the upper module is the master station module, the MCU of the master station module sends a lower-level existence confirmation data frame to the FPGA chip of the master station module, inquiring whether the lower-level module existence flag exists in the FPGA chip. If so, the master station module determines that the lower-level module exists in itself; if not, the master station module determines that the lower-level module does not exist in itself;

[0022] When the upper module is the slave module, the master module sends the lower-level existence confirmation data frame to the current slave module to inquire whether the lower-level module existence flag exists. If yes, the master module determines that the lower-level module exists in the current slave module; if no, the master module determines that the lower-level module does not exist in the current slave module;

[0023] All the existing lower-level modules are aggregated to obtain all the slave station modules.

[0024] By adopting the above-mentioned technical means, each module can confirm whether it has a subordinate module through its own existence confirmation data frame. The master station module and the slave station module know whether they have a subordinate module through different confirmation methods. The master station module can determine all the existing slave station modules by querying all the subordinate modules.

[0025] Preferably, the determining of all existing slave modules based on all existing lower-level modules, wherein the master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules, specifically comprises the following steps:

[0026] The master station module sends an allocation ID data frame to the corresponding subordinate slave station module. After the current slave station module obtains and records the allocated ID number according to the allocation ID data frame, the slave station module sends an allocation success data frame to the master station module through its own sending interface. When the master station module receives the allocation success data frame, it is determined that the ID allocation of the current slave station module is successful;

[0027] After the ID of the current slave module is successfully allocated, the master module sends an attribute acquisition data frame to the current slave module. The current slave module replies with its own attribute setting data to the master module based on the attribute acquisition data frame. The master module receives and stores the attribute setting data of the current slave module. The attribute setting data includes the first order number and the first PD data length.

[0028] By adopting the above technical means, the master module first assigns IDs to the existing slave modules, and then obtains the order numbers and PD data lengths of these slave modules. The method by which the master module obtains slave module data is described in detail.

[0029] Preferably, after the master module receives and stores the attribute setting data of the current slave module, the method further includes the following steps:

[0030] After the master module assigns an ID to the slave module as its own subordinate module and obtains the attribute setting data of the slave module, the master module sends the subordinate existence confirmation data frame to the slave module;

[0031] When the slave module replies to the master module that a slave module at the next level exists, the master module assigns an ID to the currently confirmed slave module according to a preset assignment rule, wherein the assignment rule includes incrementing the ID number of the currently confirmed slave module relative to the ID number of the corresponding upper-level module. After assigning the ID number of the currently confirmed slave module, the master module obtains the attribute setting data of the currently confirmed slave module.

[0032] The master module stops allocating IDs until the master module receives a reply from the slave module indicating that the slave module at the next level does not exist.

[0033] By adopting the above technical means, the method of assigning slave module IDs by the master module is described in detail. Each time the master module assigns an ID to a slave module, it obtains the attribute setting data of the slave module. In this way, IDs are assigned to all slave modules one by one, and the attribute setting data of all slave modules are obtained.

[0034] Preferably, the master station module obtains configuration setting data from the controller of the high-speed backplane system, compares the configuration setting data with the attribute setting data and obtains a comparison result, specifically comprising the following steps:

[0035] The master module receives configuration setting data sent by the controller of the high-speed backplane system, wherein the configuration setting data includes the second order number and the second PD data length of the slave module;

[0036] After the master module obtains the property setting data of all the slave modules, the master module compares the configuration setting data with the property setting data and obtains a comparison result, wherein the data comparison includes determining whether the first order number and the second order number of the same slave module are consistent, and whether the lengths of the first PD data and the second PD data match;

[0037] After the data comparison is completed, the master station module obtains the comparison results corresponding to each slave station module.

[0038] By using the above technical means, the configuration setting data in the controller is compared with the attribute setting data of the scanned slave module, which can confirm whether the data in the slave module is correct and ensure the data accuracy and security of subsequent communication between modules.

[0039] Preferably, after the data comparison of all the lower-level modules is completed, the master station module sends continuous data frames to all the slave station modules in combination with the comparison results for data communication, which includes the following steps:

[0040] When the comparison result is successful, judging whether the master module needs to send the configuration parameters of the current slave module to the slave module according to a preset data sending rule, wherein the configuration parameters are determined according to the configuration setting data, and determining the command type of the segment data frame of the current slave module according to the judgment result, wherein the command type includes sending configuration parameters, sending slave output data, and abnormal communication display;

[0041] When the comparison result is failure, the command type in the segment data frame of the current slave module is abnormal communication display;

[0042] After obtaining the segment data frames of all the slave modules, the master module sends the continuous data frames to the slave modules, where the continuous data frames are composed of the segment data frames of all the slave modules.

[0043] By adopting the above technical means, the command type of the segment data frame of each slave module is determined by comparing the attribute setting data of the slave module with the configuration setting data in the controller, thereby determining the continuous data frame sent by the master module to ensure normal communication between the master and slave stations.

[0044] Preferably, the step of determining the command type of the segment data frame of the current slave module according to the judgment result specifically includes the following steps:

[0045] If the result of the judgment is necessary, the current command type of the slave module is the sending configuration parameters, and the master module sends the configuration parameters to the slave module. After the configuration parameters are sent, the current command type of the slave module is modified to the sending slave output data. The slave output data is obtained by the master module from the controller and is used to send to the slave module and control the slave module.

[0046] If the result of the judgment is that it is not necessary, the command type of the current slave module is the sending slave output data.

[0047] By adopting the above technical means, the process of confirming the command type of the segment data frame of the slave module that has been successfully compared is described in detail, so as to determine the specific content of the continuous data frame transmission.

[0048] Preferably, when the master station module sends the continuous data frames to the slave station module, the method further includes the following steps:

[0049] When the data frame received by the slave module is not any one of the allocation ID data frame, the attribute acquisition data frame, and the self-existence confirmation data frame, the current slave module enters a continuous receiving and continuous sending state;

[0050] After the slave module enters the continuous receiving and sending state, the slave module continues to send slave input data to its own upper module. The slave input data is the data generated by the slave module itself. If the current slave module has a lower-level slave module, the slave input data received from the lower-level slave module will be attached to its own slave input data, and the data will be combined and sent to its own upper module until the slave input data is sent to the master module.

[0051] By adopting the above technical means, the master station module sends continuous data frames and the slave station module continuously receives and sends data simultaneously. The sending and receiving channels of the master station module and the slave station module are independent of each other, realizing high-speed full-duplex communication, reducing the system data exchange cycle and improving operation efficiency.

[0052] In summary, this application has at least the following beneficial effects:

[0053] 1. The method of the present application realizes the connection and data exchange between the master station module and the slave station module through the communication of various data frames between the master station module and the slave station module, so as to achieve the purpose of the master station module controlling the slave station module and obtaining the information of the slave station module, realizes high-speed full-duplex communication, reduces the cycle of system data exchange, improves the efficiency of use on site, and reduces costs.

[0054] 2. The system structure of this application is simple, which makes the connection between modules stable and reliable, improves on-site use efficiency and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is an architectural diagram of a high-speed backplane system that implements LVDS communication based on FPGA in an embodiment of the present application;

[0056] Figure 2 This is a flow chart of a method for implementing LVDS communication based on FPGA in an embodiment of the present application;

[0057] Figure 3 This is a flow chart of connecting a master station module with its subordinate slave station module in a method for implementing LVDS communication based on FPGA in an embodiment of the present application;

[0058] Figure 4 This is a flow chart of a method for realizing LVDS communication based on FPGA in an embodiment of the present application, in which a master station module is connected to the remaining slave station modules through its subordinate slave station module. DETAILED DESCRIPTION

[0059] The present application provides a high-speed backplane system and method for implementing LVDS communication based on FPGA. In order to make the purpose, technical solution and advantages of the present application clearer, the implementation method of the present application will be further described in detail below.

[0060] The following is a further detailed description of an embodiment of a high-speed backplane system for implementing LVDS communication based on FPGA in the present application in conjunction with the drawings of the specification.

[0061] A high-speed backplane system for implementing LVDS communication based on an FPGA includes a controller and a communication component. In this embodiment, the controller is a PLC, and the communication component includes multiple communication modules, specifically including a master module and at least one slave module. The controller is connected to the master module, and both the master module and the slave module are provided with an FPGA chip. The FPGA chip in the master module is also electrically connected to an MCU.

[0062] The FPGA chip is required in the slave module, and the MCU can determine whether it is required based on the complexity of the slave module's functions. The MCU and FPGA chip in the master module are connected via SPI, QSPI, or parallel port for data exchange.

[0063] The master station module and the slave station module each include at least one sending interface and one receiving interface. The master station module and the slave station module exchange data frames via an interface component consisting of the sending interface and the receiving interface.

[0064] In a specific embodiment, as Figure 1 As shown in the figure, the master module and the slave modules, as well as the slave modules and the slave modules are connected through LVDS interfaces. The master module has one LVDS transmit interface and one LVDS receive interface. Most slave modules have two LVDS transmit interfaces and two LVDS receive interfaces, but the last slave module has one LVDS transmit interface and one LVDS receive interface. Figure 1 The first slave module and the second slave module have two LVDS transmitting interfaces and two LVDS receiving interfaces, and the third slave module has one LVDS transmitting interface and one LVDS receiving interface.

[0065] All communication modules are connected in series, each communication module has at least one corresponding lower-level module or one upper-level module, and the communication modules send and receive data frames through interface components.

[0066] like Figure 1 As shown, in this embodiment, the lower module of the master module is the first slave module, and the corresponding upper module of the first slave module is the master module. In this embodiment, the LVDS interface in the interface component is named according to the output direction of the data.

[0067] For example, for the master module, two LVDS interfaces are defined as a downstream transmit interface and an upstream receive interface; for the slave module, four LVDS interfaces are defined as a downstream receive interface, a downstream transmit interface, an upstream receive interface, and an upstream transmit interface.

[0068] Data frames include continuous data frames and non-continuous data frames. Continuous data frames are composed of segment data frames from each slave module. Assuming there is one master module and three slave modules, a continuous data frame consists of the segment data frame from the first slave module, the segment data frame from the second slave module, and the segment data frame from the third slave module.

[0069] In short, a non-continuous data frame is a data frame that contains data from only one communication module, and a continuous data frame is a data frame that contains data from multiple communication modules.

[0070] The segment data frame uses hexadecimal and consists of a frame interval byte (0xAA), ID number, segment data frame length, CMD (command type), data, and CRC. For example, the segment data frame is AA 01 00 07 06 11 22 CRC, where the 0x01 byte is the ID number, the 00 07 bytes are the segment data frame length (the length is expressed in two bytes, of which AA is an identifier and is not included in the data length), the 0x01 byte is the command type, and the 11 22 bytes are the data.

[0071] The master module uses discontinuous data to assign IDs to all slave modules, obtain the slave module order number and the input and output PD data length information of the slave module, and inquire whether the slave module has the next-level slave module.

[0072] When a slave module has a lower-level module, the slave module establishes a hardware-triggered forwarding channel and forwards continuous data frames to its own lower-level module through the downlink transmission interface B without delay at the nanosecond level. Therefore, for the continuous data frames sent by the master module, all slave modules can be considered to have received the same continuous data frames synchronously.

[0073] The master module exchanges input and output data of all slave modules through continuous data frames. When the master module continuously sends continuous data frames to all slave modules, all slave modules enter the continuous receiving and sending state.

[0074] In another specific embodiment, a method for implementing LVDS communication based on FPGA is disclosed, which adopts the following technical solution:

[0075] A method for realizing LVDS communication based on FPGA, such as Figure 2 As shown, based on the above Figure 1 The high-speed backplane system shown includes the following steps:

[0076] S1. Start all communication modules. All lower-level modules continuously send their own existence data frames to the corresponding upper-level modules. Each communication module determines whether it has a lower-level module based on its own existence data frames. Specifically, the steps include:

[0077] S11, connect all communication modules in series, connect the master module to the PLC controller, and start all communication modules;

[0078] Combine Figure 3 As shown, after all the slave modules are started, they actively start the uplink sending interface to continuously and uninterruptedly send their own existence data frames to their own upper-level modules, and start the uplink receiving interface to facilitate receiving the self-existence data frames sent by the lower-level slave modules.

[0079] After the master station module is started, the FPGA chip starts the uplink receiving interface to receive the self-existing data frame sent by the slave station module using the uplink sending interface.

[0080] S12. After each upper-level module receives its own existence data frame sent by the corresponding lower-level module, the upper-level module generates a lower-level module existence flag based on its own existence data frame and stores it in its own FPGA chip.

[0081] S13. When the upper module is the master module, the MCU of the master module sends a lower-level existence confirmation data frame to its own FPGA chip, and uses the scan command to inquire whether there is a lower-level module existence mark in the FPGA chip. The FPGA chip replies to the MCU based on whether there is a lower-level module existence mark.

[0082] If it exists, the master module determines that it has a lower-level module; if it does not exist, the master module determines that it has no lower-level module.

[0083] If there is only a master module in the system, the FPGA chip of the master module cannot receive its own data frames from the lower-level slave modules, and the scan command will be repeated between the MCU and FPGA.

[0084] S14. When the upper module is a slave module, the master module sends a lower-level existence confirmation data frame to the current slave module to inquire whether there is a lower-level module existence flag. If yes, the master module determines that the current slave module has a lower-level module; if no, the master module determines that the current slave module does not have a lower-level module;

[0085] S15. Summarize all existing lower-level modules to obtain all slave modules.

[0086] For a system with multiple slave modules, the above steps can be considered to be performed synchronously after the system is powered on.

[0087] S2. Determine all existing slave modules based on all existing lower-level modules. The master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules, including the following steps:

[0088] S21. The master module sends an allocation ID data frame to the corresponding lower-level slave module.

[0089] In a specific implementation, the ID number sent by the master module to its subordinate slave module is 1.

[0090] S22. After the downlink receiving interface of the current slave module obtains the assigned ID number according to the assigned ID data frame, it stops the uplink sending interface from continuously sending its own data frames and records the assigned ID.

[0091] The slave module sends an allocation success data frame to the master module through its own uplink transmission interface, indicating that it has received the allocated ID;

[0092] When the master module receives the allocation success data frame, it determines that the ID allocation of the current slave module is successful.

[0093] S23. After the ID of the current slave module is successfully allocated, the master module sends a property acquisition data frame to the current slave module to obtain the property setting data of the first slave module. In this embodiment, the property setting data includes the first order number and the first PD data length of the first slave module.

[0094] S24 , the current first slave module replies with its own attribute setting data to the master module according to the attribute acquisition data frame, and the master module receives and stores the attribute setting data of the current slave module.

[0095] In summary, when the subordinate module exists, the master module assigns an ID to the existing subordinate module. When the ID of the subordinate module is successfully assigned, the master module obtains the property setting data of the current subordinate module. Through the above steps, the subordinate module of the master module, that is, the first slave module, has successfully completed the connection with the master module.

[0096] S25. The master station module sends a lower-level existence confirmation data frame to the first slave station module. The first slave station module replies to the master station module based on whether it has a lower-level module existence flag stored in it. If there is a lower-level module existence flag, the lower-level module exists; otherwise, the lower-level module does not exist.

[0097] S26, Combination Figure 4 As shown, when the first slave module replies to the master module that there is a slave module at the next level, the master module assigns an ID to the currently confirmed slave module according to a preset assignment rule;

[0098] In this embodiment, the allocation rule includes incrementing the ID number of the currently confirmed existing slave module relative to the ID number of the corresponding upper module. Therefore, the ID number allocated to the lower module of the first slave module is 2.

[0099] S27. After allocating the ID number of the currently confirmed existing slave module, the master module obtains the attribute setting data of the currently confirmed existing slave module, that is, obtains the first order number and the first PD data length of the second slave module.

[0100] It should be noted that after the slave module assigns an ID, it does not process the assigned ID data frame whose ID is greater than its own ID internally, and directly forwards it to the downlink sending interface.

[0101] That is to say, when the slave module has not been assigned an ID, it needs to process the allocation ID data frame received by the downstream interface, and the processing method is to reply with an allocation success data frame; if the slave module has been assigned an ID, it does not process the received allocation ID data frame, but directly forwards it to the downstream sending interface and sends it to the lower-level slave module.

[0102] This processing method is not only used for the allocation ID data frame, but also for the sending attribute acquisition data frame and the replied attribute setting data.

[0103] For example, in a specific implementable method, after the first slave station module is successfully connected to the master station module, when the downstream receiving interface receives an allocation ID data frame, an attribute acquisition data frame or a lower-level existence confirmation data frame, since the first slave station module has successfully allocated the ID, the first slave station module does not process the allocation ID data frame, the attribute acquisition data frame and the lower-level existence confirmation data frame of the second slave station module or other slave station modules internally, and directly forwards them to the downstream sending interface; similarly, the first slave station module does not process the allocation success data frame, the attribute setting data replied and the reply to the lower-level existence confirmation data frame received by the upstream receiving interface of the first slave station module internally, and directly forwards them to the upstream sending interface.

[0104] S28. Repeat the above steps until the master module receives a reply from the last slave module indicating that there is no next-level slave module. Then, the master module stops allocating IDs.

[0105] Here, the master module receives a reply from the last slave module that the next-level slave module does not exist. It is not that the last slave module directly replies to the master module. The master module's inquiry is forwarded by several intermediate slave modules to the last slave module, and the last slave module replies that the next-level slave module does not exist. The last slave module forwards this reply result to the master module through the uplink sending interface through several slave modules.

[0106] At this point, all slave modules have been successfully scanned by the master module, and the master module ends the system scanning action. During this period, all data frames are non-continuous data frames.

[0107] S3. The master module obtains configuration setting data from the controller of the high-speed backplane system, compares the configuration setting data with the attribute setting data and obtains the comparison result, including the following steps:

[0108] S31 . The master module receives configuration setting data sent by the controller of the high-speed backplane system. The configuration setting data includes the second order number and the second PD data length of the slave module.

[0109] In a specific implementation method, the master station module acts as a coupler to receive information about the set slave station module in the PLC controller (or other types of programmable logic controller), which is referred to as configuration setting data, including the slave station module order number and PD length set in the order of the allocation rule, called the second order number and the second PD data length. Each set of the second order number and the second PD data length has an ID number in the order of the allocation rule.

[0110] S32. After the master module obtains the property setting data of all the slave modules, the master module compares the configuration setting data with the property setting data and obtains a comparison result.

[0111] Data comparison includes determining whether the first order number and the second order number of the same slave module are consistent, and whether the lengths of the first PD data and the second PD data match. The comparison is based on comparing the configuration setting data and the attribute setting data with the same ID number.

[0112] The length of the PD data is downward compatible, that is, the length of the first PD data can be less than or equal to the length of the second PD data, and cannot be greater than the length of the second PD data.

[0113] After the data comparison is completed, the master module obtains the corresponding comparison results of each slave module.

[0114] S4. After the data comparison of all lower-level modules is completed, the master module sends continuous data frames to all slave modules based on the comparison results for data communication, which specifically includes the following steps:

[0115] S41. When the comparison result is successful, the master module sets the definition of the slave module to normal, and determines whether the master module needs to send the configuration parameters of the current slave module to the slave module according to the preset data sending rules. The configuration parameters are determined according to the configuration setting data.

[0116] Data sending rules refer to whether to send configuration parameters based on the different connected PLC controllers. The master station module will connect to PLC controllers with different protocols. Some protocols can carry configuration parameters themselves, while some cannot. Therefore, whether to send configuration parameters is determined based on the protocol carried by the PLC controller.

[0117] For analog slave modules, the PLC controller can set the configuration parameters for measuring voltage or current.

[0118] S42. Determine the command type of the segment data frame of the current slave module based on the judgment result. The command types include sending configuration parameters, sending slave output data, and abnormal communication display. The method of determining the command type specifically includes the following steps:

[0119] S421: If the result of the judgment is that it is needed, the current command type of the slave module is to send configuration parameters, and the master module sends the configuration parameters to the slave module. In a specific embodiment, when the command type is to send configuration parameters, the CMD field in the segment data frame is 0x0B.

[0120] S422: After the configuration parameters are sent, the command type of the current slave module is changed to sending slave output data. The slave output data is obtained by the master module from the controller and is sent to the slave module to control the slave module.

[0121] In a specific implementation method, when the command type is to send slave output data, the CMD field in the segment data frame is 0x06, that is, when the master station module completes sending the configuration parameters of the slave station module, CMD is changed from 0x0B to 0x06, and the master station module starts to send slave output data to the slave station module.

[0122] S423: If the result of the judgment is that it is not necessary, the current command type of the slave module is to send slave output data. The master module directly sends the slave output data to the slave module.

[0123] S43. When the comparison result is failure, the master module sets the definition of the slave module as type error, and the command type in the segment data frame of the current slave module is displayed as abnormal communication.

[0124] The reason for the comparison failure is that the first order number and the second order number of the slave module are inconsistent, or the lengths of the first PD data and the second PD data do not match.

[0125] In one specific embodiment, when the command type is abnormal communication display, the CMD field in the segment data frame is 0x0C, indicating that the slave module has failed the comparison. For the slave module that failed the comparison, the master module will continue to send data frames to it. The slave module will control the control system indicator to flash red rapidly based on the abnormal communication display command, indicating that the slave module has experienced a fault of the wrong type.

[0126] S44. After obtaining the segment data frames of all the slave modules, the master module sends continuous data frames to the slave modules.

[0127] A continuous data frame is composed of segment data frames of all slave modules. In a specific implementation mode, assuming there is 1 master module and 3 slave modules, the continuous data frame is composed of the segment data frame of the first slave module + the segment data frame of the second slave module + the segment data frame of the third slave module, for example: (AA 01 00 07 06 11 22 CRC AA02 00 07 06 33 44 CRC AA 03 00 07 06 55 66 CRC).

[0128] After receiving the continuous data frame, the slave module intercepts the segment data frame corresponding to its own ID number from the continuous data frame. The specific method of interception is as follows: the slave module is triggered by 0xAA to receive data judgment, and judges whether the next byte of 0xAA is its own ID. After judging that it matches its own ID, it receives the segment data frame length defined by the subsequent two bytes, and receives its own segment data frame according to the segment data frame length.

[0129] After receiving the segment data frame according to the segment data frame length, the received segment data frame is verified to determine whether there is an error in the data transmission process. The specific method of data verification is as follows: the received segment data frame contains a given CRC value. At this time, the slave module calculates a new CRC value based on the data content of the segment data frame and compares the CRC value of the received segment data frame with the calculated new CRC value to see if they are the same. If they are the same, the verification is successful; otherwise, the verification fails. If the verification fails, the slave module returns a received frame CRC error, and the CMD field is 0x10.

[0130] When the master module sends continuous data frames, it sends the next frame without interval after sending one frame, which can ensure high-speed communication. Even if the data frame changes, it can be sent out immediately, ensuring data update with the highest efficiency.

[0131] S5, while the master module sends continuous data frames to the slave module, also includes the following steps:

[0132] S51, when the data frame received by the slave module is not any of the allocation ID data frame, the attribute acquisition data frame and the self-existence confirmation data frame, the current slave module enters the continuous receiving and continuous sending state;

[0133] The ID allocation data frame, attribute acquisition data frame, and self-existence confirmation data frame are all non-continuous data frames.

[0134] S52, after the slave module enters the continuous receiving and sending state, the slave module continuously sends slave input data to its own superior module through the uplink sending interface. The slave input data is data generated by the slave module itself.

[0135] It should be noted that the slave input data is different from the slave output data. In this embodiment, the slave output data is the data sent by the PLC to the slave module through the master module, and the purpose is to control the slave module; while the slave input data is the data sent by the slave module to the master module, and the purpose is to feedback its own data status to the master module. For example, the slave input data can be some digital inputs. The slave module is connected to some sensors, and then these sensors will have some values ​​returned to the PLC. These values ​​are the slave input data. The slave input data can also be some analog inputs such as voltage and current.

[0136] In this embodiment, if the master module sends configuration parameters to the slave module, the slave module will also send a parameter confirmation data frame to the master module to indicate to the master module that it has received the configuration parameters.

[0137] S53. If the current slave module has a subordinate slave module, the slave input data received from the subordinate slave module via the uplink receive interface is appended to the slave input data of the current slave module, and the combined data is sent to the superior module via the uplink transmit interface. This continues until the combined slave input data of all the slave modules' uplink data is sent to the master module. Uplink data is data sent toward the master module.

[0138] Since the last slave module does not have a next-level slave module, it only sends its own data frames, including confirmation parameter data frames and slave input data, through the uplink transmission interface.

[0139] In this embodiment, when all slave modules are in the continuous transmission / reception state, after sending their own data frames plus the uplink data from the lower-level slave modules received by the downlink receiving interface through the uplink transmission interface, they continuously transmit their own data frames plus the uplink data from the lower-level slave modules received by the downlink receiving interface. This ensures data updates with the highest efficiency. Even if the data frames change, the updated data frames can be sent out at the fastest speed, thus avoiding data update delays.

[0140] The uplink receiving interface and uplink sending interface of the slave module work independently. When the uplink sending interface sends a data frame, it does not need to wait for the uplink receiving interface to finish receiving it, which can also ensure the data update efficiency.

[0141] Through the above steps, a communication method based on a high-speed backplane system is implemented, which maximizes the data exchange speed between communication modules and improves the communication efficiency between communication modules.

[0142] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for implementing LVDS communication based on FPGA, the method being applied to a high-speed backplane system that implements LVDS communication using FPGA, characterized in that: The system includes a controller and a communication component, the communication component includes multiple communication modules, all of the communication modules are connected in series, and each of the communication modules has at least one corresponding lower-level module or one upper-level module; the communication component specifically includes a master station module and at least one slave station module, the controller is connected to the master station module, and the master station module and the slave station module are each provided with an FPGA chip, and the FPGA chip in the master station module is also electrically connected to an MCU; the master station module and the slave station module each include at least one sending interface and one receiving interface, and the master station module and the slave station module exchange data frames through an interface component composed of the sending interface and the receiving interface, and the data frames include continuous data frames and discontinuous data frames. The method includes the following steps: All communication modules are started, and all lower-level modules continuously send their own existence data frames to the corresponding upper-level modules, and each communication module determines whether it exists in the lower-level module based on the own existence data frames; Determining all existing slave modules based on all existing lower-level modules, the master module performing module scanning on all existing slave modules to obtain attribute setting data of all the slave modules, the attribute setting data including a first order number and a first PD data length; The master module obtains configuration setting data from the controller of the high-speed backplane system, the configuration setting data including the second order number and the second PD data length of the slave module, and compares the configuration setting data with the attribute setting data to obtain a comparison result; When the data comparison of all the lower-level modules is completed, the master station module sends continuous data frames to all the slave station modules based on the comparison results for data communication; specifically, when the master station module continues to send the continuous data frames to all the slave station modules, all the slave station modules enter a continuous receiving and continuous sending state, and the slave station module continues to send slave station input data to its own upper-level module until the slave station input data is sent to the master station module.

2. The method for implementing LVDS communication based on FPGA according to claim 1, wherein: The communication module of the system sends and receives the data frame via the interface component; When a slave module has a subordinate module, the slave module establishes a hardware-triggered forwarding channel to forward the continuous data frames to its own subordinate module without delay.

3. The method for realizing LVDS communication based on FPGA according to claim 2, wherein: Each of the communication modules determines whether it has the lower-level module according to the data frame it has, specifically including the following steps: After each upper-level module receives the self-existence data frame sent by the corresponding lower-level module, the upper-level module generates a lower-level module existence flag based on the self-existence data frame and stores it in its own FPGA chip; When the upper module is the master station module, the MCU of the master station module sends a lower-level existence confirmation data frame to the FPGA chip of the master station module, inquiring whether the lower-level module existence flag exists in the FPGA chip. If so, the master station module determines that the lower-level module exists in itself; if not, the master station module determines that the lower-level module does not exist in itself; When the upper module is the slave module, the master module sends the lower-level existence confirmation data frame to the current slave module to inquire whether the lower-level module existence flag exists. If so, the master module determines that the lower-level module exists in the current slave module. If not, the master station module determines that the slave station module does not have the lower-level module; All the existing lower-level modules are aggregated to obtain all the slave station modules.

4. The method for realizing LVDS communication based on FPGA according to claim 3, wherein: The method of determining all existing slave modules based on all existing lower-level modules, wherein the master module performs module scanning on all existing slave modules to obtain attribute setting data of all slave modules, specifically includes the following steps: The master station module sends an allocation ID data frame to the corresponding subordinate slave station module. After the current slave station module obtains and records the allocated ID number according to the allocation ID data frame, the slave station module sends an allocation success data frame to the master station module through its own sending interface. When the master station module receives the allocation success data frame, it is determined that the ID allocation of the current slave station module is successful; After the ID of the current slave module is successfully allocated, the master module sends an attribute acquisition data frame to the current slave module. The current slave module replies with its own attribute setting data to the master module based on the attribute acquisition data frame. The master module receives and stores the attribute setting data of the current slave module.

5. The method for realizing LVDS communication based on FPGA according to claim 4, wherein: After the master module receives and stores the attribute setting data of the current slave module, the following steps are also included: After the master module assigns an ID to the slave module as its own subordinate module and obtains the attribute setting data of the slave module, the master module sends the subordinate existence confirmation data frame to the slave module; When the slave module replies to the master module that a slave module at the next level exists, the master module assigns an ID to the currently confirmed slave module according to a preset assignment rule, wherein the assignment rule includes incrementing the ID number of the currently confirmed slave module relative to the ID number of the corresponding upper-level module. After assigning the ID number of the currently confirmed slave module, the master module obtains the attribute setting data of the currently confirmed slave module. The master module stops allocating IDs until the master module receives a reply from the slave module indicating that the slave module at the next level does not exist.

6. The method for realizing LVDS communication based on FPGA according to claim 4, wherein: The master station module obtains configuration setting data from the controller of the high-speed backplane system, compares the configuration setting data with the attribute setting data and obtains a comparison result, specifically comprising the following steps: The master station module receives configuration setting data sent by the controller of the high-speed backplane system; After the master module obtains the property setting data of all the slave modules, the master module compares the configuration setting data with the property setting data and obtains a comparison result, wherein the data comparison includes determining whether the first order number and the second order number of the same slave module are consistent, and whether the lengths of the first PD data and the second PD data match; After the data comparison is completed, the master station module obtains the comparison results corresponding to each slave station module.

7. The method for realizing LVDS communication based on FPGA according to claim 4, wherein: When the data comparison of all the lower-level modules is completed, the master station module sends continuous data frames to all the slave station modules based on the comparison results for data communication, including the following steps: When the comparison result is successful, judging whether the master module needs to send the configuration parameters of the current slave module to the slave module according to a preset data sending rule, wherein the configuration parameters are determined according to the configuration setting data, and determining the command type of the segment data frame of the current slave module according to the judgment result, wherein the command type includes sending configuration parameters, sending slave output data, and abnormal communication display; When the comparison result is failure, the command type in the segment data frame of the current slave module is abnormal communication display; After obtaining the segment data frames of all the slave modules, the master module sends the continuous data frames to the slave modules, where the continuous data frames are composed of the segment data frames of all the slave modules.

8. The method for realizing LVDS communication based on FPGA according to claim 7, wherein: Determining the command type of the segment data frame of the current slave module based on the judgment result specifically includes the following steps: If the result of the judgment is necessary, the current command type of the slave module is the sending configuration parameters, and the master module sends the configuration parameters to the slave module. After the configuration parameters are sent, the current command type of the slave module is modified to the sending slave output data. The slave output data is obtained by the master module from the controller and is used to send to the slave module and control the slave module. If the result of the judgment is that it is not necessary, the command type of the current slave module is the sending slave output data.

9. The method for realizing LVDS communication based on FPGA according to claim 7, wherein: When the master station module sends the continuous data frames to the slave station module, the following steps are also included: When the data frame received by the slave module is not any one of the allocation ID data frame, the attribute acquisition data frame, and the self-existence confirmation data frame, the current slave module enters a continuous receiving and continuous sending state; After the slave module enters the continuous receiving and sending state, the slave module continues to send slave input data to its own upper module. The slave input data is the data generated by the slave module itself. If the current slave module has a lower-level slave module, the slave input data received from the lower-level slave module will be attached to its own slave input data, and the data will be combined and sent to its own upper module until the slave input data is sent to the master module.

Images