A signal processing system, method, control device, and readable storage medium

Abstract

The present application discloses a signal processing system, method, control device and readable storage medium. The system includes: an image sensor; an encoding unit, configured to obtain original video stream data and a corresponding original clock frequency; determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state; reduce the clock frequency corresponding to the continuous data to a target clock frequency, and keep the clock frequency corresponding to the discontinuous data as the original clock frequency; package the original video stream data into target video stream data and output it, with the continuous data output at the target clock frequency and the discontinuous data output at the original clock frequency; a decoding unit, configured to receive the target video stream data after long-distance transmission and decode it into original video stream data. The embodiments of the present application can improve the stability of long-distance transmission of video streams over extremely thin wires, and have low requirements for the material and impedance specifications of the transmission wires, and low cost.

Description

Technical Field

[0001] This application relates to the technical field of signal processing, and particularly to a signal processing system, method, control device, and readable storage medium. Background Art

[0002] In the fields of camera biomedicine and industrial detection, it is usually necessary to perform long-distance transmission of video streams detected by image sensors output through differential signal interfaces. However, long-distance transmission of camera video streams can cause problems such as attenuation of video stream signals and high bit error rates. Therefore, the requirements for transmission wires are relatively high. For industrial detection scenarios, existing ordinary wires can already solve problems such as attenuation of video stream signals and high bit error rates. However, in biomedicine scenarios, for example, devices such as endoscopes in the human body require extremely thin wires with very high impedance and serious signal attenuation, and video cannot be transmitted. Therefore, the requirements for the material and impedance specifications of the transmission wires are even higher, and the R & D cost of the wires is also higher. Summary of the Invention

[0003] This application aims to at least solve one of the technical problems existing in the prior art. For this purpose, this application proposes a signal processing system that can improve the stability of long-distance transmission of video streams through extremely thin wires, and has low requirements for the material and impedance specifications of the transmission wires and low costs.

[0004] This application also provides a signal processing method, a control device, and a computer-readable storage medium.

[0005] The signal processing system according to the first aspect embodiment of this application includes:

[0006] An image sensor for detecting original video stream data;

[0007] An encoding unit for obtaining the original video stream data and the corresponding original clock frequency; determining the continuity state of the original video stream data, and dividing the original video stream data into continuous data and discontinuous data according to the continuity state. The continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits; reducing the clock frequency corresponding to the continuous data to a target clock frequency, and keeping the clock frequency corresponding to the discontinuous data as the original clock frequency; packing the original video stream data into target video stream data and outputting it, where the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency;

[0008] A decoding unit for receiving the target video stream data transmitted over a long distance and decoding it into the original video stream data.

[0009] The signal processing system according to the embodiments of this application has at least the following beneficial effects:

[0010] Since the differential potential of the visible signal will be greatly attenuated after long-distance transmission, when there are consecutive data bits, the differential potential is enlarged, resulting in errors in subsequent data parsing. In the embodiment of the present application, the encoding unit re-encodes the original video stream data. First, the continuity state of the original video stream data is confirmed, then the clock frequency is adaptively adjusted, the clock frequency corresponding to the continuous data is reduced, the clock frequency corresponding to the non-continuous data is kept unchanged, and then it is packed and transmitted over a long distance to the decoding unit for decoding. This can not only ensure that the mutant data has more time to change to ensure correct transmission, improve the stability of long-distance transmission of the video stream of extremely thin wires, but also transmit data at a high frequency. Compared with the traditional fixed low-frequency method, it has a higher bandwidth, can meet the bandwidth requirements of long-distance transmission of extremely thin wires, and has low requirements for the material and impedance specifications of the transmission wire, and low cost.

[0011] According to some embodiments of the present application, both the encoding unit and the decoding unit adopt FPGA.

[0012] According to the signal processing method of the second aspect embodiment of the present application, the method includes:

[0013] Obtain the original video stream data and the corresponding original clock frequency;

[0014] Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and non-continuous data according to the continuity state. The continuous data includes at least two consecutive data bits and one non-continuous data bit, and the non-continuous data includes two different data bits;

[0015] Reduce the clock frequency corresponding to the continuous data to the target clock frequency, and keep the clock frequency corresponding to the non-continuous data as the original clock frequency;

[0016] Pack the original video stream data into target video stream data for long-distance transmission, wherein the continuous data is output at the target clock frequency, and the non-continuous data is output at the original clock frequency.

[0017] The signal processing method according to the embodiment of the present application has at least the following beneficial effects:

[0018] Since the differential potential of the visible signal will be greatly attenuated after long-distance transmission, when there are continuous data bits, the differential potential is enlarged, resulting in errors in subsequent data parsing. In the embodiments of the present application, by re-encoding the original video stream data, first, the continuity state of the original video stream data is confirmed, then the clock frequency is adaptively adjusted, the clock frequency corresponding to the continuous data is reduced, the clock frequency corresponding to the discontinuous data is kept unchanged, and then it is packed for long-distance transmission. This can not only allow more change time for the mutation data to ensure correct transmission, improve the stability of long-distance transmission of the video stream of extremely thin wires, but also transmit data at a high frequency, with a higher bandwidth compared to the traditional fixed low-frequency method, which can meet the bandwidth requirements of long-distance transmission of extremely thin wires, and has low requirements for the material and impedance specifications of the transmission wire and low cost.

[0019] According to some embodiments of the present application, the target clock frequency is obtained through the following steps:

[0020] Determine the number of consecutive data bits in the continuous data;

[0021] Determine the target clock frequency according to the number of consecutive data bits in the continuous data and the original clock frequency, where the number of consecutive data bits is negatively correlated with the magnitude of the target clock frequency.

[0022] According to some embodiments of the present application, the method further includes:

[0023] Determine the number of consecutive data bits in the continuous data;

[0024] Determine multiple different adjustment percentages based on the number of consecutive data bits in the continuous data, where the number of consecutive data bits is negatively correlated with the magnitude of the adjustment percentage.

[0025] According to some embodiments of the present application, the determining the target clock frequency according to the number of consecutive data bits in the continuous data and the original clock frequency includes:

[0026] Determine the corresponding target adjustment percentage from multiple different adjustment percentages according to the number of consecutive data bits in the continuous data;

[0027] Determine the target clock frequency based on the target adjustment percentage and the original clock frequency.

[0028] According to some embodiments of the present application, the determining the target clock frequency based on the target adjustment percentage and the original clock frequency includes:

[0029] Take the product of the target adjustment percentage and the original clock frequency as the target clock frequency.

[0030] According to some embodiments of the present application, the original clock frequency is the highest transmission clock frequency.

[0031] The control device according to the embodiment of the third aspect of the present application includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the signal processing method as described in the embodiment of the second aspect above. Since the control device adopts all the technical solutions of the signal processing method in the above embodiment, it at least has all the beneficial effects brought by the technical solutions in the above embodiment.

[0032] The computer-readable storage medium according to the embodiment of the fourth aspect of the present application stores computer-executable instructions for executing the signal processing method as described in the embodiment of the second aspect above. Since the computer-readable storage medium adopts all the technical solutions of the signal processing method in the above embodiment, it at least has all the beneficial effects brought by the technical solutions in the above embodiment.

[0033] Other features and advantages of the present application will be described in the subsequent specification, and part of them will become obvious from the specification or be understood by implementing the present application. Description of the Drawings

[0034] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0035] Figure 1 is a structural block diagram of a signal processing system according to an embodiment of the present application;

[0036] Figure 2 is a structural block diagram of an encoding unit according to an embodiment of the present application;

[0037] Figure 3 is a structural block diagram of a decoding unit according to an embodiment of the present application;

[0038] Figure 4 is a flowchart of a signal processing method according to an embodiment of the present application;

[0039] Figure 5 is a waveform diagram of the output signal of an encoding unit in the prior art;

[0040] Figure 6 is a waveform diagram of the received signal of a decoding unit in the prior art;

[0041] Figure 7 is a waveform diagram of the output signal of an encoding unit according to an embodiment of the present application;

[0042] Figure 8It is the waveform diagram of the received signal of the decoding unit according to an embodiment of the present application;

[0043] Figure 9 It is the waveform diagram of the output signal of the encoding unit corresponding to when the decoding unit according to an embodiment of the present application can normally parse the signal;

[0044] Figure 10 It is the waveform diagram of the received signal of the decoding unit corresponding to when the decoding unit according to an embodiment of the present application can normally parse the signal;

[0045] Figure 11 It is the waveform diagram of the output signal of the encoding unit corresponding to when the decoding unit according to an embodiment of the present application cannot normally parse the signal;

[0046] Figure 12 It is the waveform diagram of the received signal of the decoding unit corresponding to when the decoding unit according to an embodiment of the present application cannot normally parse the signal.

[0047] Reference numerals:

[0048] Image sensor 100;

[0049] Encoding unit 200, first received data unit 210, transmission protocol parsing unit 220, valid transmission data processing unit 230, first valid data caching unit 240, first cached data packetizing unit 250, data continuity judgment processing unit 260, clock frequency adaptive processing unit 270, cached data secondary packetizing processing unit 280, first output data unit 290;

[0050] Decoding unit 300, second received data unit 310, data caching processing unit 320, high-speed clock parsing data unit 330, second valid data caching unit 340, second cached data packetizing unit 350, protocol packetizing unit 360, second output data unit 370. Detailed implementation manners

[0051] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as limiting the present application.

[0052] In the description of the present application, if it is described as first, second, etc., it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0053] In the description of the present application, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by "upper", "lower", etc., is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0054] In the description of the present application, it should be noted that unless otherwise clearly defined, terms such as "set", "install", "connect", etc. should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present application in combination with the specific content of the technical solution.

[0055] To facilitate a better understanding of the solutions of the embodiments of the present application, the related technologies will be introduced first below.

[0056] Differential signal: It is an interface standard for high-speed data transmission. By simultaneously transmitting two opposite signals, positive and negative, on the transmission line, circuit noise and transmission loss are reduced.

[0057] Camera Serial Interface (Mobile Industry Processor Interface, MIPI): It is an interface standard for connecting an image sensor 100 and an image processor. It uses MIPI D-PHY as the physical layer, provides a high-speed image data transmission channel, and supports functions such as multi-channel and multiplexing.

[0058] Field-Programmable Gate Array (FPGA): It is a programmable logic device that can be configured and reconfigured in real time according to the user's needs to implement various different digital logic functions.

[0059] In the fields of camera-based biomedical and industrial detection, long-distance transmission of video streams detected by an image sensor 100 with a differential signal interface is usually required. The requirements for video stream transmission are relatively high, and the frame rate needs to be stable. The traditional MIPI transmission has a length limit of no more than 0.3 meters, and the conventional video stream transmission based on differential signals also does not exceed 1 meter. Long-distance transmission of camera video streams will cause problems such as attenuation of video stream signals and high error rates, so the requirements for transmission wires are relatively high. For industrial detection scenarios, existing ordinary wires can already solve problems such as attenuation of video stream signals and high error rates. However, in biomedical scenarios, for example, devices such as endoscopes in the human body require extremely thin wires with very high impedance and severe signal attenuation (i.e., there are problems of high impedance, high latency, and a significant slowdown in the rising and falling times of signal edges). The signal no longer conforms to the differential standard protocol and cannot be parsed through the standard protocol, resulting in the inability to transmit the video. Therefore, the requirements for the material and impedance specifications of the transmission wire are even higher, and the R & D cost of the wire is also higher. Moreover, the long-distance transmission bandwidth of wires with a diameter within 0.1 mm is extremely low and cannot meet scenarios with requirements for the diameter of the transmission line.

[0060] The following will combine Figures 1 to 12 to clearly and completely describe the signal processing system of the embodiments of the present application. Obviously, the following described embodiments are some embodiments of the present application, not all embodiments.

[0061] The signal processing system according to the first aspect embodiment of the present application includes an image sensor 100, an encoding unit 200, and a decoding unit 300.

[0062] The image sensor 100 is used to detect the original video stream data;

[0063] The encoding unit 200 is used to obtain the original video stream data and the corresponding original clock frequency; determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state. The continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits; reduce the clock frequency corresponding to the continuous data to the target clock frequency, and keep the clock frequency corresponding to the discontinuous data as the original clock frequency; pack the original video stream data into the target video stream data and output it, where the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency;

[0064] The decoding unit 300 is used to receive the target video stream data transmitted over a long distance and decode it into the original video stream data.

[0065] Refer to Figure 1 , Figure 1The structural block diagram of a signal processing system according to an embodiment of the present application includes an image sensor 100, an encoding unit 200, and a decoding unit 300. The image sensor 100 is connected to the encoding unit 200 and is located on the detection end side; the encoding unit 200 is connected to the decoding unit 300 through a long-distance transmission line; the output end of the decoding unit 300 is connected to the backend system platform, and the backend system platform directly receives the original video stream data output by the decoding unit 300 without considering the limitation of the transmission distance.

[0066] Reference Figure 2 and Figure 3 , Figure 2 The structural block diagram of the encoding unit 200 according to an embodiment of the present application Figure 3 The structural block diagram of the decoding unit 300 according to an embodiment of the present application. The encoding unit 200 includes a first received data unit 210, a transmission protocol parsing unit 220, a valid transmission data processing unit 230, a first valid data caching unit 240, a first cached data packetizing unit 250, a data continuity judgment and processing unit 260, a clock frequency adaptive processing unit 270, a cached data secondary packetizing unit 280, and a first output data unit 290. Among them, the data continuity judgment and processing unit 260 is used to determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state; the clock frequency adaptive processing unit 270 is used to reduce the clock frequency corresponding to the continuous data to the target clock frequency and keep the clock frequency corresponding to the discontinuous data as the original clock frequency. The first received data unit 210 is used to receive the MIPI output of the image sensor 100, and the first output data unit 290 is used to output the target video stream data for long-distance transmission of differential signals.

[0067] It should be noted that the working principles and functions of the first received data unit 210, the transmission protocol parsing unit 220, the valid transmission data processing unit 230, the first valid data caching unit 240, the first cached data packetizing unit 250, the cached data secondary packetizing unit 280, and the first output data unit 290 are all prior arts known to those skilled in the art and will not be elaborated here.

[0068] The decoding unit 300 includes a second received data unit 310, a data caching and processing unit 320, a high-speed clock parsing data unit 330, a second valid data caching unit 340, a second cached data packetizing unit 350, a protocol packetizing unit 360, and a second output data unit 370. It should be noted that the specific structure, working principle, and function of the decoding unit 300 are all prior arts known to those skilled in the art and will not be elaborated here.

[0069] Reference Figure 5 and Figure 6, Figure 5 is a waveform diagram of the output signal of the coding unit 200 in the prior art; Figure 6 is a waveform diagram of the received signal of the decoding unit 300 in the prior art. As can be seen from Figure 5 and Figure 6 , after the visible signal is transmitted over a long distance, the differential potential of the signal will be greatly attenuated. When transmitting multiple "1"s or multiple "0"s continuously, the differential potential is widened, resulting in incorrect subsequent data parsing. To ensure the correct data transmission, the traditional method is to reduce the clock frequency as a whole, but the bandwidth will be severely limited.

[0070] Referring to Figure 7 and Figure 8 , Figure 7 is a waveform diagram of the output signal of the coding unit 200 according to an embodiment of the present application; Figure 8 is a waveform diagram of the received signal of the decoding unit 300 according to an embodiment of the present application. In the coding unit 200, by determining the continuity state of the original video stream data, the original video stream data can be divided into continuous data and discontinuous data. The continuous data includes at least two continuous data bits and one discontinuous data bit, such as "001", "0001", "11110"; the discontinuous data includes two different data bits, such as "01", "10". When transmitting multiple "0"s or "1"s continuously, the corresponding clock frequency is dynamically adjusted. The clock frequency corresponding to the continuous data is reduced to the target clock frequency, and the clock frequency corresponding to the discontinuous data is maintained at the original clock frequency. That is, when transmitting "001", "0001", "11110", the corresponding clock frequency is reduced, and when transmitting "01", "10", the corresponding clock frequency is maintained at the original clock frequency, which can make the mutant data have more change time to ensure correct transmission. Compared with the traditional fixed low-frequency method, the embodiment of the present application only reduces the clock frequency corresponding to some data bits, and can transmit data at a high frequency as a whole, with a higher bandwidth, which can meet the bandwidth requirements of long-distance transmission of extremely thin wires, and has low requirements for the material and impedance specifications of the transmission wires, and low cost. The embodiment of the present application can achieve real-time and stable transmission of long-distance video streams of at least 5 meters to 30 meters.

[0071] In some embodiments of the present application, when determining the continuity status of the original video stream data, first determine the number of consecutive data bits in the consecutive data, and then determine multiple different adjustment percentages based on the number of consecutive data bits in the consecutive data. Among them, the number of consecutive data bits is negatively correlated with the magnitude of the adjustment percentage. For example, when the consecutive data is "001", there are two consecutive data bits "00", and the corresponding adjustment percentage is 80%; when the consecutive data is "0001", there are three consecutive data bits "000", and the corresponding adjustment percentage is 70%; when the consecutive data is "11110", there are four consecutive data bits "1111", and the corresponding adjustment percentage is 60%. And so on, the more consecutive data bits, the smaller the corresponding adjustment percentage. Then determine the corresponding target adjustment percentage from the multiple different adjustment percentages according to the number of consecutive data bits in the consecutive data, and use the product of the target adjustment percentage and the original clock frequency as the target clock frequency. For example, when the consecutive data is "001", it is transmitted at a transmission frequency of the original clock frequency * 80%.

[0072] In one embodiment, assume that the original video stream data is "01011011110". Then, when disassembled, it can be divided into "01", "10", "01", "110", "01", "11110". Correspondingly, set the clock frequency corresponding to "110" to the original clock frequency * 80%, set the clock frequency corresponding to "11110" to the original clock frequency * 60%, and keep the clock frequencies corresponding to other non-consecutive data unchanged at the original clock frequency.

[0073] It should be noted that both the original clock frequency and the target clock frequency are less than or equal to the highest transmission clock frequency and greater than or equal to the lowest transmission clock frequency. Among them, the highest transmission clock frequency can be obtained by continuously increasing the differential clock signal frequency until the decoding unit 300 cannot parse out the fixed differential data signal, and the lowest transmission clock frequency is not less than the normal non-frequency-changing transmission frequency.

[0074] Reference Figures 9 to 12 , Figure 9 is the waveform diagram of the output signal of the encoding unit 200 corresponding to when the decoding unit 300 of an embodiment of the present application can normally parse the signal; Figure 10 is the waveform diagram of the received signal of the decoding unit 300 corresponding to when the decoding unit 300 of an embodiment of the present application can normally parse the signal; Figure 11 is the waveform diagram of the output signal of the encoding unit 200 corresponding to when the decoding unit 300 of an embodiment of the present application cannot normally parse the signal; Figure 12It is a waveform diagram of the received signal of the decoding unit 300 corresponding to the situation where the decoding unit 300 of an embodiment of the present application cannot correctly parse the signal. The encoding unit 200 outputs a fixed differential data signal "010101010". When the decoding unit 300 can correctly parse the fixed differential data signal, the parsed result is "010101010"; when the decoding unit 300 cannot correctly parse the fixed differential data signal, the parsed result may be "0001010", as Figure 12 shown, two "1"s are missing.

[0075] In an embodiment of the present application, when multiple "1"s or multiple "0"s are continuously transmitted, the differential potential is enlarged, resulting in errors in subsequent data parsing. The more the number of consecutive data bits, the higher the error rate. By determining multiple different adjustment percentages according to the number of consecutive data bits, the more the number of consecutive data bits, the smaller the corresponding clock frequency is set, which can make the mutant data have more change time to ensure correct transmission and can further ensure the correctness of data transmission.

[0076] It should be noted that the way of setting the adjustment percentage is only one embodiment. It can also be that for each additional consecutive data bit, a fixed value is subtracted from the original clock frequency. The specific way of reducing the clock frequency cannot be regarded as a limitation to the present application.

[0077] In one embodiment, the original clock frequency is the highest transmission clock frequency. When the original clock frequency is the highest transmission clock frequency, on the one hand, it can make the adjustable range of the target clock frequency larger, so that the clock frequencies corresponding to consecutive data with different numbers of consecutive data bits can be divided more finely, and the correctness of data transmission can be improved. On the other hand, it can improve the overall transmission frequency, thereby increasing the bandwidth.

[0078] According to the signal processing system of the embodiments of the present application, since the signal differential potential will be greatly attenuated after the visible signal is transmitted over a long distance, when there are consecutive data bits, the differential potential is enlarged, resulting in errors in subsequent data parsing. In the embodiments of the present application, the encoding unit 200 re-encodes the original video stream data. First, it confirms the continuity state of the original video stream data, then adaptively adjusts the clock frequency, reduces the clock frequency corresponding to consecutive data, keeps the clock frequency corresponding to non-consecutive data unchanged, and then packs and transmits it over a long distance to the decoding unit 300 for decoding. This can not only make the mutant data have more change time to ensure correct transmission and improve the stability of long-distance transmission of the video stream of ultra-thin wires, but also transmit data at a high frequency, with a higher bandwidth than the traditional fixed low-frequency method, which can meet the bandwidth requirements of long-distance transmission of ultra-thin wires, and has low requirements for the material and impedance specifications of the transmission wire and low cost.

[0079] In some embodiments of the present application, both the encoding unit 200 and the decoding unit 300 employ FPGAs. Traditional network transmission can solve the problem of stable transmission of video streams over long distances. However, the circuit module design cannot achieve a very small area, and the power consumption is also high, which cannot meet the scenarios with requirements for the product volume. Moreover, the power consumption and bandwidth of the wireless transceiver module cannot meet the requirements. In the embodiments of the present application, without a driver, the encoding and decoding driving capabilities are increased, and the transmission scheme is optimized directly at the output and input ends of the FPGA, which can be applied to products with requirements for the size of the device, such as medical endoscopes or industrial endoscopes and other scenarios with strict requirements for volume.

[0080] Reference Figure 4 , Figure 4 is a flowchart of a signal processing method according to an embodiment of the present application. According to the signal processing method of the second aspect embodiment of the present application, the method includes:

[0081] Obtain the original video stream data and the corresponding original clock frequency;

[0082] Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state. The continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits;

[0083] Reduce the clock frequency corresponding to the continuous data to the target clock frequency, and keep the clock frequency corresponding to the discontinuous data as the original clock frequency;

[0084] Pack the original video stream data into target video stream data for long-distance transmission, wherein the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency.

[0085] From Figure 5 and Figure 6 It can be seen that after the visible signal is transmitted over a long distance, the differential potential of the signal will be greatly attenuated. When transmitting multiple "1"s or multiple "0"s continuously, the differential potential is enlarged, resulting in errors in subsequent data parsing. To ensure the correct data transmission, the traditional method is to reduce the clock frequency as a whole, but the bandwidth will be severely limited.

[0086] In the embodiment of the present application, after obtaining the original video stream data, the original video stream data is first re-encoded. By determining the continuity state of the original video stream data, the original video stream data can be divided into continuous data and discontinuous data. The continuous data includes at least two consecutive data bits and one discontinuous data bit, such as "001", "0001", "11110"; the discontinuous data includes two different data bits, such as "01", "10". When transmitting multiple "0"s or "1"s continuously, the corresponding clock frequency is dynamically adjusted, and the clock frequency corresponding to the continuous data is reduced to the target clock frequency, while keeping the clock frequency corresponding to the discontinuous data as the original clock frequency. That is, when transmitting "001", "0001", "11110", its corresponding clock frequency is reduced, and when transmitting "01", "10", its corresponding clock frequency is kept as the original clock frequency, which can make the mutated data have more change time to ensure correct transmission. Compared with the traditional fixed low-frequency method, the embodiment of the present application only reduces the clock frequency corresponding to some data bits, and can transmit data at a high frequency as a whole, with a higher bandwidth, which can meet the bandwidth requirements for long-distance transmission of extremely thin wires, and has low requirements for the material and impedance specifications of the transmission wires, and low cost.

[0087] According to the signal processing method of the embodiment of the present application, since the signal differential potential will be greatly attenuated after the visible signal is transmitted over a long distance, when there are consecutive data bits, the differential potential is enlarged, resulting in incorrect subsequent data parsing. In the embodiment of the present application, by re-encoding the original video stream data, first, the continuity state of the original video stream data is confirmed, then the clock frequency is adaptively adjusted, the clock frequency corresponding to the continuous data is reduced, the clock frequency corresponding to the discontinuous data is kept unchanged, and then it is packed for long-distance transmission. This can not only make the mutated data have more change time to ensure correct transmission, improve the stability of long-distance transmission of the video stream of extremely thin wires, but also transmit data at a high frequency. Compared with the traditional fixed low-frequency method, it has a higher bandwidth, can meet the bandwidth requirements for long-distance transmission of extremely thin wires, and has low requirements for the material and impedance specifications of the transmission wires, and low cost.

[0088] In some embodiments of the present application, the target clock frequency is obtained through the following steps:

[0089] Determine the number of consecutive data bits in the continuous data;

[0090] Determine the target clock frequency according to the number of consecutive data bits in the continuous data and the original clock frequency, where the number of consecutive data bits is negatively correlated with the magnitude of the target clock frequency.

[0091] Reference Figure 5 and Figure 6, it can be seen that the differential potential of the visible signal will be greatly attenuated after long-distance transmission. When multiple "1"s or multiple "0"s are continuously transmitted, the differential potential is enlarged, resulting in errors in subsequent data parsing. The more consecutive data bits there are, the higher the error rate. Therefore, the more consecutive data bits there are, the smaller the corresponding target clock frequency can be set to further ensure the correctness of data transmission.

[0092] In some embodiments of the present application, the method further includes:

[0093] Determine the number of consecutive data bits in the consecutive data;

[0094] Based on the number of consecutive data bits in the consecutive data, determine multiple different adjustment percentages, where the number of consecutive data bits is negatively correlated with the magnitude of the adjustment percentage.

[0095] In one embodiment, when the consecutive data is "001", there are two consecutive data bits "00", and the corresponding adjustment percentage can be set to 80%; when the consecutive data is "0001", there are three consecutive data bits "000", and the corresponding adjustment percentage can be set to 70%; when the consecutive data is "11110", there are four consecutive data bits "1111", and the corresponding adjustment percentage can be set to 60%. And so on, the more consecutive data bits there are, the smaller the corresponding adjustment percentage.

[0096] In one embodiment, assuming the original video stream data is "01011011110", then when disassembled, it can be divided into "01", "10", "01", "110", "01", "11110". Correspondingly, set the clock frequency corresponding to "110" to the original clock frequency * 80%, set the clock frequency corresponding to "11110" to the original clock frequency * 60%, and keep the clock frequencies corresponding to other non-consecutive data unchanged at the original clock frequency.

[0097] In the embodiments of the present application, when multiple "1"s or multiple "0"s are continuously transmitted, the differential potential is enlarged, resulting in errors in subsequent data parsing. The more consecutive data bits there are, the higher the error rate. By determining multiple different adjustment percentages based on the number of consecutive data bits, the more consecutive data bits there are, the smaller the corresponding clock frequency is set, which can allow more change time for mutant data to ensure correct transmission and can further ensure the correctness of data transmission.

[0098] It should be noted that the way of setting the adjustment percentage is only one embodiment, and it can also be that for each additional consecutive data bit, a fixed value is subtracted from the original clock frequency. The specific way of reducing the clock frequency cannot be regarded as a limitation to the present application.

[0099] In some embodiments of the present application, determining the target clock frequency according to the number of consecutive data bits in the consecutive data and the original clock frequency includes:

[0100] Determining the corresponding target adjustment percentage from a plurality of different adjustment percentages according to the number of consecutive data bits in the consecutive data;

[0101] Determining the target clock frequency based on the target adjustment percentage and the original clock frequency.

[0102] In some embodiments of the present application, determining the target clock frequency based on the target adjustment percentage and the original clock frequency includes: using the product of the target adjustment percentage and the original clock frequency as the target clock frequency.

[0103] In one embodiment, when the consecutive data is "001", it is transmitted at a transmission frequency of the original clock frequency * 80%; when the consecutive data is "0001", it is transmitted at a transmission frequency of the original clock frequency * 70%; when the consecutive data is "00001", it is transmitted at a transmission frequency of the original clock frequency * 60%, and so on.

[0104] It should be noted that the target clock frequency can also be determined by other calculation methods based on the target adjustment percentage and the original clock frequency, as long as the target clock frequency is lower than the original clock frequency, which cannot be regarded as a limitation to the present application.

[0105] In some embodiments of the present application, the original clock frequency is the highest transmission clock frequency. In the case where the original clock frequency is the highest transmission clock frequency, on the one hand, it can make the adjustable range of the target clock frequency larger, which can make the clock frequencies corresponding to consecutive data with different numbers of consecutive data bits divided more finely, and can improve the stability of data transmission. On the other hand, it can improve the overall transmission frequency, thereby increasing the bandwidth.

[0106] In addition, an embodiment of the present application further provides a control device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor. The processor and the memory can be connected through a bus or other means.

[0107] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely set relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0108] The non-transitory software program and instructions required to implement the signal processing method of the above embodiments are stored in a memory, and when executed by a processor, implement the signal processing method in the above embodiments.

[0109] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0110] In addition, an embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor or a controller, for example, executed by the above-mentioned processor, the above-mentioned processor can be caused to execute the signal processing method in the above embodiments.

[0111] Those of ordinary skill in the art can understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0112] The embodiments of the present application have been described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made without departing from the spirit of the present application within the scope of knowledge possessed by those of ordinary skill in the art.

Claims

1. A signal processing system, characterized in that: include: Image sensor for detecting raw video stream data; An encoding unit, used for obtaining the original video stream data and the corresponding original clock frequency; Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and discontinuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one discontinuous data bit, and the discontinuous data includes two different data bits; reduce the clock frequencies corresponding to at least two continuous data bits and one discontinuous data bit in the continuous data to the target clock frequency, and keep the clock frequency corresponding to the discontinuous data as the original clock frequency; package the original video stream data into target video stream data and output it, wherein the continuous data is output at the target clock frequency, and the discontinuous data is output at the original clock frequency; the target clock frequency is obtained by the following steps: determine the number of continuous data bits in the continuous data, and determine the target clock frequency according to the number of continuous data bits in the continuous data and the original clock frequency, wherein the number of continuous data bits is negatively correlated with the size of the target clock frequency; The decoding unit is used to receive the target video stream data transmitted over a long distance and decode it into the original video stream data.

2. The signal processing system according to claim 1, characterized in that The encoding unit and the decoding unit both adopt FPGA.

3. A signal processing method, characterized in that: The method comprises: Get the original video stream data and the corresponding original clock frequency; Determine the continuity state of the original video stream data, and divide the original video stream data into continuous data and non-continuous data according to the continuity state, wherein the continuous data includes at least two continuous data bits and one non-continuous data bit, and the non-continuous data includes two different data bits; The clock frequencies corresponding to at least two consecutive data bits and one non-continuous data bit in the continuous data are all reduced to the target clock frequency, and the clock frequency corresponding to the non-continuous data is kept at the original clock frequency; the target clock frequency is obtained by the following steps: determining the number of consecutive data bits in the continuous data, and determining the target clock frequency according to the number of consecutive data bits in the continuous data and the original clock frequency, wherein the number of consecutive data bits is negatively correlated with the target clock frequency; The original video stream data is packaged into target video stream data for long-distance transmission, wherein the continuous data is output at the target clock frequency and the non-continuous data is output at the original clock frequency.

4. The signal processing method according to claim 3, characterized in that: The method further comprises: Determining the number of consecutive data bits in the consecutive data; A plurality of different adjustment percentages are determined based on the number of continuous data bits in the continuous data, wherein the number of continuous data bits is negatively correlated with the size of the adjustment percentage.

5. The signal processing method according to claim 4, characterized in that: The determining the target clock frequency according to the number of continuous data bits in the continuous data and the original clock frequency comprises: Determining a corresponding target adjustment percentage from a plurality of different adjustment percentages according to the number of continuous data bits in the continuous data; The target clock frequency is determined based on the target adjustment percentage and the original clock frequency.

6. The signal processing method according to claim 5, characterized in that: The determining the target clock frequency based on the target adjustment percentage and the original clock frequency comprises: The product of the target adjustment percentage and the original clock frequency is used as the target clock frequency.

7. The signal processing method according to any one of claims 3 to 6, characterized in that: The original clock frequency is the highest transmission clock frequency.

8. A control device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the signal processing method according to any one of claims 3 to 7 is implemented.

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