Application programming interface for causing software program allocation

Abstract

The invention discloses an application programming interface for causing allocation of software programs. Apparatuses, systems, and techniques for executing APIs to indicate allocation of wireless signal processing operations are disclosed. In at least one embodiment, the distributed unit and the radio unit perform one or more operations based at least in part on the indicated allocation. In at least one embodiment, a processor comprising one or more circuitry executes an application programming interface to indicate allocation of wireless signal processing operations between one or more open radio access network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application incorporates the entire disclosure of concurrently filed U.S. Patent Application No. 18 / 220,162, entitled "APPLICATION PROGRAMMING INTERFACE TO INDICATE ALLOCATION OF OPERATIONS," for all purposes. Technical Field

[0003] At least one embodiment relates to an open radio access network (O-RAN) that distributes signal processing operations.For example, one or more APIs indicate a functional split of signal processing operations between one or more units. Background Art

[0004] Using O-RAN to process signals may include a default allocation of tasks between radio units (RUs) and distributed units (DUs). The default allocation of signal processing may be restrictive. For example, the default allocation of tasks may limit bandwidth, latency, or other network attributes that network users may wish to optimize. As another example, a network using default settings may use a significant amount of time and computing resources based on the default allocation, or may be less flexible. Therefore, the ability of the units to process signals may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram illustrating a system for allocating signal processing operations based at least in part on segmentation information, according to at least one embodiment;

[0006] Figure 2 is a block diagram illustrating an example of indicating functional partitioning to a system according to at least one embodiment;

[0007] Figure 3 is a block diagram illustrating an example of functional partitioning information indicating a variant to a system according to at least one embodiment;

[0008] Figure 4 is a block diagram illustrating an example of inline acceleration according to at least one embodiment;

[0009] Figure 5 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0010] Figure 6is a block diagram illustrating one or more APIs for communicating segmentation information according to at least one embodiment;

[0011] Figure 7 is a process flow diagram illustrating acceleration using one or more libraries based at least in part on a partitioned architecture, according to at least one embodiment;

[0012] Figure 8 is a process flow diagram illustrating acceleration using dynamic linking of blocks of a library based at least in part on a partitioned architecture, in accordance with at least one embodiment;

[0013] Figure 9 is a process flow diagram illustrating acceleration using dynamic switching of blocks of a library based at least in part on a partitioned architecture, in accordance with at least one embodiment;

[0014] Figure 10 is a process flow diagram illustrating acceleration using dynamic fusion of blocks of a library based at least in part on a partitioned architecture, in accordance with at least one embodiment;

[0015] Figure 11 An example including a processor and modules according to at least one embodiment is shown;

[0016] Figure 12 An example data center system is shown in accordance with at least one embodiment;

[0017] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0018] Figure 13B According to at least one embodiment, Figure 13A Examples of camera positions and fields of view for autonomous vehicles;

[0019] Figure 13C According to at least one embodiment Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0020] Figure 13D is a diagram illustrating a method for one or more cloud-based servers and Figure 13A A diagram of a system for communicating between autonomous vehicles;

[0021] Figure 14 is a block diagram illustrating a computer system according to at least one embodiment;

[0022] Figure 15 is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 16 A computer system according to at least one embodiment is shown;

[0024] Figure 17 A computer system according to at least one embodiment is shown;

[0025] Figure 18A A computer system according to at least one embodiment is shown;

[0026] Figure 18B A computer system according to at least one embodiment is shown;

[0027] Figure 18C A computer system according to at least one embodiment is shown;

[0028] Figure 18D A computer system according to at least one embodiment is shown;

[0029] Figure 18E and Figure 18F illustrates a shared programming model according to at least one embodiment;

[0030] Figure 19 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0031] Figure 20A and Figure 20B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0032] Figure 21A and Figure 21B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0033] Figure 22 A computer system according to at least one embodiment is shown;

[0034] Figure 23A A parallel processor according to at least one embodiment is shown;

[0035] Figure 23B shows a partition unit according to at least one embodiment;

[0036] Figure 23C illustrates a processing cluster according to at least one embodiment;

[0037] Figure 23D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0038] Figure 24 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0039] Figure 25A graphics processor according to at least one embodiment is shown;

[0040] Figure 26 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0041] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Figure 31 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Figure 32A and Figure 32B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0047] Figure 33 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0048] Figure 34 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0049] Figure 35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0050] Figure 36 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0051] Figure 37 A network for communicating data within a 5G wireless communication network is shown in accordance with at least one embodiment;

[0052] Figure 38 illustrates a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0053] Figure 39 is a diagram illustrating some basic functionality of a mobile telecommunications network / system operating according to LTE and 5G principles, according to at least one embodiment;

[0054] Figure 40 illustrates a radio access network that may be part of a 5G network architecture in accordance with at least one embodiment;

[0055] Figure 41 An example illustration of a 5G mobile communication system in which multiple different types of devices are used is provided according to at least one embodiment;

[0056] Figure 42 An example high-level system according to at least one embodiment is shown;

[0057] Figure 43 shows the architecture of a network system according to at least one embodiment;

[0058] Figure 44 illustrates example components of a device according to at least one embodiment;

[0059] Figure 45 illustrates an example interface for a baseband circuit according to at least one embodiment;

[0060] Figure 46 An example of an uplink channel according to at least one embodiment is shown;

[0061] Figure 47 shows the architecture of a network system according to at least one embodiment;

[0062] Figure 48 illustrates a control plane protocol stack according to at least one embodiment;

[0063] Figure 49 illustrates a user plane protocol stack according to at least one embodiment;

[0064] Figure 50 illustrates components of a core network according to at least one embodiment;

[0065] Figure 51 Components of a system supporting network function virtualization (NFV) according to at least one embodiment are shown; and

[0066] Figure 52 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0067] In at least one embodiment, operations in 5G signal processing are statically distributed between the RU and DU (e.g., using a "7.2" split). However, this distribution may not always be ideal. In at least some embodiments, it may be advantageous for the RU and / or DU to perform more or fewer operations.

[0068] In at least one embodiment, the systems and methods implemented according to the present disclosure are used to execute an application programming interface (API) to instruct the allocation of wireless signal processing operations between one or more open radio access network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs) and / or otherwise perform the operations described herein. In at least one embodiment, the systems and methods implemented according to the present disclosure are used to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein.

[0069] In at least one embodiment, an open radio access network (O-RAN) allocates different signal processing operations between radio units (e.g., units used for transmit / receive, the O-RU 106 in O-RAN) and distributed units (e.g., O-DUs in O-RAN, units used for computationally intensive operations such as channel estimation) according to the 7.2 split. In at least one embodiment, the "7.2 split" is a version of how different signal processing operations are allocated to the RU or DU. In at least one embodiment, in 7.2, the O-RU 106 performs receive / transmit operations (e.g., receives an analog signal, samples it, and converts the analog signal to a digital signal), while the O-DU performs more intensive operations (e.g., channel estimation, demapping, and / or descrambling). However, in at least one embodiment, there are advantages to performing operations differently than in the 7.2 split version to optimize bandwidth (e.g., performing channel estimation in the O-RU rather than in the O-DU as in 7.2).

[0070] In at least one embodiment, one or more units in the system perform operations based on a functional partition (e.g., the allocation of functionality between the RU and the DU). In at least one embodiment, one or more APIs are used to communicate the partition information to allocate functionality between the RU and the DU. In at least one embodiment, by allowing the DU and the RU to handle different functional allocations, the network can meet different standards for different clients (e.g., autonomous vehicles will have different network performance compared to standard voice services).

[0071] In at least one embodiment, a processor is used to execute an API to indicate how to allocate 5G signal processing operations between the DUs and RUs of the O-RAN. In at least one embodiment, the input to the API is an identifier of one of several ways to split the operation (e.g., a function of a 5G or 6G network). In at least one embodiment, the processor executing the API causes the DU to receive information indicating which operations the DU is to perform and which operations the RU is to perform. When the DU receives the identifier, the DU can use the identifier to look up what function the DU should perform and what operation the RU is to perform. In at least one embodiment, the DU then provides the operation allocation to each RU, and each RU can use this information to configure itself accordingly.

[0072] In at least one embodiment, a processor is configured to execute an API to provide a specific library to an accelerator (e.g., a GPU) of a DU to perform its functions based on the allocation indicated by executing the first API (described above). In at least one embodiment, the CPU of the DU executes the API. In at least one embodiment, the input to the API is an identifier of the accelerator and an identifier from the first API (described above) indicating how operations should be allocated between the DU and the RU. The DU executes the API by using the identifier to locate a software kernel to schedule it onto the identified accelerator so that the accelerator can perform the operations allocated to the DU. In at least one embodiment, the processor using or executing the API can cause the O-RU or O-DU to skip, bypass, or otherwise skip functional operations. For example, the processor using the API can cause the O-RU or O-DU to skip or bypass a demapping operation because it is being performed by another unit (e.g., not the O-DU, but the O-RU). In at least one embodiment, the processor using the API can cause certain cells (e.g., antenna groups providing 5G or 6G) to have different functional partitioning than other cells. For example, the O-RUs of one cell group may perform more operations than the O-RUs of another cell group so that bandwidth can be saved or used differently in different cells or different parts of the network.

[0073] In the preceding and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth to provide a thorough understanding of possible ways to implement the techniques. However, it will be apparent that the techniques described below can be practiced in different configurations without these specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0074] Figure 11 is a block diagram illustrating a system 100 for distributing signal processing operations based at least in part on indicated partition 102 information, according to at least one embodiment. In at least one embodiment, the system 100 uses the partition 102 information (e.g., a partition 102 architecture identifier) ​​to distribute one or more operations among one or more units. For example, the system 100 distributes the operations based on the partition 102 information identifying a functional partition for distributing the one or more operations (e.g., to adjust L1 acceleration of the system 100).

[0075] In at least one embodiment, system 100 performs communication 112 between DU 104 and RU 106, for example, using a first API that indicates split 102 information and / or otherwise performs operations described herein. In at least one embodiment, a CPU executing DU 104 receives split 102 information (e.g., from a network administrator or client), where the split 102 information indicates a split version, where each version corresponds to a different allocation of functionality between RU 106 and DU 104. In at least one embodiment, the unit (e.g., DU 104 and / or RU 106) performs the functionality corresponding to the split information, such as an indication of a split architecture. For example, input to the first API may be "split 7.3," where 7.3 is a split 102 indicating that RU 106 performs demodulation (rather than the standard 7.2 split where DU 104 performs demodulation). In at least one embodiment, when DU 104 receives the split 102 information, it can use this information to determine what functionality (e.g., demodulation) the DU 104 should perform and what functionality the RU 106 should perform, based on the version. For example, the DU 104 has a database that stores split 102 versions and corresponding functional allocations between the DU 104 and the RU 106. In at least one embodiment, after determining the split 102 information for the DU 104, the DU 104 provides the split 102 information to the RU 106, and the RU 106 can use it to configure itself accordingly. In at least one embodiment, the first API allows the O-RAN network to receive a split 102 version (including a version that is different from the standard) and then configure the network to perform according to the information indicating the functional split 102. For example, the processor includes one or more circuits that are configured to execute an application programming interface (API) to cause one or more DUs 104 to, at least in part, cause one or more functions to be performed by one or more RUs 106 based on input indicating allocation of one or more functions between one or more distributed units 104 and one or more radio units 106, and / or otherwise perform the operations described herein. For example, the input indicating the split 102 information indicating allocation of one or more functions includes an input indicating the functional split 102 (e.g., Figure 2 and / or Figure 3 The functional partitioning shown in (e.g., 202 or 302)) is described in detail.

[0076] In at least one embodiment, the system 100 performs communication 112 between the DU 104 and the RU 106, for example, by using a second API that allows an accelerator (e.g., a GPU) to use a specific library to perform its functions based at least in part on the received partition 102 information. In at least one embodiment, the CPU executing the DU 104 receives the partition 102 information and the accelerator ID (e.g., the GPU ID). In at least one embodiment, using the partition 102 information and the accelerator ID, the CPU looks up (e.g., in a database) what functions need to be performed based on the partition 102 version and what libraries the accelerator needs to use to perform these functions. In at least one embodiment, based on the one or more libraries found, the CPU can then configure the accelerator to perform the operations necessary to perform the functions for the partition 102 version. In at least one embodiment, the communication 112 includes an API that allows the DU 104 to find one or more libraries for different accelerators and then configure the accelerator to perform operations based on the one or more libraries. For example, the processor includes: one or more circuits for executing an application programming interface (API) so that the one or more processors indicate a library to be used to perform operations based at least in part on input indicating how to allocate one or more functions between one or more distributed units 104 and one or more radio units 106 and one or more instructions to one or more accelerators, and / or otherwise perform the operations described herein. In at least one embodiment, the library may include operations for performing specific 5G, 6G, or other wireless protocol operations, such as demapping, demodulation, modulation, or other signal processing operations. In at least one embodiment, the signal processing operations refer to fifth generation (5G), sixth generation (6G), or other wireless communication standards indicated by 802.11 IEEE.

[0077] In at least one embodiment, the system 100 performs communication 112 between the DU 104 and the RU 106, for example, by using a second API that allows an accelerator (e.g., a GPU) to use a specific library to perform its functions based at least in part on the received segmentation 102 information. In at least one embodiment, the accelerator includes one or more hardware accelerators, such as a GPU, an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a data processing unit (DPU), or a combination thereof. In at least one embodiment, the APIs of the present disclosure can specify an accelerator ID (e.g., an identification, a processor ID, a memory location, a bus address) such that the APIs specify the functional segmentation of operations and which accelerators will execute which portions of the functional segmentation. In at least one embodiment, the APIs of the present disclosure specify a layer or portion of a layer of the O-RAN software stack (e.g., layer 1, layer 2, layer 3, or a portion thereof) that is a portion of the DU or RU to be executed by one or more accelerators based on the functional segmentation.

[0078] In at least one embodiment, the system 100 comprises a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more communication 112 processes, such as the processes described herein. In at least one embodiment, the system 100 is a software program executed on computer hardware, an application executed on computer hardware, and / or variations thereof. In at least one embodiment, one or more processes of the system 100 are executed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU)), a data processing unit (DPU) (described below) in any suitable manner, including sequentially, in parallel, and / or variations thereof. In at least one embodiment, the system 100 implements and executes the operations described herein using a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to instruct the allocation of operations for processing wireless signals and / or to perform the operations. In at least one embodiment, as an example, training a neural network model includes using a server (e.g., an NVIDIA DGX server) that also includes at least a GPU (e.g., AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using a GAN loss).

[0079] In at least one embodiment, system 100 is comprised of modules (e.g., modules 1104-1110, see Figure 11 ) such that the system 100 executes an application programming interface (API) to instruct the allocation of wireless signal processing operations between one or more open radio access network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs). In at least one embodiment, the system 100 is composed of modules (e.g., modules 1104-1110, see Figure 11 ) is configured so that the system 100 executes an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API. For example, the system 100 includes modules for performing signal processing, such as modules 1104-1110 (see Figure 11 ). In at least one embodiment, the module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform the functions. In at least one embodiment, the module includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, the controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuits configured to perform the functions. In at least one embodiment, the software includes a software package, code, a programming language, a driver, instructions, an instruction set, or some combination thereof. In at least one embodiment, the hardware includes hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, firmware that stores instructions executed by programmable circuits, or some combination thereof.

[0080] In at least one embodiment, system 100 is comprised of a logic unit comprising firmware logic, hardware logic, or some combination thereof configured to provide any functionality as further described herein. In at least one embodiment, the logic unit comprises circuitry (e.g., an IC, SoC, CPU, GPU, DPU) that forms part of a larger system 100. In at least one embodiment, the logic unit comprises logic circuitry for implementing firmware and / or hardware to execute an API to instruct and / or cause one or more software programs.

[0081] In at least one embodiment, the system 100 is comprised of an engine comprising modules and / or logic units as further described herein. In at least one embodiment, the components comprise modules and / or logic units as further described herein. In at least one embodiment, the engine comprises software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functionality as further described herein. In at least one embodiment, the components comprise software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functionality as further described herein. In at least one embodiment, the operations performed by hardware and / or firmware may alternatively be implemented by a software module, which may be embodied as a software package, code, and / or instruction set. In at least one embodiment, the logic unit may also utilize a portion of software to implement its functionality.

[0082] In at least one embodiment, fifth generation new radio ("5G-NR") is a radio access technology for mobile networks. In at least one embodiment, 5G-NR complies with the global standard for the air interface of 5G networks, as an example. In at least one embodiment, the 5G-NR system 100, methods, and / or operations described herein may also be used to perform network operations in other networks, such as wired networks, 1st, 2nd, 3rd, 4th, 6th generation networks, and / or other further generations of networks (e.g., XG-NR).

[0083] In at least one embodiment, a network interface controller (NIC) is a hardware component that connects one or more computing systems to one or more computing networks. In at least one embodiment, the NIC receives data to be processed by a first processor or a second processor (e.g., a hardware accelerator) and sends the data processed by the first processor or the second processor to another component in the O-RAN network (e.g., a base station). In at least one embodiment, the NIC receives data to be processed via one or more functions of an acceleration abstraction layer interface and sends data to be processed via one or more functions of an acceleration abstraction layer interface. In at least one embodiment, the NIC interacts with the radio unit 106 as part of providing 5G-NR services. In at least one embodiment, the radio unit 106 is O-RAN compliant. In at least one embodiment, the radio unit 106 (RU) uses different radio frequencies. In at least one embodiment, a remote radio head (RRH) (also referred to as a remote radio unit 106 (RRU) in wireless networks) is a remote radio transceiver that is connected to an operator radio control panel via an electrical or wireless interface. In at least one embodiment, the radio unit 106 comprises an RRU. In at least one embodiment, the radio unit 106 comprises a small-cell deployment in which components of the L1 and L2 processing chains are implemented more centrally in a distributed unit 104 (DU), connected via 3GPP split 7.2-x / split 6 and / or other split variants described herein. As examples, the radio unit 106 is an ARTTHA5G RADIO UNIT, NEC's MMWAVE MASSIVE MIMO AAS, SUB6GHZ MASSIVE MIMO AAS, SUB6GHZ RU, SUB6GHZ RU, and / or other radio units 106 described herein.

[0084] In at least one embodiment, the system 100 includes a processor for distributing signal processing operations between one or more units (e.g., distributed units 104 and / or radio units 106). For example, the radio unit 106 is a unit for transmitting and / or receiving signals, such as an Open-RU 106 (O-RU) in an O-RAN. For example, the distributed unit 104 is a unit for computing one or more intensive operations (e.g., channel estimation). For example, the distributed unit 104 is an Open-DU 104 (O-DU) in an O-RAN. In at least one embodiment, the system 100 distributes one or more operations between the DU 104 and the RU 106 according to the functional partition 102, for example, to perform one or more signal processing operations.

[0085] In at least one embodiment, a unit communicates (e.g., API queries and / or responses) information to a second unit, such as an indication of the functional partition 102. For example, the distributed unit 104 communicates with the radio unit 106 via an API query to obtain the functional partition 102, such as API 510 (see Figure 5 In at least one embodiment, information indicating the functional partitioning 102 is included in a communication 112 between one or more units, such as via one or more signals including one or more data packets.

[0086] In at least one embodiment, one or more units 104 and / or 106 perform one or more operations (e.g., functions) including layer demapping (e.g., 204A and / or 304B), demodulation decoding (e.g., 204B and / or 304B), equalizer (e.g., 204C and / or 306H), equalizer weight calculation (e.g., 204D and / or 306G), demodulation reference signal (DMRS) channel estimation (e.g., 204E and / or 306E), SRS or DMRS extraction (e.g., 204F and / or 306F), and the like. 6B), beamforming weight (BFW) calculation (e.g., 208A and / or 306F), sound reference signal (SRS) or DMRS channel estimation (e.g., 208B), fast Fourier transform (FFT) and cyclic prefix (CP) removal (e.g., 206A and / or 306A), SRS extraction (e.g., 206B), PUSCH extraction (e.g., 206C and / or 306C) and / or physical uplink shared channel (PUSCH) beamforming port reduction (e.g., 206D and / or 306D) (see Figure 2 and / or Figure 3 For example, the system 100 includes a DU 104 for performing layer demapping (e.g., 204A and / or 304B), demodulation decoding (e.g., 204B and / or 304B), an equalizer (e.g., 204C and / or 306H), equalizer weight calculation (e.g., 204D and / or 306G), DMRS channel estimation (e.g., 204E and / or 306E), DMRS extraction (e.g., 204F and / or 306B), BFW calculation (e.g., 208A and / or 306F), DMRS or SRS channel estimation (e.g., 208B), FFT and CP removal (e.g., 206A and / or 306A), SRS extraction (e.g., 206B), PUSCH extraction (e.g., 206C and / or 306C), and / or PUSCH beamforming port reduction (e.g., 206D and / or 306D) (see Figure 2 and / or Figure 3For example, the system 100 includes a RU 106 for performing layer demapping (e.g., 204A and / or 304B), demodulation decoding (e.g., 204B and / or 304B), equalizer (e.g., 204C and / or 306H), equalizer weight calculation (e.g., 204D and / or 306G), DMRS channel estimation (e.g., 204E and / or 306E), DMRS extraction (e.g., 204F and / or 306B), BFW calculation (e.g., 208A and / or 306F), DMRS or SRS channel estimation (e.g., 208B), FFT and CP removal (e.g., 206A and / or 306A), SRS extraction (e.g., 206B), PUSCH extraction (e.g., 206C and / or 306C), and / or PUSCH beamforming port reduction (e.g., 206D and / or 306D) (see Figure 2 and / or Figure 3 ). In at least one embodiment, one or more distributed unit signal processing blocks 108 (if implemented) are used to perform layer demapping (e.g., 204A and / or 304B), demodulation decoding (e.g., 204B and / or 304B), equalizer (e.g., 204C and / or 306H), equalizer weight calculation (e.g., 204D and / or 306G), DMRS channel estimation (e.g., 204E and / or 306E), DMRS extraction (e.g., 204F and / or 306B), BFW calculation (e.g., 208A and / or 306F), DMRS or SRS channel estimation (e.g., 208B), FFT and CP removal (e.g., 206A and / or 306A), SRS or DMRS extraction (e.g., 206B), PUSCH extraction (e.g., 206C and / or 306C), and / or PUSCH beamforming port reduction (e.g., 206D and / or 306D) (see Figure 2 and / or Figure 3In at least one embodiment, one or more radio signal processing blocks 110, if implemented, are operable to perform layer demapping (e.g., 204A and / or 304B), demodulation decoding (e.g., 204B and / or 304B), equalizer (e.g., 204C and / or 306H), equalizer weight calculation (e.g., 204D and / or 306G), DMRS channel estimation (e.g., 204E and / or 306E), DMRS extraction (e.g., 204F and / or 306B), BFW calculation (e.g., 208A and / or 306F), DMRS or SRS channel estimation (e.g., 208B), FFT and CP removal (e.g., 206A and / or 306A), SRS extraction (e.g., 206B), PUSCH extraction (e.g., 206C and / or 306C), and / or PUSCH beamforming port reduction (e.g., 206D and / or 306D) (see Figure 2 and / or Figure 3 ).

[0087] In at least one embodiment, the communication 112 is one or more APIs, e.g., for querying (e.g., calling) and / or responding with information to indicate the functional partition 102. In at least one embodiment, the functional partition is one or more units that are assigned functions to perform based at least in part on unit-specific operations. For example, the unit-specific operations are one or more signal processing blocks 108 and / or 110. In at least one embodiment, the unit performs one or more signal processing blocks 108 and / or 110. In at least one embodiment, the one or more signal processing blocks 108 and / or 110 include one or more functions (e.g., functions 1-N), e.g., for performing operations including layer demapping (e.g., 204A and / or 304B), demodulation decoding (e.g., 204B and / or 304B), equalizer (e.g., 204C and / or 306H), equalizer weight calculation (e.g., 204D and / or 306G), DMRS channel estimation (e.g., 204E and / or 306E), DMRS extraction (e.g., 204F and / or 306B), BFW calculation (e.g., 208A and / or 306F), DMRS or SRS channel estimation (e.g., 208B), FFT and CP removal (e.g., 206A and / or 306A), SRS or DMRS extraction (e.g., 206B), PUSCH extraction (e.g., 206C and / or 306C), and / or PUSCH beamforming port reduction (e.g., 206D and / or 306D) (see Figure 2 and / or Figure 3 In at least one embodiment, the communication 112 indicates a preferred allocation of functions between the distributed unit 104 and the radio unit 106 (eg, 1-N).

[0088] In at least one embodiment, the distributed unit 104 executes one or more distributed unit 104 signal processing blocks 108. In at least one embodiment, the radio unit 106 executes (e.g., uses) one or more radio unit 106 signal processing blocks 110. As an example, executing is invoking, using, executing, and / or processing in other ways. In at least one embodiment, a processor (e.g., processor 1102) uses a signal processing block (e.g., software stored in a library) to perform one or more operations assigned to the unit using information indicating the functional partition 102. For example, the system 100 including the distributed unit 104 uses one or more distributed unit 104 signal processing blocks 108, e.g., according to Figure 2 and / or Figure 3 For example, the system 100 including the radio unit 106 uses one or more radio unit 106 signal processing blocks 110, for example, according to Figure 2 and / or Figure 3 In at least one embodiment, the system 100 uses one or more APIs 510 (see Figure 5 ) to perform communication 112, for example, using Figure 7-10 The processes further shown in (eg, 700, 800, 900, or 1000) are further accelerated.

[0089] In at least one embodiment, the O-RAN Alliance has standardized the fronthaul interface between the DU 104 and the RU 106 of the radio access network (RAN) following a 7.2-x split. In at least one embodiment, this split 102 separates the physical layer (PHY) (L1) functionality into a high PHY (e.g., residing in the DU 104) and a low PHY (e.g., residing in the RU 106). In at least one embodiment, further O-RAN has employed various approaches to accelerate the computationally intensive portion of the DU 104, the L1 high PHY, using bypass and inline acceleration. In at least one embodiment, with the dimensionality of the RAN expanding, with the emergence of massive multiple-input multiple-output (MIMO) architectures in 5G advanced use cases, the large number of antennas at the RU 106, and the resulting increased fronthaul (FH) bandwidth requirements carrying large amounts of data from the RU 106 to the DU 104, the 7.2-x split appears to be unsuitable for UL massive MIMO. In at least one embodiment, Figure 6-10 The option of incorporating the split 102 of the 7.2-x variants in O-RAN to improve UL massive MIMO performance is further described.

[0090] In at least one embodiment, if the O-RAN employs different partitions 102 for UL massive MIMO, then the centralization of DUs 104 and acceleration of L1 will need to support more than one partition 102 architecture, depending on the set of O-RUs 106 served by a single centralized DU 104 (e.g., BBU pooling) and what the capabilities of those RUs 106 are (e.g., what PHY partitions 102 they support).

[0091] In at least one embodiment, the system 100 performs dynamic adaptation of L1 processing at the DU 104 based on system dimensions (e.g., and the resulting RU 106 capabilities) using one or more of the described techniques: 1) using different L1 SW libraries for different partitions 102 and partitioning the L1 compute resources into logical partitions to run these multiple L1 SW libraries in parallel; 2) using the same software library, but dynamically selecting functional blocks from the library and linking them to form L1 pipelines based on the partitions 102, and similar to solution 1, using L1 compute resource partitioning to run the different linked pipelines in parallel using the same SW library, where the functional blocks are pre-linked, but selectively turning blocks on / off based on partition 102 requirements and reconfiguring the block interconnects accordingly (for blocks preceding and following the turned-off blocks), and then, similar to solution 1, using L1 compute resource partitioning to run the different reconfigured pipelines in parallel, and further, after reconfiguration, selectively fusing functional blocks to improve / optimize performance for the specific partition 102 architecture. In at least one embodiment, system 100 performs acceleration based at least in part on software-defined programmable L1 acceleration using an inline high PHY mode (e.g., using an L1 software library implemented at a "component" level rather than an end-to-end fixed pipeline) rather than existing fixed-function accelerators.

[0092] For example, the system 100 includes a processor that includes one or more circuits for executing an API to instruct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. For example, the system 100 includes a processor that includes one or more circuits for executing an API so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, a set of instructions is stored on a machine-readable medium that, if executed by one or more processors included in the system 100, causes the one or more processors to execute an API to instruct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. In at least one embodiment, a machine-readable medium stores a set of instructions that, if executed by one or more processors included in the system 100, cause the one or more processors to execute an API so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the system 100 performs one or more operations, such as Figure 1-11 In at least one embodiment, the system 100 uses the Figure 12-52 The described hardware and / or software in combination perform one or more operations.

[0093] Figure 2 is a block diagram illustrating an example of indicating a functional partition 202 to a system 200 according to at least one embodiment. In at least one embodiment, the system 200 includes an architecture (e.g., 7.2-x and / or 7.2-x variants) wherein the O-DU 204 and the O-RU 206 perform operations according to the functional partition 202 (e.g., 7.2-x partition and / or 7.2-x variant partition) indicated by the information. In at least one embodiment, the system 100 (see Figure 1 ) includes a system 200. In at least one embodiment, the exemplary system 200 includes a DU 104 and a RU 106, such as Figure 1 In at least one embodiment, the exemplary system 200 includes an O-DU 204 and an O-RU 206. As an example, the O-DU 204 is the DU 104 (see Figure 1 ). As an example, O-RU 206 is RU 106 (see Figure 1 In at least one embodiment, one or more O-DU 204 unit signal processing blocks 108 (see Figure 1 ) includes layer demapping 204A, demodulation decoding 204B, equalizer 204C, equalizer weight calculation 204D, demodulation reference signal (DMRS) channel estimation 204E, DMRS extraction 204F, BFW calculation 208A, channel estimation 208B (e.g., sound reference signal (SRS) or DMRS), fast Fourier transform (FFT) and cyclic prefix (CP) removal 206A, extraction 206B (DMRS or SRS), physical uplink shared channel (PUSCH) extraction 206C, and / or PUSCH beamforming port reduction 206D.

[0094] For example, the 7.2-x functional split 202 includes an O-DU 204 that performs layer demapping 204A, demodulation decoding 204B, equalizer 204C, equalizer weight calculation 204D, demodulation reference signal (DMRS) channel estimation 204E, DMRS extraction 204F, beamforming weight (BFW) calculation 208A, and channel estimation 208B (e.g., DMRS or SRS). For example, the 7.2-x functional split 202 includes an O-RU 206 that performs FFT and CP removal 206A, extraction 206B (e.g., DMRS or SRS), PUSCH extraction 206C, and beamforming port reduction 206D.

[0095] For example, the 7.2-x variant functional partitioning 202 includes an O-DU that performs layer demapping 204A, demodulation decoding 204B, equalizer 204C, equalizer weight calculation 204D, demodulation reference signal (DMRS) channel estimation 204E, and DMRS extraction 204F. For example, the 7.2-x functional partitioning 202 includes an O-RU that performs FFT and CP removal 206A, extraction 206B (e.g., DMRS or SRS), PUSCH extraction 206C, beamforming port reduction 206D, BFW calculation 208A, and channel estimation 208B (e.g., DMRS). In at least one embodiment, the partitioning information 202 indicates how the operations of one or more signal processing blocks (e.g., 204A-F, 206A-D, 208A, and B) are distributed within the architecture. For example, block 208 includes signal processing blocks 208A and B, which are allocated to O-DUs or O-RUs based at least in part on the partitioning 202 information 208A and B. In at least one embodiment, the partitioning 202 information includes information indicating allocation of one or more signal processing blocks 204A-F, 206A-D, 208A, 208B, or a combination thereof, among one or more units (e.g., RU 206 and / or DU 204).

[0096] In at least one embodiment, O-RAN has specified an O-RAN architecture that employs a 7.2-x split 202 between its two logical nodes, the O-DU 204 and the O-RU 206. In at least one embodiment, in the 7.2-x split 202, most of the PHY layer (L1) processing is done in the O-DU 204 (High PHY), while a small set of PHY functions (Low PHY) is hosted by the O-RU 206. In at least one embodiment, when the 7.2 functional split does not achieve the required uplink (e.g., when the system dimensions are significantly expanded (e.g., Massive MIMO)), one or more APIs indicating the split 202 information are used to perform Figure 1 and / or Figure 3 A variant of the functional split shown in .

[0097] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 206 receives a signal as input and performs FFT and CP removal 206A. In at least one embodiment, FFT is an algorithm that computes the discrete Fourier transform and / or its inverse. For example, the processor performs an FFT operation to convert a signal between its original domain (e.g., time or space) and a representation in the frequency domain. In at least one embodiment, performing FFT removal 206A removes one or more components using the FFT and / or its inverse. In at least one embodiment, CP removal 206A can improve spectral efficiency. In at least one embodiment, the processor (e.g., processor 1102) executing O-RU 206 performs FFT and CP removal 206A on the signal using one or more operations, generating an output signal from which the FFT and CP have been removed. In at least one embodiment, the output of FFT and CP removal 206A is received as input by extraction 206B (e.g., SRS or DMRS) and PUSCH extraction 206C.

[0098] In at least one embodiment, the processor executing the O-RU 206 (e.g., processor 1102) receives the signal from which the FFT and CP have been removed (e.g., the output of the FFT and CP removal 206A) and uses one or more operations to perform SRS extraction 206B. In at least one embodiment, the SRS is transmitted on the uplink and allows the network to estimate the channel quality at different frequencies. In at least one embodiment, the processor performs SRS extraction 206B using a wideband mode, a non-frequency hopping SRS, a frequency hopping mode, and / or a frequency hopping SRS. In at least one embodiment, the processor outputs the SRS while performing SRS extraction 206B, for example, to the processor executing the O-DU 204 to perform SRS channel estimation 208B.

[0099] In at least one embodiment, a processor executing O-DU 204 (e.g., processor 1102) receives an SRS (e.g., the output of SRS extraction 206B) and uses one or more operations to perform SRS channel estimation 208B. In at least one embodiment, the processor performs SRS channel estimation 208B by estimating the quality of a large bandwidth uplink channel outside of the assigned span. In at least one embodiment, the processor generates an output, such as an estimated SRS channel, when performing SRS channel estimation 208B. In at least one embodiment, the processor executing O-DU 204 receives the output from SRS channel estimation 208B as input to perform BFW calculation 208A.

[0100] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 206 (including executing DMRS channel estimation 208B) receives input including the output of DMRS extraction 206B. In at least one embodiment, the processor performs DMRS channel estimation 208B by estimating the channel of a demodulation reference signal. In at least one embodiment, the channel information is represented as a tensor. In at least one embodiment, DMRS channel estimation 208B is used to derive channel responses at all time-frequency locations based on the DMRS subchannel matrix, e.g., to recover the full channel matrix. In at least one embodiment, the processor generates output including the channel information represented as a tensor when executing channel estimation 208B. In at least one embodiment, the processor executing O-RU 206 receives the output from DMRS channel estimation 208B as input to perform BFW calculation 208A.

[0101] In at least one embodiment, a processor (e.g., processor 1102) executing O-DU 206 to perform BFW calculation 208A receives as input an estimated SRS channel (e.g., from SRS channel estimate 208B). In at least one embodiment, the processor performs BFW calculation 208A. In at least one embodiment, the processor generates an output when performing BFW calculation 208A, such as a data format including signal information of one or more beamforming weights. In at least one embodiment, the processor executing O-RU 206 receives as input the output from BFW calculation 208A to perform PUSCH beamforming port reduction 206D.

[0102] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 206 to perform PUSCH extraction 206C receives as input a signal from which FFT and CP have been removed (e.g., from FFT and CP removal 206A). In at least one embodiment, PUSCH is a physical uplink channel that carries user data. In at least one embodiment, PUSCH carries RRC signaling messages, uplink control information (UCI), and / or application data. In at least one embodiment, the processor executes one or more operations to perform PUSCH extraction 206C, such that the output of the one or more operations includes the extracted PUSCH. In at least one embodiment, the processor generates an output, such as a PUSCH, when executing PUSCH extraction 206C. In at least one embodiment, the processor executing O-RU 206 receives as input the output from PUSCH extraction 206C to perform PUSCH beamforming port reduction 206D.

[0103] In at least one embodiment, a processor (e.g., processor 1102) that performs one or more operations to execute the O-RU 206 for PUSCH beamforming port reduction 206D receives input including extracted PUSCH (e.g., from PUSCH extraction 206C) and / or BFW calculation 208A (e.g., output of one or more operations of performing BFW calculation 208A). In at least one embodiment, the processor generates output using one or more beamforming algorithms when performing PUSCH beamforming port reduction 206D. In at least one embodiment, the processor that executes the O-DU 204 receives output from PUSCH beamforming port reduction 206D as input to the equalizer 204C and / or performs one or more operations of performing DMRS extraction 204F.

[0104] In at least one embodiment, a processor (e.g., processor 1102) performing O-DU 204 (including performing DMRS extraction 204F) receives input including the output of PUSCH beamforming port reduction 206D. In at least one embodiment, DMRS extraction 204F includes demodulation to extract the original information of the signal from the modulated carrier. In at least one embodiment, DMRS extraction 204F utilizes a demodulator, such as by using a diode rectifier envelope detector, a product detector, and / or synchronous detection. In at least one embodiment, in DMRS extraction 204F, the carrier and message signals are separated to produce the original information transmitted. In at least one embodiment, the processor generates an output including the extracted DMRS when performing DMRS extraction 204F. In at least one embodiment, the processor performing O-DU 204 receives the output from DMRS extraction 204F into DMRS channel estimation 204E.

[0105] In at least one embodiment, a processor (e.g., processor 1102) executing O-DU 204 (including executing DMRS channel estimation 204E) receives input including the output of DMRS extraction 204F. In at least one embodiment, the processor performs DMRS channel estimation 204E by estimating the channel of the demodulation reference signal. In at least one embodiment, the channel information is represented as a tensor. In at least one embodiment, DMRS channel estimation 204E is used to derive channel responses at all time-frequency locations based on the DMRS subchannel matrix, for example, to recover the full channel matrix. In at least one embodiment, the processor generates an output when executing channel estimation 204E to include channel information represented as a tensor. In at least one embodiment, the processor executing O-DU 204 receives the output from channel estimation 204E into equalizer weight calculation 204D.

[0106] In at least one embodiment, a processor (e.g., processor 1102) that performs O-DU 204 equalizer weight calculation 204D receives an input comprising a channel information tensor (e.g., the output of DMRS channel estimate 204E). In at least one embodiment, the processor that performs pre-equalizer operations includes equalizer weight calculation 204D. For example, equalizer weight calculation 204D adjusts one or more equalizer weights, such as to achieve a minimum error between the equalized signal and the original input signal. In at least one embodiment, the processor, when performing equalizer weight calculation 204D, generates an output comprising one or more weights for the equalizer. In at least one embodiment, the processor that performs O-DU 204 receives the output from equalizer weight calculation 204D for use in demodulation decoding 204B and / or equalizer 204C.

[0107] In at least one embodiment, a processor (e.g., processor 1102) executing O-DU 204 (including executing equalizer 204C) receives inputs including the output of PUSCH beamforming port reduction 206D and / or the output of equalizer weight calculation 204D (e.g., pre-equalizer). In at least one embodiment, equalizer 204C adjusts one or more frequency bands of the audio signal. For example, equalizer 204C performs one or more filtering operations on the input. In at least one embodiment, the processor generates an output when executing equalizer 204C. In at least one embodiment, the processor executing O-DU 204 receives the output from equalizer 204C as input to layer demapping 204A.

[0108] In at least one embodiment, the processor executing the O-DU 204 (e.g., processor 1102) performs layer demapping 204A using one or more operations, and the layer demapping 204A receives the output of the equalizer 204C. For example, the demapping 204A includes a posteriori (APP) demapping, iterative demapping, demapping using Rayleigh distribution, demapping algorithm for phase shift keying (APSK) modulation, demapping using Gaussian noise, and / or demapping using a Poisson model. In at least one embodiment, Figure 44 and / or Figure 46 204A. In at least one embodiment, the processor generates an output (e.g., a tensor with signal information) when performing layer demapping 204A. In at least one embodiment, the processor executing O-DU 204 receives the output of one or more operations from layer demapping 204A as input to demodulation decoding 204B.

[0109] In at least one embodiment, a processor executing O-DU 204 (e.g., processor 1102) performs demodulation and decoding 204B using one or more operations. Demodulation and decoding 204B receives input from operations performing layer demapping 204A and / or equalizer weight calculation 204D. In at least one embodiment, demodulation and decoding 204B is used to decode the modulated signal into its original form. In at least one embodiment, demodulation converts symbols into raw bits, while decoding converts these raw bits into data bytes. In at least one embodiment, the processor generates output (e.g., data bytes) when performing demodulation and decoding 204B. In at least one embodiment, the processor receives the output of demodulation and decoding 204B.

[0110] For example, the system 200 includes a processor that includes one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. For example, the system 200 includes a processor that includes one or more circuits for executing an API so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the system 200 performs one or more operations, such as in conjunction with Figure 1-11 In at least one embodiment, the system 200 uses a combination of Figure 12-52 The described hardware and / or software performs one or more operations.

[0111] Figure 3is a block diagram illustrating an example of functional partitioning information indicating a variant to a system 300 in accordance with at least one embodiment. In at least one embodiment, the system 300 utilizes a 7.2-x variant, wherein the O-DU 304 and the O-RU 306 operate according to the functional partitioning 302 of the 7.2-x variant indicated by the information.

[0112] In at least one embodiment, system 100 (see Figure 1 ) includes a system 300. In at least one embodiment, the exemplary system 300 includes a DU 104 and a RU 106, such as Figure 1 In at least one embodiment, the exemplary system 300 includes an O-DU 304 and an O-RU 306. As an example, the O-DU 304 is the DU 104 (see Figure 1 ). As an example, O-RU 306 is RU106 (see Figure 1 In at least one embodiment, one or more O-DU 304 units signal processing blocks 108 (see Figure 1 ) includes layer demapping 304A and / or demodulation decoding 304B. For example, the functional partition 302 includes the O-DU performing layer demapping 304A and / or demodulation decoding 304B, with other operations being allocated to the O-RU 306. In at least one embodiment, one or more O-RU 306 unit signal processing blocks 110 (see Figure 1 ) includes FFT and CP removal 306A, DMRS extraction 306B, PUSCH extraction 306C, PUSCH beamforming port reduction 306D, DMRS channel estimation 306E, BFW calculation 306F, equalizer weight calculation 306G and / or equalizer 306H. In at least one embodiment, the functional partitioning 302 indicated by the partitioning information improves the performance of massive MIMO (mMIMO).

[0113] In at least one embodiment, a processor executing the O-RU 306 (e.g., processor 1102) receives a signal as input and performs an FFT and CP removal 306A. In at least one embodiment, an FFT is an algorithm that computes a discrete Fourier transform and / or its inverse. For example, the processor performs an FFT operation to convert a signal between its original domain (e.g., time or space) and a representation in the frequency domain. In at least one embodiment, performing FFT removal 306A removes one or more components using the FFT and / or its inverse. In at least one embodiment, CP removal 306A can improve spectral efficiency. In at least one embodiment, the processor executing the O-RU 306 performs an FFT and CP removal 306A on the signal using one or more operations, generating an output signal from which the FFT and CP have been removed. In at least one embodiment, the output of the FFT and CP removal 306A is received as input by the DMRS extraction 306B and PUSCH extraction 306C.

[0114] In at least one embodiment, a processor executing O-RU 306 (e.g., processor 1102) receives the signal from which the FFT and CP have been removed (e.g., the output of FFT and CP removal 306A) and performs DMRS extraction 306B using one or more operations. In at least one embodiment, DMRS extraction 306B includes demodulation, which extracts the original information of the signal from the modulated carrier. In at least one embodiment, DMRS extraction 306B uses a demodulator, such as by using a diode rectifier envelope detector, a product detector, and / or synchronous detection. In at least one embodiment, in DMRS extraction 306B, the carrier and message signals are separated to produce the original transmitted information. In at least one embodiment, the processor generates an output including the extracted DMRS when performing DMRS extraction 306B. In at least one embodiment, the processor executing O-RU 306 receives the output from DMRS extraction 306B into DMRS channel estimation 306E.

[0115] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 306 (including executing DMRS channel estimation 306E) receives input including the output of DMRS extraction 306B. In at least one embodiment, the processor performs DMRS channel estimation 306E by estimating the channel of a demodulation reference signal. In at least one embodiment, the channel information is represented as a tensor. In at least one embodiment, DMRS channel estimation 306E is used to derive channel responses at all time-frequency locations based on the DMRS subchannel matrix, for example, to recover the full channel matrix. In at least one embodiment, the processor generates output when executing channel estimation 306E to include channel information represented as a tensor. In at least one embodiment, the processor executing O-RU 306 receives the output from DMRS channel estimation 306E as input to perform BFW calculation 306F.

[0116] In at least one embodiment, a processor executing O-RU 306 (e.g., processor 1102) performs BFW calculation 306F, which receives as input an estimated DMRS channel (e.g., from DMRS channel estimate 306E). In at least one embodiment, the processor performs BFW calculation 306F. In at least one embodiment, the processor generates an output when performing BFW calculation 306F, such as a data format including signal information of one or more beamforming weights. In at least one embodiment, the processor executing O-RU 306 receives as input the output from BFW calculation 306F to perform PUSCH beamforming port reduction 306D and / or equalizer weight calculation 306G.

[0117] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 306 to perform PUSCH extraction 306C receives a signal from which FFT and CP have been removed (e.g., from FFT and CP removal 306A). In at least one embodiment, PUSCH is a physical uplink channel that carries user data. In at least one embodiment, PUSCH carries RRC signaling messages, uplink control information (UCI), and / or application data. In at least one embodiment, the processor executes one or more operations to perform PUSCH extraction 306C, such that the output of the one or more operations includes extracted PUSCH. In at least one embodiment, the processor generates an output, such as a PUSCH, when executing PUSCH extraction 306C. In at least one embodiment, the processor executing O-RU 306 receives the output from PUSCH extraction 306C as input to perform PUSCH beamforming port reduction 306D.

[0118] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 306 using one or more operations to perform PUSCH beamforming port reduction 306D receives input including extracted PUSCH (e.g., from PUSCH extraction 306C) and / or BFW calculation 306F (e.g., output of one or more operations executing BFW calculation 306F). In at least one embodiment, the processor generates output using one or more beamforming algorithms when executing PUSCH beamforming port reduction 306D. In at least one embodiment, the processor executing O-DU 304 receives output from PUSCH beamforming port reduction 306D as input to equalizer 306G.

[0119] In at least one embodiment, a processor (e.g., processor 1102) executing O-RU 306 (including executing equalizer 306H) receives input including the output of PUSCH beamforming port reduction 306D and / or the output of equalizer weight calculation 306G (e.g., pre-equalizer). In at least one embodiment, equalizer 306H adjusts one or more frequency bands of the audio signal. For example, equalizer 306H performs one or more filtering operations on the input. In at least one embodiment, the processor generates an output when executing equalizer 306H. In at least one embodiment, a processor executing O-DU 304 receives the output from equalizer 306H as input to layer demapping 304A.

[0120] In at least one embodiment, a processor executing O-DU 304 (e.g., processor 1102) performs layer demapping 304A using one or more operations, and layer demapping 304A receives the output of equalizer 306H. For example, demapping 304A includes a posteriori (APP) demapping, iterative demapping, demapping using Rayleigh distribution, demapping algorithm for phase shift keying (APSK) modulation, demapping using Gaussian noise, and / or demapping using a Poisson model. In at least one embodiment, Figure 44 and / or Figure 46 304A. In at least one embodiment, the processor generates an output (e.g., a tensor with signal information) when performing layer demapping 304A. In at least one embodiment, the processor executing O-DU 304 receives the output of one or more operations from layer demapping 304A as input to demodulation decoding 304B.

[0121] In at least one embodiment, a processor executing O-DU 304 (e.g., processor 1102) performs demodulation and decoding 304B using one or more operations. Demodulation and decoding 304B receives input from operations performing layer demapping 304A and / or equalizer weight calculation 306G. In at least one embodiment, demodulation and decoding 304B is used to decode the modulated signal into its original form. In at least one embodiment, demodulation converts symbols into raw bits, while decoding converts these raw bits into data bytes. In at least one embodiment, the processor generates output (e.g., data bytes) when performing demodulation and decoding 304B. In at least one embodiment, the processor receives the output of demodulation and decoding 304B.

[0122] For example, the system 300 includes a processor that includes one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. For example, the system 300 includes a processor that includes one or more circuits for executing an API so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the system 300 performs one or more operations, such as in conjunction with Figure 1-11 In at least one embodiment, the system 300 uses a combination of Figure 12-52 The described hardware and / or software performs one or more operations.

[0123] Figure 4 is a block diagram illustrating an example 400 of inline acceleration according to at least one embodiment. In at least one embodiment, the system 100 (see Figure 1 ) includes a system 400. In at least one embodiment, the exemplary system 400 includes Figure 1 DU 104 and RU 106 are shown in FIG. In at least one embodiment, exemplary system 400 includes O-DU 402 and O-RU 414. As an example, O-DU 402 is DU 104 (see FIG. Figure 1 ). As an example, O-RU 414 is RU 106 (see Figure 1 In at least one embodiment, one or more O-DU 402 unit signal processing blocks 108 (see Figure 1 ) includes one or more functions 410A-410D. For example, the functional partition 302 (see Figure 3) includes the O-DU performing layer demapping 304A and / or demodulation decoding 304B as function 1 410A and function 2 410B, with other operations being assigned to the O-RU 414. In at least one embodiment, the functional split 202 (see Figure 2 ) includes an O-DU 402 performing layer demapping 204A, demodulation decoding 204B, equalizer 204C, equalizer weight calculation 204D, DMRS channel estimation 204E and / or DMRS extraction 204F, with other operations being assigned to the O-RU 414. In at least one embodiment, one or more O-RU 414 unit signal processing blocks 110 (see Figure 1 ) includes performing one or more operations (e.g., 102, 202, and / or 302) according to the functional partition. In at least one embodiment, the functional partition is indicated by functional partition information 416. In at least one embodiment, using the partition information 416 and the accelerator ID, the CPU 404 looks up (e.g., in a database) the accelerator ID according to the partition 102 (see Figure 1 ) version needs to perform what functions (e.g., 410A-D) and what libraries the accelerator needs to use to perform these functions (e.g., 410A-D). In at least one embodiment, based on the one or more libraries found, the CPU 404 can then configure the accelerator to perform the partition 102 indicated by the partition information 416 (see Figure 1 ) version of the functionality (e.g., 410A-D).

[0124] In at least one embodiment, the system 400 utilizes one or more processors (e.g., GPU 410 and / or CPU 404) to improve L1 performance using inline acceleration. In at least one embodiment, the O-DU 402 L1-High PHY can be hardware accelerated (HWA) in inline mode, for example, when an FH partition (e.g., 7.2-x) is located between the accelerator component of the O-DU 402 and the O-RU 414. For example, the O-RAN (e.g., AAL) standardizes the interface between the O-DU L2+ 406 and the O-DU 402 L1, and also standardizes the interface between the O-DU 402 L1 and the O-RU 414 (e.g., open FH-7.2-x). In at least one embodiment, to improve UL performance based at least in part on the functional partition (e.g., 102, 202, and / or 302), one or more functions (e.g., L2+ 406, functions 1-n 410A-D) can be optimized based on the partition. In at least one embodiment, the hardware accelerator is a GPU, GPGPU, PPU, CPU, SoC, and / or DPU. In at least one embodiment, the hardware accelerator uses an interface, such as the interfaces non-exclusively shown in Figures 13-18 and / or the interfaces described otherwise herein.

[0125] In at least one embodiment, the Acceleration Abstraction Layer (AAL) 408 is an interface. In at least one embodiment, the Fronthaul (FH) 7.2 412 is an O-RAN WG4 open fronthaul interface. In at least one embodiment, L1 (e.g., 410A-410B) represents functional units, such as those performed in real time by a DU. In at least one embodiment, L2+ 406 represents scheduling functions and / or non-real time functions performed by a centralized unit (CU) (e.g., CPU 404). In at least one embodiment, the CPU is as further described herein, such as in Figure 12-52 In at least one embodiment, the O-DU 402 L1 needs to process different sets of functions based at least in part on which O-RU is providing service, and if two O-RUs 414 are providing service simultaneously using the techniques described herein, different sets of functions are processed simultaneously. In at least one embodiment, the O-DU 402 dynamically adjusts its L1 processing pipeline (e.g., for LTE and / or NR) to serve dynamically configurable units.

[0126] In at least one embodiment, example 400 includes accelerating one or more operations based at least in part on a processor comprising one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein. In at least one embodiment, example 400 includes accelerating one or more operations based at least in part on a processor comprising one or more circuits for executing an API to cause one or more software programs indicated by the API to be allocated to one or more 5G DUs indicated by the API and / or otherwise performing the operations described herein. In at least one embodiment, example 400 illustrates performing one or more functions (e.g., in conjunction with Figure 1-11 In at least one embodiment, the example 400 for accelerating and / or otherwise performing the operations described herein includes combining Figure 12-52 The hardware and / or software described.

[0127] Figure 5 5 is a block diagram 500 illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, the software program 502 is a software module. In at least one embodiment, the software program 502 includes one or more software modules. In at least one embodiment, the software modules such as Figure 510. In at least one embodiment, one or more APIs 510 are software instruction sets that, if executed, cause one or more processors (e.g., processor 1102) to perform one or more computing operations. In at least one embodiment, one or more APIs 510 are distributed or otherwise provided as part of one or more libraries 506, runtimes 504, drivers 504, and / or any other software and / or executable code groupings described further herein. In at least one embodiment, one or more APIs 510 perform one or more computing operations in response to a call by a software program 502. In at least one embodiment, a software program 502 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets, such as APIs 510 or API functions 512, to be executed. In at least one embodiment, the functionality provided by one or more APIs 510 includes software functions 512, such as software functions that can be used to accelerate one or more portions of the software program 502 using one or more parallel processing units (PPUs) (e.g., a graphics processing unit (GPU)).

[0128] In at least one embodiment, the API 510 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 510 described herein are implemented to perform the following operations in conjunction with Figure 1-11 In at least one embodiment, one or more software programs 502 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the following operations in conjunction with Figure 1-11 One or more techniques further described.

[0129] In at least one embodiment, a software program 502 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 510 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, the one or more APIs 510 provide a set of callable functions 512, referred to herein as APIs, API functions, and / or functions, that each perform one or more computational operations, such as computational operations related to parallel computing. For example, in one embodiment, the one or more APIs 510 provide functions 512 to use 516 partitioning information, for example, to select a library and / or a block within a library that is specific to a partitioning architecture.

[0130] In at least one embodiment, one or more software programs 502 interact with or otherwise communicate with one or more APIs 510 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations that are accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 502 interact with one or more APIs 510 to perform audio-to-text processing.

[0131] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 512 provided by the one or more APIs 510. In at least one embodiment, the software programs 502 use the native interface when a software developer compiles the one or more software programs 502 in conjunction with one or more libraries 506 that include or otherwise provide access to the one or more APIs 510. In at least one embodiment, the one or more software programs 502 are statically compiled with precompiled libraries 506 or uncompiled source code that include instructions for executing the one or more APIs 510. In at least one embodiment, the one or more software programs 502 are dynamically compiled and linked to the one or more precompiled libraries 506 that include the one or more APIs 510 using a linker.

[0132] In at least one embodiment, when a software developer executes a software program, the software program 502 uses a remote interface that utilizes or otherwise communicates with a library 506 containing one or more APIs 510 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 506 containing one or more APIs 510 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 506 containing one or more APIs 510 are executed by any other computing host that provides the one or more APIs 510 to the one or more software programs 502.

[0133] In at least one embodiment, a processor (e.g., processor 1102) executing or using one or more software programs 502 calls, uses, executes, or otherwise implements one or more APIs 510 to allocate and otherwise manage memory 514 to be used by the software programs 502. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 to allocate and otherwise manage memory 514 to be used by one or more portions of the software programs 502 that are to be accelerated using one or more PPUs (e.g., GPUs) or any other accelerators or processors further described herein. These software programs 502 request that a neural network perform signal processing using functions 512 provided, in one embodiment, by the one or more APIs 510.

[0134] In at least one embodiment, API 510 is an API for facilitating parallel computing. In at least one embodiment, API 510 is any other API described further herein. In at least one embodiment, API 510 is provided by a driver and / or runtime 504. In at least one embodiment, API 510 is provided by a CUDA user-mode driver. In at least one embodiment, API 510 is provided by a CUDA runtime. In at least one embodiment, driver 504 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 512 of API 510 during the loading and execution of one or more portions of software program 502. In at least one embodiment, runtime 504 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 512 of API 510 during the execution of software program 502. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 implemented or otherwise provided by a driver and / or runtime 504 to perform combined arithmetic operations by the one or more software programs 502 during execution by one or more PPUs (e.g., GPUs).

[0135] In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by a driver and / or runtime 504 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 510 provide combined arithmetic operations through the driver and / or runtime 504, as described above. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by the driver and / or runtime 504 to allocate or otherwise reserve one or more blocks of memory 514 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by the driver and / or runtime 504 to allocate or otherwise reserve blocks of memory 514. In at least one embodiment, the one or more APIs 510 call a neural network to perform the function of selecting one or more banks using 516 segmentation information, as described below in conjunction with Figure 1-11 Any one of the above.

[0136] To improve the usability of the software program 502 and / or to improve the optimization of one or more portions of the software program 502 to be accelerated by one or more PPUs (e.g., GPUs), in one embodiment, the one or more APIs 510 provide one or more API functions 512 for using 516 the partitioning information, as described above and in conjunction with the following. Figure 1-11 Further description. In at least one embodiment, the exemplary block diagram 500 depicts a processor (e.g., processor 1102) comprising one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the exemplary block diagram 500 depicts a system comprising one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor (e.g., processor 1102) uses the API to indicate segmentation information, uses functions to use the segmentation information, and / or otherwise performs the operations described herein. In at least one embodiment, the exemplary block diagram 500 shows an API for using 516 segmentation information when processing one or more signals. In at least one embodiment, the processor uses the exemplary API and uses one or more functions 512, wherein the functions are using 516 segmentation information, for example, to indicate a segmentation preference of the processor. For example, the processor uses the API 510 to perform Figure 6-11 One or more operations shown in .

[0137] As an example, block diagram 500 illustrates a processor including one or more circuits for executing API 510 to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein. In at least one embodiment, block diagram 500 illustrates a processor including one or more circuits for executing API 510 to cause one or more software programs indicated by API 510 to be allocated to one or more 5GDUs indicated by API 510 and / or otherwise performing the operations described herein. In at least one embodiment, block diagram 500 illustrates a processor executing one or more functions 512, for example, in conjunction with Figure 1-11 In at least one embodiment, block diagram 500 illustrates an API 510, such as one that is combined with Figure 12-52 Describes the API implemented by the hardware.

[0138] Figure 6 6 is a block diagram 600 illustrating one or more APIs for communicating segmentation information in accordance with at least one embodiment. In at least one embodiment, L1 606 (e.g., 510A-510B) represents functional units executed in real time, such as those executed by O-DU 602. In at least one embodiment, L2+ 604 represents scheduling functions and / or non-real time functions executed by O-DU 602.

[0139] In at least one embodiment, system 100 (see Figure 1 ) includes a system 600. In at least one embodiment, the exemplary system 600 includes Figure 1 DU 104 and RU 106 are shown in FIG. In at least one embodiment, exemplary system 600 includes O-DU 602 and O-RU 608. As an example, O-DU 602 is DU 104 (see FIG. Figure 1 ). As an example, O-RU 608 is RU106 (see Figure 1 In at least one embodiment, O-RU1 608 is a 7.2-x architecture radio unit. In at least one embodiment, O-RU 2 610 is a 7.2-x variant architecture radio unit. In at least one embodiment, one or more O-DU 602 units signal processing block 108 (see Figure 1 )include Figure 1 For example, the O-DU uses one or more APIs 510 (see Figure 5) to perform an O-RU 1 608 capability query (e.g., for a 7.2-x split) or an O-RU 2 610 capability query (e.g., for a 7.2-x split variant) to calculate resources of an L1 implementation 606 (e.g., an implementation of a library and / or driver), calculate resources of an L1 implementation 606 of a 7.2-x variant, a cell configuration of a 7.2x and / or variant with an L1 implementation 606, and / or trigger an uplink (UL) of a 7.2-x and / or variant. In at least one embodiment, the L2+ 604 application of the O-DU 602 receives the communication 112 (see Figure 1 ) and responds, for example, using an API response to an O-RU 1 capability query of 7.2-x and / or 7.2-x variants, a compute resource response of 7.2-x and / or 7.2-x variants, a cell configuration response of 7.2-x and / or 7.2-x variants, a returned L1 output of 7.2-x and / or 7.2-x variants. In at least one embodiment, the L1 implementation (e.g., library and / or driver) sends the C-Plane to O-RU 1 608 and / or sends the U-Plane to send the C-Plane query (e.g., using an O-RU 1 UL receive). In at least one embodiment, the L1 606 implementation (e.g., driver and / or library) receives the communication 112 (see Figure 1 ) and respond, for example, using the API to respond to a 7.2-x split O-RU capability query, respond to split version computing resources, respond to cell configuration, and / or return L1 output. In at least one embodiment, O-RU 1 608 receives the API communication 112 (see Figure 1 ), and then responds using the API, such as a response to an O-RU 1 608 capability query, a response to a U-plane, and / or an O-RU 1 UL reception 608. In at least one embodiment, the O-RU 2 610 of the 7.2-x variant receives the API's communication 112 (see Figure 1 ), and respond to O-RU 2 610 capability queries (e.g., using an API), send U-plane in response to a request to send C-plane, and / or perform O-RU 2 UL reception. In at least one embodiment, the system 600 including the O-DU 602 and the O-RUs 608 and 610 uses one or more of the processes described herein, e.g. Figure 7-11 The process shown in .

[0140] In at least one embodiment, the system 600 performs software-defined L1 processing using different software libraries. For example, an O-DU 602 serves an O-RU (e.g., 608 and / or 610), where the O-RU supports a 7.2 split architecture and a second O-RU supports a 7.2-x variant of the split architecture. In at least one embodiment, the O-DU L1 606 is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU) where different software libraries implement different split architectures, such as different sets of signal processing blocks based at least in part on physical splits. In at least one embodiment, the L2+ 604 application, upon discovering the capabilities of the O-RU 608 and / or 610, assigns dedicated L1 compute resources based on the split architecture and configures one or more cells supported by the O-RU 608 and / or 610. In at least one embodiment, internally, in response, the L1 instantiates execution instances of different software libraries dedicated to processing the L1 pipelines of the different splits. In at least one embodiment, L2+ 604 triggers uplink (UL) processing to L1, which sends the corresponding C-plane to the O-RU for UL reception and uses appropriate software libraries and dedicated computing resources to process the U-plane received from multiple O-RUs with different split architectures and returns the output of the L1 UL processing to the L2+ application. In at least one embodiment, discovering the capabilities of the O-RU 608 and / or 610 and configuring one or more cells supported by the O-RU can be combined into one step (e.g., a function call) or as separate API calls.

[0141] In at least one embodiment, the system 600 performs dynamic chaining of L1 functional blocks. For example, an O-DU 602 is serving an O-RU (e.g., 608 and / or 610), where the O-RU supports a 7.2 split architecture and a second O-RU supports a split architecture 7.2-x variant. In at least one embodiment, the O-DU L1 606 is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU), where different software libraries implement different split architectures based at least in part on physical splits, such as different sets of signal processing blocks. In at least one embodiment, the L2+ 604 application, upon discovering the capabilities of the O-RU 608 and / or 610, assigns dedicated L1 compute resources and configures one or more cells supported by the O-RU 608 and / or 610, where the L2+ application configures the one or more cells supported by the O-RU based on the split architecture. For example, internally, L1 606 has a pool of different functional block implementations (e.g., in the same software library) that can be individually selected and then linked together in sequence to create an L1 processing pipeline. In at least one embodiment, L1 606 selects a set of functional blocks and / or components from the pool (e.g., based on functional partitioning) and links these components to create a high PHY processing pipeline. In at least one embodiment, Figure 7 Unlike the different software libraries in the previous examples shown in , L1 606 uses a different set of chained components to handle the uplink U-plane corresponding to the different architectures.

[0142] In at least one embodiment, the system 600 performs dynamic switching (e.g., turning on or off) of L1 functional blocks. For example, an O-DU 602 is serving an O-RU (e.g., 608 and / or 610), where the O-RU supports a 7.2 split architecture and a second O-RU supports a 7.2-x variant of the split architecture. In at least one embodiment, the O-DU L1 606 is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU), where different software libraries implement different split architectures based at least in part on physical splits, such as different sets of signal processing blocks. In at least one embodiment, the L2+ 604 application, upon discovering the capabilities of the O-RU 608 and / or 610, assigns dedicated L1 compute resources and configures one or more cells supported by the O-RU 608, and / or the L2+ 604 application configures one or more cells supported by the O-RU 608 and / or 610 based on the architecture. For example, internally, L1 606 has a pre-linked L1 pipeline (e.g., with the same software library), with a set of functional blocks that can be selectively switched (e.g., turned on or off). In at least one embodiment, when a block is turned off, the interconnections of the blocks before and after it are reconfigured. In at least one embodiment, L1 606 selects a set of functional blocks (e.g., components) based on functional partitioning and reconfigures the L1 pipeline chain. In at least one embodiment, as an alternative to different software libraries (e.g., such as Figure 7 ), L1 606 uses different L1 reconfigured pipelines (eg, with different blocks turned on or off) to process the uplink U-plane corresponding to the split architecture.

[0143] In at least one embodiment, system 600 performs dynamic fusion of L1 functional blocks. For example, O-DU 602 is serving an O-RU (e.g., 608 and / or 610), where the O-RU supports a 7.2 split architecture and a second O-RU supports a 7.2-x variant of the split architecture. In at least one embodiment, O-DU L1 606 is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU), where different software libraries implement different split architectures based at least in part on physical splits, such as different sets of signal processing blocks. In at least one embodiment, an L2+ 604 application, upon discovering the capabilities of O-RU 608 and / or 610, assigns dedicated L1 compute resources and configures cells supported by O-RU 608. The L2+ 604 application configures one or more cells supported by O-RU 608 and / or 610 based on the architecture, and a processor (e.g., processor 1102) performs selective fusion of enabled functional blocks to further optimize performance (e.g., customizable to the split architecture). In at least one embodiment, as an alternative to different software libraries (e.g., Figure 7), L1 606 uses a different L1 reconfiguration pipeline, in which turned-on blocks are selectively merged and the uplink U-plane corresponding to the split architecture is processed.

[0144] As an example, block diagram 600 illustrates a processor including one or more circuits for executing API 510 (see Figure 5 ) to indicate the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. In at least one embodiment, block diagram 600 illustrates a processor including one or more circuits for executing API 510 (see Figure 5 ) so that by API 510 (see Figure 5 ) is assigned to one or more software programs indicated by API 510 (see Figure 5 ) and / or otherwise perform the operations described herein. In at least one embodiment, block diagram 600 illustrates a processor that executes one or more processes, such as in conjunction with Figure 1-11 In at least one embodiment, block diagram 600 illustrates distributing one or more operations and / or otherwise performing the operations described herein, such as by combining Figure 12-52 Describes the operations performed by the hardware.

[0145] Figure 7 7 is a flow chart illustrating a process 700 for accelerating using one or more libraries based at least in part on a partitioned architecture, according to at least one embodiment. In at least one embodiment, process 700 begins 702 when invoked by one or more processors, such as in response to an API. In at least one embodiment, a system (e.g., 100, 200, 300, 400, 500, and / or 600) utilizing process 700 performs software-defined L1 processing utilizing different software libraries.

[0146] In at least one embodiment, part or all of process 700 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions that are executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 700 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 700 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (eg, hardware, software, or a combination of hardware and software) performs process 700 .

[0147] For example, in process 700, the O-DU is serving the O-RU (e.g., 608 and / or 610, see Figure 6 ), wherein one O-RU supports a 7.2 split architecture and a second O-RU supports a 7.2-x variant of the split architecture. In at least one embodiment, process 700 includes one or more steps of configuring 704 a cell for functional split (e.g., 7.2-x and / or a 7.2-x variant), selecting 706 an L1 software library from a library pool, performing processing according to the functional split using 708 the library, and / or sending a success or failure response. In at least one embodiment, a processor uses 708 the library according to the functional split (e.g., indicated by functional split information), for example, the processor instantiates the library.

[0148] In at least one embodiment, once the processor executing process 700 uses the library 708, the process proceeds to decision block 710. In at least one embodiment, if the process is successful (e.g., the processing is performed according to the functional partition using the library 708), the decision in decision block 710 is "yes." In at least one embodiment, otherwise, the decision in decision block 710 is "no." In at least one embodiment, if the answer is "yes" in decision block 710, the process proceeds to end 712. In at least one embodiment, if the answer is "no" in decision block 710, the process re-attempts process 700 by continuing to step 704 and / or ends 712 with a failure indication.

[0149] In at least one embodiment, the O-DU L1 606 is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU) in which different software libraries implement different partitioning architectures, such as different sets of signal processing blocks, based at least in part on the physical partitioning. In at least one embodiment, the L2+ 604 application, upon discovering the capabilities of the O-RU, selects 706 dedicated L1 compute resources based on the partitioning architecture and configures 704 one or more cells supported by the O-RU. In at least one embodiment, internally, in response, the L1 instantiates (e.g., using 708 libraries) execution instances of different software libraries dedicated to processing the L1 pipelines for the different partitions. In at least one embodiment, the L2+ triggers uplink (UL) processing to the L1, which sends the corresponding C-plane to the O-RU for UL reception, uses appropriate software libraries and dedicated compute resources to process the U-planes received from multiple O-RUs with different partitioning architectures, and returns the output of the L1 UL processing to the L2+ application. In at least one embodiment, discovering the capabilities and configuration of the O-RU supported by the O-RU (e.g., configuring one or more cells for functional segmentation in 704) can be combined into one step (e.g., a function call) or a separate API call. In at least one embodiment, the software continues normal operation after sending a success or failure response and / or then ends 712.

[0150] As an example, process 700 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein. As an example, process 700 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 such that one or more software programs indicated by API 510 are allocated to one or more 5G DUs indicated by API 510 and / or otherwise performing the operations described herein. In at least one embodiment, the processor performs process 700 and / or the operations described herein, for example, in conjunction with Figure 1-11 In at least one embodiment, hardware performs process 700 and / or the operations described herein, for example in conjunction with Figure 12-52 Describe the hardware.

[0151] Figure 8800 is a flow chart illustrating a process 800 for accelerating dynamic linking of blocks of a library based at least in part on a partitioned architecture, according to at least one embodiment. In at least one embodiment, a system (e.g., 100, 200, 300, 400, 500, and / or 600) using process 800 performs dynamic linking of L1 function blocks.

[0152] In at least one embodiment, part or all of process 800 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions that are executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 800 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 800 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (eg, hardware, software, or a combination of hardware and software) performs process 800 .

[0153] In at least one embodiment, process 800 begins 802 when called by one or more processors (e.g., processor 1102), such as in response to an API 510 (see Figure 5 In at least one embodiment, a system using process 800 performs dynamic linking of L1 functional blocks. In at least one embodiment, process 800 includes one or more steps for configuring 804 a cell for functional partitioning (e.g., 7.2-x and / or 7.2-x variants), selecting 806 an L1 software library from a library pool, linking 808 one or more blocks, and / or sending a success or failure response.

[0154] In at least one embodiment, once the processor executing process 800 links 808 one or more blocks, the process proceeds to decision block 810. In at least one embodiment, if the process is successful (e.g., one or more blocks are linked 808 according to the partitioning information), the decision in decision block 810 is "yes." In at least one embodiment, otherwise, the decision in decision block 810 is "no." In at least one embodiment, if the decision is "yes," the process proceeds to end 812. In at least one embodiment, if the decision in decision block 810 is "no," the process retries process 800 by continuing to step 804 and / or ends with a failure indication 812.

[0155] For example, O-DU 602 is serving an O-RU (e.g., 608 and / or 610, see Figure 6 ), where the first O-RU supports the 7.2 split architecture and the second O-RU supports the split architecture 7.2-x variant. In at least one embodiment, the O-DU L1 606 (see Figure 6 ) is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU) in which different software libraries implement different partitioning architectures based at least in part on physical partitioning, such as different sets of signal processing blocks. In at least one embodiment, the L2+ application, upon discovering the capabilities of the O-RU, assigns dedicated L1 compute resources and configures 804 one or more cells supported by the O-RU, wherein the L2+ application configures 804 the one or more cells supported by the O-RU based on the partitioning architecture. For example, internally, the L1 has a pool of different functional block implementations (e.g., in the same software library) that can be picked separately and then linked 808 in sequence to create the L1 processing pipeline. In at least one embodiment, the L1 selects 806 a set of functional blocks and / or components from the pool (e.g., based on functional partitioning) and links 808 these components to create a high PHY processing pipeline. In at least one embodiment, the L1 uses a different set of linked 808 components to process the uplink U-plane corresponding to the different architectures, rather than as Figure 7 In at least one embodiment, the software continues normal operation and / or then ends 812 when a response of success or failure is sent.

[0156] As an example, process 800 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 (see Figure 5) to indicate the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. As an example, process 800 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 (see Figure 5 ) so that by API 510 (see Figure 5 ) is assigned to one or more software programs indicated by API 510 (see Figure 5 ) and / or otherwise perform the operations described herein. In at least one embodiment, the processor performs process 800 and / or the operations described herein, for example in conjunction with Figure 1-11 In at least one embodiment, hardware performs process 800 and / or the operations described herein, for example in conjunction with Figure 12-52 The hardware described.

[0157] Figure 9 9 is a flow chart illustrating a process 900 for accelerating L1 functional blocks using dynamic switching of libraries based at least in part on a partitioned architecture, according to at least one embodiment. In at least one embodiment, a system (e.g., 100, 200, 300, 400, 500, and / or 600) using process 900 performs dynamic switching (e.g., turning on or off) of L1 functional blocks.

[0158] In at least one embodiment, part or all of process 900 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 900 are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 900 is performed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (eg, hardware, software, or a combination of hardware and software) performs process 900 .

[0159] In at least one embodiment, process 900 begins 902 when called by one or more processors (e.g., processor 1102), such as in response to an API 510 (see Figure 5 In at least one embodiment, the system performing process 900 performs dynamic switching (e.g., turning on or off) of L1 functional blocks. In at least one embodiment, the system performs process 900, which includes one or more steps for configuring 904 cells for functional partitioning, selecting 906 one or more L1 blocks, using 908 an L1 pipeline with selective turn-on or turn-off options, reconfiguring 910 the interconnect, and / or sending a response of success or failure (e.g., to one or more processors).

[0160] In at least one embodiment, once the processor executing process 900 reconfigures 910 the interconnect, the process 900 proceeds to decision block 912. In at least one embodiment, if the process is successful (e.g., the interconnect is reconfigured 910 based at least in part on the partitioning information), the decision in decision block 912 is "yes." In at least one embodiment, otherwise, the decision in decision block 912 is "no." In at least one embodiment, if the answer is "yes" in decision block 912, the process proceeds to end 914. In at least one embodiment, if the answer is "no" in decision block 912, the process retries process 900 by proceeding to step 904 and / or ends 914 with a failure indication.

[0161] For example, an O-DU 602 is serving an O-RU (e.g., 608 and / or 610), where the O-RU supports a 7.2 split architecture and a second O-RU supports a 7.2-x variant of the split architecture. In at least one embodiment, the O-DU L1 is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU) where different software libraries implement different split architectures based at least in part on physical partitioning, such as different sets of signal processing blocks. In at least one embodiment, the L2+ 604 application, upon discovering the capabilities of the O-RU and / or, selects 906 dedicated L1 compute resources and configures 904 one or more cells supported by the O-RU and / or the L2+ application configuration supported by the O-RU based on the architecture configuration (e.g., configuring 904 one or more cells based on functional partitioning). For example, internally, the L1 has a pre-linked L1 pipeline (e.g., using the same software library), where the processor uses 908 the pipeline with a set of functional blocks that can be selectively switched (e.g., turned on or off). In at least one embodiment, when a block is shut down, the interconnections of the blocks preceding and following it are reconfigured 910. In at least one embodiment, the L1 selects 906 a group of functional blocks (e.g., components), for example, based on functional partitioning, and reconfigures 910 the L1 pipeline chain. In at least one embodiment, as an alternative to different software libraries (e.g., Figure 7 ), the L1 uses different L1 reconfiguration 910 pipelines (e.g., turning different blocks on or off) to process the uplink U-plane corresponding to the split architecture. In at least one embodiment, the software continues normal operation and / or then ends 914 when sending a success or failure response.

[0162] As an example, process 900 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 (see Figure 5 ) to indicate the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. As an example, process 900 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 (see Figure 5 ) so that by API 510 (see Figure 5 ) is assigned to one or more software programs indicated by API 510 (see Figure 5 ) and / or otherwise perform the operations described herein. In at least one embodiment, the processor performs process 900 and / or the operations described herein, for example in conjunction with Figure 1-11In at least one embodiment, hardware performs process 900 and / or the operations described herein, for example in conjunction with Figure 12-52 Describe the hardware.

[0163] Figure 10 1 is a flow chart illustrating a process 1000 for accelerating L1 functional blocks using dynamic fusion of library blocks based at least in part on a partitioned architecture, according to at least one embodiment. In at least one embodiment, a system (e.g., 100, 200, 300, 400, 500, and / or 600) using process 1000 performs dynamic fusion of L1 functional blocks (e.g., dynamic fusion of enabled blocks).

[0164] In at least one embodiment, part or all of process 1000 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform process 1000 are not stored solely using transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 1000 is executed at least in part on a computer system (e.g., a computer system described elsewhere in this disclosure). In at least one embodiment, logic (eg, hardware, software, or a combination of hardware and software) performs process 1000 .

[0165] In at least one embodiment, process 1000 begins 1002 when called by one or more processors (e.g., processor 1102), such as in response to an API 510 (see Figure 5 In at least one embodiment, a system using process 1000 performs dynamic fusion of L1 functional blocks. In at least one embodiment, the system performs process 1000, which includes one or more steps of configuring 1004 one or more cells for functional partitioning, selecting 1006 one or more L1 blocks, using 1008 an L1 pipeline with selective on or off options, reconfiguring 1010 the interconnect, selecting 1012 blocks to combine (e.g., selective fusion), and / or sending a success or failure response.

[0166] In at least one embodiment, once the processor executing process 1000 selects 1012 blocks to combine, process 1000 proceeds to decision block 1014. In at least one embodiment, if the process is successful (e.g., blocks to combine are selected 1012 based at least in part on the segmentation information), the decision in decision block 1014 is "yes." In at least one embodiment, otherwise, the decision in decision block 1014 is "no." In at least one embodiment, if the answer is "yes" in decision block 1014, the process proceeds to end 1016. In at least one embodiment, if the answer is "no" in decision block 1014, the process retries process 1000 by proceeding to step 1004 and / or ends with a failure indication 1016.

[0167] For example, O-DU 602 is serving an O-RU (e.g., 608 and / or 610), where the O-RU supports the 7.2 split architecture, while a second O-RU supports the split architecture 7.2-x variant. In at least one embodiment, O-DU L1 (e.g., 606, see Figure 6 ) is an inline acceleration solution (e.g., a software-defined programmable HWA such as a GPU) in which different software libraries implement different partitioning architectures based at least in part on physical partitioning, such as selecting 1006 different sets of signal processing blocks. In at least one embodiment, the L2+ 604 application discovers the O-RU (e.g., 608 and / or 610, see Figure 6 ), dedicated L1 computing resources are assigned and one or more cells supported by the O-RU 608 are configured 1004, the L2+ 604 application performs configurations supported by the O-RU 608 and / or 610 according to the architecture (to configure 1004 one or more cells according to the functional partitioning), and the processor (e.g., processor 1102) selects 1012 blocks to be combined from among the turned-on functional blocks to further optimize performance (e.g., customizable to the partitioned architecture). In at least one embodiment, as an alternative to different software libraries (e.g., such as Figure 7 ), L1 606 uses 1008 a different L1 reconfiguration 1010 pipeline (where the selected 1012 block is turned on) and processes the uplink U-plane corresponding to the split architecture. In at least one embodiment, the software continues normal operation and / or then ends 1016 when sending a success or failure response.

[0168] As an example, process 1000 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 (see Figure 5) to indicate the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise perform the operations described herein. As an example, process 1000 includes configuring a cell based at least in part on a processor comprising one or more circuits configured to execute API 510 (see Figure 5 ) so that by API 510 (see Figure 5 ) is assigned to one or more software programs indicated by API 510 (see Figure 5 ) and / or otherwise perform the operations described herein. In at least one embodiment, the processor performs process 1000 and / or the operations described herein, for example in conjunction with Figure 1-11 In at least one embodiment, hardware performs process 1000 and / or the operations described herein, for example in conjunction with Figure 12-52 Describe the hardware.

[0169] Figure 11 An example 1100 of a processor according to at least one embodiment is shown. In at least one embodiment, the processor 1102 executes one or more processes, such as the processes described herein, to execute an application programming interface (API) to direct the allocation of wireless signal processing operations between one or more open radio access network (O-RAN) radio units (RUs) and one or more O-RAN distributed units (DUs) and / or otherwise perform the operations described herein. In at least one embodiment, the processor 1102 executes one or more processes, such as the processes described herein, to execute an application programming interface (API) to cause one or more software programs indicated by the API to be assigned to one or more 5G DUs indicated by the API ... Figure 1 In at least one embodiment, the processor 1102 executes one or more processes, such as in conjunction with Figure 1-11 One or more processes described.

[0170] In at least one embodiment, the processor 1102 includes a processor such as a Figure 12-52In at least one embodiment, the processor 1102 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, DPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, the processor 1102 includes an API module 1104, an acceleration module 1106, a functional splitting module 1108, and / or a functional block module 1110. In at least one embodiment, the API module 1104, the acceleration module 1106, the functional splitting module 1108, and / or the functional block module 1110 are distributed among multiple processors that communicate via a bus, a network, by writing to a shared memory, and / or any suitable communication process, such as the communication process described herein.

[0171] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or clearly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware that stores instructions executed by programmable circuits, alone or in any combination. In at least one embodiment, modules may be embodied collectively or individually as circuits that constitute part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or the like. In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units (e.g., one or more CPUs, GPUs, GPGPUs, DPUs, PPUs, and / or variants thereof).

[0172] In at least one embodiment, the application programming interface (API) module 1104 is a module for executing one or more APIs, such as using an API to indicate allocation and / or perform allocation of one or more signal processing operations. In at least one embodiment, the application programming interface (API) module 1104 performs one or more processes (e.g., those described herein) by at least including or otherwise encoding instructions that cause the execution or are otherwise usable (e.g., by the processor 1102) to perform the one or more processes. In at least one embodiment, the application programming interface (API) module 1104 obtains or otherwise indicates segmentation information (e.g., by one or more systems, such as, in conjunction with Figure 1-10In at least one embodiment, the application programming interface (API) module 1104 includes executing the API using the segmentation information. In at least one embodiment, the runtime executes the application programming interface (API) module 1104, for example in conjunction with Figure 5 Those described.

[0173] In at least one embodiment, the acceleration module 1106 is based at least in part on Figure 1-10 In at least one embodiment, the acceleration module 1106 accelerates one or more processes (such as those described herein) by at least including or otherwise encoding instructions that cause the execution or are otherwise usable (e.g., by the processor 1102) of the one or more processes. In at least one embodiment, the acceleration module 1106 accelerates based at least in part on the operations to be assigned indicated by the API in combination with the API module 1104. In at least one embodiment, the acceleration module 1106 accelerates one or more operations in the 5G-NR network. In at least one embodiment, the acceleration module 1106 accelerates one or more operations in the 5G-NR network based at least in part on the operations to be assigned indicated by the API in combination with the API module 1104. Figure 1-10 The process described) indicates the segmentation information to speed up the operation.

[0174] In at least one embodiment, the functional partitioning module 1108 is a module that performs one or more operations based at least in part on the functional partitioning information indicated by the processor. In at least one embodiment, the functional partitioning module 1108 performs one or more processes, such as the processes described herein, by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise operable to perform the one or more processes (e.g., by the processor 1102). In at least one embodiment, the functional partitioning module 1108 obtains the functional partitioning information through an API (e.g., the API described herein) and selects from the memory operations to be performed, such as in conjunction with Figure 7-10 In at least one embodiment, the functional partitioning module 1108 indicates the operations to be performed by the functional block module 1110. In at least one embodiment, the functional partitioning module 1108 combines the functional partitioning information with one or more processes (e.g., Figure 1-10 The process described above) is used in combination.

[0175] In at least one embodiment, the functional block module 1110 is a module for executing one or more functional blocks. In at least one embodiment, the functional block module 1110 performs one or more processes, such as those described herein, by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise operable to perform the one or more processes (e.g., for execution by the processor 1102). In at least one embodiment, the functional block module 1110 obtains partitioning information from the functional partitioning information module 1108. In at least one embodiment, the functional block module 1110 uses one or more selected blocks, such as in conjunction with Figure 6 and / or Figure 8-10 In at least one embodiment, the functional block module 1110 uses one or more processes (e.g., Figure 1-10 The process described in conjunction with the above) executes one or more blocks from memory.

[0176] As an example, the processor 1102 includes one or more circuits for executing the API 510 (see Figure 5 ) to indicate the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RANDUs and / or otherwise perform the operations described herein. As an example, the processor 1102 includes configuring a cell based at least in part on a processor including one or more circuits for executing API 510 (see Figure 5 ) so that API 510 (see Figure 5 ) is assigned to one or more software programs indicated by API510 (see Figure 5 ) indicates one or more 5G DUs and / or otherwise perform the operations described herein. In at least one embodiment, the processor 1102 performs the operations described herein, for example in conjunction with Figure 1-11 In at least one embodiment, the processor 1102 uses a combination of Figure 12-52 The described hardware and / or software performs one or more operations.

[0177] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the concepts of the present invention may be practiced without one or more of these specific details.

[0178] Data Center

[0179] Figure 12An example data center 1200 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0180] In at least one embodiment, Figure 12 As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, grouped computing resources 1214, and node computing resources ("node CRs") 1216(1)-1216(N), where "N" represents any integer, positive integer. In at least one embodiment, the node CRs 1216(1)-1216(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1216(1)-1216(N) may be a server having one or more of the above-mentioned computing resources.

[0181] In at least one embodiment, the grouped computing resources 1214 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0182] In at least one embodiment, resource coordinator 1212 may configure or otherwise control one or more nodes CR 1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may comprise a software design infrastructure ("SDI") management entity for data center 1200. In at least one embodiment, resource coordinator 1212 may comprise hardware, software, or some combination thereof.

[0183] In at least one embodiment, Figure 12 As shown, framework layer 1220 includes a job scheduler 1232, a configuration manager 1234, a resource manager 1236, and a distributed file system 1238. In at least one embodiment, framework layer 1220 may include a framework that supports the software 1232 of software layer 1230 and / or one or more applications 1242 of application layer 1240. In at least one embodiment, software 1232 or applications 1242 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which may utilize distributed file system 1238 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1232 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 1200. In at least one embodiment, a configuration manager 1234 may be capable of configuring different layers, such as a software layer 1230 and a framework layer 1220 including Spark and a distributed file system 1238 for supporting large-scale data processing. In at least one embodiment, a resource manager 1236 may be capable of managing clustered or grouped computing resources mapped to or allocated to support the distributed file system 1238 and the job scheduler 1232. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1214 on the data center infrastructure layer 1210. In at least one embodiment, the resource manager 1236 may coordinate with the resource coordinator 1212 to manage these mapped or allocated computing resources.

[0184] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0185] In at least one embodiment, the one or more applications 1242 included in the application layer 1240 may include one or more types of applications used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0186] In at least one embodiment, any of configuration manager 1234, resource manager 1236, and resource coordinator 1212 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1200 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0187] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using the resources described above with respect to data center 1200.

[0188] In at least one embodiment, data center 1200 can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0189] In at least one embodiment, Figure 12 One or more systems described in the foregoing are used to execute one or more APIs (e.g., in conjunction with Figure 1In at least one embodiment, Figure 12 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor comprising one or more circuits for executing an API to direct allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0190] Figure 13A An example of an autonomous vehicle 1300 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1300 (alternatively referred to herein as "vehicle 1300") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1300 can be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 1300 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0191] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") of the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 1300 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 1300 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0192] In at least one embodiment, the vehicle 1300 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1300 may include, but is not limited to, a propulsion system 1350, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1350 may be connected to a drive train of the vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of the vehicle 1300. In at least one embodiment, the propulsion system 1350 may be controlled in response to receiving a signal from a throttle / accelerator 1352.

[0193] In at least one embodiment, when propulsion system 1350 is operating (e.g., when the vehicle is traveling), a steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, steering system 1354 may receive signals from steering actuator 1356. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1346 may be used to operate the vehicle brakes in response to signals received from brake actuator 1348 and / or brake sensors.

[0194] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 13A) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 can send signals to operate vehicle brakes via brake actuator 1348, operate steering system 1354 via one or more steering actuators 1356, and operate propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, one or more controllers 1336 can include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist a driver in driving vehicle 1300. In at least one embodiment, the one or more controllers 1336 may include a first controller 1336 for autonomous driving functionality, a second controller 1336 for functional safety functionality, a third controller 1336 for artificial intelligence functionality (e.g., computer vision), a fourth controller 1336 for infotainment functionality, a fifth controller 1336 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1336 may handle two or more of the aforementioned functions, two or more controllers 1336 may handle a single function, and / or any combination thereof.

[0195] In at least one embodiment, one or more controllers 1336 provide signals for controlling one or more components and / or systems of the vehicle 1300 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1358 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more inertial measurement unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360 degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 13A Not shown), mid-range camera ( Figure 13A), one or more speed sensors 1344 (e.g., for measuring the speed of the vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of a brake sensor system 1346), and / or other sensor types are received.

[0196] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from a dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1334, an audible annunciator, a speaker, and / or other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 13A ), location data (e.g., the location of the vehicle 1300, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1336, etc. For example, in at least one embodiment, the HMI display 1334 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0197] In at least one embodiment, the vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, the network interface 1324 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1326 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN and SigFox) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0198] In at least one embodiment, Figure 13AThe one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 13A One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0199] Figure 13B According to at least one embodiment, Figure 13A 1300. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1300.

[0200] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1300. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0201] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0202] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to cut out stray light and reflections from within the vehicle (e.g., reflections from the dashboard reflecting in the windshield mirror) that might interfere with the camera's ability to capture image data. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be custom 3D printed such that the camera mounting plate matches the shape of the rearview mirror.

[0203] In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated into the four pillars at each corner of the car.

[0204] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1300 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 1336 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0205] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 13B Only one wide-angle camera 1370 is shown in FIG. 1 , however, in other embodiments, there may be any number (including zero) of wide-angle cameras on vehicle 1300 .

[0206] In at least one embodiment, any number of remote cameras 1398 (e.g., a remote stereo camera pair) can be used for depth-based object detection, particularly for objects for which a neural network has not been trained. In at least one embodiment, the remote cameras 1398 can also be used for object detection and classification and basic object tracking.

[0207] In at least one embodiment, any number of stereo cameras 1368 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1300 environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1300 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions.

[0208] In at least one embodiment, other types of stereo cameras 1368 besides those described herein may be used.

[0209] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 1300 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, the surround camera 1374 (e.g., Figure 13B Four surround cameras 1374 (shown) can be positioned on the vehicle 1300. In at least one embodiment, the one or more surround cameras 1374 can include, but are not limited to, any number and combination of wide-angle cameras 1370, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 1300. In at least one embodiment, the vehicle 1300 can use three surround cameras 1374 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0210] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1300 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0211] In at least one embodiment, Figure 13B The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 13B One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0212] Figure 13C According to at least one embodiment, Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300 is provided. In at least one embodiment, Figure 13C Each of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as being connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1300 that facilitates control of various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1302 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1302 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0213] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1302 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1302 may be used for collision avoidance functionality, and a second bus 1302 may be used for actuation control. In at least one embodiment, each bus 1302 may communicate with any component of the vehicle 1300, and two or more buses 1302 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips ("SoCs") 1304, each of one or more controllers 1336, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0214] In at least one embodiment, the vehicle 1300 may include one or more controllers 1336, such as those described herein with respect to Figure 13A In at least one embodiment, the controller 1336 can be used for a variety of functions. In at least one embodiment, the controller 1336 can be coupled to any of the various other components and systems of the vehicle 1300 and can be used to control the vehicle 1300, the artificial intelligence of the vehicle 1300, the infotainment and / or other functions of the vehicle 1300.

[0215] In at least one embodiment, the vehicle 1300 may include any number of SoCs 1304. Each of the SoCs 1304 may include, but is not limited to, a central processing unit ("CPU(s)") 1306, a graphics processing unit ("GPU(s")) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data stores 1316, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1304 may be used to control the vehicle 1300 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 1304 may be combined in a system (e.g., a system of the vehicle 1300) with a high-definition ("HD") map 1322 that may be downloaded from one or more servers (e.g., a system of the vehicle 1300) via a network interface 1324. Figure 13C) to obtain map refreshes and / or updates.

[0216] In at least one embodiment, one or more CPUs 1306 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1306 may be active at any given time.

[0217] In at least one embodiment, one or more CPUs 1306 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1306 can further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a simplified power state entry sequence in software, where the work is offloaded to the microcode. In at least one embodiment, the processing core is referred to as a compute unit or arithmetic unit.

[0218] In at least one embodiment, one or more GPUs 1308 may include an integrated GPU (or alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1308 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may utilize an enhanced tensor instruction set. In one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may utilize a computing application programming interface (API). In at least one embodiment, one or more GPUs 1308 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0219] In at least one embodiment, one or more GPUs 1308 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1308 can be fabricated on fin field-effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0220] In at least one embodiment, one or more GPUs 1308 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0221] In at least one embodiment, the one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the one or more GPUs 1308 to directly access the one or more CPUs 1306 page tables. In at least one embodiment, when the one or more GPUs 1308 memory management units ("MMUs") experience a miss, an address translation request may be sent to the one or more CPUs 1306. In response, in at least one embodiment, the one or more CPUs 1306 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 1308. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1306 and the one or more GPUs 1308, thereby simplifying programming the one or more GPUs 1308 and porting applications to the one or more GPUs 1308.

[0222] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0223] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a level 3 ("L3") cache available to one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0224] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks of one or more GPUs 1308 (e.g., freeing up more cycles of one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0225] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). One or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone 1396; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0226] In at least one embodiment, a DLA can perform any function of one or more GPUs 1308, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1308. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1308 and / or other one or more accelerators 1314.

[0227] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1338, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0228] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0229] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1306. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0230] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0231] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0232] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0233] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61408 standards, although other standards and protocols may be used.

[0234] In at least one embodiment, one or more SoCs 1304 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0235] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that is used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the algorithmic domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, an autonomous vehicle, such as in vehicle 1300, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0236] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0237] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0238] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1366 associated with vehicle 1300 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1364 or one or more RADAR sensors 1360), etc.

[0239] In at least one embodiment, one or more SoCs 1304 (e.g., a hardware acceleration cluster) may include one or more data stores 1316 (e.g., memory). In at least one embodiment, one or more data stores 1316 may be on-chip memory of one or more SoCs 1304 that may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data stores 1316 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1312 may include an L2 or L3 cache.

[0240] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, one or more SoCs 1304 thermal and temperature sensor management, and / or one or more SoCs 1304 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1304 may use the ring oscillator to detect the temperature of one or more CPUs 1306, one or more GPUs 1308, and / or one or more accelerators 1314. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1304 into a lower power consumption state and / or place the vehicle 1300 into a driver's safe parking pattern (e.g., bringing the vehicle 1300 to a safe stop).

[0241] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine can be an audio subsystem that can provide hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0242] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0243] In at least one embodiment, one or more processors 1310 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0244] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1304, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0245] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0246] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, without requiring one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0247] In at least one embodiment, one or more of the SoCs 1304 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1304 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0248] In at least one embodiment, one or more of the SoCs 1304 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. The one or more SoCs 1304 may be configured to process data from cameras (e.g., via Gigabit multimedia serial links and Ethernet connections), sensors (e.g., one or more LIDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via Ethernet), data from the bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., via Ethernet bus or CAN bus connections), and the like. In at least one embodiment, one or more of the SoCs 1304 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload the one or more CPUs 1306 from routine data management tasks.

[0249] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data stores 1316, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0250] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0251] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1320) may include text and word recognition, thereby allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the signs and pass this semantic understanding to a path planning module running on the CPU Complex.

[0252] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1308.

[0253] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1300. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0254] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1362 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0255] In at least one embodiment, the vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1304 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1318 may include an X86 processor, for example, and the one or more CPUs 1318 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and the one or more SoCs 1304, and / or monitoring the status and health of one or more controllers 1336 and / or an information system on a chip ("information SoC") 1330.

[0256] In at least one embodiment, the vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1304 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 1320 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input (e.g., sensor data) from sensors of the vehicle 1300.

[0257] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas 1326 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via the internet with a cloud (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1300 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1300). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1300.

[0258] In at least one embodiment, the network interface 1324 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, the network interface 1324 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0259] In at least one embodiment, the vehicle 1300 may further include one or more data stores 1328, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1304) storage. In at least one embodiment, the one or more data stores 1328 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0260] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0261] In at least one embodiment, the vehicle 1300 may further include one or more RADAR sensors 1360. One or more RADAR sensors 1360 may be used by the vehicle 1300 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1360 are pulse Doppler RADAR sensors.

[0262] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between static and moving objects and can be used by the ADAS system 1338 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1300 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may provide an expanded field of view, allowing for quick detection of vehicles entering or exiting the vehicle's 1300 lane.

[0263] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in an ADAS system 1338 for blind spot detection and / or lane change assistance.

[0264] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. In at least one embodiment, one or more ultrasonic sensors 1362, which may be positioned on the front, rear, and / or sides of the vehicle 1300, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1362 may operate at an ASIL B functional safety level.

[0265] In at least one embodiment, the vehicle 1300 can include one or more LIDAR sensors 1364. The one or more LIDAR sensors 1364 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1364 can be functional safety level ASIL B. In at least one embodiment, the vehicle 1300 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1364 that can use Ethernet (e.g., provide data to a Gigabit Ethernet switch).

[0266] In at least one embodiment, one or more LIDAR sensors 1364 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1364 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors 1364 may be used. In such an embodiment, one or more LIDAR sensors 1364 may be implemented as small devices embedded in the front, rear, sides, and / or corners of vehicle 1300. In at least one embodiment, one or more LIDAR sensors 1364 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 1364 may be configured for a horizontal field of view between 45 and 135 degrees.

[0267] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1300 to the object. In at least one embodiment, flash LIDAR can enable the generation of a highly accurate and distortion-free image of the surrounding environment with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving components other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0268] In at least one embodiment, the vehicle 1300 may also include one or more IMU sensors 1366. In at least one embodiment, the one or more IMU sensors 1366 may be located at the center of the rear axle of the vehicle 1300. In at least one embodiment, the one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1366 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1366 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0269] In at least one embodiment, one or more IMU sensors 1366 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1366 can enable vehicle 1300 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 can be combined in a single integrated unit.

[0270] In at least one embodiment, the vehicle 1300 can include one or more microphones 1396 positioned within and / or around the vehicle 1300. In at least one embodiment, the one or more microphones 1396 can be used for emergency vehicle detection and identification, among other things.

[0271] In at least one embodiment, the vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long range cameras 1398, one or more mid range cameras 1376, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1300. In at least one embodiment, the type of camera used depends on the vehicle 1300. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 13A and Figure 13B Each camera can be described in more detail.

[0272] In at least one embodiment, vehicle 1300 may further include one or more vibration sensors 1342. In at least one embodiment, one or more vibration sensors 1342 may measure vibration of a component (e.g., an axle) of vehicle 1300. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1342 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0273] In at least one embodiment, the vehicle 1300 may include an ADAS system 1338. The ADAS system 1338 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0274] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately ahead of the vehicle 1300 and automatically adjusts the speed of the vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1300 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0275] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 1324 and / or one or more wireless antennas 1326. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1300 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1300, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0276] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0277] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions.

[0278] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when vehicle 1300 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, a LKA system is a variation of the LDW system. If vehicle 1300 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1300.

[0279] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0280] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 1300 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0281] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the results of the primary or secondary computer (e.g., the first controller 1336 or the second controller 1336). For example, in at least one embodiment, the ADAS system 1338 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1338 can be provided to a supervisory MCU. In at least one embodiment, if the outputs from the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0282] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0283] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine, based at least in part on outputs from the primary and secondary computers, conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1304.

[0284] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and a different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0285] In at least one embodiment, the output of the ADAS system 1338 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0286] In at least one embodiment, the vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1330 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., a navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1300. For example, the infotainment SoC 1330 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1334, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1330 may be further configured to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0287] In at least one embodiment, the infotainment SoC 1330 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 can communicate with other devices, systems, and / or components of the vehicle 1300 via a bus 1302 (e.g., a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1330 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the vehicle's 1300 main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1330 can cause the vehicle 1300 to enter a driver-to-safety stop mode, as described herein.

[0288] In at least one embodiment, the vehicle 1300 may further include an instrument panel 1332 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1332 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1330 and the instrument panel 1332. In at least one embodiment, the instrument panel 1332 may be included as part of the infotainment SoC 1330, or vice versa.

[0289] In at least one embodiment, Figure 13C The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 13C One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0290] Figure 13D In accordance with at least one embodiment, a cloud-based server and Figure 13A 13. A diagram of a system 1377 for communicating between autonomous vehicles 1300. In at least one embodiment, system 1377 may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. One or more servers 1378 may include, but is not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPUs 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switches 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPUs 1380). GPUs 1384, CPUs 1380, and PCIe switches 1382 may be interconnected with high-speed connections, such as, but not limited to, NVLink interface 1388 developed by NVIDIA and / or PCIe connections 1386. The GPUs 1384 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1384 and PCIe switches 1382 are connected via a PCIe interconnect. In at least one embodiment, although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1378 may include, but is not limited to, any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382 in any combination. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0291] In at least one embodiment, one or more servers 1378 may receive image data representing an image from a vehicle via one or more networks 1390 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1378 may transmit a neural network 1392, an updated neural network 1392, and / or map information 1394, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1390. In at least one embodiment, updates to the map information 1394 may include, but not limited to, updates to the HD map 1322, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1392, the updated neural network 1392, and / or the map information 1394 may be generated by new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1378 and / or other servers).

[0292] In at least one embodiment, one or more servers 1378 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390, and / or the machine learning model can be used by one or more servers 1378 to remotely monitor the vehicle.

[0293] In at least one embodiment, one or more servers 1378 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1378 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 can include the deep learning infrastructure of a data center using CPU power.

[0294] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1300, such as an image sequence and / or objects that the vehicle 1300 has located within that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1300, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1300 is malfunctioning, the one or more servers 1378 may send a signal to the vehicle 1300 instructing the vehicle's 1300 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0295] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-powered servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers powered by CPUs, FPGAs, and other processors can be used for inference.

[0296] Computer system

[0297] Figure 14 14 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1400 may include a processor such as the Intel® processor 1402 available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, CoreTM or The computer system 1400 may be based on a Nervana™ microprocessor, although other systems may also be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, the computer system 1400 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0298] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0299] In at least one embodiment, computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 1400 is a single-processor desktop or server system, but in another embodiment, system 1400 may be a multi-processor system. In at least one embodiment, processor 1402 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1402 may be coupled to a processor bus 1410, which may transmit data signals between processor 1402 and other components in computer system 1400.

[0300] In at least one embodiment, processor 1402 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1406 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0301] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating point operations, is also located in the processor 1402. In at least one embodiment, the processor 1402 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1408 may include logic for processing a packed instruction set 1409. In at least one embodiment, by including the packed instruction set 1409 in the instruction set of the general-purpose processor 1402, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1402. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0302] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0303] In at least one embodiment, a system logic chip can be coupled to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1416, and the processor 1402 can communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 can provide a high-bandwidth memory path 1418 to the memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1416 can initiate data signals between the processor 1402, the memory 1420, and other components in the computer system 1400, and bridge data signals between the processor bus 1410, the memory 1420, and the system I / O 1422. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to the memory 1420 via a high-bandwidth memory path 1418 , and the graphics / video card 1412 may be coupled to the MCH 1416 via an Accelerated Graphics Port (“AGP”) interconnect 1414 .

[0304] In at least one embodiment, computer system 1400 may use system I / O 1422, which is a proprietary hub interface bus, to couple MCH 1416 to I / O controller hub ("ICH") 1430. In at least one embodiment, ICH 1430 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub ("Flash BIOS") 1428, a wireless transceiver 1426, a data store 1424, a traditional I / O controller 1423 including a user input and keyboard interface, a serial expansion port 1427 (e.g., a universal serial bus (USB)), and a network controller 1434. In at least one embodiment, data store 1424 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0305] In at least one embodiment, Figure 14 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 14 A system on a chip (SoC) may be shown. In at least one embodiment, Figure 14The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1400 are interconnected using a Compute Express Link (CXL) interconnect.

[0306] In at least one embodiment, Figure 14 The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 14 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0307] Figure 15 1 is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0308] In at least one embodiment, system 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled using a bus or interface, such as an IC bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 15 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 15 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 15The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0309] In at least one embodiment, Figure 15 It may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1539, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1522, a DSP 1560, a drive “SSD or HDD” 1520 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) 1555, a camera (“USB 3.0 camera”) 1554 (e.g., a USB 3.0 camera), or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0310] In at least one embodiment, other components may be communicatively coupled to processor 1510 via the components described above. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1564, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1564 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as the WLAN unit 1550 and the Bluetooth unit 1552 and the WWAN unit 1556 may be implemented as a next generation form factor (NGFF).

[0311] In at least one embodiment, Figure 15The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 15 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0312] Figure 16 Illustrated is a computer system 1600 in accordance with at least one embodiment. In at least one embodiment, the computer system 1600 is configured to implement the various processes and methods described throughout this disclosure.

[0313] In at least one embodiment, computer system 1600 includes, but is not limited to, at least one central processing unit ("CPU") 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1604 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1622 provides an interface to other computing devices and networks for receiving data from computer system 1600 and transmitting data to other systems.

[0314] In at least one embodiment, computer system 1600 includes, but is not limited to, input device 1608, parallel processing system 1612, and display device 1606, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1608 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the aforementioned modules can be located on a single semiconductor platform to form a processing system.

[0315] In at least one embodiment, Figure 16 The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 16 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0316] Figure 17 A computer system 1700 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1700 includes, but is not limited to, a computer 1710 and a USB stick 1720. In at least one embodiment, computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0317] In at least one embodiment, the USB stick 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1730 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1730 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1730 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning inference operations.

[0318] In at least one embodiment, USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1750 can include any number and type of logic that enables processing unit 1730 to connect to a device (e.g., computer 1710) via USB connector 1740.

[0319] In at least one embodiment, Figure 17 The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 17 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0320] Figure 18AAn exemplary architecture is shown in which multiple GPUs 1810-1813 are communicatively coupled to multiple multi-core processors 1805-1806 via high-speed links 1840-1843 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, the high-speed links 1840-1843 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0321] Furthermore, in one embodiment, two or more GPUs 1810-1813 are interconnected via high-speed links 1829-1830, which may be implemented using the same or different protocols / links as used for high-speed links 1840-1843. Similarly, two or more multi-core processors 1805-1806 may be connected via high-speed link 1828, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 18A All communications between the various system components shown in .

[0322] In one embodiment, each multi-core processor 1805-1806 is communicatively coupled to processor memory 1801-1802 via memory interconnects 1826-1827, respectively, and each GPU 1810-1813 is communicatively coupled to GPU memory 1820-1823 via GPU memory interconnects 1850-1853, respectively. Memory interconnects 1826-1827 and 1850-1853 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1801-1802 and GPU memory 1820-1823 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1801-1802 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0323] As described herein, although the various processors 1805-1806 and GPUs 1810-1813 may each be physically coupled to a specific memory 1801-1802, 1820-1823, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 1801-1802 may each contain 64GB of system memory address space, and the GPU memories 1820-1823 may each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0324] Figure 18B 1807 and a graphics acceleration module 1846. The graphics acceleration module 1846 may include one or more GPU chips integrated on a line card that is coupled to the processor 1807 via a high-speed link 1840. Alternatively, the graphics acceleration module 1846 may be integrated on the same package or chip as the processor 1807.

[0325] In at least one embodiment, the illustrated processor 1807 includes a plurality of cores 1860A-1860D, each having a translation lookaside buffer 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, the cores 1860A-1860D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1862A-1862D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1856 may be included in the caches 1862A-1862D and shared by each group of cores 1860A-1860D. For example, one embodiment of the processor 1807 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1807 and the graphics acceleration module 1846 are connected to the system memory 1814, which may include Figure 18A Processor memory 1801-1802 in.

[0326] Coherence is maintained for data and instructions stored in the various caches 1862A-1862D, 1856, and system memory 1814 via inter-core communication over a coherence bus 1864. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1864 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1864 to snoop cache accesses.

[0327] In one embodiment, proxy circuitry 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864, thereby allowing graphics acceleration module 1846 to participate in a cache coherence protocol as a peer of cores 1860A-1860D. In particular, in at least one embodiment, interface 1835 provides connectivity to proxy circuitry 1825 via high-speed link 1840 (e.g., a PCIe bus, NVLink, etc.), and interface 1837 connects graphics acceleration module 1846 to link 1840.

[0328] In one implementation, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1831, 1832, N of the graphics acceleration module. The graphics processing engines 1831, 1832, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1831, 1832, N may selectively comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1846 may be a GPU having multiple graphics processing engines 1831-1832, N, or the graphics processing engines 1831-1832, N may be individual GPUs integrated into a common package, line card, or chip.

[0329] In one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1814. The MMU 1839 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1838 may store commands and data for efficient access by the graphics processing engines 1831-1832, N. In at least one embodiment, data stored in cache 1838 and graphics memory 1833-1834, M is kept consistent with the core caches 1862A-1862D, 1856, and system memory 1814. As previously described, this task may be accomplished via proxy circuitry 1825 acting on behalf of cache 1838 and graphics memory 1833-1834, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1862A-1862D, 1856 to cache 1838 and receiving updates from cache 1838).

[0330] A set of registers 1845 stores context data for threads executed by graphics processing engines 1831-1832, N, and context management circuitry 1848 manages thread contexts. For example, context management circuitry 1848 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1848 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0331] In one implementation, the MMU 1839 converts virtual / effective addresses from the graphics processing engine 1831 into real / physical addresses in the system memory 1814. One embodiment of the accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. The graphics accelerator module 1846 can be dedicated to a single application executing on the processor 1807, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1831-1832, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0332] In at least one embodiment, the accelerator integrated circuit 1836 acts as a bridge to the system for the graphics acceleration module 1846 and provides address translation and system memory caching services. In addition, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1831-1832.

[0333] Because the hardware resources of graphics processing engines 1831-1832, N are explicitly mapped into the real address space seen by host processor 1807, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1836 is to physically separate graphics processing engines 1831-1832, N so that they appear as independent units to the system.

[0334] In at least one embodiment, one or more graphics memories 1833-1834, M are respectively coupled to each graphics processing engine 1831-1832, N. Graphics memories 1833-1834, M store instructions and data, which are processed by each graphics processing engine 1831-1832, N. Graphics memories 1833-1834, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0335] In one embodiment, to reduce data traffic on link 1840, biasing techniques can be used to ensure that the data stored in graphics memory 1833-1834, M is the data most frequently used by graphics processing engines 1831-1832, N, and preferably not used (at least not frequently) by cores 1860A-1860D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the core (and preferably not graphics processing engines 1831-1832, N) in the core's cache 1862A-1862D, 1856 and system memory 1814.

[0336] Figure 18C Another exemplary embodiment is shown in which an accelerator integrated circuit 1836 is integrated into the processor 1807. In this embodiment, the graphics processing engines 1831-1832, N communicate directly with the accelerator integrated circuit 1836 via interfaces 1837 and 1835 (which may also utilize any form of bus or interface protocol) over a high-speed link 1840. The accelerator integrated circuit 1836 can perform operations related to Figure 18B The operations described above are identical to those described above. However, due to its close proximity to the coherence bus 1864 and caches 1862A-1862D, 1856, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0337] In at least one embodiment, the graphics processing engines 1831-1832, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to the graphics processing engines 1831-1832, N, thereby providing virtualization within a VM / partition.

[0338] In at least one embodiment, graphics processing engines 1831-1832,N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1831-1832,N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1831-1832,N. In at least one embodiment, the operating system can virtualize graphics processing engines 1831-1832,N to provide access to each process or application.

[0339] In at least one embodiment, the graphics acceleration module 1846 or individual graphics processing engines 1831-1832,N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 1814 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1831-1832,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0340] Figure 18D An exemplary accelerator integrated slice 1890 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 1836. An application is an effective address space 1882 in system memory 1814 that stores process elements 1883. In one embodiment, process elements 1883 are stored in response to a GPU call 1881 from an application 1880 executing on processor 1807. Process elements 1883 contain the process state of the corresponding application 1880. A work descriptor (WD) 1884 contained in process element 1883 may be a single job requested by the application, or may contain a pointer to a job queue. In at least one embodiment, WD 1884 is a pointer to a job request queue in the application's address space 1882.

[0341] The graphics acceleration module 1846 and / or the individual graphics processing engines 1831-1832, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1884 to the graphics acceleration module 1846 to start a job in a virtualized environment can be included.

[0342] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns either a graphics acceleration module 1846 or an individual graphics processing engine 1831. Since the hypervisor initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1846 is owned by a single process, the operating system initializes the accelerator integrated circuit 1836 for the owning process when the graphics acceleration module 1846 is assigned.

[0343] In operation, the WD fetch unit 1891 in the accelerator integrated slice 1890 fetches the next WD 1884, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1846. Data from WD 1884 can be stored in registers 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing segment / page tables 1886 within the OS virtual address space 1885. The interrupt management circuitry 1847 can process interrupt events 1892 received from the graphics acceleration module 1846. When executing graphics operations, effective addresses 1893 generated by the graphics processing engines 1831-1832, N are converted into real addresses by the MMU 1839.

[0344] In one embodiment, the same set of registers 1845 is replicated for each graphics processing engine 1831-1832, N, and / or graphics acceleration module 1846, and the registers 1845 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1890. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0345]

[0346] Example registers that may be initialized by the operating system are shown in Table 2.

[0347]

[0348] In one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831-1832, N. It contains all the information needed by the graphics processing engine 1831-1832, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0349] Figure 18E 1896 , which virtualizes the graphics acceleration module engine for the operating system 1895.

[0350] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1846. There are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing.

[0351] In this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. For the graphics acceleration module 1846 to support virtualization through the hypervisor 1896, the graphics acceleration module 1846 may adhere to the following: (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context save and restore mechanism, (2) the graphics acceleration module 1846 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1846 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1846 processes must be ensured when operating in a directed shared programming model.

[0352] In at least one embodiment, an application 1880 is required to make an operating system 1895 system call using a graphics acceleration module 1846 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1846 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1846 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1846 and can take the form of a graphics acceleration module 1846 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 1846. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integrated circuit 1836 and graphics acceleration module 1846 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1896 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into process element 1883. In at least one embodiment, CSRP is one of registers 1845 that contains the effective address of an area in the application's address space 1882 for graphics acceleration module 1846 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory.

[0353] Upon receiving the system call, the operating system 1895 may verify that the application 1880 has been registered and granted permission to use the graphics acceleration module 1846. The operating system 1895 then uses

[0354] The information shown in Table 3 is used to call the management program 1896.

[0355]

[0356] Upon receiving the hypervisor call, the hypervisor 1896 verifies that the operating system 1895 has registered and been granted permission to use the graphics acceleration module 1846. The hypervisor 1896 then places the process element 1883 into a linked list of process elements of the corresponding graphics acceleration module 1846 type. The process element may include the information shown in Table 4.

[0357]

[0358] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1890 registers 1845 .

[0359] like Figure 18F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 1801-1802 and GPU memories 1820-1823. In this implementation, operations executed on GPUs 1810-1813 utilize the same virtual / effective memory address space to access processor memories 1801-1802, and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801, a second portion is allocated to second processor memory 1802, a third portion is allocated to GPU memory 1820, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1801-1802 and GPU memories 1820-1823, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0360] In one embodiment, bias / coherency management circuitry 1894A-1894E within one or more MMUs 1839A-1839E ensures cache coherency between the caches of one or more host processors (e.g., 1805) and GPUs 1810-1813 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 18F Multiple instances of bias / coherence management circuits 1894A- 1894E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1805 and / or within an accelerator integrated circuit 1836 .

[0361] One embodiment allows GPU attached memory 1820-1823 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU attached memory 1820-1823 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows software of the host processor 1805 to set operands and access calculation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU attached memory 1820-1823 without cache coherence overhead can be critical to the execution time of the offloaded calculation. For example, in situations with large amounts of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1810-1813. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0362] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1820-1823, with or without a bias cache in GPUs 1810-1813 (e.g., to cache frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0363] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1820-1823 is accessed, resulting in the following operations. First, local requests from GPUs 1810-1813 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1820-1823. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1805 (e.g., via a high-speed link as described above). In one embodiment, a request from processor 1805 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request to a GPU biased page can be forwarded to GPUs 1810-1813. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0364] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1805 bias to GPU bias, but not for the reverse migration.

[0365] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1805. To access these pages, processor 1805 may request access from GPU 1810, which may or may not immediately grant access. Therefore, to reduce communication between processor 1805 and GPU 1810, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1805, and vice versa.

[0366] Figure 19 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0367] Figure 19is a block diagram illustrating an exemplary system on a chip integrated circuit 1900 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1900 includes peripheral or bus logic, including a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I.sup.2S / I.sup.2C controller 1940. In at least one embodiment, integrated circuit 1900 may include a display device 1945 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1950 and a Mobile Industry Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by a flash memory subsystem 1960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1970 .

[0368] In at least one embodiment, Figure 19 The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 19 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0369] Figures 20A-20B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0370] Figures 20A-20Bis a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Figure 20B Another exemplary graphics processor 2040 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 20A The graphics processor 2010 is a low power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 can be Figure 19 A variant of the graphics processor 1910.

[0371] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D through 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 can execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 2015A-2015N use the primitives and vertex data generated by the vertex processor 2005 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0372] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a mapping of virtual to physical addresses for the graphics processor 2010, including for the vertex processor 2005 and / or the fragment processors 2015A-2015N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B may synchronize with other MMUs within the system, including with other MMUs. Figure 19 One or more MMUs associated with one or more application processors 1905, graphics processor 1915, and / or video processor 1920 enable each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable graphics processor 2010 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0373] In at least one embodiment, graphics processor 2040 includes Figure 20A One or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B of the graphics processor 2010. In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F through 2055N-1 and 2055N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2055A-2055N and a tiling unit 2058 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0374] In at least one embodiment, one or more systems depicted in FIG. 20 are used to execute one or more APIs having various algorithms, formulas, and processes, such as in conjunction with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, one or more systems depicted in FIG. 20 are used to implement one or more systems and / or processes, for example, in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0375] Figures 21A-21B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 21A Shows that can be included in Figure 19 Graphics core 2100 within graphics processor 1910, and in at least one embodiment, may be such as Figure 20B Unified shader cores 2055A-2055N are shown. Figure 21B A highly parallel, general-purpose graphics processing unit 2130 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0376] In at least one embodiment, graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and cache / shared memory 2120, which are common to execution resources within graphics core 2100. In at least one embodiment, graphics core 2100 may include multiple slices 2101A-2101N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 2100. Slices 2101A-2101N may include support logic including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional function units (AFUs 2112A-2112N), floating point units (FPUs 2114A-2114N), integer arithmetic logic units (ALUs 2116A-2116N), address calculation units (ACUs 2113A-2113N), double-precision floating point units (DPFPUs 2115A-2115N), and matrix processing units (MPUs 2117A-2117N).

[0377] In at least one embodiment, the FPUs 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2115A-2115N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2117-2117N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2112A-2112N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0378] In at least one embodiment, Figure 21A The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 In at least one embodiment, the present invention may include executing an application programming interface (API) to cause one or more software programs indicated by the API to be assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. Figure 21A One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor comprising one or more circuits for executing an API to direct allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0379] Figure 21BA general purpose processing unit (GPGPU) 2130 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 2130 can be directly linked to other instances of GPGPU 2130 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2130 includes a host interface 2132 to enable connection to a host processor. In at least one embodiment, host interface 2132 is a PCI Express interface. In at least one embodiment, host interface 2132 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to assign execution threads associated with those commands to a group of compute clusters 2136A-2136H. In at least one embodiment, compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, cache memory 2138 may serve as a higher level of cache for cache memory within compute clusters 2136A-2136H.

[0380] In at least one embodiment, the GPGPU 2130 includes memory 2144A-2144B coupled to the compute cluster 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, the memory 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0381] In at least one embodiment, the computing clusters 2136A-2136H each include a set of graphics cores, e.g. Figure 21A The graphics core 2100 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0382] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to function as a compute cluster. In at least one embodiment, the communication used by compute clusters 2136A-2136H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate via a host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to a GPU link 2140, enabling direct connections to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 reside in separate data processing systems and communicate via a network device accessible through host interface 2132. In at least one embodiment, GPU link 2140 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 2132 .

[0383] In at least one embodiment, the GPGPU 2130 can be configured to train a neural network. In at least one embodiment, the GPGPU 2130 can be used within an inference platform. In at least one embodiment, where the GPGPU 2130 is used for inference, the GPGPU can include fewer compute clusters 2136A-2136H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2144A-2144B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0384] In at least one embodiment, Figure 21B The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 In at least one embodiment, the present invention may include executing an application programming interface (API) to cause one or more software programs indicated by the API to be assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. Figure 21BOne or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor comprising one or more circuits for executing an API to direct allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0385] Figure 22 A block diagram of a computer system 2200 is shown, according to at least one embodiment. In at least one embodiment, computer system 2200 includes a processing subsystem 2201 having one or more processors 2202 and a system memory 2204, which communicates via an interconnect path that may include a memory hub 2205. In at least one embodiment, memory hub 2205 may be a separate component within a chipset assembly or may be integrated within one or more processors 2202. In at least one embodiment, memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In one embodiment, I / O subsystem 2211 includes an I / O hub 2207, which may enable computer system 2200 to receive input from one or more input devices 2208. In at least one embodiment, I / O hub 2207 may enable a display controller, which may be included in one or more processors 2202, to provide output to one or more display devices 2210A. In at least one embodiment, the one or more display devices 2210A coupled to the I / O hub 2207 may include local, internal, or embedded display devices.

[0386] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to the memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 can be any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2212 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2212 form a graphics processing subsystem that can output pixels to one of one or more display devices 2210A coupled via the I / O hub 2207. In at least one embodiment, the one or more parallel processors 2212 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 2210B.

[0387] In at least one embodiment, a system storage unit 2214 can be connected to the I / O hub 2207 to provide a storage mechanism for the computer system 2200. In at least one embodiment, an I / O switch 2216 can be used to provide an interface mechanism to enable connections between the I / O hub 2207 and other components, such as a network adapter 2218 and / or a wireless network adapter 2217 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2220. In at least one embodiment, the network adapter 2218 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2219 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0388] In at least one embodiment, the computer system 2200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2207. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 22 Communication paths for various components in a chip, such as NV-Link high-speed interconnect or interconnect protocol.

[0389] In at least one embodiment, one or more parallel processors 2212 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2212 include circuits optimized for general-purpose processing. In at least one embodiment, the components of the computer system 2200 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2212, memory hub 2205, processor 2202, and I / O hub 2207 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 2200 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2200 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computer system.

[0390] In at least one embodiment, Figure 22 The one or more systems described in the embodiment are used to execute one or more APIs having various algorithms, formulas and processes, such as in combination with Figure 1 Those described herein, such as to execute an application programming interface (API) so that one or more software programs indicated by the API are assigned to one or more 5G DUs indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, Figure 22 One or more systems described in are used to implement one or more systems and / or processes, such as in conjunction with Figure 1-11 Those described, such as a processor including one or more circuits for executing an API to direct the allocation of wireless signal processing operations between one or more O-RAN RUs and one or more O-RAN DUs and / or otherwise performing the operations described herein.

[0391] processor

[0392] Figure 23A 2300 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2300 is shown as a processor according to an exemplary embodiment. Figure 22 A variation of the one or more parallel processors 2212 shown.

[0393] In at least one embodiment, parallel processor 2300 includes parallel processing unit 2302. In at least one embodiment, parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of parallel processing unit 2302. In at least one embodiment, I / O unit 2304 can be directly connected to other devices. In at least one embodiment, I / O unit 2304 connects to other devices using a hub or switch interface (e.g., memory hub 2305). In at least one embodiment, the connection between memory hub 2305 and I / O unit 2304 forms a communication link. In at least one embodiment, I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, where host interface 2306 receives commands for performing processing operations and memory crossbar switch 2316 receives commands for performing memory operations.

[0394] In at least one embodiment, when host interface 2306 receives command buffers via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to distribute commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is properly configured and in a valid state before distributing tasks to processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2312 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2312 by scheduler 2310 logic within a microcontroller that includes scheduler 2310 .

[0395] In at least one embodiment, processing cluster array 2312 can include up to "N" processing clusters (e.g., cluster 2314A, cluster 2314B, through cluster 2314N). In at least one embodiment, each cluster 2314A-2314N of processing cluster array 2312 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2310 can assign work to clusters 2314A-2314N of processing cluster array 2312 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by scheduler 2310 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2312. In at least one embodiment, different clusters 2314A-2314N of processing cluster array 2312 can be assigned to process different types of programs or to perform different types of computations.

[0396] In at least one embodiment, processing cluster array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2312 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2312 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0397] In at least one embodiment, processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2302 may transfer data from system memory via I / O units 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to system memory.

[0398] In at least one embodiment, when parallel processing unit 2302 is used to perform graphics processing, scheduler 2310 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2314A-2314N of processing cluster array 2312. In at least one embodiment, portions of processing cluster array 2312 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In ...

Claims

1. A processor, comprising: One or more circuits, the one or more circuits are used to execute an application programming interface API so that one or more software programs indicated by the API are distributed to one or more fifth-generation 5G distributed units DU indicated by the API.

2. The processor of claim 1 , wherein the one or more 5G DUs assigned to the API include: One or more accelerators are caused to perform one or more wireless signal processing operations based at least in part on information indicating how the wireless signal processing operations are to be distributed between the radio unit RU and the one or more DUs.

3. The processor of claim 1 , wherein the indicated one or more software programs accelerate wireless signal processing operations based at least in part on an allocation of functions between the one or more 5G DUs and one or more 5G RUs.

4. The processor of claim 1 , wherein the one or more circuits are configured to use the API to cause one or more software programs to be assigned to one or more 5G RUs based at least in part on instructions by the API. 5 . The processor of claim 1 , wherein the one or more software programs indicated by the API include one or more operations on a block of memory selected from a memory pool. 6 . The processor of claim 1 , wherein the one or more software programs indicated by the API include software programs of a library selected based at least in part on an assignment of operations indicated by the API.

7. The processor of claim 1, wherein the one or more software programs indicated by the API include operations on a memory pool that is selectively enabled based at least in part on an allocation of the one or more 5G DUs.

8. A system comprising: One or more processors, the one or more processors are used to execute an application programming interface API so that one or more software programs indicated by the API are distributed to one or more fifth-generation 5G distributed units DU indicated by the API.

9. The system of claim 8, wherein the one or more 5G DUs assigned to the API include: The one or more accelerators are caused to perform one or more wireless signal processing operations based at least in part on information indicating how the wireless signal processing operations are to be distributed between the radio unit RU and the one or more DUs.

10. The system of claim 8, wherein the indicated one or more software programs accelerate wireless signal processing operations based at least in part on an allocation of functionality between the one or more 5G DUs and one or more 5G RUs.

11. The system of claim 8, wherein the one or more processors for executing the API are further configured to cause one or more software programs to be assigned to one or more 5G RUs based at least in part on instructions from the API.

12. The system of claim 8, wherein the one or more software programs indicated by the API include one or more operations on a block of memory selected from a memory pool.

13. The system of claim 8, wherein the one or more software programs indicated by the API include software programs of a library selected based at least in part on the assignment of operations indicated by the API.

14. The system of claim 8, wherein the one or more software programs indicated by the API include operations on a memory pool that is selectively enabled based on allocation of the one or more 5G DUs.

15. A method comprising: An application programming interface API is executed so that one or more software programs indicated by the API are distributed to one or more fifth-generation 5G distributed units DU indicated by the API.

16. The method of claim 15, wherein being allocated to one or more 5G DUs indicated by the API comprises: One or more accelerators are caused to perform one or more wireless signal processing operations based at least in part on information indicating how the wireless signal processing operations are to be distributed between the radio unit RU and the one or more DUs.

17. The method of claim 15, wherein the indicated one or more software programs accelerate wireless signal processing operations based at least in part on an allocation of functionality between the one or more 5G DUs and one or more 5G RUs.

18. The method of claim 15, wherein executing the API is used to cause one or more software programs to be assigned to one or more 5G RUs based at least in part on instructions by the API.

19. The method of claim 15, wherein the one or more software programs include one or more libraries, the method further comprising: The one or more libraries are loaded into a memory location accessible to one or more accelerators for performing one or more 5G signal processing operations, wherein the one or more 5GDUs are used to set up a kernel to perform the one or more 5G signal processing operations based at least in part on the one or more libraries.

20. The method of claim 15, wherein the one or more software programs indicated by the API include software programs of a library selected based at least in part on an assignment of operations indicated by the API.

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