Semiconductor device structure and manufacturing method thereof

Abstract

The embodiments of the present disclosure relate to the field of semiconductor technology and provide a semiconductor device structure and a method for manufacturing the same. The semiconductor device structure includes: a substrate having a source region and a drain region spaced apart from each other; a gate structure disposed on the upper surface of the substrate; and a plurality of conductive pillars respectively contacting the source region and / or the drain region; wherein the gate structure includes a gate extending in a first direction and a gate oxide layer disposed between the gate and the substrate; the source region and / or the drain region having at least one recessed structure, and at least one conductive pillar disposed within the recessed structure; and among the plurality of conductive pillars contacting one of the source region or the drain region, the positions at which two adjacent conductive pillars contact the substrate have different heights in the thickness direction of the substrate. The embodiments of the present disclosure are at least conducive to reducing the coupling effect between different conductive pillars and improving the integration density of the semiconductor device structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor device structure and a manufacturing method thereof. Background Art

[0002] In dynamic random access memory (DRAM), it is desirable to further reduce the layout area of ​​various circuits, enabling further DRAM scalability. However, as DRAM integration density increases, the performance of individual electrical components, such as transistors, decreases. Furthermore, the reduced spacing between components increases coupling effects, limiting DRAM scalability. Summary of the Invention

[0003] The embodiments of the present disclosure provide a semiconductor device structure and a manufacturing method thereof, which are at least beneficial in reducing the coupling effect between different conductive pillars and improving the integration density of the semiconductor device structure.

[0004] According to some embodiments of the present disclosure, on the one hand, embodiments of the present disclosure provide a semiconductor device structure, comprising: a substrate provided with a source region and a drain region spaced apart from each other; a gate structure arranged on the upper surface of the substrate; and a plurality of conductive pillars respectively contacting the source region and / or the drain region; wherein the gate structure comprises a gate having a length extending along a first direction and a gate oxide layer arranged between the gate and the substrate; the source region and / or the drain region has at least one recessed structure, and at least one conductive pillar is arranged in the recessed structure; among the plurality of conductive pillars contacting one of the source region or the drain region, the positions at which two adjacent conductive pillars contact the substrate are different in height in the thickness direction of the substrate.

[0005] In some embodiments, the source region and / or the drain region has a plurality of recessed structures arranged at intervals along the first direction.

[0006] In some embodiments, the substrate further includes a channel region disposed between the source region and the drain region, and the channel region also has a plurality of the recessed structures spaced apart along the first direction.

[0007] In some embodiments, the plurality of recessed structures disposed on the substrate are arranged in an array.

[0008] In some embodiments, a plurality of the recessed structures spaced apart along the first direction form a column of recessed groups, and the recessed structures in two adjacent columns of the recessed groups are staggered.

[0009] In some embodiments, the substrate further includes a channel region disposed between the source region and the drain region, and a groove having a length extending along the first direction is disposed in the substrate, and the groove is at least partially located in the channel region.

[0010] In some embodiments, the source region has a first portion close to the channel region and a second portion away from the channel region, and the thickness of the first portion in the second direction gradually decreases along the direction from the source region to the drain region; and / or, the drain region has a third portion close to the channel region and a fourth portion away from the channel region, and the thickness of the third portion in the second direction gradually increases along the direction from the source region to the drain region; wherein the second direction is the thickness extension direction of the gate.

[0011] In some embodiments, along the second direction, the first portion has a first side and a second side relative to each other, the first side is inclined toward the second side, and the second side is inclined toward the first side; and / or, along the second direction, the third portion has a third side and a fourth side relative to each other, the third side is inclined toward the fourth side, and the fourth side is inclined toward the third side.

[0012] In some embodiments, at least a portion of the gate is located in the groove, the first direction and the second direction constitute a reference plane, and in the second direction, the length of the overlapping area of ​​the gate and the positive projection of any of the conductive pillars on the reference plane is less than the thickness of the gate, wherein the second direction is the thickness extension direction of the gate.

[0013] In some embodiments, the gate and the gate oxide layer both have shapes matching the surface of the channel region.

[0014] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for manufacturing a semiconductor device structure, comprising: providing a substrate, the substrate comprising an initial substrate and a first doping region and a second doping region disposed in the initial substrate; forming a mask layer on the substrate, the mask layer having at least one first opening directly opposite to the first doping region and / or the second doping region to expose a portion of the surface of the first doping region and / or the second doping region; performing an oxidation treatment on the substrate based on the mask layer to form an oxide layer; removing the mask layer and the oxide layer to leave the initial substrate as a substrate, The remaining first doped region is a source region, and the remaining second doped region is a drain region, so that the source region and / or the drain region has at least one recessed structure; a gate structure is formed based on the substrate, the length of which extends along the first direction; a dielectric layer is formed to cover at least the source region and the drain region, and a plurality of vias are provided in the dielectric layer; conductive pillars are formed in the plurality of vias, and at least one conductive pillar is arranged in the recessed structure; wherein, among the plurality of conductive pillars in contact with one of the source region or the drain region, the positions at which two adjacent conductive pillars contact the substrate are different in height in the thickness direction of the substrate.

[0015] In some embodiments, the mask layer directly facing the first doping region and / or the second doping region has a plurality of first openings arranged at intervals along the first direction.

[0016] In some embodiments, the mask layer has a middle portion directly opposite to the first doping region and the second doping region, and the middle portion also has a plurality of first openings arranged at intervals along the first direction to expose a portion of the surface of the initial substrate located between the first doping region and the second doping region.

[0017] In some embodiments, the plurality of first openings in the mask layer are arranged in an array.

[0018] In some embodiments, the mask layer has a middle portion facing between the first doping region and the second doping region, and the middle portion has a second opening extending along the first direction.

[0019] In some embodiments, the second opening further exposes a portion of the surface of the first doping region and a portion of the surface of the second doping region.

[0020] In some embodiments, after forming the mask layer and before forming the oxide layer, the manufacturing method further includes: performing patterning on the substrate using the mask layer as a mask so that the surface of the remaining substrate exposed by the first opening is recessed toward the interior of the substrate.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] At least one of the source region and the drain region has at least one recessed structure. It is understandable that whichever of the source region and the drain region has a recessed structure will have an uneven surface. On this basis, at least one of the multiple conductive pillars in contact with one of the source region or the drain region is disposed within the recessed structure, which is advantageous in that the positions where two adjacent conductive pillars in contact with the substrate of the multiple conductive pillars in contact with one of the source region or the drain region are in contact with the substrate have different heights in the thickness direction of the substrate, that is, the conductive pillars located in different areas of the substrate surface are staggered in the thickness direction of the substrate, which is advantageous in reducing the facing area between adjacent conductive pillars, thereby reducing the coupling effect between different conductive pillars. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars, the spacing between adjacent conductive pillars can be further reduced to improve the integration density of the semiconductor device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of a partial top view of a semiconductor device structure provided by an embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a first cross-sectional direction AA1;

[0026] Figure 3 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a second cross-sectional direction BB1;

[0027] Figure 4 A schematic diagram of a partial top view of a substrate in a semiconductor device structure provided in one embodiment of the present disclosure;

[0028] Figure 5 5a is another partial top view of the substrate in the semiconductor device structure provided by an embodiment of the present disclosure;

[0029] Figure 5 5b is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a third cross-sectional direction CC1;

[0030] Figures 6 to 9 Four other partial top-view structural schematic diagrams of a substrate in a semiconductor device structure provided in an embodiment of the present disclosure;

[0031] Figures 10 to 12 Schematic diagrams of three partial cross-sectional structures of a semiconductor device structure provided by an embodiment of the present disclosure along a fourth cross-sectional direction DD1;

[0032] Figure 13 A flow chart of a method for manufacturing a semiconductor device structure according to another embodiment of the present disclosure;

[0033] Figures 14 to 25 This is a structural schematic diagram corresponding to each step in a method for manufacturing a semiconductor device structure provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] As can be seen from the background technology, the performance of semiconductor device structures needs to be improved, and the integration density needs to be improved.

[0035] The present disclosure provides a semiconductor device structure and a method for manufacturing the same. In the semiconductor device structure, at least one of the source region and the drain region has at least one recessed structure. It is understandable that whichever of the source region and the drain region has the recessed structure will have an uneven surface. On this basis, at least one of the multiple conductive pillars in contact with one of the source region or the drain region is disposed within the recessed structure, which is advantageous for ensuring that, among the multiple conductive pillars in contact with one of the source region or the drain region, the positions at which two adjacent conductive pillars contact the substrate are at different heights in the thickness direction of the substrate, that is, the conductive pillars located in different areas of the substrate surface are staggered in the thickness direction of the substrate, which is advantageous for reducing the facing area between adjacent conductive pillars, thereby reducing the coupling effect between different conductive pillars. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars, the spacing between adjacent conductive pillars can be further reduced to improve the integration density of the semiconductor device structure.

[0036] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0037] An embodiment of the present disclosure provides a semiconductor device structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 A schematic diagram of a partial top view of a semiconductor device structure provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a first cross-sectional direction AA1; Figure 3 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a second cross-sectional direction BB1; Figure 4 A schematic diagram of a partial top view of a substrate in a semiconductor device structure provided in one embodiment of the present disclosure; Figure 5 5a is another partial top view of the substrate in the semiconductor device structure provided by an embodiment of the present disclosure;

[0038] Figure 5 5b is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a third cross-sectional direction CC1; Figures 6 to 9 Four other partial top-view structural schematic diagrams of a substrate in a semiconductor device structure provided in an embodiment of the present disclosure; Figures 10 to 12 Schematic diagrams of three partial cross-sectional structures of a semiconductor device structure provided by an embodiment of the present disclosure along a fourth cross-sectional direction DD1.

[0039] refer to Figures 1 to 12 The semiconductor device structure includes: a substrate 100 provided with a source region 110 and a drain region 120 spaced apart from each other; a gate structure 101 provided on the upper surface of the substrate 100; and a plurality of conductive pillars 102 respectively contacting the source region 110 and / or the drain region 120; wherein the gate structure 101 includes a gate 111 extending along a first direction X and a gate oxide layer 121 provided between the gate 111 and the substrate 100; the source region 110 and / or the drain region 120 has at least one recessed structure 104, and at least one conductive pillar 102 is provided in the recessed structure 104; among the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions at which two adjacent conductive pillars 102 contact the substrate 100 are different in height in the thickness direction of the substrate 100.

[0040] It should be noted that the at least one conductive pillar 102 is disposed in the recessed structure 104 in at least the following two situations:

[0041] In some embodiments, reference Figure 1 and Figure 2All the conductive pillars 102 are located in the recessed structure 104, but different conductive pillars 102 can be located in different areas of the same recessed structure 104 or in different recessed structures 104, so that among the multiple conductive pillars 102 that contact one of the source region 110 or the drain region 120, the positions where two adjacent conductive pillars 102 contact the substrate 100 are different in height in the thickness direction of the substrate 100.

[0042] In some embodiments, the substrate 100 further includes a shallow trench isolation structure 180 embedded therein. The region of the substrate 100 other than the source region 110, the drain region 120, and the shallow trench isolation structure 180 is a base plate 190. It will be understood that the channel region 130 described below is a portion of the thickness of the base plate 190 along the second direction Y.

[0043] In other embodiments, reference Figure 3 Part of the conductive pillars 102 can be located in the recessed structure 104, and other parts of the conductive pillars 102 can be located in an area of ​​the source region 110 or the drain region 120 where there is no recessed structure 104, so that among the multiple conductive pillars 102 that contact one of the source region 110 or the drain region 120, the positions where two adjacent conductive pillars 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100.

[0044] Furthermore, the thickness direction of the substrate 100 is the second direction Y, and the first direction X and the second direction Y constitute a reference plane. The fact that two adjacent conductive pillars 102 have different heights in the thickness direction of the substrate 100 at locations where they contact the substrate 100 means that, in the second direction, the height of the overlapping region of the orthographic projections of the two adjacent conductive pillars 102 on the reference plane is less than the height of at least one of the two adjacent conductive pillars 102. In other words, with the flat surface of the substrate 100 away from the gate structure 101 as the reference plane, the fact that two adjacent conductive pillars 102 have different heights in the thickness direction of the substrate 100 at locations where they contact the substrate 100 means that the vertical distances between the two adjacent conductive pillars 102 and the reference plane are different.

[0045] The positional relationship between the plurality of conductive pillars 102 and the source region 110 and the drain region 120 includes at least the following three situations:

[0046] In some embodiments, reference Figure 2 The source region 110 has at least one recessed structure 104 , and the plurality of conductive pillars 102 are all in contact with the source region 110 . The positions where two adjacent conductive pillars 102 contact the source region 110 are at different heights in the second direction Y.

[0047] In other embodiments, reference Figure 3The drain region 120 has at least one recessed structure 104 , and the plurality of conductive pillars 102 are all in contact with the drain region 120 . The positions where two adjacent conductive pillars 102 contact the drain region 120 are at different heights in the second direction Y.

[0048] In some other embodiments, reference Figure 4 The source region 110 and the drain region 120 each have at least one recessed structure 104. Some of the multiple conductive pillars 102 are in contact with the source region 110, while the remaining conductive pillars 102 are in contact with the drain region 120. Among the multiple conductive pillars 102 in contact with the source region 110, the locations where two adjacent conductive pillars 102 contact the source region 110 are at different heights in the second direction Y; and among the multiple conductive pillars 102 in contact with the drain region 120, the locations where two adjacent conductive pillars 102 contact the drain region 120 are at different heights in the second direction Y.

[0049] It should be noted that the positional relationship between the plurality of conductive pillars 102 and the recessed structure 104 will be described in detail later. To facilitate distinguishing the conductive pillars 102 in contact with the source region 110 and the drain region 120 , the conductive pillars 102 in contact with the source region 110 are referred to as first conductive pillars 112 , while the conductive pillars 102 in contact with the drain region 120 are referred to as second conductive pillars 122 .

[0050] It is understood that if either the source region 110 or the drain region 120 has a recessed structure 104, its surface will exhibit an uneven topography. Based on this, at least one of the multiple conductive pillars 102 contacting one of the source region 110 or the drain region 120 is disposed within the recessed structure 104. This facilitates ensuring that the positions at which two adjacent conductive pillars 102 contact the substrate 100, in the thickness direction of the substrate 100, are at different heights. That is, the conductive pillars 102 located on different regions of the surface of the substrate 100 are staggered in the thickness direction of the substrate 100. This facilitates reducing the area of ​​facing each other between adjacent conductive pillars 102, thereby reducing the coupling effect between different conductive pillars 102. Furthermore, while reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced, thereby increasing the integration density of the semiconductor device structure.

[0051] An embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0052] In some embodiments, reference Figure 2The source region 110 has a plurality of recessed structures 104 spaced apart along the first direction X. It is understood that in practical applications, the source region 110 may also have only one recessed structure 104 , and the plurality of conductive pillars 102 contacting the source region 110 are located at different positions of the recessed structure 104 .

[0053] In other embodiments, reference Figure 3 The drain region 120 has a plurality of recessed structures 104 spaced apart along the first direction X. It is understood that in practical applications, the drain region 120 may also have only one recessed structure 104 , and the plurality of conductive pillars 102 contacting the source region 110 are located at different positions of the recessed structure 104 .

[0054] It should be noted that, in order to clearly illustrate the concave structure 104, Figure 2 and Figure 3 The dotted line in FIG. 1 shows the approximate area of ​​the recessed structure 104. Figure 1 The recess structure 104 is not shown, and the shallow trench isolation structure 180 in the substrate 100 is not drawn.

[0055] In some other embodiments, reference Figure 4 , the source region 110 and the drain region 120 both have a plurality of recessed structures 104 spaced apart along the first direction X, with reference to Figures 2 to 4 , some of the multiple conductive pillars 102 are in contact with the source region 110, and the remaining conductive pillars 102 are in contact with the drain region 120. It is understood that in actual applications, the source region 110 and the drain region 120 may each have only one recessed structure 104, and the multiple conductive pillars 102 in contact with one of the source region 110 and the drain region 120 are located at different positions of the corresponding recessed structure 104.

[0056] It should be noted that, in order to clearly illustrate the concave structure 104, Figure 4 The approximate area of ​​the recessed structure 104 is indicated by an ellipse, and the recessed structure 104 is not filled and drawn in the same manner as the source region 110 or the drain region 120. Figure 4 The shallow trench isolation structure 180 in the substrate 100 is not depicted.

[0057] It will be appreciated that in each of the above-described embodiments, the conductive pillars 102 located in different regions of the surface of the substrate 100 can be staggered in the thickness direction of the substrate 100, i.e., the second direction Y. This allows the positions of two adjacent conductive pillars 102 in contact with the substrate 100, among the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120, to be at different heights in the thickness direction of the substrate 100. This helps reduce the facing area between adjacent conductive pillars 102, thereby reducing the coupling effect between different conductive pillars 102. Furthermore, based on the reduction in the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced to increase the integration density of the semiconductor device structure.

[0058] In some embodiments, reference Figure 5 The substrate 100 may further include a channel region 130 disposed between the source region 110 and the drain region 120 . The channel region 130 also has a plurality of recess structures 104 arranged at intervals along the first direction X.

[0059] The channel region 130 has a plurality of recessed structures 104 spaced apart along the first direction X, so that the surface of the channel region 130 exhibits an uneven topography. For example, the surface of the channel region 130 exhibits a wavy shape, and the wavy shape fluctuates along the first direction X. It is understood that, compared to a channel region with a flat surface, the channel region 130 provided in an embodiment of the present disclosure has a larger channel width, and does not increase the width of the channel region 130 along the first direction X. Therefore, without increasing the channel length of the channel region 130, it is beneficial to increase the width-to-length ratio of the channel region 130. The source region 110, the drain region 120, the channel region 130, and the gate structure 101 together constitute a transistor. The on-resistance of the transistor decreases as the width-to-length ratio of the channel region 130 increases, thereby facilitating an increase in the turn-on / off speed of the transistor, thereby improving the performance of the transistor without increasing the size of the transistor.

[0060] It should be noted that the channel width of the channel region 130 refers to the extension width of the uneven surface of the channel region 130 along the first direction X; and the channel length of the channel region 130 refers to the extension length of the uneven surface of the channel region 130 along the third direction Z. The third direction Z is the direction from the source region 110 to the drain region 120.

[0061] In some embodiments, reference Figure 6 and Figure 7 , a plurality of recessed structures 104 disposed on the substrate 100 are arranged in an array.

[0062] In some embodiments, reference Figure 6The plurality of recessed structures 104 in the substrate 100 are arranged in a quadrilateral arrangement, that is, the plurality of recessed structures 104 are arranged at intervals along the first direction X and also along the third direction Z. In one example, the first direction X and the third direction Z may be perpendicular to each other. In practical applications, the first direction X and the third direction Z may also intersect in other situations.

[0063] In other embodiments, reference Figure 7 , a plurality of recessed structures 104 spaced apart along the first direction X form a row of recessed groups 114, and the recessed structures 104 in two adjacent rows of recessed groups 114 are staggered. In one example, continue to refer to Figure 7 , the recess structures 104 in two adjacent rows of recess groups 114 are not arranged at intervals along the third direction Z. In the three adjacent rows of recess groups 114, the recess structures 104 in the two recess groups 114 on both sides of the middle row of recess groups 114 are arranged at intervals along the third direction Z. It should be noted that, Figure 7 This is only one case where the recess structures 104 in two adjacent rows of recess groups 114 are staggered. An embodiment of the present disclosure does not limit the specific case of the staggered arrangement of the recess structures 104 in two adjacent rows of recess groups 114. It only needs to ensure the staggering, and the specific degree of staggering is not limited.

[0064] It should be noted that Figure 7 The plurality of recess structures 104 framed by a dotted frame constitutes a row of recess groups 114 , and only two dotted frames are used to illustrate two adjacent recess groups 114 .

[0065] In the above two embodiments, the multiple recessed structures 104 arranged in an array and provided in the substrate 100 may refer to the multiple recessed structures 104 provided only in the source region 110 and the channel region 130; or, may refer to the multiple recessed structures 104 provided only in the drain region 120 and the channel region 130; or, may refer to the multiple recessed structures 104 provided in the source region 110, the drain region 120 and the channel region 130.

[0066] In this way, the width-to-length ratio of the channel region 130 is increased while reducing the coupling effect between adjacent conductive pillars 102 , thereby improving the electrical performance of the semiconductor device structure.

[0067] It should be noted that, in order to clearly illustrate the arrangement of the plurality of recessed structures 104 in the substrate 100, Figure 6 and Figure 7 The different filling methods used for the recessed structure 104 and the substrate 100 are drawn, and Figure 6 and Figure 7 The source region 110 of the substrate 100 is not aligned with the source region 110 (refer to Figure 5 ), the drain region 120 (reference Figure 5 ) and the channel region 130 (reference Figure 5 ) to distinguish. In addition, Figure 6 and Figure 7 The recessed structure 104 is schematically shown in a rectangle. It is understandable that the top view of the recessed structure 104 has various shapes. The specific shape of the recessed structure 104 will be described later.

[0068] In some embodiments, reference Figure 8 and Figure 12 The substrate 100 may further include a channel region 130 disposed between the source region 110 and the drain region 120 . A groove 105 extending along the first direction X is disposed in the substrate 100 . The groove 105 is at least partially located in the channel region 130 .

[0069] It should be noted that Figure 8 and Figure 12 In the figure, the groove 105 is not only located in the channel region 130, but also located in the portion of the source region 110 in contact with the channel region 130 and the portion of the drain region 120 in contact with the channel region 130. In actual applications, the groove 105 may be located only in the channel region 130, or only in the channel region 130 and the portion of the source region 110 in contact with the channel region 130, or only in the channel region 130 and the portion of the drain region 120 in contact with the channel region 130.

[0070] It should be noted that Figure 8 The thicker dotted line in FIG. 1 shows the approximate area where the groove 105 is located. Figure 12 The dotted line in the figure indicates the approximate area where the groove 105 is located.

[0071] In other embodiments, reference Figure 9 The substrate 100 may further include a channel region 130 disposed between the source region 110 and the drain region 120 . The substrate 100 may include a plurality of grooves 105 extending along the first direction X. The plurality of grooves 105 are arranged at intervals along the third direction Z, and each groove 105 is at least partially located in the channel region 130 .

[0072] It should be noted that Figure 9 The groove 105 is schematically shown as a long rectangle, and the groove 105 and the channel region 130 without the groove 105 are drawn in different ways. Figure 9 The number of grooves 105 is 3 as an example. In actual applications, the number of grooves 105 can be adjusted according to actual needs.

[0073] It should be noted that an embodiment of the present disclosure does not limit the number of recesses 105 in the channel region 130 .

[0074] It is understandable that Figure 8 and Figure 9 In the example shown, the channel region 130 has at least one groove 105 extending along the second direction Y. Thus, the surface of the channel region 130 exhibits an uneven topography. For example, the surface of the channel region 130 exhibits a wave shape, and the wave fluctuates along the third direction Z. Thus, compared to a channel region with a flat surface, the channel region 130 provided in an embodiment of the present disclosure has a longer channel length without increasing the overall layout area of ​​the channel region 130 in the semiconductor device structure. Furthermore, the smaller the channel length of the channel region 130 in a transistor, the more severe the mismatch between identical transistors. Therefore, increasing the channel length of the channel region 130 reduces the mismatch of the transistors.

[0075] In some embodiments, reference Figure 10 The source region 110 has a first portion 110a close to the channel region 130 and a second portion 110b away from the channel region 130. In the direction from the source region 110 to the drain region 120, that is, along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases.

[0076] It can be understood that the source region 110 of the transistor contains doped ions, and along the third direction Z, the thickness of the first part 110a in the second direction Y gradually decreases. The number of doped ions in the first part 110a closer to the channel region 130 is smaller, so as to suppress the hot carrier effect and thus improve the performance of the transistor.

[0077] In some embodiments, along the second direction Y, an average thickness of the second portion 110 b is greater than a maximum thickness of the first portion 110 a .

[0078] In other embodiments, reference Figure 11 The drain region 120 has a third portion 120a close to the channel region 130 and a fourth portion 120b away from the channel region 130. In the direction from the source region 110 to the drain region 120, that is, along the third direction Z, the thickness of the third portion 120a in the second direction Y gradually increases.

[0079] It can be understood that the drain region 120 of the transistor contains doped ions, and along the third direction Z, the thickness of the third part 120a in the second direction Y gradually increases. The number of doped ions in the third part 120a closer to the channel region 130 is smaller, so as to suppress the hot carrier effect and thus improve the performance of the transistor.

[0080] In some embodiments, along the second direction Y, an average thickness of the fourth portion 120 b is greater than a maximum thickness of the third portion 120 a .

[0081] In some other embodiments, reference Figure 12The source region 110 includes a first portion 110a close to the channel region 130 and a second portion 110b remote from the channel region 130. The drain region 120 includes a third portion 120a close to the channel region 130 and a fourth portion 120b remote from the channel region 130. Along the third direction Z, the thickness of the first portion 110a gradually decreases in the second direction Y, while the thickness of the third portion 120a gradually increases in the second direction Y. In this manner, both the first portion 110a and the third portion 120a can suppress hot carrier effects, thereby further improving transistor performance.

[0082] In some embodiments, along the second direction Y, the average thickness of the second portion 110 b is greater than the maximum thickness of the first portion 110 a , and the average thickness of the second portion 110 b is greater than the maximum thickness of the first portion 110 a .

[0083] It should be noted that Figures 10 to 12 In the figures, a dotted line is used to indicate the approximate area of ​​the groove 105, another dotted line is used to indicate the approximate area of ​​the channel region 130, and another dotted line is used to indicate the first part 110a and the second part 110b in the source region 110 and the third part 120a and the fourth part 120b in the drain region 120.

[0084] In the above embodiment, the second direction Y is the thickness extension direction of the gate 111 , that is, the thickness extension direction of the substrate 100 .

[0085] It should be noted that the doping type of the doping ions in the source region 110 and the drain region 120 can be the same, for example, both are first doping ions, and the channel region 130 has second doping ions that are different from the first doping ions. One of the first doping ions and the second doping ions is a P-type doping ion, and the other is an N-type doping ion. Specifically, the N-type doping ion is at least one of arsenic ions, phosphorus ions, or antimony ions; and the P-type doping ion is at least one of boron ions, indium ions, or gallium ions.

[0086] The first portion 110 a and the third portion 120 a are described in detail below.

[0087] In some embodiments, reference Figure 10 Along the second direction Y, the first portion 110 a has a first side a and a second side b opposite to each other, the first side a is inclined toward the second side b, and the second side b is inclined toward the first side a. In other words, the source region 110 has a tip toward the channel region 130 .

[0088] In other embodiments, reference Figure 11Along the second direction Y, the third portion 120 a has a third side c and a fourth side d opposite to each other, the third side c is inclined toward the fourth side d, and the fourth side d is inclined toward the third side c. In other words, the drain region 120 has a tip toward the channel region 130 .

[0089] In some other embodiments, reference Figure 12 Along the second direction Y, the first portion 110a has a first side a and a second side b that are opposite to each other, and the third portion 120a has a third side c and a fourth side d that are opposite to each other, with the third side c being inclined toward the fourth side d. Specifically, the first side a is inclined toward the second side b, the second side b is inclined toward the first side a, the third side c is inclined toward the fourth side d, and the fourth side d is inclined toward the third side c. It should be noted that the same or corresponding parts as those in the previous embodiment are not repeated here.

[0090] It should be noted that Figure 10 and Figure 12 Only one situation in which "along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases" is illustrated. Figure 11 and Figure 12 Only one situation is illustrated in which "along the third direction Z, the thickness of the third part 120a in the second direction Y gradually increases". In actual applications, an embodiment of the present disclosure does not limit the manner in which the thickness of the first part 110a in the second direction Y gradually decreases along the third direction Z, nor does it limit the manner in which the thickness of the third part 120a in the second direction Y gradually increases along the third direction Z.

[0091] In some embodiments, reference Figures 10 to 12 At least part of the gate 111 is located in the groove 105, the first direction X and the second direction Y constitute a reference plane, and in the second direction Y, the length of the overlapping area between the gate 111 and the orthographic projection of any conductive pillar 102 on the reference plane is less than the thickness of the gate 111, wherein the second direction Y is the thickness extension direction of the gate 111.

[0092] It can be understood that, in the second direction Y, the length of the overlapping area between the orthographic projections of the gate 111 and any conductive pillar 102 on the reference plane is less than the thickness of the gate 111. This facilitates reducing the area of ​​direct contact between the gate 111 and any conductive pillar 102 by disposing at least a portion of the gate 111 in the recess 105, thereby facilitating reduced coupling effects between the gate 111 and any conductive pillar 102. Furthermore, based on the reduced coupling effects between the gate 111 and any conductive pillar 102, the spacing between the gate 111 and the conductive pillar 102 can be further reduced, thereby increasing the integration density of the semiconductor device structure.

[0093] In other words, taking the flat surface of the side of the substrate 100 away from the gate structure 101 as the reference plane, in the second direction Y, the length of the overlapping area between the gate 111 and the orthographic projection of any conductive pillar 102 on the reference plane is less than the thickness of the gate 111, which means that: the minimum vertical distance between the gate 111 and the reference plane is less than the minimum vertical distance between any conductive pillar and the reference plane.

[0094] In some embodiments, reference Figure 2 、 Figure 3 、 Figure 5 5b, and Figures 10 to 12 The gate 111 and the gate oxide layer 121 both have shapes that match the surface of the channel region 130. In other words, along the second direction Y, the gate 111 and the gate oxide layer 121 both have uniform thicknesses, i.e., the gate structure 101 as a whole has a uniform thickness. This helps improve the gate 111's ability to control whether the channel region 130 in the transistor is turned on or off, thereby improving transistor performance.

[0095] The positional relationship between the plurality of conductive pillars 102 and the recessed structure 104 is described in detail below.

[0096] It is understandable that the conductive pillar 102 contacting the source region 110 is the first conductive pillar 112 , and the conductive pillar 102 contacting the drain region 120 is the second conductive pillar 122 , with the flat surface of the substrate 100 away from the gate structure 101 being the reference plane.

[0097] In some embodiments, reference Figure 2 Among the multiple first conductive pillars 112 spaced apart from each other and in contact with the source region 110, the minimum vertical distance between one of two adjacent first conductive pillars 112 and the reference plane is a first distance, and the minimum vertical distance between the other first conductive pillar 112 and the reference plane is a second distance. The first distance and the second distance are different to ensure that the positions where the two adjacent first conductive pillars 112 contact the source region 110 are at different heights in the second direction Y.

[0098] In other embodiments, reference Figure 3 Among the multiple second conductive pillars 122 spaced apart from each other and in contact with the drain region 120, the minimum vertical distance between one of two adjacent second conductive pillars 122 and the reference plane is a third distance, and the minimum vertical distance between the other second conductive pillar 122 and the reference plane is a fourth distance. The third distance is different from the fourth distance to ensure that the positions where the two adjacent second conductive pillars 122 contact the drain region 120 are at different heights in the second direction Y.

[0099] In the above various embodiments, whether it is the recessed structure 104 or the groove 105, in a cross section parallel to the second direction Y, the cross-sectional shape of the recessed structure 104 or the groove 105 can be as follows: Figure 2 、 Figure 3 、 Figure 5 5b, and Figures 10 to 12 The shape shown is an arc. In actual applications, the cross-sectional shape of the recessed structure 104 or the groove 105 may also be a trapezoid, a rectangle, or a sawtooth shape.

[0100] It should be noted that the semiconductor device structure provided in an embodiment of the present disclosure can be applied to the sensing amplifier circuit in DRAM. By improving the performance of transistors in the semiconductor device structure and reducing the coupling between different conductive columns, the size of the semiconductor device structure can be further reduced without affecting the performance of the semiconductor device structure, that is, the semiconductor device structure can be scaled, and the sensing amplifier circuit can be further scaled without affecting its performance.

[0101] In summary, the surface of the source region 110 and / or the drain region 120 exhibits an uneven topography. Based on this, the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120 are disposed on the uneven topography, i.e., at least one conductive pillar 102 is disposed within the recessed structure 104. This advantageously ensures that, among the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions at which two adjacent conductive pillars 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100. In other words, the conductive pillars 102 located in different regions of the surface of the substrate 100 are staggered in the thickness direction of the substrate 100. This advantageously reduces the area of ​​facing each other between adjacent conductive pillars 102, thereby reducing the coupling effect between different conductive pillars 102. Furthermore, while reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced, thereby increasing the integration density of the semiconductor device structure.

[0102] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The method for manufacturing a semiconductor device structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 13 A flow chart of a method for manufacturing a semiconductor device structure according to another embodiment of the present disclosure; Figures 14 to 25 This is a structural schematic diagram corresponding to each step in a method for manufacturing a semiconductor device structure provided by another embodiment of the present disclosure.

[0103] It should be noted that, in order to facilitate description and clearly illustrate the steps of the semiconductor device structure manufacturing method, the Figures 14 to 25In addition, the same or corresponding parts of the above embodiments will not be described in detail here.

[0104] refer to Figures 1 to 25 , a method for manufacturing a semiconductor device structure comprises the following steps:

[0105] S101: Reference Figure 13 and Figure 14 , providing a substrate 140 , the substrate 140 includes an initial substrate 150 and a first doping region 160 and a second doping region 170 disposed in the initial substrate 150 .

[0106] In some embodiments, different dopant ions are implanted into different regions of the substrate 140, so that the dopant ions in the first doping region 160 and the second doping region 170 are of the same doping type, for example, first dopant ions, and the dopant ions in at least a portion of the initial substrate 150 other than the first doping region 160 and the second doping region 170 are second dopant ions. One of the first dopant ion and the second dopant ion is a P-type dopant ion, and the other is an N-type dopant ion.

[0107] It can be understood that the first doped region 160 is used to form the source region 110 later, the second doped region 170 is used to form the drain region 120 later, and the initial substrate 150 is used to form the channel region 130 later.

[0108] S102: Reference Figure 13 and Figure 15 A mask layer 106 is formed on the substrate 140 , and the mask layer 106 has at least one first opening 116 facing the first doping region 160 and / or the second doping region 170 to expose a portion of the surface of the first doping region 160 and / or the second doping region 170 .

[0109] The mask layer 106 will be described in detail below.

[0110] In some embodiments, reference Figure 15 The mask layer 106 facing the first doping region 160 has a plurality of first openings 116 spaced apart along the first direction X. The first doping region 160 exposed by the plurality of first openings 116 is subsequently processed to form Figure 1 The source region 110 is shown. It is understood that, in practical applications, the mask layer 106 directly facing the first doped region 160 may also have only one first opening 116 .

[0111] It should be noted that Figure 15The plurality of first openings 116 in the mask layer 106 directly opposite the first doped region 160 are not only spaced apart along the first direction X, but also spaced apart along the third direction Z. In practical applications, the plurality of first openings 116 in the mask layer 106 directly opposite the first doped region 160 may be spaced apart only along the first direction X.

[0112] In other embodiments, reference Figure 16 The mask layer 106 facing the second doping region 170 has a plurality of first openings 116 arranged at intervals along the first direction X. Subsequently, the second doping region 170 exposed by the plurality of first openings 116 is processed to form Figure 3 The drain region 120 is shown. It is understood that, in practical applications, the mask layer 106 directly facing the second doped region 170 may also have only one first opening 116 .

[0113] It should be noted that Figure 16 The plurality of first openings 116 in the mask layer 106 directly facing the second doped region 170 are not only spaced apart along the first direction X, but also spaced apart along the third direction Z. In practical applications, the plurality of first openings 116 in the mask layer 106 directly facing the second doped region 170 may be spaced apart only along the first direction X.

[0114] In some other embodiments, reference Figure 17 The mask layer 106 facing the first doping region 160 and the second doping region 170 has a plurality of first openings 116 arranged at intervals along the first direction X. Subsequently, the first doping regions 160 and the second doping regions 170 exposed by the plurality of first openings 116 are processed to form Figure 4 The source region 110 and the drain region 120 are shown. It is understood that in actual applications, the mask layer 106 facing the first doped region 160 may also have only one first opening 116 , and the mask layer 106 facing the second doped region 170 may also have only one first opening 116 .

[0115] It should be noted that Figure 17 The plurality of first openings 116 in the mask layer 106 directly opposite the first doping region 160 and the second doping region 170 are not only spaced apart along the first direction X, but also spaced apart along the third direction Z. In practical applications, the plurality of first openings 116 in the mask layer 106 directly opposite the first doping region 160 and the second doping region 170 may be spaced apart only along the first direction X.

[0116] In some embodiments, reference Figure 18The mask layer 106 has a middle portion 126 directly between the first doping region 160 and the second doping region 170, and the middle portion 126 also has a plurality of first openings 116 arranged at intervals along the first direction X to expose a portion of the surface of the initial substrate 150 located between the first doping region 160 and the second doping region 170. It can be understood that the middle portion 126 in the mask layer 106 and the channel region 130 (refer to Figure 5 ) is opposite, that is, the orthographic projection of the middle portion 126 on the reference plane covers the orthographic projection of the channel region 130 on the reference plane, so that after the exposed substrate 140 is processed based on the first opening 116, the following Figure 1 The source region 110 shown and Figure 3 On the basis of the drain region 120 shown in FIG. 1 , a structure as shown in FIG. 1 may be further formed. Figure 5 A channel region 130 is shown.

[0117] It should be noted that Figure 18 The plurality of first openings 116 in the middle portion 126 are not only spaced apart along the first direction X, but also spaced apart along the third direction Z. In practical applications, the plurality of first openings 116 in the middle portion 126 may be spaced apart only along the first direction X.

[0118] In some embodiments, the plurality of first openings 116 of the mask layer 106 are arranged in an array.

[0119] In some embodiments, reference Figure 19 The plurality of first openings 116 of the mask layer 106 are arranged in a quadrilateral pattern, that is, the plurality of first openings 116 are arranged at intervals along the first direction X and also at intervals along the third direction Z. Subsequently, the substrate 140 exposed by the plurality of first openings 116 is processed to form Figure 6 The substrate 100 is shown.

[0120] In other embodiments, reference Figure 20 , a plurality of first openings 116 spaced apart along the first direction X form a column of first opening groups 146, and the first openings 116 in two adjacent columns of first opening groups 146 are staggered. In one example, continue to refer to Figure 20 , the first openings 116 in two adjacent columns of first opening groups 146 are not arranged at intervals along the third direction Z. In the three adjacent columns of first opening groups 146, the first openings 116 in the two groups of first opening groups 146 on both sides of the first opening group 146 in the middle column are arranged at intervals along the third direction Z. It should be noted that Figure 20 This is only one case where the first openings 116 in two adjacent columns of the first opening groups 146 are staggered. An embodiment of the present disclosure does not limit the specific case of the staggered arrangement of the first openings 116 in two adjacent columns of the first opening groups 146. It only needs to ensure the staggering, and the specific degree of the staggering is not limited.

[0121] It should be noted that Figure 20 The plurality of first openings 116 framed by a dotted frame constitutes a row of first opening groups 146 , and only two dotted frames are used to illustrate two adjacent first opening groups 146 .

[0122] In the above two embodiments, the multiple first openings 116 arranged in an array and provided on the substrate 140 may refer to the multiple first openings 116 provided only in the mask layer 106 and the middle portion 126 opposite the first doping region 160; or, may refer to the multiple first openings 116 provided only in the mask layer 106 and the middle portion 126 opposite the second doping region 170; or, may refer to the multiple first openings 116 provided in the mask layer 106 and the middle portion 126 opposite the first doping region 160 and the second doping region 170.

[0123] It should be noted that the mask layer 106 directly opposite the first doping region 160 refers to the mask layer 106 whose orthographic projection on the reference plane coincides with the orthographic projection of the first doping region 160 on the reference plane; the mask layer 106 directly opposite the second doping region 170 refers to the mask layer 106 whose orthographic projection on the reference plane coincides with the orthographic projection of the second doping region 170 on the reference plane.

[0124] In some embodiments, reference Figure 21 The mask layer 106 has a middle portion 126 (referring to Figure 18 ), and the middle portion 126 has a second opening 136 extending along the first direction X. It is understood that the second opening 136 exposes at least a portion of the substrate 140 facing the middle portion 126. The substrate 140 exposed by the second opening 136 is subsequently processed to form Figure 8 A channel region 130 is shown.

[0125] In some embodiments, continue to refer to Figure 21 On the basis that the middle portion 126 has a second opening 136 extending along the first direction X, the second opening 136 can also expose a portion of the surface of the first doping region 160 and a portion of the surface of the second doping region 170. The substrate 140 exposed by the second opening 136 is subsequently processed to form Figure 8 or Figure 12 A channel region 130 is shown.

[0126] It is understandable that in the step of processing the substrate 140 exposed by the second opening 136 , the first doping region 160 , the second doping region 170 and a portion of the initial substrate 150 between the first doping region 160 and the second doping region 170 will all be processed.

[0127] It should be noted that, on the basis of the second opening 136 exposing the substrate 140 for forming the channel region 130 later, the second opening 136 may also expose a portion of the surface of the first doping region 160 or a portion of the surface of the second doping region 170 to form Figure 10 or Figure 11 The substrate 100 is shown.

[0128] In other embodiments, reference Figure 22 The middle portion 126 may have a plurality of second openings 136 extending along the first direction X, the plurality of second openings 136 being arranged at intervals along the third direction Z, and each second opening 136 exposing a portion of the substrate 140 facing the middle portion 126. The substrate 140 exposed by the plurality of second openings 136 is subsequently processed to form Figure 9 A channel region 130 is shown.

[0129] It should be noted that, in one embodiment of the present disclosure, there is no limitation on the number of the second openings 136 in the middle portion 126 of the mask layer 106 .

[0130] In some embodiments, in conjunction with reference Figure 21 and Figure 23 After forming the mask layer 106 and before subsequently forming the oxide layer 107, the method for manufacturing the semiconductor device structure may further include: performing patterning on the substrate 140 using the mask layer 106 as a mask, so that the surface of the remaining substrate 140 exposed by the first opening 116 is recessed toward the interior of the substrate 140.

[0131] In some embodiments, the mask layer 106 has a first opening 116, and patterning the substrate 140 using the mask layer 106 as a mask means: patterning the substrate 140 exposed by the first opening 116 through the first opening 116, so that the recessed degree of the recessed structure 104 subsequently formed based on the remaining substrate 140 exposed by the first opening 116 is greater, thereby facilitating further increasing the width of the subsequently formed channel region 130 along the first direction X. Therefore, without increasing the channel length of the channel region 130, it is beneficial to further increase the width-to-length ratio of the channel region 130. In addition, it is also beneficial to further reduce the facing area between adjacent conductive pillars 102 formed subsequently, so as to further reduce the coupling effect between adjacent conductive pillars 102.

[0132] In other embodiments, in addition to the first opening 116 in the mask layer 106, the mask layer 106 further comprises a second opening 136. Patterning the substrate 140 using the mask layer 106 as a mask further comprises: patterning the portion of the substrate 140 exposed by the second opening 136 through the second opening 136, such that the recess 105 subsequently formed based on the remaining portion of the substrate 140 exposed by the second opening 136 is more deeply recessed, thereby further increasing the length of the subsequently formed channel region 130 along the third direction Z. This further reduces the channel length modulation effect of the transistor and further reduces the facing area between the subsequently formed gate 111 and any conductive pillar 102, thereby further reducing the coupling effect between the gate 111 and any conductive pillar 102.

[0133] S103: Combined with reference Figure 21 and Figure 24 or Figure 23 and Figure 24 , the substrate 140 is oxidized based on the mask layer 106 to form an oxide layer 107 .

[0134] In some embodiments, the mask layer 106 has a first opening 116 . Oxidation of the substrate 140 based on the mask layer 106 refers to oxidation of the substrate 140 exposed by the first opening 116 through the first opening 116 . It is understandable that an oxide layer 107 is formed in each first opening 116 .

[0135] In other embodiments, based on the first opening 116 in the mask layer 106, the mask layer 106 further has a second opening 136. Oxidation treatment of the substrate 140 based on the mask layer 106 further includes: oxidation treatment of the substrate 140 exposed by the second opening 136 through the second opening 136. It is understood that an oxide layer 107 is formed in each second opening 136.

[0136] It should be noted that Figure 24 This is only an example of “oxidizing the substrate 140 based on the mask layer 106 to form the oxide layer 107”. The various mask layers 106 described in the above embodiments are applicable to this step to form multiple oxide layers 107 of various styles. Figure 24 The shape of the oxide layer 107 shown in the figure is only an example. In actual applications, the shape of the oxide layer 107 can be adjusted according to actual needs depending on the mold oxidation process parameters.

[0137] S104: Binding residue Figure 24 and Figure 12, the mask layer 106 and the oxide layer 107 are removed, so that the source region 110 and / or the drain region 120 has at least one recessed structure 104 , the remaining initial substrate 150 is the substrate 100 , the remaining first doping region 160 is the source region 110 , and the remaining second doping region 170 is the drain region 120 .

[0138] In some embodiments, in the step of forming the oxide layer 107, a portion of the first doped region 160 will be oxidized as part of the oxide layer 107. In the step of removing the oxide layer 107, the oxidized first doped region 160 will also be removed, so that when the remaining first doped region 160 that has not been oxidized and removed serves as the source region 110, the source region 110 has a first portion 110a close to the channel region 130 and a second portion 110b away from the channel region 130, and along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases.

[0139] In other embodiments, in the step of forming the oxide layer 107, part of the second doped region 170 will be oxidized as part of the oxide layer 107. Then, in the step of removing the oxide layer 107, the oxidized second doped region 170 will also be removed, so that when the remaining second doped region 170 that has not been oxidized and removed serves as the drain region 120, the drain region 120 has a third portion 120a close to the channel region 130 and a fourth portion 120b away from the channel region 130, and along the third direction Z, the thickness of the third portion 120a in the second direction Y gradually increases.

[0140] It should be noted that, in another embodiment of the present disclosure, Figure 12 The substrate 100 shown is used as an example to explain step S104 in detail. In practical applications, various substrates 100 described in the above embodiments can be formed by this step S104. Figure 12 The semiconductor device structure shown is described in detail as an example.

[0141] S105: Reference Figure 25 , based on the substrate 100, a length is formed along the first direction X (see Figure 1 The gate structure 101 includes a gate 111 extending along a first direction X and a gate oxide layer 121 disposed between the gate 111 and the substrate 100.

[0142] S106: Reference Figure 25 A dielectric layer 108 is formed to cover at least the source region 110 and the drain region 120. The dielectric layer 108 has a plurality of vias 118. It is understood that the vias 118 are used to expose a portion of the surface of the source region 110 or the drain region 120, and the conductive pillars 102 are subsequently formed in the vias 118.

[0143] S107: Combined with reference Figure 25 and Figure 12 Conductive pillars 102 are formed in the plurality of vias 118, with at least one conductive pillar 102 disposed within the recessed structure 104. Among the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions at which two adjacent conductive pillars 102 contact the substrate 100 are at different heights along the thickness direction of the substrate 100. It is understood that there is a one-to-one correspondence between the vias 118 and the conductive pillars 102.

[0144] In summary, in a semiconductor device structure formed by a manufacturing method provided by another embodiment of the present disclosure, the surface of the source region 110 and / or the drain region 120 exhibits an uneven topography. Based on this, the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120 are disposed on the uneven topography, i.e., at least one conductive pillar 102 is disposed within the recessed structure 104. This advantageously ensures that, among the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions at which two adjacent conductive pillars 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100. In other words, the conductive pillars 102 located in different regions of the surface of the substrate 100 are staggered in the thickness direction of the substrate 100. This advantageously reduces the area of ​​facing each other between adjacent conductive pillars 102, thereby reducing the coupling effect between different conductive pillars 102. Furthermore, while reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced, thereby increasing the integration density of the semiconductor device structure.

[0145] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor device structure, characterized in that: include: A substrate having a source region and a drain region spaced apart from each other; a gate structure disposed on the upper surface of the substrate; and a plurality of conductive pillars respectively contacting the source region and / or the drain region; In which, the gate structure includes a gate whose length extends along a first direction and a gate oxide layer arranged between the gate and the substrate; the source region and / or the drain region has at least one recessed structure, and at least one conductive column is arranged in the recessed structure; among the multiple conductive columns contacting one of the source region or the drain region, the positions at which two adjacent conductive columns contact the substrate are different in height in the thickness direction of the substrate.

2. The semiconductor device structure according to claim 1, wherein: The source region and / or the drain region has a plurality of recessed structures arranged at intervals along the first direction.

3. The semiconductor device structure according to claim 2, wherein: The substrate further includes a channel region disposed between the source region and the drain region, and the channel region also has a plurality of the recessed structures spaced apart along the first direction.

4. The semiconductor device structure according to claim 3, wherein: The plurality of recessed structures disposed on the substrate are arranged in an array.

5. The semiconductor device structure according to claim 4, wherein: A plurality of the recessed structures spaced apart along the first direction form a column of recessed groups, and the recessed structures in two adjacent columns of the recessed groups are staggered.

6. The semiconductor device structure according to claim 1, wherein: The substrate further includes a channel region disposed between the source region and the drain region. A groove having a length extending along the first direction is disposed in the substrate, and the groove is at least partially located in the channel region.

7. The semiconductor device structure according to claim 6, wherein: The source region comprises a first portion close to the channel region and a second portion away from the channel region, and a thickness of the first portion in the second direction gradually decreases along a direction from the source region to the drain region; and / or, The drain region comprises a third portion close to the channel region and a fourth portion away from the channel region, and a thickness of the third portion gradually increases in the second direction along a direction from the source region to the drain region; The second direction is a thickness extension direction of the gate.

8. The semiconductor device structure according to claim 7, wherein: In the second direction, the first portion has a first side and a second side opposite to each other, the first side is inclined toward the second side, and the second side is inclined toward the first side; and / or, In the second direction, the third portion has a third side and a fourth side opposite to each other, the third side is inclined toward the fourth side, and the fourth side is inclined toward the third side.

9. The semiconductor device structure according to claim 6, wherein: At least part of the gate is located in the groove, the first direction and the second direction constitute a reference plane, and in the second direction, the length of the overlapping area of ​​the gate and the positive projection of any of the conductive pillars on the reference plane is less than the thickness of the gate, wherein the second direction is the thickness extension direction of the gate.

10. The semiconductor device structure according to any one of claims 3 to 9, characterized in that: The gate and the gate oxide layer both have shapes matching the surface of the channel region.

11. A method for manufacturing a semiconductor device structure, characterized in that: include: Providing a substrate, the substrate comprising an initial substrate and a first doping region and a second doping region disposed in the initial substrate; forming a mask layer on the substrate, wherein the mask layer has at least one first opening directly opposite to the first doping region and / or the second doping region to expose a portion of a surface of the first doping region and / or the second doping region; performing an oxidation treatment on the substrate based on the mask layer to form an oxide layer; removing the mask layer and the oxide layer, leaving the remaining initial substrate as the substrate, the remaining first doped region as the source region, and the remaining second doped region as the drain region, so that the source region and / or the drain region has at least one recessed structure; forming a gate structure having a length extending along a first direction based on the substrate; forming a dielectric layer covering at least the source region and the drain region, wherein the dielectric layer has a plurality of via holes; Conductive pillars are formed in the plurality of vias, and at least one of the conductive pillars is disposed in the recessed structure; wherein, among the plurality of conductive pillars contacting one of the source region or the drain region, positions at which two adjacent conductive pillars contact the substrate have different heights in the thickness direction of the substrate.

12. The manufacturing method according to claim 11, characterized in that: The mask layer directly facing the first doping region and / or the second doping region has a plurality of first openings arranged at intervals along the first direction.

13. The manufacturing method according to claim 12, characterized in that: The mask layer has a middle portion facing the first doping region and the second doping region, and the middle portion also has a plurality of first openings arranged at intervals along the first direction to expose a portion of the surface of the initial substrate located between the first doping region and the second doping region.

14. The manufacturing method according to claim 13, characterized in that: The plurality of first openings of the mask layer are arranged in an array.

15. The manufacturing method according to claim 11, characterized in that: The mask layer has a middle portion facing the first doping region and the second doping region, and the middle portion has a second opening extending along the first direction.

16. The manufacturing method according to claim 14, characterized in that: The second opening further exposes a portion of the surface of the first doping region and a portion of the surface of the second doping region.

17. The manufacturing method according to any one of claims 11 to 16, characterized in that: After forming the mask layer and before forming the oxide layer, the method further includes: The substrate is patterned using the mask layer as a mask, so that the surface of the substrate remaining exposed by the first opening is recessed toward the interior of the substrate.

Images