Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device, the display substrate comprises a driving circuit layer arranged on a substrate, and a pixel driving circuit comprises a driving transistor, a second switch transistor and a capacitor; the driving transistor comprises a first active layer, the second switch transistor comprises a third active layer, the capacitor comprises a second pole plate, the third active layer is arranged on the side, away from the substrate, of the first active layer, and the second pole plate is arranged between the first active layer and the third active layer. The second pole plate is connected with the second end of the first active layer through a first via hole, the second pole plate forms a concave area in the first via hole, a dielectric layer is arranged on one side, far away from the substrate, of the second pole plate, and at least part of the dielectric layer is arranged in the concave area; and the orthographic projection of the third active layer on the substrate is overlapped with the orthographic projection of the concave area on the substrate.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] On the one hand, the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate, the driving circuit layer includes at least a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, a second switching transistor and a capacitor; the driving transistor includes a first active layer, the second switching transistor includes a third active layer, the capacitor includes a second electrode plate, the third active layer is arranged on a side of the first active layer away from the substrate, the second electrode plate is arranged between the first active layer and the third active layer, the second electrode plate is connected to the second end of the first active layer through a first via hole, the second electrode plate forms a recessed area in the first via hole, a dielectric layer is arranged on a side of the second electrode plate away from the substrate, at least a portion of the dielectric layer is arranged in the recessed area, and an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the recessed area on the substrate.

[0005] In an exemplary embodiment, a surface of the dielectric layer away from the substrate and a surface of the second electrode plate away from the substrate form a plane.

[0006] In an exemplary embodiment, an orthographic projection of the third active layer on the substrate includes an orthographic projection of the recessed region on the substrate.

[0007] In an exemplary embodiment, an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the first active layer on the substrate.

[0008] In an exemplary embodiment, the first via is polygonal in shape, and the length of at least one side of the first via is less than or equal to 1 micron; or, the first via is circular in shape, and the diameter of the first via is less than or equal to 1 micron; or, the first via is elliptical in shape, and the length of the short axis of the first via is less than or equal to 1 micron.

[0009] In an exemplary embodiment, the driving transistor also includes a second gate, which is arranged between the first active layer and the second electrode plate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate, the capacitor includes a first electrode plate, the second gate serves as the first electrode plate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

[0010] In an exemplary embodiment, the driving transistor further includes a first gate, the first gate is located on a side of the first active layer close to the substrate, and an orthographic projection of the first gate on the substrate overlaps with an orthographic projection of the first active layer on the substrate.

[0011] In an exemplary embodiment, the pixel driving circuit further includes a first power line, the first power signal line is disposed on a side of the third active layer away from the substrate, and the first power signal line is connected to a first end of the first active layer through a fifth via hole.

[0012] In an exemplary embodiment, the second switch transistor further includes a third gate, the third gate is located between the third active layer and the second electrode plate, and an orthographic projection of the third gate on the substrate overlaps with an orthographic projection of the third active layer on the substrate.

[0013] In an exemplary embodiment, it also includes a light-emitting structure layer arranged on the side of the driving circuit layer away from the substrate, the light-emitting structure layer includes a light-emitting device, and the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate. The pixel driving circuit also includes a second connecting electrode, the second connecting electrode is located between the third active layer and the first electrode, at least a portion of the second connecting electrode is in contact with a surface of the second end of the third active layer away from the substrate, the second connecting electrode is connected to the second electrode plate through a sixth via hole, and the second connecting electrode is connected to the first electrode.

[0014] In an exemplary embodiment, the pixel driving circuit further includes a sensing signal line located on a side of the third active layer away from the substrate, and at least a portion of the sensing signal line contacts a surface of the first end of the third active layer away from the substrate.

[0015] In an exemplary embodiment, the pixel driving circuit also includes a first switching transistor, the first switching transistor includes a second active layer, the second active layer is located between the second electrode plate and the third active layer, a first transfer electrode is provided on the surface of the second active layer close to the substrate side, the first transfer electrode is in contact with the second active layer, a second gate is provided on the side of the first transfer electrode close to the substrate, the first transfer electrode is connected to the second gate through a third via hole; the second gate serves as the gate electrode of the driving transistor.

[0016] In an exemplary embodiment, an orthographic projection of the second active layer on the substrate includes an orthographic projection of the first switching electrode on the substrate.

[0017] In an exemplary embodiment, an orthographic projection of the first via electrode on the substrate includes an orthographic projection of the third via hole on the substrate.

[0018] In an exemplary embodiment, the pixel driving circuit also includes a first switching transistor, the first switching transistor includes a second active layer, the second active layer is located between the second electrode plate and the third active layer, a second transfer electrode is provided on the surface of the second active layer close to the substrate side, the second transfer electrode is in contact with the second active layer, a data signal line is provided on the second transfer electrode close to the substrate side, and the second transfer electrode is connected to the data signal line through a fourth via hole.

[0019] In an exemplary embodiment, an orthographic projection of the second active layer on the substrate includes an orthographic projection of the second switching electrode on the substrate.

[0020] In an exemplary embodiment, an orthographic projection of the second switching electrode on the substrate includes an orthographic projection of the fourth via hole on the substrate.

[0021] In an exemplary embodiment, the pixel driving circuit also includes a first connecting electrode, the first connecting electrode and the second electrode are located in the same film layer, the first connecting electrode is located between the data signal line and the second switching electrode, the second switching electrode is connected to the first connecting electrode through the fourth via hole, and the first connecting electrode is connected to the data signal line through the second via hole.

[0022] On the other hand, the present disclosure also provides a method for preparing a display substrate, comprising:

[0023] A driving circuit layer is formed on a substrate, wherein the driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit, and the pixel driving circuit includes a second switching transistor, a driving transistor and a capacitor; the driving transistor includes a first active layer, the second switching transistor includes a third active layer, the capacitor includes a second electrode plate, the third active layer is arranged on a side of the first active layer away from the substrate, the second electrode plate is arranged between the first active layer and the third active layer, the second electrode plate is connected to the second end of the first active layer through a first via hole, the second electrode plate forms a recessed area in the first via hole, a dielectric layer is arranged on a side of the second electrode plate away from the substrate, at least a portion of the dielectric layer is arranged in the recessed area, and an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the recessed area on the substrate.

[0024] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0025] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0027] Figure 1 is a structural schematic diagram of a display device;

[0028] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0030] Figure 4 An equivalent circuit diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 5a It is a schematic diagram of an exemplary embodiment of the present disclosure after a first hole is formed in a process of preparing a first via hole in a display substrate;

[0032] Figure 5bIt is a schematic diagram of an exemplary embodiment of the present disclosure after an inorganic dielectric layer is formed in a process of preparing a first via hole in a display substrate;

[0033] Figure 5c It is a schematic diagram of an exemplary embodiment of the present disclosure after a first via hole is formed in a preparation process of a first via hole in a display substrate.

[0034] Figure 6 This is a schematic diagram of a display substrate after a first conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0035] Figure 7a and Figure 7b This is a schematic diagram of a display substrate after a second conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0036] Figure 8a and Figure 8b This is a schematic diagram of a display substrate after a first semiconductor layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0037] Figure 9a and Figure 9b This is a schematic diagram of a display substrate after a third conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0038] Fig.10 It is a schematic diagram of a display substrate after a fifth insulating layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0039] Fig.11a and Fig.11b This is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0040] Fig.12a and Figure 12b This is a schematic diagram of a display substrate after a dielectric layer is formed in a preparation process of the embodiment of the present disclosure;

[0041] Fig.13 It is a schematic diagram of a display substrate after a sixth insulating layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0042] Fig.14a and Fig.14b It is a schematic diagram of a display substrate after a fifth conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0043] Fig.15a , Fig.15b and Fig.15c This is a schematic diagram of a display substrate after a second semiconductor layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0044] Fig.16a and Fig.16b This is a schematic diagram of a display substrate after a sixth conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0045] Fig.17a , Fig.17b and Fig.17c This is a schematic diagram of a display substrate after a third semiconductor layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0046] Fig.18 It is a schematic diagram of a display substrate after an eighth insulating layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0047] Fig.19a and Fig.19b This is a schematic diagram of a display substrate after a seventh conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0048] Fig. 20 It is a schematic diagram of a display substrate after a ninth insulating layer pattern is formed in a preparation process of the embodiment of the present disclosure;

[0049] Fig.21a and Figure 21b It is a schematic diagram of a display substrate after an eighth conductive layer pattern is formed in a preparation process of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0051] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0052] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0053] The inventors of the present disclosure have found that in the design of the relevant display backplane, the active layer of the low-temperature polysilicon thin-film transistor and the active layer of the oxide thin-film transistor do not overlap with the deep hole below, preventing the semiconductor layer from climbing at the deep hole position and causing uneven characteristics due to morphological differences. The active layer in the relevant display backplane does not overlap with the deep hole, and the space cannot be effectively utilized, which reduces the length of the channel and the storage capacitance, resulting in adverse effects such as short channel effect and parasitic capacitance, which in turn leads to display abnormalities.

[0054] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0055] Figure 2FIG. 1 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. Figure 2 As shown, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device, and the light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0056] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0057] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0058] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0059] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, the circuit units may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, the light-emitting units may include at least a light-emitting device, and the light-emitting device may include an anode, an organic light-emitting layer, and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0060] In exemplary embodiments, the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0061] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0062] Figure 4 FIG. 1 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 9T2C structure. Figure 4 As shown, the pixel driving circuit of the exemplary embodiment of the present disclosure can be a 3T1C structure, which can include 3 transistors (a first transistor T1 to a third transistor T3) and a storage capacitor C. The pixel driving circuit is respectively connected to a sensing signal line SL, a data signal line DATA, a first power line VDD, a second power line VSS, and a scanning signal line SCAN.

[0063] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a fourth node N4, and a fifth node N5. The first node N1 is respectively connected to the second electrode of the second transistor, the gate of the first transistor T1, and the first end of the storage capacitor C, the second node N2 is respectively connected to the second electrode of the third transistor, the second end of the storage capacitor C, the second electrode of the first transistor T1, and the first electrode of the light emitting device EL, the fourth node N4 is respectively connected to the data signal line DATA and the first electrode of the second transistor; the fifth node N5 is respectively connected to the sensing signal line SL and the first electrode of the third transistor.

[0064] In an exemplary embodiment, a first end (first plate) of the storage capacitor C is connected to the first node N1 , and a second end (second plate) of the storage capacitor C is connected to the second node N2 .

[0065] In an exemplary embodiment, the first transistor T1 is a driving transistor; the second transistor T2 is a first switching transistor for writing a data signal; and the third transistor T3 is a second switching transistor for extracting a threshold voltage or current.

[0066] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first node N1, connected to the second electrode of the second transistor and the first end of the storage capacitor C through the first node N1, the first electrode of the first transistor T1 is connected to the first power line VDD, the second electrode of the first transistor T1 is connected to the second node N2, and respectively connected to the second electrode of the third transistor, the second end of the storage capacitor C and the first electrode of the light emitting device EL through the second node N2, and the second electrode of the light emitting device EL is connected to the second power line VSS. The first transistor T1 is used to generate a corresponding current at the second electrode of the first transistor T1 under the control of the data signal received by its gate electrode, so as to control the light emitting device EL to emit light. The gate electrode of the second transistor T2 is connected to the scan signal line SCAN, the first electrode of the second transistor T2 is connected to the data signal line DATA through the fourth node N4, the second electrode of the second transistor T2 is connected to the first node N1, and connected to the first end of the capacitor C and the gate of the first transistor T1 through the first node N1, and the second transistor T2 is used to receive the data signal transmitted by the data signal line DATA under the control of the scan signal line SCAN. The gate electrode of the third transistor T3 is connected to the scan signal line SCAN, the first electrode of the third transistor T3 is connected to the sensing signal line SL through the fifth node N5, the second electrode of the third transistor T3 is connected to the second node N2, and is connected to the second end of the capacitor C, the second electrode of the first transistor T1 and the first electrode of the light-emitting device EL through the second node N2. The third transistor T3 is used to extract the threshold voltage Vth and the mobility of the third transistor T3 in response to the compensation timing to compensate for the threshold voltage Vth.

[0067] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode (anode), a light-emitting functional layer, and a second electrode (cathode); the light-emitting device EL may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode); or, the light-emitting device EL may be an LED.

[0068] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the second node N2, a second electrode of the light emitting device EL is connected to a second power line VSS, a signal of the second power line VSS is a continuously provided low level signal, and a signal of the first power line VDD is a continuously provided high level signal.

[0069] In an exemplary embodiment, the second transistor T2 and the third transistor T3 may be oxide thin film transistors, and the first transistor T1 may be a low temperature polysilicon thin film transistor. The active layer of the low temperature polysilicon thin film transistor is low temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate, i.e., LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, can achieve low frequency driving, can reduce power consumption, and can improve display quality.

[0070] An embodiment of the present disclosure provides a display substrate, comprising a driving circuit layer arranged on a substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a second switching transistor and a capacitor; the driving transistor comprising a first active layer, the second switching transistor comprising a third active layer, the capacitor comprising a second electrode plate, the third active layer being arranged on a side of the first active layer away from the substrate, the second electrode plate being arranged between the first active layer and the third active layer, the second electrode plate being connected to a second end of the first active layer through a first via hole, the second electrode plate forming a recessed area in the first via hole, a dielectric layer being arranged on a side of the second electrode plate away from the substrate, at least a portion of the dielectric layer being arranged in the recessed area, and an orthographic projection of the third active layer on the substrate overlapping with an orthographic projection of the recessed area on the substrate.

[0071] In an exemplary embodiment, a surface of the dielectric layer away from the substrate and a surface of the second electrode plate away from the substrate form a plane.

[0072] In an exemplary embodiment, an orthographic projection of the third active layer on the substrate includes an orthographic projection of the recessed region on the substrate.

[0073] In an exemplary embodiment, an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the first active layer on the substrate.

[0074] In an exemplary embodiment, the first via is polygonal in shape, and the length of at least one side of the first via is less than or equal to 1 micron; or, the first via is circular in shape, and the diameter of the first via is less than or equal to 1 micron; or, the first via is elliptical in shape, and the length of the short axis of the first via is less than or equal to 1 micron.

[0075] In an exemplary embodiment, the driving transistor also includes a second gate, which is arranged between the first active layer and the second electrode plate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate, the capacitor includes a first electrode plate, the second gate serves as the first electrode plate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

[0076] In an exemplary embodiment, the driving transistor further includes a first gate, the first gate is located on a side of the first active layer close to the substrate, and an orthographic projection of the first gate on the substrate overlaps with an orthographic projection of the first active layer on the substrate.

[0077] In an exemplary embodiment, the pixel driving circuit further includes a first power line, the first power signal line is disposed on a side of the third active layer away from the substrate, and the first power signal line is connected to a first end of the first active layer through a fifth via hole.

[0078] In an exemplary embodiment, the second switch transistor further includes a third gate, the third gate is located between the third active layer and the second electrode plate, and an orthographic projection of the third gate on the substrate overlaps with an orthographic projection of the third active layer on the substrate.

[0079] In an exemplary embodiment, it also includes a light-emitting structure layer arranged on the side of the driving circuit layer away from the substrate, the light-emitting structure layer includes a light-emitting device, and the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate. The pixel driving circuit also includes a second connecting electrode, the second connecting electrode is located between the third active layer and the first electrode, at least a portion of the second connecting electrode is in contact with a surface of the second end of the third active layer away from the substrate, the second connecting electrode is connected to the second electrode plate through a sixth via hole, and the second connecting electrode is connected to the first electrode.

[0080] In an exemplary embodiment, the pixel driving circuit further includes a sensing signal line located on a side of the third active layer away from the substrate, and at least a portion of the sensing signal line contacts a surface of the first end of the third active layer away from the substrate.

[0081] In an exemplary embodiment, the pixel driving circuit also includes a first switching transistor, the first switching transistor includes a second active layer, the second active layer is located between the second electrode plate and the third active layer, a first transfer electrode is provided on the surface of the second active layer close to the substrate side, the first transfer electrode is in contact with the second active layer, a second gate is provided on the side of the first transfer electrode close to the substrate, the first transfer electrode is connected to the second gate through a third via hole; the second gate serves as the gate electrode of the driving transistor.

[0082] In an exemplary embodiment, an orthographic projection of the second active layer on the substrate includes an orthographic projection of the first switching electrode on the substrate.

[0083] In an exemplary embodiment, an orthographic projection of the first via electrode on the substrate includes an orthographic projection of the third via hole on the substrate.

[0084] In an exemplary embodiment, the pixel driving circuit also includes a first switching transistor, the first switching transistor includes a second active layer, the second active layer is located between the second electrode plate and the third active layer, a second transfer electrode is provided on the surface of the second active layer close to the substrate side, the second transfer electrode is in contact with the second active layer, a data signal line is provided on the second transfer electrode close to the substrate side, and the second transfer electrode is connected to the data signal line through a fourth via hole.

[0085] In an exemplary embodiment, an orthographic projection of the second active layer on the substrate includes an orthographic projection of the second switching electrode on the substrate.

[0086] In an exemplary embodiment, an orthographic projection of the second switching electrode on the substrate includes an orthographic projection of the fourth via hole on the substrate.

[0087] In an exemplary embodiment, the pixel driving circuit also includes a first connecting electrode, the first connecting electrode and the second electrode are located in the same film layer, the first connecting electrode is located between the data signal line and the second switching electrode, the second switching electrode is connected to the first connecting electrode through the fourth via hole, and the first connecting electrode is connected to the data signal line through the second via hole.

[0088] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0089] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to a region divided according to a light-emitting device.

[0090] In an exemplary embodiment, the position of the light emitting unit's orthographic projection on the substrate may correspond to the position of the circuit unit's orthographic projection on the substrate, or the position of the light emitting unit's orthographic projection on the substrate may not correspond to the position of the circuit unit's orthographic projection on the substrate.

[0091] In an exemplary embodiment, a plurality of circuit units sequentially arranged along the first direction D1 may be referred to as unit rows, and a plurality of circuit units sequentially arranged along the second direction D2 may be referred to as unit columns. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction D1 intersects the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2.

[0092] In an exemplary embodiment, taking 3 circuit units in the m-th unit row and 3 circuit units in the m+1-th unit row as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0093] (101) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate, patterning the first conductive film through a patterning process so that the first insulating film forms a first insulating layer covering the substrate, and forming the first conductive film into a first conductive layer pattern disposed on the first insulating layer, such as Figure 6 shown.

[0094] In an exemplary embodiment, the first conductive layer pattern may include data signal lines 11, which may be strip-shaped and extend along the second direction D2. The data signal lines 11 of circuit units adjacent to each other in the second direction D2 in the mth and m+1th unit rows may be connected as one.

[0095] In an exemplary embodiment, the data signal line 11 is provided with first connection parts 11-1 on opposite sides in the first direction D1, and the shape of the first connection parts 11-1 may be a rectangular block, and the first connection parts 11-1 extend out of opposite sides in the first direction D1 of the data signal line 11. The first connection parts 11-1 of the data signal line 11 of the circuit unit in the m-th unit row are located at one end of the data signal line 11 in the opposite direction of the second direction D2, and the first connection parts 11-1 of the data signal line 11 of the circuit unit in the m+1-th unit row are located at one end of the data signal line 11 in the second direction D2, and the first connection parts 11-1 of the circuit units adjacent to each other in the second direction D2 in the m-th unit row and the m+1-th unit row are connected as one body.

[0096] In an exemplary embodiment, the data signal line 11 may be a single-layer structure, such as copper or molybdenum; or, the data signal line 11 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0097] In example embodiments, the first insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0098] (102) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process so that the second insulating film forms a second insulating layer covering the first conductive layer pattern, and forming the second conductive film into a second conductive layer pattern disposed on the second insulating layer, such as Figure 7a and Figure 7b shown.

[0099] In an exemplary embodiment, the second conductive layer pattern may include a first gate electrode 12, the first gate electrode 12 including a first portion 12-1 extending along the first direction D1 and a second portion 12-2 extending along the second direction D2. The first portion 12-1 of the circuit unit in the m-th unit row is located on one side of the circuit unit in the second direction D2, the first portions 12-1 of adjacent circuit units in the m-th unit row are connected as a whole to form a strip structure extending along the first direction D1, and the second portion 12-2 of the circuit unit in the m-th unit row is connected to the first portion 12-1 on the side opposite to the second direction D2; the first portion 12-1 of the circuit unit in the m+1-th unit row is located on the side opposite to the second direction D2 of the circuit unit, the first portions 12-1 of adjacent circuit units in the m+1-th unit row are connected as a whole to form a strip structure extending along the first direction D1, and the second portion 12-2 of the circuit unit in the m+1-th unit row is connected to the first portion 12-1 on the side opposite to the second direction D2.

[0100] In an exemplary embodiment, the first gate 12 may be a single-layer structure, such as copper or molybdenum; or, the first gate 12 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0101] In example embodiments, the second insulating layer may be a silicon nitride compound.

[0102] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a third insulating film and a first semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor film through a patterning process so that the third insulating film forms a third insulating layer covering the second conductive layer pattern, and forming the first semiconductor film into a first semiconductor layer pattern disposed on the third insulating layer, such as Figure 8a and Figure 8b shown.

[0103] In an exemplary embodiment, the first semiconductor layer pattern may include a first active layer 13, the first active layer 13 includes a first main body 13-1 extending along the second direction D2, and a second connection portion 13-2 and a third connection portion 13-3 disposed at opposite ends of the first main body 13-1 in the second direction D2, the first main body 13-1 may be in a strip shape, the second connection portion 13-2 and the third connection portion 13-3 may be in a rectangular block shape, the orthographic projection of the first main body 13-1 on the substrate overlaps with the orthographic projection of the first gate 12 on the substrate, and the orthographic projections of the second connection portion 13-2 and the third connection portion 13-3 on the substrate do not overlap with the orthographic projection of the first gate 12 on the substrate. The third connection portion 13-3 is connected to the first power signal line as the first end of the first transistor T1, and the second connection portion 13-2 is connected to the first electrode of the light emitting device, the first electrode plate (the second gate 14) of the capacitor C, and the second end of the third transistor T3 as the second end of the first transistor T1.

[0104] In exemplary embodiments, the first active layer 13 may be low temperature polysilicon.

[0105] In example embodiments, the third insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0106] (104) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fourth insulating film and a third conductive layer in sequence on the substrate having the aforementioned pattern, patterning the third conductive layer through a patterning process so that the fourth insulating film forms a fourth insulating layer covering the first semiconductor layer pattern, and forming the third conductive film into a third conductive layer pattern disposed on the fourth insulating layer, such as Figure 9a and Figure 9b shown.

[0107] In an exemplary embodiment, the third conductive layer pattern may include a second gate 14, the second gate 14 may be in the shape of a rectangular block, the orthographic projection of the second gate 14 on the substrate overlaps with the orthographic projection of the first main body portion 13-1 of the first active layer 13 on the substrate, and the orthographic projection of the second gate 14 on the substrate does not overlap with the orthographic projections of the second connection portion 13-2 and the third connection portion 13-3 on the substrate. The first gate 12, the second gate 14 and the first active layer 13 form a first transistor T1, the first transistor T1 is a dual-gate structure, and the first gate 12 and the second gate 14 are respectively two gate electrodes of the first transistor T1.

[0108] In an exemplary embodiment, the second gate 14 may be a single-layer structure, such as copper or molybdenum; or, the second gate 14 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0109] In example embodiments, the fourth insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0110] (105) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern, wherein the fifth insulating layer in each circuit unit is provided with a plurality of via holes, such as Fig.10 shown.

[0111] In an exemplary embodiment, the multiple vias of the fifth insulating layer in each circuit unit include a first via V1 and a second via V2, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the third connection portion 13-3 of the first active layer 13 on the substrate, the fifth insulating layer and the fourth insulating layer in the first via V1 are etched away to expose the surface of the second connection portion 13-2 of the first active layer 13, and the first via V1 is configured to connect the subsequently formed second electrode plate 15-1 to the second connection portion 13-2 of the first active layer 13 through the via.

[0112] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the first connecting portion 11-1 of the data signal line 11 on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first connecting portion 11-1 of the data signal line 11, and the second via hole V2 is configured to connect the subsequently formed first connecting electrode 15-2 to the first connecting portion 11-1 of the data signal line 11 through the via hole.

[0113] In an exemplary embodiment, the second via holes V2 of the circuit cells in the m-th cell row and the m+1-th cell row adjacent to each other in the second direction D2 are connected as one.

[0114] (106) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive layer on the substrate having the aforementioned pattern, patterning the fourth conductive layer through a patterning process, so that the fourth conductive film forms a fourth conductive layer pattern disposed on the fifth insulating layer, such as Fig.11a and Fig.11b shown.

[0115] In an exemplary embodiment, the fourth conductive layer pattern includes a second electrode plate 15-1 and a first connection electrode 15-2, and the shapes of the second electrode plate 15-1 and the first connection electrode 15-2 both include a rectangular block shape. The second electrode plate 15-1 of the circuit unit in the m-th unit row is located on one side of the first connection electrode 15-2 of the circuit unit in the m-th unit row in the second direction D2, and the second electrode plate 15-1 of the circuit unit in the m+1-th unit row is located on one side of the first connection electrode 15-2 of the circuit unit in the m+1-th unit row in the opposite direction of the second direction D2, and the first connection electrodes 15-2 of the circuit units adjacent to each other in the second direction D2 in the m-th unit row and the m+1-th unit row are connected as a whole.

[0116] In an exemplary embodiment, the orthographic projection of the first portion of the second electrode plate 15 - 1 on the substrate overlaps with the orthographic projection of the second gate 14 on the substrate to form a capacitor C. The second gate 14 serves as the first electrode plate of the capacitor C.

[0117] In an exemplary embodiment, the second portion of the second electrode plate 15-1 is connected to the second connection portion 13-2 of the first active layer 13 through the first via hole V1. The second portion of the second electrode plate 15-1 forms a recessed area in the first via hole V1.

[0118] In an exemplary embodiment, the first connection electrode 15 - 2 is connected to the first connection portion 11 - 1 of the data signal line 11 through the second via hole V2 .

[0119] In an exemplary embodiment, the second electrode 15-1 and the first connection electrode 15-2 can both be a single-layer structure, such as copper or molybdenum; or, the second electrode 15-1 and the first connection electrode 15-2 can both be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0120] In example embodiments, the fifth insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0121] (107) Forming a dielectric layer. In an exemplary embodiment, forming the dielectric layer may include: depositing an organic insulating film on the substrate having the aforementioned pattern, patterning the organic insulating film through an exposure and development process, so that the organic insulating film forms a dielectric pattern disposed on the fourth conductive layer pattern; then patterning the dielectric pattern through an ashing process to form a dielectric layer 20, such as Fig.12a and Figure 12b As shown. Among them, Figure 12b Can be Fig.12a Cross-sectional view along the a-a' direction.

[0122] In an exemplary embodiment, the orthographic projection of the dielectric layer 20 on the substrate is located within the orthographic projection of the second electrode plate 15-1 on the substrate, the orthographic projection of the dielectric layer 20 on the substrate overlaps with the orthographic projection of the first via hole V1 on the substrate, the dielectric layer 20 fills the recessed area formed by the second electrode plate 15-1 at the first via hole V1, and the dielectric layer 20 contacts the entire surface of the second electrode plate 15-1 located in the first via hole V1.

[0123] In an exemplary embodiment, the surface of the dielectric layer 20 away from the substrate is substantially flush with the surface of the second electrode plate 15 - 1 away from the substrate, so that the surface of the dielectric layer 20 away from the substrate and the surface of the second electrode plate 15 - 1 away from the substrate form a plane.

[0124] In an exemplary embodiment, the material of the dielectric layer 20 may include an organic material, for example, resin.

[0125] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fourth conductive layer pattern and the dielectric layer, wherein the sixth insulating layer in each circuit unit is provided with a plurality of vias, such as Fig.13 shown.

[0126] In an exemplary embodiment, the multiple vias of the sixth insulating layer in each circuit unit include a third via V3 and a fourth via V4, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the second gate 14 on the substrate, the sixth insulating layer and the fifth insulating layer in the third via V3 are etched away to expose a portion of the surface of the second gate 14, and the third via V3 is configured to connect a subsequently formed first transfer electrode to the second gate 14 through the via.

[0127] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the orthographic projection of the first connecting electrode 15-2 on the substrate, the sixth insulating layer in the fourth via hole V4 is etched away to expose a portion of the surface of the first connecting electrode 15-2, and the fourth via hole V4 is configured to connect a subsequently formed second transfer electrode to the first connecting electrode 15-2 through the via hole.

[0128] In example embodiments, the sixth insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0129] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film through a patterning process, so that the fifth conductive film forms a fifth conductive layer pattern disposed on the sixth insulating layer, such as Fig.14a and Fig.14b shown.

[0130] In an exemplary embodiment, the fifth conductive layer pattern includes a first switching electrode 16-1 and a second switching electrode 16-2, and the shapes of the first switching electrode 16-1 and the second switching electrode 16-2 both include a rectangular block shape. The first switching electrode 16-1 of the circuit unit in the m-th unit row is located on one side of the second switching electrode 16-2 of the circuit unit in the m-th unit row in the second direction D2, the first switching electrode 16-1 of the circuit unit in the m+1-th unit row is located on one side of the second switching electrode 16-2 of the circuit unit in the m+1-th unit row in the opposite direction of the second direction D2, and the second switching electrodes 16-2 of the circuit units adjacent in the second direction D2 in the m-th unit row and the m+1-th unit row are connected as one.

[0131] In an exemplary embodiment, the first switching electrode 16 - 1 and the second switching electrode 16 - 2 may both be a multi-layer structure, for example, a titanium nitride / molybdenum stacking structure, or a titanium / aluminum / titanium stacking structure.

[0132] (110) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a second semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process, so that the second semiconductor film forms a second semiconductor layer pattern disposed on the fifth conductive layer pattern, such as Fig.15a , Fig.15b and Fig.15c As shown. Among them, Fig.15c for Fig.15a Cross-sectional view along the b-b' direction.

[0133] In an exemplary embodiment, the second semiconductor layer pattern may include a second active layer 17, the second active layer 17 includes a second main body 17-1 extending along the second direction D2, and a fourth connection portion 17-2 and a fifth connection portion 17-3 arranged on one side of the second main body 17-1 in the first direction D1, the second main body 17-1 may be in a strip shape, the fourth connection portion 17-2 and the fifth connection portion 17-3 may be in a rectangular block shape, the fourth connection portion 17-2 and the fifth connection portion 17-3 are located at opposite ends of the second main body 17-1 in the second direction D2, the orthographic projection of the fourth connection portion 17-2 on the substrate includes the orthographic projection of the first switching electrode 16-1 on the substrate, and the fourth connection portion 17-2 is in direct contact with the first switching electrode 16-1; the orthographic projection of the fifth connection portion 17-3 on the substrate includes the orthographic projection of the second switching electrode 16-2 on the substrate, and the fifth connection portion 17-3 is in direct contact with the second switching electrode 16-2. The fifth connection portion 17 - 3 can be used as the first end of the second transistor T2 and connected to the data signal line 11 ; the fourth connection portion 17 - 2 can be used as the second end of the second transistor T2 and connected to the second gate 14 of the first transistor T1 .

[0134] In an exemplary embodiment, the orthographic projection of the first transfer electrode 16-1 on the substrate includes the orthographic projection of the third via V3 on the substrate, and the first transfer electrode 16-1 is connected to the second gate 14 through the third via V3; the orthographic projection of the second transfer electrode 16-2 on the substrate includes the orthographic projection of the fourth via V4 on the substrate, the second transfer electrode 16-2 is connected to the first connection electrode 15-2 through the fourth via V4, and the first connection electrode 15-2 is connected to the data signal line 11 through the second via V2.

[0135] In an exemplary embodiment, an orthographic projection of the second active layer 17 on the substrate does not overlap with an orthographic projection of the second electrode plate 15 - 1 on the substrate.

[0136] (111) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer pattern may include: depositing a seventh insulating film and a sixth conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film through a patterning process so that the seventh insulating film forms a seventh insulating layer, and forming the sixth conductive film into a sixth conductive layer pattern disposed on the seventh insulating layer, such as Fig.16a and Fig.16b shown.

[0137] In an exemplary embodiment, the sixth conductive layer pattern includes a third gate 18, and the shape of the third gate 18 includes a rectangular strip. The orthographic projection of the first region of the third gate 18 on the substrate includes the orthographic projection of the dielectric layer 20 on the substrate. The first region of the third gate 18 is configured to serve as the gate of the third transistor T3 formed subsequently. The orthographic projection of the second region of the third gate 18 on the substrate overlaps with the orthographic projection of the second active layer 17 on the substrate, and the second region of the third gate 18 serves as the gate of the first transistor T1. The second active layer 17 and the second portion of the third gate 18 form the second transistor T2.

[0138] In an exemplary embodiment, the orthographic projection of the third gate electrode 18 on the substrate does not overlap with the orthographic projections of the first switching electrode 16 - 1 and the second switching electrode 16 - 2 on the substrate.

[0139] In an exemplary embodiment, the third gates 18 of the circuit units in the mth unit row are connected as a whole to form a strip extending along the first direction, and the third gates 18 of the circuit units in the (m+1)th unit row are connected as a whole to form a strip extending along the first direction.

[0140] In an exemplary embodiment, the third gate 18 may be a multi-layer structure, for example, a titanium nitride / molybdenum stacked structure, or a titanium / aluminum / titanium stacked structure.

[0141] In example embodiments, the seventh insulating layer may be a silicon oxide compound.

[0142] (112) Forming a third semiconductor layer pattern. In an exemplary embodiment, forming the third semiconductor layer pattern may include: depositing an eighth insulating film and a third semiconductor film in sequence on the substrate having the aforementioned pattern, patterning the third semiconductor film through a patterning process so that the eighth insulating film forms an eighth insulating layer covering the sixth conductive layer pattern, and forming the third semiconductor film into a third semiconductor layer pattern disposed on the eighth insulating layer, such as Fig.17a , Fig.17b and Fig.17c As shown. Among them, Fig.17c for Fig.17a Cross-sectional view along the c-c' direction.

[0143] In an exemplary embodiment, the third semiconductor layer pattern may include a third active layer 19, the third active layer 19 may be in a rectangular block shape, the orthographic projection of the third active layer 19 on the substrate overlaps with the orthographic projection of the second region of the third gate 18 on the substrate, the orthographic projection of the third active layer 19 on the substrate overlaps with the orthographic projection of the first active layer 13 on the substrate, the orthographic projection of the third active layer 19 on the substrate includes the orthographic projection of the dielectric layer 20 on the substrate, and the orthographic projection of the third active layer 19 on the substrate includes the orthographic projection of the recessed region of the second electrode plate 15-1 on the substrate. The orthographic projection of the third active layer 19 on the substrate does not overlap with the orthographic projection of the second active layer 17 on the substrate. Among them, the third active layer 19 and the third gate 18 form a third transistor T3.

[0144] (113) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming the eighth insulating layer pattern may include: patterning the eighth insulating layer using a patterning process, so that the eighth insulating layer in each circuit unit forms a plurality of via holes, such as Fig.18 shown.

[0145] In an exemplary embodiment, the multiple vias of the eighth insulating layer in each circuit unit include a fifth via V5 and a sixth via V6, the orthographic projection of the fifth via V5 on the substrate is located within the orthographic projection of the third connection portion 13-3 of the first active layer 13 on the substrate, the eighth insulating layer, the seventh insulating layer, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifth via V5 are etched away to expose a portion of the surface of the third connection portion 13-3 of the first active layer 13, and the fifth via V5 is configured to connect a subsequently formed first power line (VDD) to the third connection portion 13-3 of the first active layer 13 through the via.

[0146] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the orthographic projection of the second electrode plate 15-1 on the substrate, the eighth insulating layer, the seventh insulating layer and the sixth insulating layer in the sixth via hole V6 are etched away, exposing a portion of the surface of the second electrode plate 15-1, and the sixth via hole V6 is configured to connect a second connecting electrode formed subsequently to the second electrode plate 15-1 through the via hole. The orthographic projection of the sixth via hole V6 on the substrate does not overlap with the orthographic projection of the dielectric layer 20 on the substrate.

[0147] (114) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming the seventh conductive layer pattern may include: depositing a seventh conductive film on the substrate on which the aforementioned pattern is formed, patterning the seventh conductive film through a patterning process, so that the seventh conductive film forms a seventh conductive layer pattern disposed on the eighth insulating layer, such as Fig.19a and Fig.19b shown.

[0148] In an exemplary embodiment, the seventh conductive layer pattern includes a first power signal line 21, a second connection electrode 22, and a sensing signal line 23. The first power signal line 21 of the circuit unit of the mth unit row is located on one side of the second direction D2 of the second connection electrode 22 of the circuit unit of the mth unit row, and the first power signal line 21 of the circuit unit of the m+1th unit row is located on the side opposite to the second direction D2 of the second connection electrode 22 of the circuit unit of the m+1th unit row. The shape of the first power signal line 21 of each circuit unit includes a strip extending along the first direction D1, and the first power signal lines 21 of adjacent circuit units of the mth unit row are connected as a whole to form a line extending along the first direction D1. The first power signal lines 21 of adjacent circuit units of the m+1th unit row are connected as a whole to form a line extending along the first direction D1. The first power signal line 21 is connected to the third connection portion 13-3 of the first active layer 13 through the fifth via hole V5.

[0149] In an exemplary embodiment, the second connection electrode 22 is located between the first power signal line 21 and the sensing signal line 23, and the shape of the second connection electrode 22 includes a rectangular block. The second connection electrode 22 is connected to the second plate 15-1 through the sixth via V6. The orthographic projection of the second connection electrode 22 on the substrate overlaps with the orthographic projection of the second end of the third active layer 19 on the substrate, and the second connection electrode 22 contacts the surface of the second end of the third active layer 19 away from the substrate. The second end of the third active layer 19 is connected to the second end of the first transistor T1, the first pole of the light-emitting device, and the second plate 15-1 of the capacitor C as the second end of the third transistor T3.

[0150] In an exemplary embodiment, the sensing signal line 23 of the circuit unit of the mth unit row is located on the side of the second connection electrode 22 of the circuit unit of the mth unit row in the opposite direction of the second direction D2, and the sensing signal line 23 of the circuit unit of the m+1th unit row is located on the side of the second connection electrode 22 of the circuit unit of the m+1th unit row in the second direction D2. The sensing signal line 23 includes a third main body portion 23-1 and a sixth connection portion 23-2, the shape of the third main body portion 23-1 includes a strip extending along the first direction D1, the third main body portions 23-1 of the plurality of circuit units of the mth unit row are connected as a whole to form a line extending along the first direction D1, and the third main body portions 23-1 of the plurality of circuit units of the m+1th unit row are connected as a whole to form a line extending along the first direction D1. The shape of the sixth connection part 23-2 includes a rectangular block. The sixth connection part 23-2 of the circuit unit of the mth unit row is arranged on the side of the second direction D2 of the third main body 23-1, and multiple circuit units in the mth unit row can share one sixth connection part 23-2; the sixth connection part 23-2 of the circuit unit of the m+1th unit row is arranged on the side of the second direction D2 of the third main body 23-1, and multiple circuit units in the m+1th unit row can share one sixth connection part 23-2; the sixth connection part 23-2 shared by multiple circuit units in the mth unit row is connected as a whole with the sixth connection part 23-2 shared by multiple circuit units in the m+1th unit row.

[0151] In an exemplary embodiment, the orthographic projection of the third body portion 23-1 on the substrate overlaps the orthographic projection of the first end of the third active layer 19 on the substrate, and the second connection electrode 22 contacts the surface of the first end of the third active layer 19 away from the substrate. The first end of the third active layer 19 serves as the first end of the third transistor T3 and is connected to the sensing signal line SL.

[0152] In an exemplary embodiment, the first power signal line 21, the second connection electrode 22 and the sensing signal line 23 can all be a single film layer structure, for example, copper or molybdenum; or, the first power signal line 21, the second connection electrode 22 and the sensing signal line 23 can all be a multi-film layer structure, for example, a titanium / aluminum / titanium stacked structure.

[0153] (115) Forming a ninth insulating layer pattern. In an exemplary embodiment, forming the ninth insulating layer pattern may include: depositing a ninth insulating film on the substrate on which the aforementioned pattern is formed, patterning the ninth insulating film through a patterning process, so that the ninth insulating film forms a ninth insulating layer covering the seventh conductive layer pattern, such as Fig. 20 shown.

[0154] In an exemplary embodiment, a seventh via hole V7 is provided in the ninth insulating layer, and the orthographic projection of the seventh via hole V7 on the substrate is located within the orthographic projection of the sixth connection portion 23-2 of the sensing signal line 23 on the substrate. The ninth insulating layer in the seventh via hole V7 is etched away to expose a portion of the surface of the sixth connection portion 23-2, and the seventh via hole V7 is configured to connect a subsequently formed third connection electrode to the sixth connection portion 23-2 through the via hole.

[0155] In an exemplary embodiment, multiple circuit units in the mth unit row may share one seventh via V7, multiple circuit units in the m+1th unit row may share one seventh via V7, and the seventh via V7 shared by multiple circuit units in the mth unit row is connected as one with the seventh via V7 shared by multiple circuit units in the m+1th unit row.

[0156] In example embodiments, the ninth insulating layer may be a silicon oxide compound, or a silicon nitride compound.

[0157] (116) Forming an eighth conductive layer pattern. In an exemplary embodiment, forming the eighth conductive layer pattern may include: depositing an eighth conductive film on the substrate on which the aforementioned pattern is formed, patterning the eighth conductive film through a patterning process, so that the eighth conductive film forms an eighth conductive layer pattern disposed on the ninth insulating layer, such as Fig.21a and Figure 21b shown.

[0158] In an exemplary embodiment, the eighth conductive layer pattern includes a third connection electrode 24, the third connection electrode 24 includes a fourth main body 24-1 and a seventh connection portion 24-2, the fourth main body 24-1 is in the shape of a line extending along the second direction D2, and the seventh connection portion 24-2 is in the shape of a rectangular block. The seventh connection portion 24-2 of the circuit unit of the mth unit row is arranged at one end of the fourth main body 24-1 in the opposite direction of the second direction D2, and the seventh connection portion 24-2 extends out of the side of the fourth main body 24-1 in the opposite direction of the first direction D1; the seventh connection portion 24-2 of the circuit unit of the m+1th unit row is arranged at one end of the fourth main body 24-1 in the second direction D2, and the seventh connection portion 24-2 extends out of the side of the fourth main body 24-1 in the opposite direction of the first direction D1. Multiple circuit units in the mth unit row share a third connecting electrode 24, and multiple circuit units in the m+1th unit row share a third connecting electrode 24. The third connecting electrode 24 shared by the mth unit row and the third connecting electrode 24 shared by the m+1th unit row are located in the same column of circuit units, and the seventh connecting portion 24-2 of the third connecting electrode 24 shared by the mth unit row is connected as a whole with the seventh connecting portion 24-2 of the third connecting electrode 24 shared by the m+1th unit row.

[0159] In an exemplary embodiment, the seventh connection portion 24 - 2 of the third connection electrode 24 is connected to the sixth connection portion 23 - 2 of the sensing signal line 23 through the seventh via hole V7 .

[0160] In an exemplary embodiment, the third connection electrode 24 may be a single-layer structure, such as copper or molybdenum; or, the third connection electrode 24 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0161] At this point, the driving circuit layer of this embodiment is prepared on the substrate. The subsequent preparation process may include forming a tenth insulating layer covering the eighth conductive layer pattern, an eleventh insulating layer disposed on the tenth insulating layer, forming an eighth via hole exposing the second connection electrode 22 in the tenth insulating layer and the eleventh insulating layer, forming a first pole of the light-emitting device on the eleventh insulating layer, and forming a pixel definition layer on the first pole. Among them, the first pole is connected to the second connection electrode 22 through the eighth via hole, and a pixel opening is formed in the pixel definition layer, and the pixel opening exposes at least part of the surface of the first pole. After the pixel definition layer is prepared, the subsequent preparation process can sequentially form a light-emitting functional layer and a second pole to complete the preparation of the light-emitting structure layer, which will not be repeated here.

[0162] The disclosed embodiment shows the preparation process of the substrate. The first via V1 connecting the second electrode plate 15-1 of the capacitor and the first active layer 13 of the first transistor is filled with the dielectric layer 20, so that the surface of the second electrode plate 15-1 is flat, so that the orthographic projection of the subsequently formed third active layer 19 on the substrate overlaps with the orthographic projection of the first active layer 13 on the substrate, and the flatness of the third active layer 19 is ensured, so as to avoid the via connecting the second electrode plate 15-1 and the first active layer 13 affecting the flatness of the third active layer 19.

[0163] The disclosed embodiment shows the preparation process of the substrate. By placing the data signal line 11 in the first conductive layer and the second electrode 15-1 in the fourth conductive layer, the crosstalk effect of the data signal line 11 is reduced, and the effect of the parasitic capacitance of the first transistor during light emission is reduced.

[0164] The disclosed embodiment shows the preparation process of the substrate. By overlapping the orthographic projection of the third active layer 19 on the substrate with the orthographic projection of the first active layer 13 on the substrate, the space utilization rate can be improved, the orthographic projection area of ​​the second electrode 15-1 on the substrate can be increased, thereby increasing the capacitance.

[0165] The disclosed embodiment shows the preparation process of the substrate. By overlapping the orthographic projection of the third active layer 19 on the substrate with the orthographic projection of the first active layer 13 on the substrate, it is possible to improve space utilization, increase the size of the first active layer 13, reduce the short channel effect, increase the subthreshold swing (SS), and improve the grayscale separation fineness.

[0166] The disclosed embodiment shows the preparation process of the substrate, by forming the first transfer electrode 16-1 and the second transfer electrode 16-2 on the surface of the second active layer 17 close to the substrate, so that the orthographic projections of the first transfer electrode 16-1 and the second transfer electrode 16-2 on the substrate can be located within the orthographic projection of the second active layer 17 on the substrate, thereby reducing the space occupied by the first transfer electrode 16-1 and the second transfer electrode 16-2.

[0167] The disclosed embodiment shows the preparation process of the substrate, where the first transfer electrode 16 - 1 and the second transfer electrode 16 - 2 are in direct contact with the second active layer 17 without via connection, thereby avoiding over-etching during the via etching process and damaging the second active layer 17 .

[0168] The disclosed embodiment shows the preparation process of the substrate. By including the orthographic projections of the first transfer electrode 16-1 and the second transfer electrode 16-2 on the substrate with the orthographic projections of the via holes thereunder on the substrate, full-hole connection is achieved, the difficulty of deep hole etching is reduced, and the connection stability is improved.

[0169] In an exemplary embodiment, the disclosed embodiment shows a process of preparing a substrate, and the shape of the orthographic projection of at least one of the first via hole V1, the second via hole V2, the third via hole V3, the fourth via hole V4, the fifth via hole V5, the sixth via hole V6 and the seventh via hole V7 on the substrate may include a polygon, such as a rectangle, a pentagon, a hexagon, etc. The length of at least one side of the polygon is less than or equal to 1 micron; or, the shape of the orthographic projection of at least one of the first via hole V1, the second via hole V2, the third via hole V3, the fourth via hole V4, the fifth via hole V5, the sixth via hole V6 and the seventh via hole V7 on the substrate may include a circle, and the diameter of the circle is less than or equal to 1 micron; or, the shape of the orthographic projection of at least one of the first via hole V1, the second via hole V2, the third via hole V3, the fourth via hole V4, the fifth via hole V5, the sixth via hole V6 and the seventh via hole V7 on the substrate may include an ellipse, and the length of the short axis of the ellipse is less than or equal to 1 micron.

[0170] In an exemplary embodiment, the first via hole V1 is taken as an example to illustrate the preparation process of each via hole of the display substrate in the embodiment of the present disclosure. Forming the first via hole V1 may include the following operations.

[0171] like Figure 5a As shown, a first hole V1-1 is first formed in the fifth insulating layer 205, and the first hole V1-1 extends to the surface of the first active layer 13, exposing a portion of the surface of the first active layer 13;

[0172] like Figure 5bAs shown, subsequently, an inorganic dielectric layer 301 is deposited on the fifth insulating layer 205, and the inorganic dielectric layer 301 covers the inner wall of the first hole V1-1; wherein the inorganic dielectric layer 301 and the fifth insulating layer 205 have different etching ratios;

[0173] like Figure 5c As shown, the inorganic dielectric layer 301 is then patterned by exposure, development and etching processes to form a second hole V1-2 in the inorganic dielectric layer 301, and the second hole V1-2 exposes the side wall of one side of the first hole V1-1 and a portion of the surface of the first active layer 13. A portion of the surface of the first active layer 13 exposed by the first hole V1-1 is covered by the inorganic dielectric layer 301, and another portion of the surface of the first active layer 13 exposed by the first hole V1-1 is exposed by the second hole V1-2. The area of ​​the first active layer 13 exposed by the first hole V1-1 and the second hole V1-2 is used as the first via hole V1, and the length a of the orthographic projection of the first via hole V1 on the substrate 101 in the second direction D2 is less than or equal to 1 micron.

[0174] The preparation process of the display substrate in the embodiment of the present disclosure achieves a high pixel density of the display substrate by controlling the size of each via hole of the display substrate to be less than or equal to 1 micron. For example, the pixel density of the display substrate can reach 1800 PPI.

[0175] The present disclosure also provides a method for preparing a display substrate, comprising:

[0176] A driving circuit layer is formed on a substrate, wherein the driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit, wherein the pixel driving circuit includes a third transistor, a first transistor and a capacitor; the first transistor includes a first active layer, the third transistor includes a third active layer, the capacitor includes a second electrode plate, the third active layer is arranged on a side of the first active layer away from the substrate, the second electrode plate is arranged between the first active layer and the third active layer, the second electrode plate is connected to the second end of the first active layer through a first via hole, the second electrode plate forms a recessed area in the first via hole, a dielectric layer is arranged on a side of the second electrode plate away from the substrate, at least a portion of the dielectric layer is arranged in the recessed area, and an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the recessed area on the substrate.

[0177] The embodiment of the present disclosure further provides a display device, including any of the above-mentioned display substrates. The display device can be: a mobile phone, a wearable device, an AR or VR display device, a vehicle-mounted display device, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiment of the present invention is not limited thereto.

[0178] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0179] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include at least one of the features.

[0180] In the description of the present application, “plurality” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0181] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0182] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0183] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0184] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: The invention comprises a driving circuit layer arranged on a substrate, wherein the driving circuit layer comprises at least a plurality of circuit units, wherein at least one circuit unit comprises a pixel driving circuit, wherein the pixel driving circuit comprises a driving transistor, a second switching transistor and a capacitor; wherein the driving transistor comprises a first active layer, wherein the second switching transistor comprises a third active layer, wherein the capacitor comprises a second electrode plate, wherein the third active layer is arranged on a side of the first active layer away from the substrate, wherein the second electrode plate is arranged between the first active layer and the third active layer, wherein the second electrode plate is connected to a second end of the first active layer through a first via hole, wherein the second electrode plate forms a recessed area in the first via hole, wherein a dielectric layer is arranged on a side of the second electrode plate away from the substrate, wherein at least a portion of the dielectric layer is arranged in the recessed area, and wherein an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the recessed area on the substrate.

2. The display substrate according to claim 1, characterized in that: A surface of the dielectric layer away from the substrate and a surface of the second electrode plate away from the substrate form a plane.

3. The display substrate according to claim 1, characterized in that: The orthographic projection of the third active layer on the substrate includes the orthographic projection of the recessed region on the substrate.

4. The display substrate according to claim 1, characterized in that: An orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the first active layer on the substrate.

5. The display substrate according to claim 1, characterized in that: The first via is polygonal in shape, and the length of at least one side of the first via is less than or equal to 1 micron; or, the first via is circular in shape, and the diameter of the first via is less than or equal to 1 micron; or, the first via is elliptical in shape, and the length of the short axis of the first via is less than or equal to 1 micron.

6. The display substrate according to any one of claims 1 to 5, characterized in that: The driving transistor also includes a second gate, which is arranged between the first active layer and the second electrode plate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate. The capacitor includes a first electrode plate, and the second gate serves as the first electrode plate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

7. The display substrate according to any one of claims 1 to 5, characterized in that: The driving transistor further includes a first gate, which is located on a side of the first active layer close to the substrate, and an orthographic projection of the first gate on the substrate overlaps with an orthographic projection of the first active layer on the substrate.

8. The display substrate according to any one of claims 1 to 5, characterized in that: The pixel driving circuit further includes a first power line. The first power signal line is arranged on a side of the third active layer away from the substrate. The first power signal line is connected to a first end of the first active layer through a fifth via hole.

9. The display substrate according to any one of claims 1 to 5, characterized in that: The second switch transistor further includes a third gate, which is located between the third active layer and the second electrode plate, and an orthographic projection of the third gate on the substrate overlaps with an orthographic projection of the third active layer on the substrate.

10. The display substrate according to any one of claims 1 to 5, characterized in that: It also includes a light-emitting structure layer arranged on the side of the driving circuit layer away from the substrate, the light-emitting structure layer includes a light-emitting device, and the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate. The pixel driving circuit also includes a second connecting electrode, the second connecting electrode is located between the third active layer and the first electrode, at least a part of the second connecting electrode is in contact with the surface of the second end of the third active layer away from the substrate, the second connecting electrode is connected to the second electrode plate through a sixth via hole, and the second connecting electrode is connected to the first electrode.

11. The display substrate according to any one of claims 1 to 5, characterized in that: The pixel driving circuit further includes a sensing signal line, which is located on a side of the third active layer away from the substrate, and at least a portion of the sensing signal line contacts a surface of a first end of the third active layer away from the substrate.

12. The display substrate according to any one of claims 1 to 5, characterized in that: The pixel driving circuit also includes a first switching transistor, which includes a second active layer, which is located between the second electrode plate and the third active layer, and a first switching electrode is arranged on a surface of the second active layer close to the substrate, the first switching electrode is in contact with the second active layer, and a second gate is arranged on a side of the first switching electrode close to the substrate, and the first switching electrode is connected to the second gate through a third via hole; the second gate serves as the gate electrode of the driving transistor.

13. The display substrate according to claim 12, characterized in that: The orthographic projection of the second active layer on the substrate includes the orthographic projection of the first switching electrode on the substrate.

14. The display substrate according to claim 12, characterized in that: The orthographic projection of the first switching electrode on the substrate includes the orthographic projection of the third via hole on the substrate.

15. The display substrate according to any one of claims 1 to 5, characterized in that: The pixel driving circuit also includes a first switching transistor, which includes a second active layer, which is located between the second electrode plate and the third active layer, and a second transfer electrode is provided on the surface of the second active layer close to the substrate, and the second transfer electrode is in contact with the second active layer, and a data signal line is provided on the side of the second transfer electrode close to the substrate, and the second transfer electrode is connected to the data signal line through a fourth via hole.

16. The display substrate according to claim 15, characterized in that: The orthographic projection of the second active layer on the substrate includes the orthographic projection of the second switching electrode on the substrate.

17. The display substrate according to claim 15, characterized in that: The orthographic projection of the second switching electrode on the substrate includes the orthographic projection of the fourth via hole on the substrate.

18. The display substrate according to claim 15, characterized in that: The pixel driving circuit also includes a first connecting electrode, which is located in the same film layer as the second electrode plate, and is located between the data signal line and the second switching electrode. The second switching electrode is connected to the first connecting electrode through the fourth via hole, and the first connecting electrode is connected to the data signal line through the second via hole.

19. A method for preparing a display substrate, characterized in that: include: A driving circuit layer is formed on a substrate, wherein the driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit, and the pixel driving circuit includes a second switching transistor, a driving transistor and a capacitor; the driving transistor includes a first active layer, the second switching transistor includes a third active layer, the capacitor includes a second electrode plate, the third active layer is arranged on a side of the first active layer away from the substrate, the second electrode plate is arranged between the first active layer and the third active layer, the second electrode plate is connected to the second end of the first active layer through a first via hole, the second electrode plate forms a recessed area in the first via hole, a dielectric layer is arranged on a side of the second electrode plate away from the substrate, at least a portion of the dielectric layer is arranged in the recessed area, and an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the recessed area on the substrate.

20. A display device, characterized in that: It comprises the display substrate as claimed in any one of claims 1 to 18.

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