A low-capacitance protection device with high ESD protection capability and its manufacturing method

Abstract

This invention relates to ESD protection devices and their manufacturing methods, specifically to a low-capacitance, high-ESD protection device and its manufacturing method, comprising a P-type substrate, an N-epitaxial layer, and a dielectric layer connected sequentially from bottom to top; an N+ buried layer with its top connected to the N-epitaxial layer is provided in the middle of the upper surface of the P-type substrate; a first P+ expansion region is provided in the middle of the upper surface of the N-epitaxial layer, and a first N+ expansion region group, a second P+ expansion region group, and a second N+ expansion region are distributed sequentially from the inside to the outside; the first N+ expansion region group includes multiple circumferentially distributed first N+ expansion regions; the second P+ expansion region group includes multiple circumferentially distributed second P+ expansion regions; an annular isolation trench penetrating into the P-type substrate is formed on the N-epitaxial layer; an annular electrical connection layer penetrating into the P-type substrate is formed on the second N+ expansion region; an anode and a cathode are provided on the dielectric layer, with the bottom of the anode connected to the first P+ expansion region and the first N+ expansion region, and the bottom of the cathode connected to the second N+ expansion region and the second P+ expansion region. This invention can achieve ultra-low capacitance while ensuring high electrostatic protection capability.

Description

Technical Field

[0001] This invention relates to ESD protection devices and their manufacturing methods, specifically to a low-capacitance, high-ESD protection device and its manufacturing method. Background Technology

[0002] With the rapid development of electronic technology, especially the commercial application of USB 4.0 technology, the requirements for electrostatic discharge (ESD) protection products are increasing. Electrostatic discharge (ESD) protection is one of the key technologies for protecting electronic devices from electrostatic damage. Traditionally, to achieve low capacitance values, a lateral silicon controlled rectifier (SCR) process is typically used.

[0003] However, this process presents a clear trade-off between capacitance and electrostatic discharge (ESD) protection: reducing capacitance often leads to a decrease in ESD protection. Although a series of process optimizations and innovations can alleviate this conflict to some extent, the improvement in ESD protection of the transverse SCR structure remains limited due to the limitations of the process itself. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problem that existing silicon controlled rectifiers often experience a decrease in electrostatic discharge (ESD) protection capability when the capacitance value is reduced, and to provide a protection device with low capacitance and high ESD protection capability and its manufacturing method.

[0005] To solve the above-mentioned technical problems, the technical solution provided by the present invention is as follows:

[0006] A low-capacitance, high ESD protection device includes a P-type substrate, an N-epitaxial layer, and a dielectric layer connected sequentially from bottom to top.

[0007] The upper surface of the P-type substrate has an N+ buried layer at the center, which is connected to the N- epitaxial layer at the top;

[0008] The upper surface of the N-epipolar region is provided with a first P+ expansion region in the middle, and a first N+ expansion region group, a second P+ expansion region group and a second N+ expansion region distributed from the inside to the outside; the first N+ expansion region group includes a plurality of circumferentially distributed first N+ expansion regions; the second P+ expansion region group includes a plurality of circumferentially distributed second P+ expansion regions.

[0009] The second N+ expansion region, together with the P-type substrate and the N+ buried layer, forms a low-trigger NPN transistor; the first P+ expansion region, together with the N- epitaxial layer, the N+ buried layer, and the P-type substrate, forms a low-capacitance PNP transistor; the first N+ expansion region, the N- epitaxial layer, and the second P+ expansion region form a guiding diode;

[0010] The N-epitaxial layer has an annular isolation trench extending into the P-type substrate for electrical isolation of low-capacitance PNP transistors and low-trigger NPN transistors.

[0011] A ring-shaped electrical connection layer extending into the P-type substrate is formed on the second N+ expansion region;

[0012] The dielectric layer is provided with an anode and a cathode. The bottom of the anode is connected to the first P+ expansion region and the first N+ expansion region, and the bottom of the cathode is connected to the second N+ expansion region and the second P+ expansion region.

[0013] Furthermore, a first trench region extending into the P-type substrate is formed on the N-epitaxial layer, and the first trench region is filled with polysilicon to form an annular isolation trench for electrical isolation of low-capacitance PNP transistors and low-trigger NPN transistors.

[0014] Furthermore, the first trench area is filled with silica to form an annular isolation trench.

[0015] Furthermore, a second trench region extending into the P-type substrate is formed on the second N+ expansion region, and the second trench region is filled with P-type silicon to form a ring-shaped electrical connection layer.

[0016] Further, the annular isolation groove includes a first annular isolation groove, a second annular isolation groove, a third annular isolation groove, and a fourth annular isolation groove that are concentric and distributed sequentially from the inside to the outside, wherein:

[0017] The inner wall of the first annular isolation groove is connected to the N+ buried layer, and the outer wall is connected to the first N+ expansion zone.

[0018] The inner wall of the second annular isolation groove is in contact with the second P+ expansion zone, and there is a gap between the outer wall and the second N+ expansion zone.

[0019] There is a gap between the inner wall of the third annular isolation groove and the second N+ expansion zone;

[0020] There is a gap between the inner wall of the fourth annular isolation groove and the inner and outer walls of the third annular isolation groove.

[0021] Furthermore, the annular electrical connection layer includes a first annular electrical connection layer, a second annular electrical connection layer, a third annular electrical connection layer, and a fourth annular electrical connection layer arranged sequentially from the inside to the outside, all concentrically.

[0022] Furthermore, the thickness of the N-epipolar layer is 5µm-12µm, and its resistivity is greater than 100Ω·cm.

[0023] Furthermore, the doping material for the second N+ expansion region and the first N+ expansion region is phosphorus;

[0024] The doping material for the first P+ expansion region and the second P+ expansion region is boron;

[0025] The anode and cathode are made of aluminum.

[0026] This invention also provides a method for fabricating a low-capacitance, high-ESD protection device, comprising the following steps:

[0027] S1. An N+ buried layer is formed by implanting N-type dopant elements into the middle of the upper surface of a P-type substrate.

[0028] S2. An N- epitaxial layer is grown on a P-type substrate and an N+ buried layer using epitaxial growth technology;

[0029] S3. Phosphorus is implanted on the N- epitaxial layer to form a second N+ expansion region. The second N+ expansion region, together with the P-type substrate and the N+ buried layer, forms a low-trigger NPN transistor.

[0030] S4. Boron is implanted into the N-epitaxial layer and annealed at 1000-1150℃ to form the first P+ expansion region and the second P+ expansion region. Phosphorus is implanted into the N-epitaxial layer and annealed at 1000-1150℃ to form the first N+ expansion region.

[0031] Among them, the first P+ expansion region, together with the N- epitaxial layer, the N+ buried layer, and the P-type substrate, forms a low-capacitance PNP transistor;

[0032] The first N+ expansion region, the N- epitaxial region, and the second P+ expansion region together form a guiding diode;

[0033] S5. An annular isolation trench and an annular electrical connection layer are formed on the N-epitaxial layer by deep trench etching and filling.

[0034] S6. Anode and cathode of the circuit are formed by sputtering aluminum and etching on the dielectric layer; thus completing the fabrication of a low-capacitance, high-ESD protection device.

[0035] Furthermore, step S5 specifically includes:

[0036] The first trench region is formed on the N-epitaxial layer by deep trench etching, and polysilicon or silicon dioxide is filled in the first trench region to form an annular isolation trench, so as to electrically isolate the low capacitance PNP transistor and the low trigger NPN transistor.

[0037] A second trench region is formed on the N-epitaxial layer by deep trench etching, and a ring-shaped electrical connection layer is formed by filling the second trench region with P-type silicon.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0039] The present invention provides a low-capacitance, high-ESD protection device and its fabrication method. It employs a vertical SCR structure consisting of a P-type substrate, an N+ buried layer, an N- epitaxial layer, and a dielectric layer arranged sequentially from bottom to top. This structure reduces the dynamic impedance of the channel and enhances current discharge capability. Furthermore, in this application, the first P+ expansion region, together with the N- epitaxial layer, the N+ buried layer, and the P-type substrate, forms a low-capacitance PNP transistor. The capacitance of the protection device can be adjusted by changing the concentration of the N-epitaxy layer. This further helps to achieve ultra-low capacitance while ensuring high electrostatic protection capability. Moreover, by setting an annular isolation trench and an annular electrical connection layer, a double-trench structure is formed, achieving electrical isolation between the low-capacitance PNP transistor and the low-trigger NPN transistor, as well as electrical connection between devices, effectively solving the drawbacks of the vertical mesa structure. Attached Figure Description

[0040] Figure 1 This is a cross-sectional structural diagram of an embodiment of the present invention;

[0041] Figure 2 This is a top view of an embodiment of the present invention;

[0042] Figure 3 This is an equivalent circuit diagram of an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures: 1 is a P-type substrate, 2 is an N- epitaxial layer, 3 is a dielectric layer, 4 is an N+ buried layer, 5 is the first P+ expansion region, 6 is the first N+ expansion region, 7 is the second P+ expansion region, 8 is the second N+ expansion region, 9 is an annular isolation trench, 91 is the first annular isolation trench, 92 is the second annular isolation trench, 93 is the third annular isolation trench, 94 is the fourth annular isolation trench, 10 is an annular electrical connection layer, 101 is the first annular electrical connection layer, 102 is the second annular electrical connection layer, 103 is the third annular electrical connection layer, 104 is the fourth annular electrical connection layer, 11 is the anode, and 12 is the cathode. Detailed Implementation

[0044] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] like Figure 1 As shown, a low-capacitance, high ESD protection device includes a P-type substrate 1, an N-epitaxial layer 2, and a dielectric layer 3 connected sequentially from bottom to top.

[0046] An N+ buried layer 4, whose top is connected to the N- epitaxial layer 2, is provided in the middle of the upper surface of the P-type substrate 1;

[0047] like Figure 2 As shown, the upper surface of the N-extend 2 is provided with a first P+ expansion region 5 in the middle, and a first N+ expansion region group, a second P+ expansion region group and a second N+ expansion region 8 distributed from the inside to the outside; the first N+ expansion region group includes a plurality of circumferentially distributed first N+ expansion regions 6; the second P+ expansion region group includes a plurality of circumferentially distributed second P+ expansion regions 7.

[0048] Among them, the thickness of N-epitaxy 2 is 5um-12um, and its resistivity is 210Ω·cm; the doping material of the first P+ expansion region 5 and the second P+ expansion region 7 is boron; the doping material of the first N+ expansion region 6 and the second N+ expansion region 8 is phosphorus.

[0049] The second N+ expansion region 8, together with the P-type substrate 1 and the N+ buried layer 4, forms a low-trigger NPN transistor with a minimum trigger voltage of 5V; the first P+ expansion region 5, together with the N- epitaxial layer, the N+ buried layer 4, and the P-type substrate 1, forms a low-capacitance PNP transistor with a capacitance of 0.15pF; the first N+ expansion region 6, the N- epitaxial layer 2, and the second P+ expansion region 7 form a guiding diode;

[0050] To electrically isolate low-capacitance PNP transistors and low-trigger NPN transistors, a first trench region extending into the P-type substrate 1 is formed on the N-epitaxial layer 2. The first trench region is filled with polysilicon to form an annular isolation trench 9. The annular isolation trench 9 includes a first annular isolation trench 91, a second annular isolation trench 92, a third annular isolation trench 93, and a fourth annular isolation trench 94, which are concentric and distributed from the inside to the outside. Specifically: the inner wall of the first annular isolation trench 91 is connected to the N+ buried layer 4, and the outer wall is connected to the first N+ expansion region 6; the inner wall of the second annular isolation trench 92 is connected to the second P+ expansion region 7, and there is a gap between the outer wall and the second N+ expansion region 8; there is a gap between the inner wall of the third annular isolation trench 93 and the second N+ expansion region 8; and there is a gap between the inner wall of the fourth annular isolation trench 94 and the inner and outer walls of the third annular isolation trench 93.

[0051] A second trench region extending into the P-type substrate 1 is formed on the second N+ expansion region 8, and the second trench region is filled with P-type silicon to form an annular electrical connection layer 10. The annular electrical connection layer 10 includes a first annular electrical connection layer 101, a second annular electrical connection layer 102, a third annular electrical connection layer 103 and a fourth annular electrical connection layer 104 arranged in a circular pattern from the inside to the outside.

[0052] The dielectric layer 3 is provided with an anode 11 and a cathode 12. The anode 11 and the cathode 12 are made of aluminum. The bottom of the anode 11 is connected to the first P+ expansion region 5 and the first N+ expansion region 6, and the bottom of the cathode 12 is connected to the second N+ expansion region 8 and the second P+ expansion region 7.

[0053] In this embodiment, the forward pulse current discharge path passes through the anode 11 of the low-capacitance, high-ESD protection device, the first P+ expansion region 5, the N- epitaxial layer 2, the N+ buried layer 4, the P+ substrate 1, the annular electrical connection layer 9, and the second N+ expansion region 8 to the cathode 12.

[0054] The second N+ expansion region 8, together with the P-type substrate 1 and the N+ buried layer 4, forms a low-trigger NPN transistor; the first P+ expansion region 5, together with the N- epitaxial layer, the N+ buried layer 4, and the P-type substrate 1, forms a low-capacitance PNP transistor; the first N+ expansion region 6, the N- epitaxial layer 2, and the second P+ expansion region 7 form a guiding diode D1; the circuit consisting of the low-trigger NPN transistor, the low-capacitance PNP transistor, and the guiding diode is as follows: Figure 3 As shown.

[0055] The specific method for fabricating a low-capacitance, high-ESD protection device is as follows:

[0056] S1. N-type dopant elements are implanted into the middle of the upper surface of the P-type substrate 1 to form an N+ buried layer 4;

[0057] S2. An N-epitaxial layer 2 is grown on the P-type substrate 1 and the N+ buried layer 4 using epitaxial growth technology;

[0058] S3. Phosphorus is implanted into the N-epitaxial layer 2 and annealed at 1000-1150℃ to form the second N+ expansion region 8. The second N+ expansion region 8, together with the P-type substrate 1 and the N+ buried layer 4, forms a low-trigger NPN transistor.

[0059] S4. Boron is implanted into N-epitaxial 2 and annealed at 1000-1150℃ to form the first P+ expansion region 5 and the second P+ expansion region 7. Phosphorus is implanted into N-epitaxial 2 and annealed at 1000-1150℃ to form the first N+ expansion region 6.

[0060] Among them, the first P+ expansion region 5, together with the N- epitaxial layer, the N+ buried layer 4, and the P-type substrate 1, forms a low capacitance PNP transistor;

[0061] The first N+ expansion region 6, the N- epitaxial region 2, and the second P+ expansion region 7 form a guiding diode;

[0062] S5. A first trench region is formed on the N-epitaxial 2 by deep trench etching. Polysilicon or silicon dioxide is filled in the first trench region to form an annular isolation trench 9, which provides electrical isolation between the low capacitance PNP transistor and the low trigger NPN transistor.

[0063] A second trench region is formed on the N-epitaxial layer 2 by deep trench etching, and a ring-shaped electrical connection layer 10 is formed by filling the second trench region with P-type silicon.

[0064] S6. Anode 11 and cathode 12 of the circuit are formed by sputtering aluminum and etching on dielectric layer 3; thus completing the fabrication of a low-capacitance, high-ESD protection device.

[0065] In other embodiments of the present invention, the first trench area is filled with silicon dioxide to form an annular isolation trench 9.

[0066] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-capacitance, high ESD protection device, characterized in that: It includes a P-type substrate (1), an N-epitaxial layer (2), and a dielectric layer (3) connected sequentially from bottom to top; The upper surface of the P-type substrate (1) is provided with an N+ buried layer (4) whose top is connected to the N- epitaxial layer (2); The upper surface of the N-extension (2) is provided with a first P+ expansion region (5) in the middle, and a first N+ expansion region group, a second P+ expansion region group and a second N+ expansion region (8) distributed from the inside to the outside; the first N+ expansion region group includes a plurality of circumferentially distributed first N+ expansion regions (6); the second P+ expansion region group includes a plurality of circumferentially distributed second P+ expansion regions (7). The second N+ expansion region (8), together with the P-type substrate (1) and the N+ buried layer (4), forms a low-trigger NPN transistor; the first P+ expansion region (5), together with the N-epitaxial layer, the N+ buried layer (4), and the P-type substrate (1), forms a low-capacitance PNP transistor; the first N+ expansion region (6), the N-epitaxial layer (2), and the second P+ expansion region (7) form a guiding diode; The N-epipolar layer (2) has an annular isolation trench (9) extending into the P-type substrate (1) for electrical isolation of low-capacitance PNP transistors and low-trigger NPN transistors. An annular electrical connection layer (10) extending into the P-type substrate (1) is formed on the second N+ expansion region (8); The dielectric layer (3) is provided with an anode (11) and a cathode (12). The bottom of the anode (11) is connected to the first P+ expansion region (5) and the first N+ expansion region (6), and the bottom of the cathode (12) is connected to the second N+ expansion region (8) and the second P+ expansion region (7).

2. The low-capacitance, high ESD protection device according to claim 1, characterized in that: The N-epipolar layer (2) has a first trench region extending into the P-type substrate (1), and the first trench region is filled with polysilicon to form an annular isolation trench (9) for electrical isolation of low capacitance PNP transistors and low trigger NPN transistors.

3. The low-capacitance, high ESD protection device according to claim 2, characterized in that: The first trench area is filled with silica to form an annular isolation trench (9).

4. The low-capacitance, high ESD protection device according to claim 1, characterized in that: A second trench region extending into the P-type substrate (1) is formed on the second N+ expansion region (8), and the second trench region is filled with P-type silicon to form an annular electrical connection layer (10).

5. The low-capacitance, high ESD protection device according to claim 1, characterized in that: The annular isolation groove (9) includes a first annular isolation groove (91), a second annular isolation groove (92), a third annular isolation groove (93), and a fourth annular isolation groove (94) that are concentric and distributed from the inside to the outside, wherein: The inner wall of the first annular isolation groove (91) is connected to the N+ buried layer (4), and the outer wall is connected to the first N+ expansion zone (6); The inner wall of the second annular isolation groove (92) is connected to the second P+ expansion zone (7), and there is a gap between the outer wall and the second N+ expansion zone (8); There is a gap between the inner wall of the third annular isolation groove (93) and the second N+ expansion zone (8); There is a gap between the inner wall of the fourth annular isolation groove (94) and the inner and outer walls of the third annular isolation groove (93).

6. The low-capacitance, high ESD protection device according to claim 1, characterized in that: The annular electrical connection layer (10) includes a first annular electrical connection layer (101), a second annular electrical connection layer (102), a third annular electrical connection layer (103), and a fourth annular electrical connection layer (104) arranged sequentially from the inside to the outside, all concentrically.

7. The low-capacitance, high ESD protection device according to claim 1, characterized in that: The thickness of the N-epipolar layer (2) is 5µm-12µm, and its resistivity is greater than 100µm.

8. The low-capacitance, high ESD protection device according to claim 1, characterized in that: The doping material of the second N+ expansion region (8) and the first N+ expansion region (6) is phosphorus; The doping material of the first P+ expansion region (5) and the second P+ expansion region (7) is boron; The anode (11) and cathode (12) are made of aluminum.

9. A method for fabricating a low-capacitance, high ESD protection device, characterized in that, Includes the following steps: S1. N-type dopant elements are implanted in the middle of the upper surface of the P-type substrate (1) to form an N+ buried layer (4); S2. An N- epitaxial layer (2) is grown on a P-type substrate (1) and an N+ buried layer (4) using epitaxial growth technology; S3. Phosphorus is implanted on the N- epitaxial layer (2) and annealed at 1000-1150℃ to form a second N+ expansion region (8). The second N+ expansion region (8), together with the P-type substrate (1) and the N+ buried layer (4), forms a low-trigger NPN transistor. S4. Boron is implanted into the N-epitaxy (2) and annealed at 1000-1150℃ to form the first P+ expansion region (5) and the second P+ expansion region (7). Phosphorus is implanted into the N-epitaxy (2) and annealed at 1000-1150℃ to form the first N+ expansion region (6). Among them, the first P+ expansion region (5), together with the N- epitaxial layer, the N+ buried layer (4), and the P-type substrate (1), form a low capacitance PNP transistor; The first N+ expansion region (6), the N- epitaxial region (2), and the second P+ expansion region (7) form a guiding diode; S5. An annular isolation trench (9) and an annular electrical connection layer (10) are formed on the N-epitaxy (2) by deep trench etching and filling; S6. Anode (11) and cathode (12) of the circuit are formed by sputtering aluminum and etching on the dielectric layer (3); thus completing the fabrication of a low-capacitance, high-ESD protection device.

10. The method for fabricating a low-capacitance, high-ESD protection device according to claim 9, characterized in that, Step S5 is as follows: A first trench region is formed on the N-epitaxial layer (2) by deep trench etching, and a ring-shaped isolation trench (9) is formed by filling the first trench region with polysilicon or silicon dioxide to electrically isolate the low capacitance PNP transistor and the low trigger NPN transistor. A second trench region is formed on the N-epitaxy (2) by deep trench etching, and a ring-shaped electrical connection layer (10) is formed by filling the second trench region with P-type silicon.

Images