Memory system, operation method thereof and computer readable storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a computer readable storage medium. The memory system includes at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each nonvolatile storage device comprises a plurality of storage blocks, and at least one storage block in at least one nonvolatile storage device forms a super block; the controller is configured to determine the sequence of the plurality of super blocks according to the number of erasure times of each super block and the number of bad blocks in each super block; wherein the erasing times of any two adjacent super blocks in the sorting meet a preset requirement; the first super blocks in the sorting are arranged at intervals, and the number of bad blocks in the first super blocks is greater than a preset value; and according to the sequence of the plurality of super blocks, determining the priority of performing the write-in operation on the plurality of super blocks.

Description

A memory system and its operating method, and computer-readable storage medium Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a memory system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] Memory systems, such as solid-state drives (SSDs), can use flash memory, dynamic random access memory (DRAM), or 3D XPoint as storage media. The Flash Translation Layer (FTL) maps the host's logical block address (LBA) to the flash memory's physical block address (PBA). In other words, the FTL requires a mapping table from LBA to PBA. This mapping table must be searched and updated in real time throughout the SSD's read and write processes to ensure accurate data reads and writes. Therefore, the quality of the FTL algorithm directly determines the performance, reliability, and endurance of the memory system (e.g., SSD).

[0003] Proper planning and use of storage devices in a memory system can optimize the FTL algorithm and is crucial for achieving high performance and low power consumption in memory systems (e.g., SSDs). Poor management of storage devices in a memory system can lead to significant performance fluctuations.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide a memory system, an operating method thereof, and a computer-readable storage medium.

[0006] In a first aspect, embodiments of the present disclosure provide a memory system, comprising at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each non-volatile memory device comprises a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device forms a super block; and the controller is configured to:

[0007] Determining an order of the plurality of super blocks based on the number of erasures of each super block and the number of bad blocks in each super block; wherein the number of erasures of any two adjacent super blocks in the order meets a preset requirement; and wherein an interval between first super blocks in the order is set, and the number of bad blocks in the first super block is greater than a preset value;

[0008] According to the order of the multiple super blocks, the priority of writing operations to the multiple super blocks is determined.

[0009] In some embodiments, the controller is specifically configured to:

[0010] The higher the ranking of the super block in the ranking, the higher the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the ranking is less than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the ranking is greater than the number of erasures of the super block with the lower ranking and the difference between the number of erasures of the two super blocks is less than a preset difference; or,

[0011] The higher the ranking of the super block in the sorting, the lower the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is greater than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is less than the number of erasures of the super block with the lower ranking and the difference in the number of erasures of the two super blocks is less than a preset difference.

[0012] In some embodiments, the controller is specifically configured to:

[0013] According to the number of erasures of each super block, a pre-order of the plurality of super blocks is determined; wherein, in the pre-order, the plurality of super blocks are arranged in order from small to large or from large to small according to the number of erasures.

[0014] In some embodiments, the controller is specifically configured to:

[0015] Determining at least two adjacently arranged first super blocks according to the pre-sorting of the plurality of super blocks;

[0016] According to the number of bad blocks in the first super block, the order or position of the first super block is adjusted to determine a first sub-sequence of multiple super blocks; wherein the number of erasures of any two adjacent super blocks in the first sub-sequence meets a preset requirement; and the first super blocks in the first sub-sequence are not arranged adjacent to each other.

[0017] In some embodiments, the plurality of super blocks further include a second super block and a third super block; wherein the number of bad blocks in the second super block is greater than 0 and less than or equal to a preset value; and the number of bad blocks in the third super block is equal to 0;

[0018] The first super block and the second super block in the first sub-sequence are arranged adjacent to each other; or the first super block and the third super block in the first sub-sequence are arranged adjacent to each other.

[0019] In some embodiments, the controller is specifically configured to:

[0020] Determining, according to the first sub-ranking of the plurality of super blocks, the first super block and the second super block that are adjacently arranged;

[0021] According to the number of bad blocks in the first super block and the second super block, the order or position of the first super block and the second super block is adjusted to determine a second sub-sequence of the multiple super blocks; wherein the number of erase times of any two adjacent super blocks in the second sub-sequence meets the preset requirements; and the first super block and the second super block in the second sub-sequence are not adjacently arranged.

[0022] In some embodiments, the two second super blocks in the second sub-sort are adjacently arranged; or, the first super block and the third super block in the second sub-sort are adjacently arranged; or, the second super block and the third super block in the second sub-sort are adjacently arranged.

[0023] In some embodiments, the controller is specifically configured to:

[0024] determining at least two adjacent second super blocks according to the second sub-rankings of the plurality of super blocks;

[0025] According to the number of bad blocks in the second super block, the order or position of the second super blocks is adjusted to determine the sorting of the plurality of super blocks; wherein the second super blocks in the sorting are not arranged adjacent to each other.

[0026] In some embodiments, the second super block and the third super block are arranged adjacent to each other in the sorting.

[0027] In some embodiments, the super block includes a free block.

[0028] In a second aspect, embodiments of the present disclosure provide a method for operating a memory system, the memory system comprising at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each non-volatile memory device comprises a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device forms a super block; the operating method comprising:

[0029] Determining an order of the plurality of super blocks based on the number of erasures of each super block and the number of bad blocks in each super block; wherein the number of erasures of any two adjacent super blocks in the order meets a preset requirement; and wherein an interval between first super blocks in the order is set, and the number of bad blocks in the first super block is greater than a preset value;

[0030] According to the order of the multiple super blocks, the priority of writing operations to the multiple super blocks is determined.

[0031] In some embodiments, determining the priority of writing to the plurality of super blocks according to the order of the plurality of super blocks includes:

[0032] The higher the ranking of the super block in the ranking, the higher the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the ranking is less than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the ranking is greater than the number of erasures of the super block with the lower ranking and the difference between the number of erasures of the two super blocks is less than a preset difference; or,

[0033] The higher the ranking of the super block in the sorting, the lower the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is greater than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is less than the number of erasures of the super block with the lower ranking and the difference in the number of erasures of the two super blocks is less than a preset difference.

[0034] In some embodiments, before determining the order of the plurality of super blocks according to the number of erasures of each super block and the number of bad blocks in each super block, the operating method further comprises:

[0035] According to the number of erasures of each super block, a pre-order of the plurality of super blocks is determined; wherein, in the pre-order, the plurality of super blocks are arranged in order from small to large or from large to small according to the number of erasures.

[0036] In some embodiments, after determining the pre-order of the plurality of super blocks according to the number of erasures of each super block, the operating method further comprises:

[0037] Determining at least two adjacently arranged first super blocks according to the pre-sorting of the plurality of super blocks;

[0038] According to the number of bad blocks in the first super block, the order or position of the first super block is adjusted to determine a first sub-sequence of multiple super blocks; wherein the number of erasures of any two adjacent super blocks in the first sub-sequence meets a preset requirement; and the first super blocks in the first sub-sequence are not arranged adjacent to each other.

[0039] In some embodiments, the plurality of super blocks further include a second super block and a third super block; wherein the number of bad blocks in the second super block is greater than 0 and less than or equal to a preset value; and the number of bad blocks in the third super block is equal to 0;

[0040] The first super block and the second super block in the first sub-sequence are arranged adjacent to each other; or the first super block and the third super block in the first sub-sequence are arranged adjacent to each other.

[0041] In some embodiments, after adjusting the order or position of the first super blocks according to the number of bad blocks in the first super block to determine a first sub-order of the plurality of super blocks, the operating method further includes:

[0042] Determining, according to the first sub-ranking of the plurality of super blocks, the first super block and the second super block that are adjacently arranged;

[0043] According to the number of bad blocks in the first super block and the second super block, the order or position of the first super block and the second super block is adjusted to determine a second sub-sequence of the multiple super blocks; wherein the number of erase times of any two adjacent super blocks in the second sub-sequence meets the preset requirements; and the first super block and the second super block in the second sub-sequence are not adjacently arranged.

[0044] In some embodiments, the two second super blocks in the second sub-sort are adjacently arranged; or, the first super block and the third super block in the second sub-sort are adjacently arranged; or, the second super block and the third super block in the second sub-sort are adjacently arranged.

[0045] In some embodiments, after adjusting the order or position of the first super block and the second super block based on the number of bad blocks in the first super block and the second super block to determine a second sub-ordering of the plurality of super blocks, the operating method further includes:

[0046] determining at least two adjacent second super blocks according to the second sub-rankings of the plurality of super blocks;

[0047] According to the number of bad blocks in the second super block, the order or position of the second super blocks is adjusted to determine the sorting of the plurality of super blocks; wherein the second super blocks in the sorting are not arranged adjacent to each other.

[0048] In some embodiments, the second super block and the third super block are arranged adjacent to each other in the sorting.

[0049] In some embodiments, the super block includes a free block.

[0050] In a third aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method of the memory system as described in the above technical solution can be implemented.

[0051] Embodiments of the present disclosure provide a memory system, an operating method thereof, and a computer-readable storage medium. In the embodiments of the present disclosure, the priority of writing to a superblock is determined by simultaneously considering the number of superblock erases and the number of bad blocks within the superblock, thereby effectively smoothing write performance and enhancing the performance stability of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1 is a block diagram of a system having a non-volatile storage device according to an embodiment of the present disclosure;

[0053] FIG2A is a schematic diagram of a memory card having a non-volatile storage device according to an embodiment of the present disclosure;

[0054] FIG2B is a schematic diagram of a solid-state drive having a non-volatile storage device according to an embodiment of the present disclosure;

[0055] FIG3 is a schematic diagram of a non-volatile memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0056] FIG4 is a cross-sectional schematic diagram of a memory cell array including memory strings according to an embodiment of the present disclosure;

[0057] FIG5 is a block diagram of a non-volatile memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0058] FIG6 is a flow chart of an operating method of a memory system according to an embodiment of the present disclosure;

[0059] FIG7 is a schematic diagram of a memory system provided by an embodiment of the present disclosure;

[0060] FIG8 is a schematic diagram of a super block provided by an embodiment of the present disclosure;

[0061] FIG9 is a sequence diagram of super blocks provided in a specific example;

[0062] FIG10 is a sequence diagram of super blocks provided in another specific example;

[0063] FIG11 is a graph showing the write rates of each superblock in the sorting. DETAILED DESCRIPTION

[0064] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0065] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0066] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0067] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0068] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0069] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0070] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0071] The non-volatile memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND non-volatile memory device. For ease of understanding, the three-dimensional NAND non-volatile memory device is used as an example for description.

[0072] Referring to FIG1 , which is a block diagram of a system having a non-volatile memory device according to an embodiment of the present disclosure, system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a non-volatile memory device.

[0073] As shown in FIG1 , system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more non-volatile storage devices 104 and a controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to or receive data from the non-volatile storage device 104.

[0074] In some embodiments, the controller 106 is coupled to the nonvolatile storage device 104 and the host 108 and is configured to control the nonvolatile storage device 104. The controller 106 may manage data stored in the nonvolatile storage device 104 and communicate with the host 108.

[0075] In some embodiments, the controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0076] In some embodiments, the controller 106 is designed to operate in a high duty cycle environment SSD or embedded Multi-Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0077] The controller 106 may be configured to control operations of the non-volatile storage device 104, such as read, erase, and program operations. The controller 106 may also be configured to manage various functions related to data stored or to be stored in the non-volatile storage device 104, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, the controller 106 is further configured to process error correction codes (ECC) on data read from or written to the non-volatile storage device 104.

[0078] The controller 106 may also perform any other suitable functions, such as formatting the non-volatile storage device 104. The controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0079] The controller 106 and the one or more non-volatile storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0080] Referring to FIG2A , FIG2A is a schematic diagram of a memory card with a non-volatile storage device according to an embodiment of the present disclosure. As shown in FIG2A , the controller 106 and the single non-volatile storage device 104 can be integrated into a memory card 202. The memory card 202 can include a Personal Computer Memory Card International Association (PCMCIA) card, a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC, RS-MMC (Reduced-Size MMC), MMCmicro), an SD (e.g., SD, miniSD (miniSD), microSD (microSD), Secure Digital High Capacity (SDHC)) card, a UFS card, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ).

[0081] Referring to FIG. 2B , FIG. 2B is a schematic diagram of a solid-state drive having a non-volatile memory device according to an embodiment of the present disclosure. As shown in FIG. 2B , the controller 106 and the plurality of non-volatile memory devices 104 may be integrated into a solid-state drive 206. The solid-state drive 206 may also include a solid-state drive connector 208 for coupling the solid-state drive 206 to a host (e.g., the host 108 in FIG. 1 ). In some embodiments, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0082] Referring to FIG3 , FIG3 is a schematic diagram of a nonvolatile memory device including peripheral circuitry according to an embodiment of the present disclosure. Nonvolatile memory device 300 may be an example of nonvolatile memory device 104 in FIG1 . Nonvolatile memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. Memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308 , each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0083] In some embodiments, each memory cell 306 may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0," where the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erased state, and the second storage state is a programmed state. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to adopt a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11," a second storage state "10," a third storage state "01," and a fourth storage state "00." Here, the threshold voltage distributions of the first, second, third, and fourth storage states correspond to first, second, third, and fourth voltage ranges, respectively. The first storage state is an erased state, and the second, third, and fourth storage states are all programmed states. Similarly, TLC can have eight storage states, including an erased state and seven programmed states; and QLC can have 16 storage states, including an erased state and 15 programmed states.

[0084] As shown in FIG3 , each memory string 308 may include a source select transistor (SST) 310 at its source terminal and a drain select transistor (DST) 312 at its drain terminal. The source select transistor 310 and the drain select transistor 312 may be configured to activate a selected memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, in some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). In some embodiments, the drain of the drain select transistor 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 312 via one or more drain select gate lines (DSL) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the source select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 310 via one or more source select gate lines (SSL) 315.

[0085] As shown in FIG3 , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a source line 314 (e.g., a common SL coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at a half-memory block level, at a quarter-memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding memory page 320 and a gate line coupling the control gates.

[0086] It should be noted that the memory page illustrated in Figure 3 is a physical page, which refers to a layer of memory cells on the physical layer. The basic data unit for programming and reading operations is the logical page. For SLC, each memory cell can store 1 bit of information. Therefore, the information stored in one layer of memory cells on the physical layer (i.e., 1 physical page) corresponds to the information of one logical page. For MLC, each memory cell can store 1 bit of information. Therefore, the information stored in one layer of memory cells on the physical layer (i.e., 1 physical page) corresponds to the information of two logical pages. For TLC, each memory cell can store 1 bit of information. Therefore, the information stored in one layer of memory cells on the physical layer (i.e., 1 physical page) corresponds to the information of three logical pages. For QLC, each memory cell can store 1 bit of information. Therefore, the information stored in one layer of memory cells on the physical layer (i.e., 1 physical page) corresponds to the information of four logical pages.

[0087] Referring to Figure 4, which is a schematic cross-sectional view of a memory cell array including memory strings according to an embodiment of the present disclosure, as shown in Figure 4, memory strings 308 may extend vertically through a memory stack layer 404 above a substrate 402. The substrate 402 may comprise silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0088] The memory stack 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack 404 may determine the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a drain select gate line 313, at the bottom of the memory stack 404 as a source select gate line 315, or between the drain select gate line 313 and the source select gate line 315 as a word line 318.

[0089] As shown in FIG4 , the memory string 308 includes a channel structure extending vertically through the memory stack layer 404 . In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a “charge trapping / storage layer”), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0090] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in substrate 402, and the source terminal of memory string 308 may contact the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string further includes a channel plug at the drain terminal of the memory string 308. It should be understood that, although not shown in FIG. 4 , additional components of memory cell array 301 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0091] 3 , the peripheral circuit 302 may be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, source select gate lines 315, and drain select gate lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuitry for facilitating the operation of the memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, source select gate lines 315, and drain select gate lines 313. The peripheral circuit 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0092] Referring to Figure 5 , which is a block diagram of a non-volatile memory device including peripheral circuits according to an embodiment of the present disclosure, the peripheral circuits include a page buffer / sense amplifier 504, a column driver / bit line driver 506, a row driver / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface (I / F) 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in Figure 5 may also be included.

[0093] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to the control signal from the control logic unit 512. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column driver / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0094] The row driver / wordline driver 508 can be configured to be controlled by the control logic unit 512 and select / deselect the memory blocks 304 of the memory cell array 301 and select / deselect the word lines 318 of the memory blocks 304. The row driver / wordline driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row driver / wordline driver 508 can also select / deselect and drive the source select gate line 315 and the drain select gate line 313. As described in detail below, the row driver / wordline driver 508 is configured to perform an erase operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0095] The control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer control commands received from a host (not shown in FIG. 5 ) and relay them to the control logic unit 512, as well as buffer status information received from the control logic unit 512 and relay it to the host. The interface 516 can also be coupled to the column driver / bit line driver 506 via the data bus 518 and act as a data input / output (I / O) interface and a data buffer to buffer data and relay it to or from the memory cell array 301.

[0096] Proper planning and use of storage devices in a memory system can optimize the FTL algorithm and is crucial for achieving high performance and low power consumption in SSDs. Poor management of storage devices in a memory system can lead to significant performance fluctuations. Currently, poor management of storage devices in memory systems is a widespread problem in the industry. This is primarily due to the complexity of managing storage devices in memory systems. The classification and sorting of storage devices in memory systems requires integration with the FTL to maximize benefits. Proper planning and use of storage devices in a memory system can be managed on a superblock basis.

[0097] In view of this, embodiments of the present disclosure provide a memory system and an operating method thereof, and a computer-readable storage medium.

[0098] Referring to FIG. 6 , FIG. 6 is a flow chart illustrating a method for operating a memory system according to an embodiment of the present disclosure. Referring to FIG. 7 , FIG. 7 is a schematic diagram illustrating a memory system according to an embodiment of the present disclosure. As shown in FIG. 6 and FIG. 7 , an embodiment of the present disclosure provides a method for operating a memory system. The memory system 102 includes at least one non-volatile memory device 104 and a controller 106 coupled to the non-volatile memory device 104. The non-volatile memory device 104 includes a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device 104 forms a super block. The operating method includes:

[0099] S601: Determine an order of multiple super blocks based on the number of erase times of each super block and the number of bad blocks in each super block; wherein the number of erase times of any two adjacent super blocks in the order meets a preset requirement; an interval is set for the first super block in the order, and the number of bad blocks in the first super block is greater than a preset value;

[0100] S602: Determine the priority of writing operations to the multiple super blocks according to the order of the multiple super blocks.

[0101] As shown in FIG7 , the controller 106 can be connected to multiple non-volatile memory devices 104 through a first channel CH1 and a second channel CH2, respectively. For example, the non-volatile memory device 104 can be a die. Specifically, the non-volatile memory devices Die_11, Die_12, through Die_1n can be connected to the first channel CH1, and the non-volatile memory devices Die_11, Die_12, through Die_1n can communicate with the controller 106 through the first channel CH1; the non-volatile memory devices Die_21, Die_22, through Die_2n can be connected to the second channel CH2, and the non-volatile memory devices Die_21, Die_22, through Die_2n can communicate with the controller 106 through the second channel CH2; wherein n is an integer greater than or equal to 1. The present disclosure does not impose any particular limitation on the number of channels or the number of non-volatile memory devices connected to each channel.

[0102] For example, the controller 106 may send a command to the non-volatile memory device Die_11 through the first channel CH1 , wherein the command includes an operation type, target data, and a target address.

[0103] Referring to Figure 8, which is a schematic diagram of a super block according to an embodiment of the present disclosure, the concepts of a super block and the number of bad blocks within a super block according to an embodiment of the present disclosure will be explained in detail below with reference to Figure 8.

[0104] As shown in Figure 8, in the non-volatile storage devices Die_0 to Die_N, each non-volatile storage device may include one or more storage planes (Plane), each storage plane may include multiple storage blocks, and each storage block may include multiple storage pages. Figure 8 illustrates that each non-volatile storage device may include two storage planes (i.e., Plane0 and Plane1), each storage plane may include storage blocks BLK0 to BLKm; wherein m is an integer greater than or equal to 0. The embodiments of the present disclosure do not impose any special restrictions on the number of storage planes included in each non-volatile storage device, the number of storage blocks included in each storage plane, and the number of storage pages included in each storage block.

[0105] In some embodiments, the controller can use a super block to manage non-volatile storage devices Die_0 to Die_N. The controller manages in units of super blocks, and a super block can include at least one storage block in at least one non-volatile storage device. For example, a super block can include storage blocks with the same sequence number across all storage planes in all non-volatile storage devices.

[0106] Still as shown in FIG8 , the memory blocks BLK0 included in each storage plane of each non-volatile memory device in Die_0 to Die_N can collectively constitute a super block Super BLK0; the memory blocks BLK1 included in each storage plane of each non-volatile memory device in Die_0 to Die_N can collectively constitute a super block Super BLK1; and the memory blocks BLKm included in each storage plane of each non-volatile memory device in Die_0 to Die_N can collectively constitute a super block Super BLKm. In this way, non-volatile memory devices Die_0 to Die_N can include super blocks Super BLK0 to Super BLKm. Of course, the embodiment of the present disclosure does not place any special limitation on the number of memory blocks included in a super block. Exemplarily, a super block may include storage blocks with the same serial number in each storage plane of each non-volatile storage device, for example, a super block includes 2n storage blocks; a super block may also include storage blocks with the same serial number in some storage planes of some non-volatile storage devices, for example, a super block includes 1 storage block, 2 storage blocks or 4 storage blocks.

[0107] The embodiments of the present disclosure do not impose any special limitations on the manner in which super blocks are divided. For example, a super block may include memory blocks with the same serial number for each storage plane of each non-volatile storage device in at least some non-volatile storage devices coupled to the same channel. For example, a super block may include memory blocks with the same serial number for each storage plane of each non-volatile storage device in Die_11 to Die_1L (L is less than or equal to n) coupled to the first channel CH1 in FIG7 ; a super block may also include memory blocks with the same serial number for each storage plane of each non-volatile storage device in Die_21 to Die_2L (L is less than or equal to n) coupled to the second channel CH2 in FIG7 . Exemplarily, a super block may also include storage blocks with the same serial number for each storage plane of each non-volatile storage device in non-volatile storage devices coupled to different channels. For example, a super block may include storage blocks with the same serial number for each storage plane of each non-volatile storage device in the non-volatile storage device Die_11 coupled to the first channel CH1 and the non-volatile storage device Die_21 coupled to the second channel CH2 in FIG. 7 .

[0108] It should be noted that any storage block shown in FIG8 may be a physical bad block (Bad Physical Block), which can also be called a bad block. In other words, both physical bad blocks and bad blocks belong to the storage block level. For example, BLK1 of the storage plane Plane1 of the non-volatile storage device Die_0 is a physical bad block. The sources of these physical bad blocks mainly include: factory bad blocks (Factory Bad Block) and grown bad blocks (Grown Bad Block); among them, factory bad blocks refer to the fact that there are more or less bad blocks when they come out of the factory; grown bad blocks refer to the fact that as the number of erases increases, the storage block may wear out and become a physical bad block.

[0109] There are two strategies for managing physical bad blocks: the Skip strategy and the Replace strategy. The Skip strategy means that when a user writes to a storage block, if a physical bad block is encountered, the write operation will be skipped and the next storage block will be written to. For example, when writing to Super BLK0, the more physical bad blocks Super BLK0 contains, the less space Super BLK0 has available for writing, and the lower the write rate for Super BLK0.

[0110] The replacement policy refers to replacing bad physical blocks with spare blocks when writing to a storage block. For example, when writing to Super BLK0, if there are bad physical blocks in Super BLK0, the bad blocks are replaced with spare blocks, and the available write space in Super BLK0 remains unchanged.

[0111] In the disclosed embodiment, the number of bad blocks in a super block is the number of physical bad blocks in the super block, and may also be referred to as the number of bad storage planes (Bad Plane Number) in the super block. This is because a super block may include multiple storage blocks. For example, a super block may include storage blocks with the same serial number as the storage planes of a non-volatile storage device. For example, a super block Super BLK1 may include 2n storage blocks BLK1, and BLK1 of the storage plane Plane1 of the non-volatile storage device Die_0 may be a physical bad block, and the number of physical bad blocks in the super block is 1. In other words, for the super block Super BLK1, the storage plane Plane1 of the non-volatile storage device Die_0 may be a bad storage plane, and the number of bad storage planes in the super block is 1.

[0112] It should be noted that when the FTL manages a Super Block, it can be divided into Free Blocks, Closed Blocks, Garbage Blocks, and Bad Blocks. In other words, Free Blocks, Closed Blocks, Garbage Blocks, and Bad Blocks all belong to the Super Block and can each include multiple storage blocks. The following briefly explains the concepts of Free Blocks, Closed Blocks, Garbage Blocks, and Bad Blocks.

[0113] A free block refers to a super block that can be used for write operations. In the embodiment of the present disclosure, when a write operation is required, the super block with the highest priority for the write operation is selected from the order of the super blocks as the target super block, and the target data is written to the target super block. A closed block refers to a super block with no remaining storage space or very little remaining storage space. In other words, only after the closed block is erased and storage space is freed up can the closed block be programmed. A garbage block refers to a super block that will undergo garbage collection (GC). During the garbage collection process, valid data in the garbage block needs to be moved to the target super block, and all data in the garbage block needs to be erased to obtain a new available super block, i.e., a free block; alternatively, during the garbage collection process, valid data in the garbage block needs to be moved to the target super block, and the garbage block can be marked as a free block. When writing data to such a free block, the erase operation will be performed on such a free block first, and then the data will be written. An unavailable block refers to a super block that cannot be used normally. Among multiple storage blocks included in the unavailable block, a certain number of storage blocks are considered bad blocks.

[0114] In the disclosed embodiment, in S601, the sorting of Super Blocks requires simultaneous consideration of two factors: the first factor is the erase count of the Super Block, and the second factor is the number of bad blocks within the Super Block. The sorting of the multiple Super Blocks is determined based on the erase counts of the Super Blocks and the number of bad blocks within the Super Blocks. For the first factor, the erase counts of any two adjacent Super Blocks in the sorting must meet a preset requirement. For the second factor, the interval between the first Super Blocks in the sorting must be set, and the number of bad blocks within the first Super Block must be greater than a preset value.

[0115] Regarding the first factor, it's important to note that a superblock consists of multiple memory blocks. A memory block is the basic unit of data for erase operations. Each erase operation causes wear on the memory block. Therefore, each memory block has a lifespan, which can be measured by the number of erase cycles. When a memory block's erase cycles exceed its lifespan, it may become defective and lose its ability to store charge. Therefore, data cannot be concentrated on a few memory blocks, as these blocks will quickly lose their ability to store charge due to the number of erase cycles exceeding their lifespan. Typically, we expect all memory blocks to evenly distribute data writes, ensuring that each block experiences roughly the same level of wear, thereby ensuring the maximum data write throughput for the memory system. Similarly, we expect all superblocks to evenly distribute data writes, ensuring that each superblock experiences roughly the same level of wear, thereby ensuring the maximum data write throughput for the memory system.

[0116] In the disclosed embodiments, the Super Block erase count is used as the first factor in Super Block sorting. The erase counts of any two adjacent Super Blocks in the sorting of multiple Super Blocks must meet a preset requirement. This ensures that each Super Block experiences substantially equal wear, thereby ensuring the maximum data write throughput for the memory system. The details of how the Super Block erase count meets this requirement will be explained later.

[0117] Regarding the second factor, it should be noted that the more bad blocks there are in a super block, the less space there is for writing data in the super block. When a write operation is performed on the super block, the amount of data that can be written in the same length of time is less, the write rate is reduced, and the performance of the memory system deteriorates.

[0118] In the disclosed embodiment, a Super Block is divided into a first Super Block, a second Super Block, and a third Super Block based on the number of bad blocks within the Super Block. The number of bad blocks within the first Super Block is greater than the preset value; the number of bad blocks within the second Super Block is greater than 0 and less than or equal to the preset value; and the number of bad blocks within the third Super Block is equal to 0. In short, the first Super Block has a higher number of bad blocks, the second Super Block has a lower number of bad blocks, and the third Super Block has no bad blocks. For two adjacent Super Blocks in the sorting process, the following five scenarios may exist: In the first scenario, two first Super Blocks are adjacent; in the second scenario, the first Super Block and the second Super Block are adjacent; in the third scenario, the first Super Block and the third Super Block are adjacent; in the fourth scenario, two second Super Blocks are adjacent; and in the fifth scenario, the second Super Block and the third Super Block are adjacent.

[0119] As described above, the write rate for write operations on the third Super Block is normal, the write rate for write operations on the second Super Block is second, and the write rate for write operations on the first Super Block is the worst. The write rate for write operations on the first Super Block is set to the first write rate, the write rate for write operations on the second Super Block is set to the second write rate, and the write rate for write operations on the third Super Block is set to the third write rate; wherein the first write rate is less than the second write rate, and the second write rate is less than the third write rate. If two First Super Blocks are positioned adjacent to each other, then when a write operation is performed on the first First Super Block, the write rate drops to the first write rate. When a write operation is continued on the second First Super Block, the write rate remains at the first write rate. In this case, the write rate of the memory system will suddenly drop to the first write rate for an extended period of time, causing significant performance fluctuations in the memory system. More specifically, when two First Super Blocks are positioned adjacent to each other, the write operation has the most severe impact on the performance of the memory system.

[0120] It should be emphasized that, in the embodiments of the present disclosure, a preset value can be set to classify Super Blocks into different types based on the number of bad blocks within the Super Block. The purpose of setting the preset value to classify Super Blocks into different types is to determine the write rate of a write operation on the Super Block based on the number of bad blocks within the Super Block. Here, the preset value is not a fixed value. Different preset values ​​can be set for different actual situations. The preset value is only used to distinguish the different write rates of different Super Blocks. For example, the write rate when performing a write operation on the first Super Block is lower than the write rate when performing a write operation on the second Super Block.

[0121] For example, the number of super blocks in the sorting process can be as high as several hundred, so the sorting chain list of super blocks is very long. Different preset values ​​can be determined for the number of bad blocks in each super block in the sorting process. For example, if the number of bad blocks in the super blocks from the 1st to the 10th super blocks in the sorting process ranges from 0 to 5, then the preset value can be set to 3. In this case, the number of bad blocks in the first super block is greater than 3, 0 is less than the number of bad blocks in the second super block, and ≤3, and the number of bad blocks in the third super block is equal to 0. For another example, if the number of bad blocks in the super blocks from the 50th to the 60th super blocks in the sorting process ranges from 0 to 20, then the preset value can be set to 10. In this case, the number of bad blocks in the first super block is greater than 10, 0 is less than the number of bad blocks in the second super block, and ≤10, and the number of bad blocks in the third super block is equal to 0. In the embodiments of the present disclosure, the specific preset values ​​are only used for illustration and do not constitute a limitation on the preset values ​​of the present disclosure.

[0122] In some embodiments, a first preset value and a second preset value can be set based on the number of bad blocks within a Super Block to divide the Super Block into the following four different types; wherein the first preset value is less than the second preset value. The multiple Super Blocks may include a first Super Block, a second Super Block, a third Super Block, and a fourth Super Block; wherein the number of bad blocks within the first Super Block is greater than the second preset value; the number of bad blocks within the second Super Block is greater than the first preset value and less than or equal to the second preset value; the number of bad blocks within the third Super Block is greater than 0 and less than or equal to the first preset value; and the number of bad blocks within the fourth Super Block is equal to 0. Of course, more preset values ​​can be set to divide Super Blocks into more types, thereby making the operation of the memory system more refined and increasing the complexity of Super Block management.

[0123] Another example is to set the first preset value to 5 and the second preset value to 10. At this time, the number of bad blocks in the first super block is greater than 10, 5<the number of bad blocks in the second super block≤10, 0<the number of bad blocks in the third super block≤5, and the number of bad blocks in the fourth super block = 0.

[0124] For ease of explanation, in the embodiments of the present disclosure, the case where a super block is divided into a first super block, a second super block, and a third super block is described.

[0125] In the disclosed embodiment, the number of bad blocks within a super block is used as the second factor to consider when sorting super blocks. As previously mentioned, when two first super blocks are set adjacent to each other, the performance of the memory system is most seriously affected when a write operation is performed. The first super blocks are set at intervals in the sorting of super blocks. In this way, a sudden drop in the write rate of the memory system will not last for a long time, which can reduce the performance fluctuation of the memory system. The first super block interval setting in the sorting refers to avoiding the situation where two first super blocks are set adjacent to each other in the sorting, that is, the first super block and the second super block are set adjacent to each other or the first super block and the third super block are set adjacent to each other in the sorting. The following text will further explain in detail how to determine the sorting of multiple super blocks based on the number of bad blocks within the super block.

[0126] In the embodiment of the present disclosure, in S602, the correspondence between the ranking of multiple super blocks and the priority of writing operations on multiple super blocks includes two cases. Among them, the priority of writing operations on multiple super blocks refers to the order in which write operations are performed on multiple super blocks. In the first case, the higher the ranking of the super block in the ranking, the higher the priority of writing operations on the super block. In other words, when writing operations on super blocks, super blocks with higher rankings are used first, and according to the ranking of multiple super blocks, these super blocks are used in sequence from front to back for writing operations. In the second case, the higher the ranking of the super block in the ranking, the lower the priority of writing operations on the super block. In other words, when writing operations on super blocks, super blocks with lower rankings are used first, and according to the ranking of multiple super blocks, these super blocks are used in sequence from back to front for writing operations.

[0127] In the disclosed embodiment, the erasure times of the super block and the number of bad blocks in the storage are simultaneously considered to determine the priority of the write operation on the super block, which can effectively smooth the write performance and enhance the performance stability of the memory system.

[0128] In the embodiment of the present disclosure, this can be achieved by improving the FW algorithm in the controller within the memory system without increasing additional costs.

[0129] It should be noted that if the erase counts of multiple Super Blocks in the sorting process are the same or similar, and the number of bad blocks within each Super Block is high, then when writing to these Super Blocks in sequence, the write rate may suddenly drop and last for a long time, causing significant performance fluctuations in the memory system. In the disclosed embodiments, when sorting multiple Super Blocks, while the erase counts meet preset requirements, both the erase counts of the Super Blocks and the number of bad blocks within each Super Block are taken into consideration. This can effectively prevent significant and prolonged performance fluctuations in the memory system, smooth write performance, and enhance the performance stability of the memory system.

[0130] In some embodiments, determining the priority of writing to the plurality of super blocks based on the order of the plurality of super blocks includes:

[0131] The higher the ranking of the Super Block in the sorting, the higher the priority of the write operation on the Super Block; wherein, the number of erasures of the Super Block with the higher ranking in any two adjacent Super Blocks in the sorting is less than or equal to the number of erasures of the Super Block with the lower ranking; or, the number of erasures of the Super Block with the higher ranking in any two adjacent Super Blocks in the sorting is greater than the number of erasures of the Super Block with the lower ranking and the difference between the number of erasures of the two Super Blocks is less than a preset difference; or,

[0132] The higher the ranking of the super block in the sorting, the lower the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is greater than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is less than the number of erasures of the super block with the lower ranking and the difference between the number of erasures of the two super blocks is less than a preset difference.

[0133] In the disclosed embodiment, in the first scenario, the higher the Super Block's ranking in the order, the higher the priority for write operations on that Super Block. The Super Blocks in the order can be arranged in ascending order by their erase counts. That is, the erase count of the Super Block with the higher ranking in the order is less than or equal to the erase count of the Super Block with the lower ranking; or, the erase count of the Super Block with the higher ranking in the order is greater than the erase count of the Super Block with the lower ranking, and the difference between the erase counts of the two Super Blocks is less than a preset difference. In this way, when writing to Super Blocks, Super Blocks with the lower erase count are prioritized from the front to the back, ensuring that the wear levels of the Super Blocks are substantially uniform. Even when considering the number of bad blocks within a Super Block, when writing to Super Blocks, Super Blocks with the higher erase count are used first, followed by Super Blocks with the lower erase count, and the difference between the erase counts of the two Super Blocks is less than a preset difference. This ensures that the wear levels of the Super Blocks are substantially uniform while maintaining smooth write performance of the memory system.

[0134] In the second scenario of the disclosed embodiment, the higher the Super Block's ranking in the order, the lower the priority for write operations on that Super Block. The Super Blocks in the order can be arranged in descending order by their erase counts: that is, the erase count of the Super Block with the higher ranking in the order is greater than or equal to the erase count of the Super Block with the lower ranking; or, the erase count of the Super Block with the higher ranking in the order is less than the erase count of the Super Block with the lower ranking, and the difference between the erase counts of the two Super Blocks is less than a preset difference. In this way, when writing to Super Blocks, Super Blocks with the lower erase count are prioritized from back to front, ensuring that the wear levels of the Super Blocks are substantially uniform. Even when considering the number of bad blocks within a Super Block, when writing to Super Blocks, Super Blocks with the higher erase count are used first, followed by Super Blocks with the lower erase count, and the difference between the erase counts of the two Super Blocks is less than a preset difference. This ensures that the wear levels of the Super Blocks are substantially uniform while maintaining smooth write performance of the memory system.

[0135] In the embodiment of the present disclosure, a preset difference value can be set based on the performance test data of the memory system. For example, the preset difference value can be 5. When performing a write operation, a super block with a large erase count (for example, an erase count of 10) can be used first, and then a super block with a small erase count (for example, an erase count of 6) can be used. The difference between the erase counts of adjacent super blocks is less than the preset difference value. If a super block with a large erase count (for example, an erase count of 18) is used first during a write operation, and then a super block with a small erase count (for example, an erase count of 6) is used, the difference between the erase counts of adjacent super blocks is greater than the preset difference value, which may also cause performance fluctuations of the memory system.

[0136] In the disclosed embodiment, the order of the multiple Super Blocks can be determined based on the priority of the Super Block write operation, that is, based on the order in which the Super Blocks are written. Furthermore, the number of erase times of each Super Block and the number of bad blocks within each Super Block can be obtained. Combined with the order of the multiple Super Blocks, a rule for ordering the multiple Super Blocks can be derived.

[0137] An embodiment of the present disclosure provides a memory system including at least one non-volatile memory device and a controller coupled to the non-volatile memory device, wherein the controller includes a first interface coupled to a host and a second interface coupled to the non-volatile memory device, and the controller can be configured to perform the following operations:

[0138] Sending a write command to the non-volatile storage device via a second interface, wherein the amount of data included in the write command is greater than the storage capacity of the two super blocks; the write command includes physical addresses mapped to multiple target super blocks, and the multiple target super blocks appear in the write command in order of priority; wherein an order of the multiple super blocks is determined based on the number of erase times of each super block and the number of bad blocks in each super block; wherein the number of erase times of any two adjacent super blocks in the order meets a preset requirement; wherein an interval is set between first super blocks in the order, and the number of bad blocks in the first super block is greater than a preset value; and determining a priority for performing a write operation on the multiple super blocks based on the order of the multiple super blocks;

[0139] The non-volatile storage device writes the data into the corresponding super block in sequence according to the order of the physical addresses in response to the write command sent by the second interface.

[0140] In the above embodiment, the write command may be a write command received from the host, a write command in a garbage collection process, a write command in a dynamic wear leveling process, or a write command in a static wear leveling process.

[0141] Exemplarily, the timing for sorting multiple super blocks in the operating method provided in the embodiment of the present disclosure may be, for example: after garbage collection, after marking a super block as a closed block, or after marking a storage block in a super block as a bad block (or, a physical bad block).

[0142] Here, the timing for sorting multiple super blocks in the operating method provided by the embodiment of the present disclosure may be after garbage collection, and the operating method provided by the embodiment of the present disclosure may be used to sort the free blocks obtained during the garbage collection process. The timing for sorting multiple super blocks in the operating method provided by the embodiment of the present disclosure may be after a super block is marked as a closed block, because after a super block is marked as a closed block, the closed block no longer participates in the sorting process. The timing for sorting multiple super blocks in the operating method provided by the embodiment of the present disclosure may be after a super block is marked as a closed block or after a storage block in a super block is marked as a bad block (or a physical bad block), because when the number of bad blocks in a super block changes, that is, the factors affecting the sorting of super blocks change, it is necessary to use the operating method provided by the embodiment of the present disclosure to adjust the order or position of the super block.

[0143] In some embodiments, the above-mentioned write operation includes at least one of the following: a write operation corresponding to a write operation command received by the controller from the host, a write operation during garbage collection, a write operation during dynamic wear leveling, and a write operation during static wear leveling.

[0144] In the embodiment of the present disclosure, the number of times a super block is erased and the number of bad blocks in the super block are taken into consideration to determine the order of multiple super blocks; based on the order of the multiple super blocks, the priority of the write operation on the super block is determined. Among them, before the write operation is performed on the super block, the order of the multiple super blocks is determined. In the embodiment of the present disclosure, the application scenario of the write operation on the super block is not particularly limited, and the application scenario of the write operation on the super block includes but is not limited to the above-mentioned write operation command received from the host, the write operation during the garbage collection process, and the write operation during the wear leveling (including dynamic wear leveling and static wear leveling). The above three application scenarios will be explained in detail below.

[0145] In a specific example, the above-mentioned write operation includes: host write (Host Write).

[0146] Here, the operating method provided by the embodiment of the present disclosure is applied to receive a write operation command from a host to perform a write operation. Considering that the memory system includes multiple super blocks, the embodiment of the present disclosure provides an operating method for selecting a target super block from multiple super blocks. In the embodiment of the present disclosure, the number of erasures of each super block and the number of bad blocks in each super block are taken into consideration to determine the sorting of multiple super blocks; the number of erasures of any two adjacent super blocks in the sorting meets the preset requirements; the first super block interval in the sorting is set, and the number of bad blocks in the first super block is greater than the preset value; based on the sorting of multiple super blocks, the priority of performing write operations on multiple super blocks is determined; the super block with the highest priority for performing write operations can be determined as the target super block. In this way, the write rate can be smoothed without causing large performance fluctuations in the memory system.

[0147] In a specific example, the above-mentioned writing operation includes: writing the target data into the target super block during the garbage collection process.

[0148] Here, the operating method provided by the embodiment of the present disclosure is applied to perform write operations during the garbage collection process. Specifically, the garbage collection process is divided into the following three steps: the first step is to select a source super block (i.e., a garbage block); wherein, valid data and invalid data are stored on the source super block, and usually the super block with the least valid data is selected as the source super block; the second step is to find valid data from the source super block; the third step is to write the valid data to the target super block. In this way, all the data in the source super block can be erased to obtain a new available super block (i.e., a free block). The above-mentioned valid data moved from the source super block to the target super block is the target data. Considering that the memory system includes multiple super blocks, the embodiment of the present disclosure provides an operating method for selecting a target super block from multiple super blocks. In the disclosed embodiment, the order of multiple Super Blocks is determined by simultaneously considering the number of erases per Super Block and the number of bad blocks within each Super Block. The erase counts of any two adjacent Super Blocks in the order meet a preset requirement. The first Super Block in the order is set to an interval, and the number of bad blocks within the first Super Block is greater than a preset value. Based on the order of the multiple Super Blocks, the priority of write operations on the multiple Super Blocks is determined. The Super Block with the highest priority for write operations can be determined as the target Super Block. This allows for smoothing the write rate without causing significant performance fluctuations in the memory system.

[0149] It should be noted that after erasing all data in the source super block and obtaining a new available super block, the new available super block (i.e., the free block) can be added to the sorting according to the operation method provided in the embodiment of the present disclosure, thereby determining the priority of the write operation on the super block.

[0150] In a specific example, the write operation includes: writing the first target data into the first target super block during the dynamic wear leveling process and writing the second target data into the second target super block during the static wear leveling process.

[0151] Here, the operating method provided by the embodiments of the present disclosure is applied to write operations during the wear leveling process. Specifically, wear leveling includes dynamic wear leveling and static wear leveling. Dynamic wear leveling involves writing hot data to a Super Block with a smaller erase count. Specifically, when selecting a Super Block for a write operation, Super Blocks with a smaller erase count are prioritized. In this case, the hot data is the first target data, and the Super Block with a smaller erase count is the first target Super Block.

[0152] Static wear leveling refers to writing cold data to a superblock with a larger number of erase times. In this case, the cold data is the second target data, and the superblock with a larger number of erase times is the second target superblock. Considering that the memory system includes multiple superblocks, the embodiment of the present disclosure provides an operating method for selecting a first target superblock and a second target superblock from multiple superblocks, while considering the number of erase times of each superblock and the number of bad blocks in each superblock to determine the order of multiple superblocks; the number of erase times of any two adjacent superblocks in the order meets the preset requirements; the first superblock interval in the order is set, and the number of bad blocks in the first superblock is greater than the preset value; based on the order of multiple superblocks, the priority of writing operations on multiple superblocks is determined; the superblock with the highest priority for writing operations can be determined as the first target superblock, and the superblock with the lowest priority for writing operations can be determined as the second target superblock. In this way, the write rate can be smoothed without causing large performance fluctuations in the memory system.

[0153] In some embodiments, before S601, the operation method further includes:

[0154] According to the number of erasures of each super block, a pre-order of the multiple super blocks is determined; wherein, in the pre-order, the multiple super blocks are arranged in order from small to large or from large to small according to the number of erasures.

[0155] In the disclosed embodiment, the pre-ordering of multiple super blocks can be determined based on the number of erasures of each super block. The correspondence between the number of erasures of a super block and the pre-ordering of the super blocks includes two cases. In the first case, the smaller the number of erasures of a super block in the pre-ordering, the higher the pre-ordering of the super block, that is, the multiple super blocks in the pre-ordering are arranged in ascending order according to the number of erasures. In the second case, the larger the number of erasures of a super block in the pre-ordering, the higher the pre-ordering of the super block, that is, the multiple super blocks in the pre-ordering are arranged in descending order according to the number of erasures.

[0156] It should be noted that after determining the pre-sort of multiple super blocks, it is necessary to consider the number of bad blocks in the super block at the same time and adjust the order and position of the super blocks. During the adjustment process, the number of erase times of any two adjacent super blocks meeting the preset requirements is used as a restriction condition to ensure that the number of erase times of the super block and the number of bad blocks in the storage are considered at the same time to determine the priority of the write operation on the super block. This can not only effectively smooth the write performance and enhance the performance stability of the memory system, but also make the wear degree of each super block basically the same, thereby ensuring that the memory system has the maximum data write volume.

[0157] As previously described, a Super Block is divided into a first Super Block, a second Super Block, and a third Super Block based on the number of bad blocks within the Super Block. The number of bad blocks within the first Super Block is greater than the preset value; the number of bad blocks within the second Super Block is greater than 0 and less than or equal to the preset value; and the number of bad blocks within the third Super Block is equal to 0. If two first Super Blocks are located adjacent to each other, a write operation to these two Super Blocks will cause a sudden and prolonged drop in write rate, which will cause significant performance fluctuations in the memory system.

[0158] In some embodiments, after determining the pre-order of the plurality of super blocks according to the number of erasures of each super block, the operation method further includes:

[0159] Determining at least two adjacent first super blocks according to the pre-sorting of the plurality of super blocks;

[0160] According to the number of bad blocks in the first super block, the order or position of the first super block is adjusted to determine a first sub-sequence of multiple super blocks; wherein the number of erasures of any two adjacent super blocks in the first sub-sequence meets a preset requirement; and the first super blocks in the first sub-sequence are not set adjacent to each other.

[0161] In an embodiment of the present disclosure, at least two adjacent first super blocks are determined based on a pre-sort of multiple super blocks. Because the number of bad blocks in a first super block is greater than a preset value, when a write operation is performed on at least two adjacent first super blocks, the write rate will suddenly decrease and last for a long time, which will cause large performance fluctuations in the memory system. Therefore, when adjusting the pre-sort of the super blocks, the order or position of the adjacent first super blocks is adjusted first to obtain a first sub-sort; so that the first super blocks in the first sub-sort are not adjacent to each other, or the first super blocks in the first sub-sort are spaced apart, that is, other super blocks (that is, the second super block or the third super block) are provided between the two first super blocks.

[0162] It should be noted that in the process of adjusting the order or position of the adjacent first super blocks, the erasure times of any two adjacent super blocks meeting the preset requirements is used as a restriction condition, so that the erasure times of any two adjacent super blocks in the first sub-sort meet the preset requirements.

[0163] It should be emphasized that at least two adjacently arranged First Super Blocks are determined based on the pre-ordering of the multiple Super Blocks. Here, the number of adjacently arranged First Super Blocks in the pre-ordering of the multiple Super Blocks is greater than or equal to two. For example, three First Super Blocks are arranged consecutively in the pre-ordering. Furthermore, the pre-ordering of the multiple Super Blocks may contain multiple locations each with at least two adjacently arranged First Super Blocks. As previously mentioned, the linked list of Super Blocks is very long, and there may be more than one location with at least two adjacently arranged First Super Blocks.

[0164] In some embodiments, the first super block and the second super block in the first sub-sequence are adjacently arranged; or, the first super block and the third super block in the first sub-sequence are adjacently arranged.

[0165] In an embodiment of the present disclosure, after adjusting the order or position of at least two adjacent first super blocks, a first sub-sequence is obtained; in the first sub-sequence, the first super block and the second super block are adjacently arranged; or, in the first sub-sequence, the first super block and the third super block are adjacently arranged.

[0166] It should be noted that if two First Super Blocks are positioned adjacent to each other, then when a write operation is performed on the two First Super Blocks, the write rate of the memory system will suddenly drop to the first write rate and persist for a relatively long time (i.e., the write rate will be equal to the duration of the first write rate while the write operation is performed on the two First Super Blocks), causing significant performance fluctuations in the memory system. If a second Super Block or a third Super Block is positioned between the two First Super Blocks, then when write operations are performed sequentially on the first Super Block, the second Super Block (or the third Super Block), and the first Super Block, the write rate of the memory system will first drop to the first write rate, then increase to the second write rate (or the third write rate), and finally drop to the first write rate. i.e., the write rate will be equal to the duration of the first write rate while the write operation is performed on one First Super Block. Compared to the case where two First Super Blocks are positioned adjacent to each other, this can effectively prevent the memory system's write rate from continuing to drop for a relatively long time, thereby reducing performance fluctuations in the memory system.

[0167] In the disclosed embodiment, after adjusting the order or position of the first Super Blocks, a first sub-sort is obtained. In the first sub-sort, the first Super Block and the second Super Block are still adjacent to each other. Because the number of bad blocks in the first Super Block is greater than a preset value, and the number of bad blocks in the second Super Block is greater than 0 and less than or equal to the preset value, when write operations are performed sequentially on the adjacent first Super Block and the second Super Block, the write rate will suddenly decrease and last for a certain period of time, which will cause certain performance fluctuations in the memory system. Therefore, it is necessary to adjust the order or position of the adjacent first Super Block and the second Super Block to further optimize the operation method of the memory system.

[0168] In some embodiments, after adjusting the order or position of the first super block based on the number of bad blocks in the first super block to determine a first sub-order of the plurality of super blocks, the method further includes:

[0169] Determining, according to the first sub-ranking of the plurality of super blocks, a first super block and a second super block that are adjacently arranged;

[0170] According to the number of bad blocks in the first super block and the second super block, the order or position of the first super block and the second super block is adjusted to determine a second sub-sequence of the multiple super blocks; wherein the number of erase times of any two adjacent super blocks in the second sub-sequence meets a preset requirement; and the first super block and the second super block in the second sub-sequence are not adjacently arranged.

[0171] In the embodiments of the present disclosure, it is precisely because of the consideration that when writing operations are performed sequentially on the adjacent first and second Super Blocks, the write rate may suddenly decrease and last for a certain period of time, which will cause certain performance fluctuations in the memory system. Therefore, the order or position of the adjacent first and second Super Blocks is adjusted to obtain a second sub-ordering; such that the first and second Super Blocks in the second sub-ordering are not adjacent to each other, or such that the first and second Super Blocks in the second sub-ordering are spaced apart, that is, another Super Block (i.e., the second Super Block or the third Super Block) is provided between the first and second Super Blocks.

[0172] It should be noted that in the process of adjusting the order or position of the adjacent first super block and the second super block, the erasure times of any two adjacent super blocks meeting the preset requirements is used as a restriction condition, so that the erasure times of any two adjacent super blocks in the second sub-sort meet the preset requirements.

[0173] In some embodiments, the two second super blocks in the second sub-sort are adjacently arranged; or, the first super block and the third super block in the second sub-sort are adjacently arranged; or, the second super block and the third super block in the second sub-sort are adjacently arranged.

[0174] In an embodiment of the present disclosure, after adjusting the order or position of the adjacent first super block and the second super block, a second sub-sorting is obtained; in the second sub-sorting, the first super block and the second super block are adjacently arranged; or, in the second sub-sorting, the first super block and the third super block are adjacently arranged.

[0175] It should be noted that if the first Super Block and the second Super Block are adjacent to each other, then when write operations are performed on the first Super Block and the second Super Block in sequence, the write rate of the memory system will tend to first decrease to the first write rate and then increase to the second write rate. The write rate may also suddenly decrease and last for a certain period of time, which will cause certain performance fluctuations in the memory system. If a second Super Block or a third Super Block is provided between the first Super Block and the second Super Block, then when write operations are performed on the first Super Block, the second Super Block (or the third Super Block), and the second Super Block in sequence, the write rate of the memory system will tend to first decrease to the first write rate and then increase to the second write rate (or, first decrease to the first write rate, then increase to the third write rate, and finally decrease to the second write rate). Compared with the case where the first Super Block and the second Super Block are adjacent to each other, this can effectively prevent the memory system's write rate from decreasing for a certain period of time, thereby reducing performance fluctuations in the memory system.

[0176] In the disclosed embodiment, after adjusting the order or position of the first Super Block and the second Super Block, a second sub-sequence is obtained. However, adjacent second Super Blocks may still exist in the second sub-sequence. Because the number of bad blocks within the second Super Block is greater than 0 and less than or equal to a preset value, when sequentially writing to the adjacent second Super Blocks, the write rate may decrease for a period of time, causing certain performance fluctuations in the memory system. Therefore, it is necessary to adjust the order or position of the adjacent second Super Blocks to further optimize the operating method of the memory system.

[0177] In some embodiments, after adjusting the order or position of the first Super Block and the second Super Block based on the number of bad blocks in the first Super Block and the second Super Block to determine a second sub-ordering of the plurality of Super Blocks, the method further includes:

[0178] Determining at least two adjacent second super blocks according to the second sub-ranking of the plurality of super blocks;

[0179] According to the number of bad blocks in the second super block, the order or position of the second super block is adjusted to determine the sorting of the plurality of super blocks; wherein the second super blocks are not arranged adjacent to each other in the sorting.

[0180] In the disclosed embodiments, the write rate may decrease and persist for a period of time when sequentially writing to adjacent second Super Blocks, causing certain performance fluctuations in the memory system. Therefore, the order or position of adjacent second Super Blocks is adjusted to obtain a sorting sequence, such that the second Super Blocks are not adjacent to each other in the sorting sequence, or the second Super Blocks are spaced apart in the sorting sequence, i.e., another Super Block (i.e., a third Super Block) is provided between the second Super Block and the second Super Block.

[0181] It should be noted that in the process of adjusting the order or position of the adjacent second super blocks, the erasure times of any two adjacent super blocks meeting the preset requirements is used as a restriction condition, so that the erasure times of any two adjacent super blocks in the sorting meet the preset requirements.

[0182] In some embodiments, the second super block and the third super block are arranged adjacent to each other in the order.

[0183] In the embodiment of the present disclosure, the order or position of the adjacently arranged second super blocks is adjusted to obtain a sorting; in the sorting, the second super block and the third super block are arranged adjacently.

[0184] It should be noted that if two second Super Blocks are positioned adjacent to each other, the memory system's write rate will decrease and persist for a certain period of time when write operations are performed on the two second Super Blocks (i.e., the write rate lasts for the duration of the second write rate while the two second Super Blocks are being written). This will cause certain performance fluctuations in the memory system. If a third Super Block is positioned between the two second Super Blocks, then when write operations are sequentially performed on the second Super Block, the third Super Block, and the second Super Block, the memory system's write rate will first decrease to the second write rate, then increase to the third write rate, and finally decrease to the second write rate. That is, the write rate lasts for the duration of the second write rate while the one second Super Block is being written. Compared to the case where two second Super Blocks are positioned adjacent to each other, this can effectively prevent the memory system's write rate from decreasing for a certain period of time, thereby reducing performance fluctuations in the memory system.

[0185] Referring to Figure 9, Figure 9 shows the ordering of super blocks provided by a specific example. Figure 9 illustrates the ordering of super blocks Super BLK1 to Super BLK10, as well as the erase count EC and the number of bad storage planes BP of each super block (i.e., the number of bad blocks within each super block). The ordering of super blocks Super BLK1 to Super BLK10 illustrated in Figure 9 is sorted in ascending order based on their erase counts. The ordering of super blocks Super BLK1 to Super BLK10 does not take into account the number of bad blocks within each super block. It is possible that two adjacent super blocks both have a large number of bad blocks. For example, super blocks Super BLK6 and Super BLK7 are adjacent to each other, the number of bad blocks within super block Super BLK6 is 6, and the number of bad blocks within super block Super BLK7 is 8.

[0186] Referring to FIG10 , FIG10 is another specific example of the ordering of super blocks provided. FIG10 also illustrates the ordering of super blocks Super BLK1 to Super BLK10, as well as the erase count EC and the number of bad storage planes BP (i.e., the number of bad blocks in each super block) of each super block. However, there is a clear difference between the ordering of super blocks illustrated in FIG10 and the ordering of super blocks illustrated in FIG9 . Based on the ordering of super blocks illustrated in FIG9 , the order (or position) of super blocks Super BLK5 and super blocks Super BLK6 are interchanged, and the order (or position) of super blocks Super BLK7 and super blocks Super BLK8 are interchanged. Thus, FIG10 illustrates that the super block with sequence number (5) in the ordering is super block Super BLK6, the super block with sequence number (6) is super block Super BLK5, the super block with sequence number (7) in the ordering is super block Super BLK8, and the super block with sequence number (8) is super block Super BLK7.

[0187] Here, first, considering that the difference in the erase counts between any two adjacent Super Blocks from Super BLK4 to Super BLK9 is less than 5, that is, the erase counts of any two adjacent Super Blocks meet the preset requirements, the order or position of Super Blocks Super BLK5 and Super BLK6, and Super Blocks Super BLK7 and Super BLK8 can be adjusted. Second, considering that there are a large number of bad blocks in Super Blocks Super BLK6 and Super BLK7, the order or position of Super Blocks Super BLK6 and Super BLK7 can be adjusted so that Super Blocks Super BLK6 and Super BLK7 are not adjacent to each other.

[0188] Referring to Figure 11, Figure 11 shows the write rate of each Super Block in the sorting. The horizontal axis of Figure 11 represents the sequence number of each Super Block in the sorting, and the vertical axis represents the write rate. Figure 11 (a) illustrates the write rate of each Super Block in the sorting of Figure 9, and Figure 11 (b) illustrates the write rate of each Super Block in the sorting of Figure 10.

[0189] As shown in Figure 11 (a), when write operations are performed on the sorted super blocks in sequence, since the number of bad blocks in super blocks Super BLK6 and Super BLK7 is relatively large, the write rate suddenly drops when the write operation is performed on super block Super BLK6, and continues until the write operation on super block Super BLK7 is completed. The write rate drops for a long time, causing large performance fluctuations in the memory system.

[0190] As shown in Figure 11 (b), after adjusting the order of super blocks, the super block with sequence number (5) in the order is super block Super BLK6, and the super block with sequence number (8) is super block Super BLK7. When writing operations are performed on the super blocks in the order, since the number of bad blocks in the super block with sequence number (5) and the super block with sequence number (8) are both large, the write rate will decrease when writing to the super block with sequence number (5). Then, when writing to the super blocks with sequence numbers (6) and (7), the write rate will increase. When writing to the super block with sequence number (8), the write rate will decrease. In this way, the time for the write rate to decrease will not last long, which can reduce the performance fluctuation of the memory system and effectively smooth the write performance of the memory system.

[0191] In some embodiments, the order of the multiple super blocks is provided in the form of a super block list (Block List). Here, by querying the super block list, the target super block to be written to can be obtained.

[0192] In other embodiments, the ordering of the plurality of superblocks is provided in the form of a red-black tree. Here, considering that the length of the linked list is getting longer and longer, adjusting the linked list to a red-black tree can improve query efficiency and save query time.

[0193] In some embodiments, a Data Super Block (Data Block) refers to a Super Block containing both valid data and invalid data, with the valid and invalid data portions located at different locations within the Super Block. Here, "valid data" and "invalid data" are related to wear leveling and are not the "valid data" and "invalid data" discussed above in the garbage collection process. More specifically, the valid data portion typically includes cold data, meaning it is accessed less frequently, while the invalid data portion typically includes hot data, meaning it is accessed more frequently.

[0194] As mentioned above, static wear leveling refers to writing cold data to a superblock with a higher erase count. In this case, the cold data is the second target data, and the superblock with a higher erase count is the second target superblock. The valid transport unit count (Valid Transport Unit Count) can be used to characterize the portion of valid data within a superblock. In the process of considering static wear leveling, some superblocks are used to store system data. These system data are cold data, and the superblocks storing these system data are superblocks with a lower erase count. These system data can be moved out and written to superblocks with a higher erase count, thereby releasing the superblocks originally used to store system data, allowing these superblocks with a lower erase count to be fully utilized.

[0195] Still referring to FIG. 7 and FIG. 8 , an embodiment of the present disclosure provides a memory system 102, which includes at least one non-volatile memory device 104 and a controller 106 coupled to the non-volatile memory device 104. Each non-volatile memory device 104 includes a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device 104 forms a super block. The controller 106 is configured to:

[0196] Determining an order of the plurality of super blocks based on the number of erasures of each super block and the number of bad blocks in each super block; wherein the number of erasures of any two adjacent super blocks in the order meets a preset requirement; and an interval is set for the first super block in the order, and the number of bad blocks in the first super block is greater than a preset value;

[0197] According to the order of the multiple super blocks, the priority of writing operations to the multiple super blocks is determined.

[0198] In some embodiments, the controller 106 is specifically configured to:

[0199] The higher the ranking of the Super Block in the sorting, the higher the priority of the write operation on the Super Block; wherein, the number of erasures of the Super Block with the higher ranking in any two adjacent Super Blocks in the sorting is less than or equal to the number of erasures of the Super Block with the lower ranking; or, the number of erasures of the Super Block with the higher ranking in any two adjacent Super Blocks in the sorting is greater than the number of erasures of the Super Block with the lower ranking and the difference between the number of erasures of the two Super Blocks is less than a preset difference; or,

[0200] The higher the ranking of the super block in the sorting, the lower the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is greater than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking in any two adjacent super blocks in the sorting is less than the number of erasures of the super block with the lower ranking and the difference between the number of erasures of the two super blocks is less than a preset difference.

[0201] In some embodiments, the controller 106 is specifically configured to:

[0202] According to the number of erasures of each super block, a pre-order of the multiple super blocks is determined; wherein, in the pre-order, the multiple super blocks are arranged in order from small to large or from large to small according to the number of erasures.

[0203] In some embodiments, the controller 106 is specifically configured to:

[0204] Determining at least two adjacent first super blocks according to the pre-sorting of the plurality of super blocks;

[0205] According to the number of bad blocks in the first super block, the order or position of the first super block is adjusted to determine a first sub-sequence of multiple super blocks; wherein the number of erasures of any two adjacent super blocks in the first sub-sequence meets a preset requirement; and the first super blocks in the first sub-sequence are not set adjacent to each other.

[0206] In some embodiments, the plurality of super blocks further include a second super block and a third super block; wherein the number of bad blocks in the second super block is greater than 0 and less than or equal to a preset value; and the number of bad blocks in the third super block is equal to 0;

[0207] In the first sub-sequence, the first super block and the second super block are adjacently arranged; or, in the first sub-sequence, the first super block and the third super block are adjacently arranged.

[0208] In some embodiments, the controller 106 is specifically configured to:

[0209] Determining, according to the first sub-ranking of the plurality of super blocks, a first super block and a second super block that are adjacently arranged;

[0210] According to the number of bad blocks in the first super block and the second super block, the order or position of the first super block and the second super block is adjusted to determine a second sub-sequence of the multiple super blocks; wherein the number of erase times of any two adjacent super blocks in the second sub-sequence meets a preset requirement; and the first super block and the second super block in the second sub-sequence are not adjacently arranged.

[0211] In some embodiments, the two second super blocks in the second sub-sort are adjacently arranged; or, the first super block and the third super block in the second sub-sort are adjacently arranged; or, the second super block and the third super block in the second sub-sort are adjacently arranged.

[0212] In some embodiments, the controller 106 is specifically configured to:

[0213] Determining at least two adjacent second super blocks according to the second sub-ranking of the plurality of super blocks;

[0214] According to the number of bad blocks in the second super block, the order or position of the second super block is adjusted to determine the sorting of the plurality of super blocks; wherein the second super blocks are not arranged adjacent to each other in the sorting.

[0215] In some embodiments, the second super block and the third super block are arranged adjacent to each other in the order.

[0216] In some embodiments, a superblock includes free blocks.

[0217] An embodiment of the present disclosure provides a computer-readable storage medium storing a computer program that, when executed, implements a method for operating a memory system as described in the above technical solution. The method includes determining an ordering of multiple Super Blocks based on the number of erase times of each Super Block and the number of bad blocks within each Super Block; wherein the number of erase times of any two adjacent Super Blocks in the ordering satisfies a preset requirement; wherein an interval is set between the first Super Blocks in the ordering, and the number of bad blocks within the first Super Block is greater than a preset value; and determining a priority for performing write operations on the multiple Super Blocks based on the ordering of the multiple Super Blocks.

[0218] In the embodiments of the present disclosure, the computer-readable storage medium may include: random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, read-only compact disks (CD-ROMs), or any other form of program code medium known in the technical field.

[0219] In the embodiment of the present disclosure, the operating method of the memory system in the above technical solution can be implemented by running firmware.

[0220] The present disclosure also provides an electronic device including the memory system of the above technical solution. The electronic device may include a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device, or a mobile power bank.

[0221] Embodiments of the present disclosure provide a memory system, an operating method thereof, and a computer-readable storage medium. In the embodiments of the present disclosure, the priority of writing to a superblock is determined by simultaneously considering the number of superblock erases and the number of bad blocks within the superblock, thereby effectively smoothing write performance and enhancing the performance stability of the memory system.

[0222] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0223] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory system, in, The memory system includes at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each of the non-volatile memory devices includes a plurality of memory blocks, and at least one memory block in at least one of the non-volatile memory devices forms a super block; and the controller is configured to: Determine the order of the plurality of super blocks according to the number of erasures of each super block and the number of bad blocks in each super block; wherein the number of erasures of any two adjacent super blocks in the order meets a preset requirement; and the first super block interval in the order is set, and the number of bad blocks in the first super block is greater than a preset value; According to the order of the multiple super blocks, the priority of writing operations to the multiple super blocks is determined.

2. The memory system according to claim 1, wherein the controller is specifically configured as follows: The higher the ranking of the super block in the ranking, the higher the priority of writing operation to the super block; in, The erasure count of the super block with the higher order in any two adjacent super blocks in the order is less than or equal to the erasure count of the super block with the lower order; or, the erasure count of the super block with the higher order in any two adjacent super blocks in the order is greater than the erasure count of the super block with the lower order and the difference in the erasure counts of the two super blocks is less than a preset difference; or, The higher the ranking of the super block in the sorting, the lower the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking among any two adjacent super blocks in the sorting is greater than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking among any two adjacent super blocks in the sorting is less than the number of erasures of the super block with the lower ranking and the difference in the number of erasures of the two super blocks is less than a preset difference.

3. The memory system according to claim 1, wherein the controller is specifically configured as follows: Determining the pre-order of the plurality of super blocks according to the number of erasures of each super block; That middle, In the pre-sorting, the plurality of super blocks are arranged in order from small to large or from large to small according to the number of erasures.

4. The memory system according to claim 3, wherein the controller is specifically configured as follows: Determining at least two adjacently arranged first super blocks according to the pre-sorting of the plurality of super blocks; According to the number of bad blocks in the first super block, the order or position of the first super block is adjusted to determine a first sub-order of the plurality of super blocks; in, The erasure times of any two adjacent super blocks in the first sub-sequence meet a preset requirement; and the first super blocks in the first sub-sequence are not arranged adjacent to each other.

5. The memory system according to claim 4, wherein the plurality of super blocks further comprises a second super block and a third super block; in, The number of bad blocks in the second super block is greater than 0 and less than or equal to a preset value; the number of bad blocks in the third super block is equal to 0; The first super block and the second super block in the first sub-sequence are arranged adjacent to each other; or the first super block and the third super block in the first sub-sequence are arranged adjacent to each other.

6. The memory system according to claim 5, wherein the controller is specifically configured as follows: Determining the first super block and the second super block that are adjacently arranged according to the first sub-ranking of the plurality of super blocks; According to the number of bad blocks in the first super block and the second super block, the order or position of the first super block and the second super block is adjusted to determine a second sub-sequence of the plurality of super blocks; in, The number of erasures of any two adjacent super blocks in the second sub-sequence meets a preset requirement; and the first super block and the second super block in the second sub-sequence are not arranged adjacent to each other.

7. The memory system according to claim 6, wherein the two second super blocks in the second sub-sort are arranged adjacent to each other; or, the first super block and the third super block in the second sub-sort are arranged adjacent to each other; or, the second super block and the third super block in the second sub-sort are arranged adjacent to each other.

8. The memory system according to claim 7, wherein the controller is specifically configured to: Determining at least two adjacently arranged second super blocks according to the second sub-rankings of the plurality of super blocks; According to the number of bad blocks in the second super block, adjusting the order or position of the second super block to determine the order of the plurality of super blocks; in, The second super blocks in the sorting are not arranged adjacently. 9 . The memory system according to claim 8 , wherein the second super block and the third super block are arranged adjacent to each other in the arrangement.

10. The memory system of claim 1, the super block comprising a free block.

11. A method of operating a memory system, in, The memory system includes at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each of the non-volatile memory devices includes a plurality of memory blocks, and at least one memory block in at least one of the non-volatile memory devices forms a super block; and the operation method includes: Determine the order of the plurality of super blocks according to the number of erasures of each super block and the number of bad blocks in each super block; wherein the number of erasures of any two adjacent super blocks in the order meets a preset requirement; and the first super block interval in the order is set, and the number of bad blocks in the first super block is greater than a preset value; According to the order of the multiple super blocks, the priority of writing operations to the multiple super blocks is determined.

12. The method for operating a memory system according to claim 11, wherein the priority of writing to the plurality of super blocks is determined according to the order of the plurality of super blocks, include: The higher the ranking of the super block in the ranking, the higher the priority of writing to the super block; wherein the number of erasures of the super block ranked higher in any two adjacent super blocks in the ranking is less than or equal to the number of erasures of the super block ranked lower; or, the number of erasures of the super block ranked higher in any two adjacent super blocks in the ranking is greater than the number of erasures of the super block ranked lower and the difference in the number of erasures of the two super blocks is less than a preset difference; or, The higher the ranking of the super block in the sorting, the lower the priority of the write operation on the super block; wherein, the number of erasures of the super block with the higher ranking among any two adjacent super blocks in the sorting is greater than or equal to the number of erasures of the super block with the lower ranking; or, the number of erasures of the super block with the higher ranking among any two adjacent super blocks in the sorting is less than the number of erasures of the super block with the lower ranking and the difference in the number of erasures of the two super blocks is less than a preset difference.

13. The operating method of the memory system according to claim 11, before determining the order of the plurality of super blocks according to the number of erasures of each super block and the number of bad blocks in each super block, the operating method further comprises: include: According to the number of erasures of each super block, a pre-order of the plurality of super blocks is determined; wherein in the pre-order, the plurality of super blocks are arranged in sequence from small to large or from large to small according to the number of erasures.

14. The operating method of the memory system according to claim 13, after determining the pre-order of the plurality of super blocks according to the number of erasures of each super block, the operating method further comprises: include: Determining at least two adjacently arranged first super blocks according to the pre-sorting of the plurality of super blocks; According to the number of bad blocks in the first super block, the order or position of the first super block is adjusted to determine a first sub-sequence of multiple super blocks; wherein the number of erase times of any two adjacent super blocks in the first sub-sequence meets a preset requirement; and the first super blocks in the first sub-sequence are not arranged adjacent to each other.

15. The method for operating a memory system according to claim 14, wherein the plurality of super blocks further comprises a second super block and a third super block; in, The number of bad blocks in the second super block is greater than 0 and less than or equal to a preset value; the number of bad blocks in the third super block is equal to 0; The first super block and the second super block in the first sub-sequence are arranged adjacent to each other; or the first super block and the third super block in the first sub-sequence are arranged adjacent to each other.

16. The method for operating a memory system according to claim 15, wherein after adjusting the order or position of the first super block according to the number of bad blocks in the first super block to determine a first sub-sequence of the plurality of super blocks, the method further comprises: include: Determining the first super block and the second super block that are adjacently arranged according to the first sub-ranking of the plurality of super blocks; According to the number of bad blocks in the first super block and the second super block, the order or position of the first super block and the second super block is adjusted to determine a second sub-sequence of the multiple super blocks; wherein the number of erase times of any two adjacent super blocks in the second sub-sequence meets a preset requirement; and the first super block and the second super block in the second sub-sequence are not adjacently arranged.

17. The operating method of the memory system according to claim 16, wherein the two second super blocks in the second sub-sort are arranged adjacent to each other; or, the first super block and the third super block in the second sub-sort are arranged adjacent to each other; or, the second super block and the third super block in the second sub-sort are arranged adjacent to each other.

18. The method for operating a memory system according to claim 17, wherein after adjusting the order or position of the first super block and the second super block according to the number of bad blocks in the first super block and the second super block to determine a second sub-sequence of the plurality of super blocks, the method further comprises: include: Determining at least two adjacently arranged second super blocks according to the second sub-rankings of the plurality of super blocks; According to the number of bad blocks in the second super block, the order or position of the second super block is adjusted to determine the order of the plurality of super blocks; wherein the second super blocks in the order are not arranged adjacent to each other.

19. The method for operating a memory system according to claim 18, wherein the second super block and the third super block are arranged adjacent to each other in the arrangement.

20. The operating method of the memory system according to claim 11, wherein the super block comprises a spare block.

21. A computer-readable storage medium storing a computer program, wherein the computer program can implement the operating method of the memory system according to any one of claims 11 to 20 when executed.

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