Semiconductor device assembly with encapsulation material with enhanced thermal

Abstract

A semiconductor device assembly is provided. The assembly includes a support layer having an inner surface, a semiconductor device, and an encapsulation material. The encapsulation material includes a host material and thermally conductive nanoparticles, each nanoparticle having an electrically insulating shell and an electrically conductive core. The semiconductor device is disposed on the inner surface of the support layer, the thermally conductive nanoparticles are uniformly distributed throughout the host material, and the encapsulating material at least partially encapsulates the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor device assemblies, and more particularly, to semiconductor device assemblies having encapsulation materials with enhanced thermal conductivity and methods of making the same. Background Art

[0002] Microelectronic devices generally have a die (i.e., chip) that includes an integrated circuit with very small components of high density. Typically, the die includes an array of very small bonding pads that are electrically coupled to the integrated circuit. The bonding pads are external electrical contacts through which supply voltages, signals, etc. are transmitted to and from the integrated circuit. After the die is formed, it is "packaged" to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power supply lines, signal lines, and ground lines. Conventional processes for packaging the die include electrically coupling the bonding pads on the die to an array of wires, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors (e.g., moisture, particles, static electricity, and physical shock). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a simplified schematic cross-sectional view of an exemplary semiconductor device assembly in accordance with an embodiment of the present technology.

[0004] Figure 2 is a detailed cross-sectional view of an encapsulation material according to an embodiment of the present technology.

[0005] Figure 3 is a simplified schematic cross-sectional view of a semiconductor device assembly in accordance with an embodiment of the present technology.

[0006] Figure 4 is a simplified schematic cross-sectional view of a semiconductor device assembly in accordance with an embodiment of the present technology.

[0007] Figure 5 is a simplified schematic cross-sectional view of a semiconductor device assembly in accordance with an embodiment of the present technology.

[0008] Figure 6 is a simplified schematic cross-sectional view of a semiconductor device assembly in accordance with an embodiment of the present technology.

[0009] Figure 7 is a schematic diagram illustrating a process of manufacturing thermally conductive nanoparticles according to an embodiment of the present technology.

[0010] Figure 8 is a schematic diagram showing a system including a semiconductor device assembly configured according to an embodiment of the present technology.

[0011] Fig. 9is a flow chart illustrating a method of manufacturing a semiconductor device assembly according to an embodiment of the present technology. DETAILED DESCRIPTION

[0012] The electronics industry relies on continuous innovation in the field of semiconductor packaging to meet the global demand for higher-function technology. Future 5G, 6G, AI and autonomous chips require higher density semiconductor devices in a single package, as well as higher integrated memory bandwidth. These packages generate extremely high heat, which reduces the life and efficiency of the devices contained therein.

[0013] One way to handle this high heat is to have an encapsulation material with high thermal conductivity for better thermal management. However, high thermal conductivity materials have disadvantages. Most high thermal conductivity materials are also highly electrically conductive. This conductivity is abominable for encapsulation materials because it will allow dielectric breakdown to occur between devices in the package at relatively low voltages. These breakdowns will result in random behavior from the device, as well as damage to the device and the package itself, when signals are lost or received at the wrong location.

[0014] To address these shortcomings and others, various embodiments of the present disclosure provide semiconductor device assemblies having encapsulation materials with enhanced thermal conductivity.

[0015] Figure 1 1 is a simplified schematic cross-sectional view of a semiconductor device assembly 100 with an encapsulation material having enhanced thermal conductivity according to an embodiment of the present technology. The assembly 100 includes a support layer 101 having an inner surface at which a semiconductor device 102 is disposed. At least partially encapsulating the semiconductor device 102 is an encapsulation material 103 having enhanced thermal conductivity.

[0016] Figure 2 2 is a detailed cross-sectional view of an encapsulation material 203 having enhanced thermal conductivity according to an embodiment of the present technology. The encapsulation material 203 at least partially encapsulates a semiconductor device 202 disposed on an inner surface of a support layer 201 as part of an assembly 200. The semiconductor device may be a NAND flash memory chip, a DRAM chip, a graphics processing unit, a light emitting diode, a transistor, etc., and the support layer may be a substrate, a section of a reconstructed wafer, etc. The encapsulation material 203 includes thermally conductive nanoparticles disposed in a body material 204 (e.g., an encapsulation molding compound or the like). Each nanoparticle includes an electrically insulating shell 206 surrounding a conductive core 205. The electrically insulating shell 206 may be silicon dioxide. The conductive core may be one of the following: copper, silver, gold, or alloys thereof, or carbon nanotubes or graphene fragments.

[0017] As part of the encapsulating material, the host material itself may include a resin and a hardener. This resin may be derived from a variety of sources, which may include polyester resins, phenolic resins, alkyd resins, polycarbonate resins, polyamide resins, polyurethane resins, polysilicone resins, epoxy resins, etc. The hardener (or it may also be called a curing agent) may include one of a variety of aliphatic amine curing agents, one of a variety of cycloaliphatic amine curing agents, one of a variety of polyvalent phenols (such as phenol novolak, aralkylphenol novolak, and the like), anhydrides (such as pyromerit anhydride, trimerit anhydride, benzophenonetetracarboxylic acid anhydride, and the like), etc.

[0018] Within the nanoparticle itself, the core and shell may have different sizes. The conductive core 205 may have a size of 100 nanometers to 250 nanometers. The core may also have a size of 250 nanometers to 500 nanometers; a size of 500 nanometers to 750 nanometers; or a size of 750 nanometers to 1 micrometer. Each electrically insulating shell 206 may have a thickness of 100 nanometers to 500 nanometers. Additionally, these shells 206 may have a thickness of 500 nanometers to 1 micrometer; a thickness of 1 micrometer to 5 micrometers, or a thickness of 5 micrometers to 10 micrometers. The total size of the thermally conductive nanoparticle including the shell may be 200 nanometers to 750 nanometers, or it may be 750 nanometers to 3 micrometers, or it may be 3 micrometers to 11 micrometers.

[0019] The disclosed encapsulation materials may form part of the packaging for various high performance assemblies. Such assemblies are labeled "high performance" due to their increased demands in terms of power and speed, which generate greater heat. Due to the properties of its thermally conductive nanoparticles, the ability of the disclosed encapsulation materials to conduct heat from the assembly (without compromising electrical insulation) enables new embodiments of these "high performance" assemblies.

[0020] Figures 3 to 6 is a simplified schematic cross-sectional view of such a “high performance” semiconductor device assembly.

[0021] Figure 3 A high bandwidth memory assembly 300 is illustrated, which may be an example of a "high performance" semiconductor device assembly that may include the disclosed encapsulation material 303 surrounding a stack of semiconductor devices 302 (which in this potential embodiment may be a stack of DRAM memory dies connected by through silicon vias to a high bandwidth memory controller die as a support layer 301).

[0022] exist Figure 4, a graphical assembly 400 is illustrated depicting another potential "high performance" embodiment of the disclosed assembly. This assembly 400 may include the disclosed encapsulation material 403, and a semiconductor device 402, which in this potential embodiment includes a heat sink, a video BIOS, a video memory chip, and a graphics processing unit. In this embodiment, the support layer 401 is a non-metallic substrate that may be made of fiberglass filaments and epoxy resin.

[0023] Figure 5 Another potential "high performance" embodiment is illustrated in FIG. This assembly 500 is a solid state drive. The solid state drive may include a ball grid array, flash memory, DRAM, 3D XPoint, or a mix of rotating disk and flash memory as its semiconductor device 502, which is encapsulated by the disclosed encapsulation material 503 and rests on an electrically insulating substrate 501.

[0024] As a final example of a "high performance" assembly that may include the disclosed encapsulating materials, Figure 6 A fan-out chip level assembly 600 is illustrated where the supporting layer is a redistribution layer 601 , the semiconductor device is fully embedded within a disclosed encapsulation material 603 , and a series of solder balls, through silicon vias, and substrate traces are connected to the device 602 .

[0025] The foregoing figures demonstrate a variety of potential form factors and package types that the disclosed encapsulation materials may be included in. The disclosed encapsulation materials may at least partially encapsulate semiconductor devices formed as a stack connected with through silicon vias, or stacked as tiles and connected with wire bonds, or embedded within various other layers of an assembly.

[0026] The aforementioned assembly may have an allowable junction temperature of 10 degrees C. For an encapsulation material having a greater thermal conductivity in Wattsper meter-Kelvin (W / mK), the assembly may have a thinner semiconductor die measured in nanometers (um) and higher power directed thereto measured in Watts without exceeding the allowable junction temperature.

[0027] An actual estimate of the thermal conductivity provided by the disclosed encapsulation material is greater than 4 Watts / meter-Kevin. This estimated thermal conductivity will enable the aforementioned assembly to have a semiconductor die having a thickness of 150 microns or less and power directed thereto measured up to and exceeding 10 Watts without the assembly exceeding the allowable junction temperature. By allowing the assembly to conduct more heat, the disclosed encapsulation material may allow such assemblies to operate at increased speeds and include thinner die, which in turn will allow more die to be included in such high performance assemblies.

[0028] Figure 7710 is a schematic diagram illustrating a process of manufacturing heat-conducting nanoparticles according to an embodiment of the present technology, wherein each nanoparticle has an electrically insulating shell and a conductive core. In a first step 710, method 700 can be started by adding ethyl silicate (e.g., TEOS) to an alcohol mixture and then adding hydrochloric acid as a catalyst. This produces a solution, which includes a solvent, a reaction medium and electrically insulating particles (e.g., silicon dioxide). Then, in a second step 712, heat-conducting nanoparticles are added to the solution. These nanoparticles can be derived from metals (e.g., copper, silver, gold or their alloys, etc.), carbon nanotubes or graphene fragments. In a third step 714, the nanoparticles are added to the solution while stirring the solution. After mixing, the solvent gradually dissolves from the reaction medium to produce heat-conducting nanoparticles, wherein each nanoparticle has an electrically insulating shell. Then, in a fourth step 716, these nanoparticles are cleaned (e.g., with alcohol) to remove organic residues. Finally, in a fifth step 718, nanoparticles are collected.

[0029] Next, as a method of creating an encapsulation material according to an embodiment of the present technology, these nanoparticles may be mixed into a host material (e.g., an encapsulation molding compound or the like) such that the nanoparticles are distributed throughout the host material. The host material may further include a resin (e.g., a polyester resin, a phenolic resin, an alkyd resin, a polycarbonate resin, a polyamide resin, a polyurethane resin, a polysilicone resin, an epoxy resin, etc.) and a hardener (e.g., an aliphatic amine curing agent, a cycloaliphatic amine curing agent, a polyvalent phenol (e.g., phenol novolac, aralkylphenol novolac, and the like) or an anhydride (e.g., a pyroanhydride, a tribasic anhydride, a benzophenone tetracarboxylic anhydride, and the like) etc.).

[0030] Although in the foregoing example embodiments, the semiconductor device assembly has been illustrated and described as comprising a single semiconductor device, in other embodiments, the assembly may be provided with additional semiconductor devices. For example, a vertical stack of semiconductor devices, a plurality of semiconductor devices, etc. may be substituted, mutatis mutandis, for example. Figure 1 , 2 , 4, 5 and / or 6 as described herein.

[0031] According to one aspect of the present disclosure, Figures 1 to 6The semiconductor device illustrated in the assembly of may be a memory die, such as a dynamic random access memory (DRAM) die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, a static random access memory (SRAM) die, or the like. In embodiments where multiple dies are provided in a single assembly, the semiconductor device may be the same kind of memory die (e.g., two NANDs, two DRAMs, etc.) or different kinds of memory dies (e.g., one DRAM and one NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly illustrated and described above may be a logic die (e.g., a controller die, a processor die, etc.), or a mix of logic and memory dies (e.g., a memory controller die and a memory die controlled by it).

[0032] References Figures 1 to 6 Any of the described semiconductor devices and semiconductor device assemblies may be incorporated into numerous larger and / or more complex systems (representative examples of which are Figure 8 The system 800 may include a semiconductor device assembly (e.g., or discrete semiconductor devices) 802, a power supply 804, a driver 806, a processor 808, and / or other subsystems or components 810. The semiconductor device assembly 802 may include the same as described above with respect to Figure 1 and Figures 3 to 6 The system 800 may be configured to perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 800 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 800 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of the system 800 may also include remote devices and any of a wide variety of computer-readable media.

[0033] Fig. 9is a flow chart illustrating a method of manufacturing a semiconductor device assembly having an encapsulation material with enhanced thermal conductivity. The method includes providing a body material including a resin (block 910). The method further includes providing thermally conductive nanoparticles, wherein each nanoparticle has an electrically insulating shell and an electrically conductive core (block 920). The method further includes mixing the thermally conductive nanoparticles into the body material such that the nanoparticles are distributed throughout the body material (block 930). The method further includes mixing a hardener into the resin (block 940). The method further includes providing a support layer having an inner surface (block 950). The method further includes disposing a semiconductor device on the inner surface (block 960). The method further includes at least partially encapsulating the semiconductor device in the encapsulation material (block 970). The method further includes curing the encapsulation material to harden it (block 980).

[0034] The above describes specific details of several embodiments of semiconductor devices and associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein may be performed at the wafer level or at the die level. Thus, depending on the context in which the term "substrate" is used, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. In addition, unless the context indicates otherwise, conventional semiconductor manufacturing techniques may be used to form the structures disclosed herein. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0035] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0036] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0037] As used herein, "or", as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of"), including in the claims, indicates an inclusive list, so that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0038] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, over / below, up / down, and left / right may be interchanged depending on the orientation.

[0039] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods may be combined.

[0040] From the foregoing, it will be appreciated that specific embodiments of the present disclosure have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present disclosure. Indeed, in the foregoing description, many specific details are discussed to provide a comprehensive and detailed description of embodiments of the present technology. However, those skilled in the art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid making other aspects of the technology unclear. In general, it should be appreciated that in addition to the specific embodiments disclosed herein, various other devices, systems, and methods may also be within the scope of the present technology.

Claims

1. A semiconductor device assembly comprising: a support layer having an inner surface; a semiconductor device disposed on the inner surface; and An encapsulation material at least partially encapsulating the semiconductor device, the encapsulation material comprising: Main material, and Thermally conductive nanoparticles are distributed throughout the host material, each nanoparticle having an electrically insulating shell and a conductive core.

2. The semiconductor device assembly of claim 1, wherein the electrically insulating housing comprises silicon dioxide. 3 . The semiconductor device of claim 1 , wherein the conductive core comprises one of: copper, silver, gold or alloys thereof, or carbon nanotubes or graphene fragments. The semiconductor device assembly of claim 1 , wherein the body material comprises a resin and a hardener.

5. The semiconductor device assembly of claim 1, wherein each conductive core has a size in a range from 100 nanometers to 1 micrometer.

6. The semiconductor device assembly of claim 1, wherein each electrically insulating housing has a thickness in a range from 100 nanometers to 10 micrometers.

7. The semiconductor device assembly of claim 1, wherein the encapsulation material further comprises a thermal conductivity greater than 4 Watts / meter-Kevin.

8. The semiconductor device assembly of claim 1 wherein power measured in excess of 10 Watts may be directed or applied to the assembly without the assembly exceeding an allowable junction temperature of 10 degrees Celsius.

9. The semiconductor device assembly of claim 1, wherein the semiconductor die has a thickness of 150 microns or less, and the assembly does not exceed an allowable junction temperature of 10 degrees Celsius.

10. An encapsulating material comprising: Subject material; and Thermally conductive nanoparticles are distributed throughout the host material, each nanoparticle having an electrically insulating shell and a conductive core. The encapsulation material of claim 10 , wherein the electrically insulating shell comprises silicon dioxide.

12. The encapsulation material of claim 10, wherein the conductive core comprises one of: copper, silver, gold or alloys thereof, or carbon nanotubes or graphene fragments. The encapsulation material according to claim 10 , wherein the main material comprises a resin and a hardener.

14. The encapsulation material of claim 10, wherein each conductive core has a size ranging from 100 nanometers to 1 micrometer.

15. The encapsulation material of claim 10, wherein each electrically insulating shell has a thickness in a range from 100 nanometers to 10 micrometers.

16. The encapsulation material of claim 10, wherein the encapsulation material further comprises a thermal conductivity greater than 4 Watts / meter-Kevin.

17. A method for producing an encapsulating material, the method comprising: Provide subject materials; Providing thermally conductive nanoparticles, each nanoparticle having an electrically insulating shell and an electrically conductive core; The thermally conductive nanoparticles are mixed into the host material such that the nanoparticles are distributed throughout the host material. The method of claim 17 , wherein the body material comprises a resin and a hardener.

19. The method according to claim 17, wherein the method further comprises: providing a support layer having an inner surface; placing a semiconductor device on the inner surface; and The semiconductor device is at least partially encapsulated in the encapsulation material.

20. The method of claim 18, wherein the method further comprises: The subject material is cured to harden it.

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