Package including substrate having bridges configured for backside power distribution network

Abstract

A package, the package including: a substrate; the bridging piece is positioned in the substrate; a first integrated device coupled to the substrate; and a second integrated device coupled to the substrate. The bridge includes: a bridge substrate; at least one first bridge dielectric layer coupled to the first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect being located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to the second surface of the bridge substrate; at least one second bridge interconnect in the at least one second bridge dielectric layer; and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application serial number 17 / 835,861 filed in the U.S. Patent Office on June 8, 2022, the entire contents of which are incorporated herein by reference as if fully set forth as a whole below and for all applicable purposes. Technical Field

[0003] Various features are directed to a package having a substrate and an integrated device. Background Art

[0004] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. There is a constant need to provide a package with better performance and to reduce the overall size of the package. Summary of the invention

[0005] Various features are directed to a package having a substrate and an integrated device.

[0006] An example provides a package, the package comprising: a substrate; a bridge, the bridge being located in the substrate; a first integrated device, the first integrated device being coupled to the substrate; and a second integrated device, the second integrated device being coupled to the substrate. The bridge comprises: a bridge substrate; at least one first bridge dielectric layer, the at least one first bridge dielectric layer being coupled to a first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect being located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer, the at least one second bridge dielectric layer being coupled to a second surface of the bridge substrate; at least one second bridge interconnect, the at least one second bridge interconnect being located in the at least one second bridge dielectric layer; and at least one bridge interconnect, the at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0007] Another example provides a device including a package. The package includes a substrate; a bridge located in the substrate; a first integrated device coupled to the substrate; and a second integrated device coupled to the substrate. The bridge includes: a bridge substrate; at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect located in the at least one second bridge dielectric layer; and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate. The method places a bridge in the substrate. The bridge includes: a bridge substrate; at least one first bridge dielectric layer, the at least one first bridge dielectric layer is coupled to a first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect is located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer, the at least one second bridge dielectric layer is coupled to a second surface of the bridge substrate; at least one second bridge interconnect, the at least one second bridge interconnect is located in the at least one second bridge dielectric layer; and at least one bridge interconnect, the at least one bridge interconnect extends through the at least one first bridge dielectric layer and the bridge substrate. The method couples a first integrated device to the substrate. The method couples a second integrated device to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference characters designate corresponding features throughout.

[0010] Figure 1 An exemplary cross-sectional profile view of a package including a substrate having a bridge is illustrated.

[0011] Figure 2 An exemplary cross-sectional profile view of a package including a substrate having a bridge is illustrated.

[0012] Figure 3 An exemplary cross-sectional profile view of a package including a substrate having a bridge is illustrated.

[0013] Figure 4 An exemplary cross-sectional profile view of a package including a substrate having a bridge is illustrated.

[0014] Figure 5 Exemplary cross-sectional profile views of bridges are illustrated.

[0015] Figure 6 Exemplary cross-sectional profile views of bridges are illustrated.

[0016] Figure 7 Exemplary cross-sectional profile views of bridges are illustrated.

[0017] FIG. 8A to FIG. 8F An exemplary process for making a bridge is illustrated.

[0018] 9A to 9D Another exemplary process for making a bridge is illustrated.

[0019] Fig.10 An exemplary flow chart of a method for manufacturing a bridge is illustrated.

[0020] FIG. 11A to FIG. 11D An exemplary process for manufacturing a package including a substrate having a bridge is illustrated.

[0021] Fig.12 An exemplary flow chart of a method for manufacturing a package including a substrate having a bridge is illustrated.

[0022] FIG. 13A to FIG. 13B An exemplary process for manufacturing a substrate including interconnects is illustrated.

[0023] Fig.14 An exemplary flow chart of a method for manufacturing a substrate including an interconnect is illustrated.

[0024] Fig.15 Various electronic devices are illustrated that may integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0025] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, those of ordinary skill in the art will appreciate that these aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid complicating these aspects with unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of the present disclosure.

[0026] The present disclosure describes a package, which includes a substrate; a bridge, the bridge is located in the substrate; a first integrated device, the first integrated device is coupled to the substrate; and a second integrated device, the second integrated device is coupled to the substrate. The bridge includes: a bridge substrate; at least one first bridge dielectric layer, the at least one first bridge dielectric layer is coupled to the first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect is located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer, the at least one second bridge dielectric layer is coupled to the second surface of the bridge substrate; at least one second bridge interconnect, the at least one second bridge interconnect is located in the at least one second bridge dielectric layer; and at least one bridge interconnect, the at least one bridge interconnect extends through the at least one first bridge dielectric layer and the bridge substrate. A passive device may be located in the substrate. The bridge may be configured to provide at least one electrical path between the first integrated device and the second integrated device. The passive device is coupled to the bridge. The passive device may be considered as part of the bridge. The encapsulation layer may be coupled to the bridge. The encapsulation layer is located in the substrate. The passive device may be coupled to the power distribution network of the bridge. As will be further described below, the package provides passive devices located closer to the first integrated device and / or the second integrated device, which helps to improve package performance while keeping the package small and thin.

[0027] Exemplary package including a substrate having a bridge

[0028] Figure 1 A cross-sectional cutaway view of a package 100 including a substrate having a bridge is illustrated. The bridge is configured to provide an electrical path for signals between integrated devices. The bridge is configured to provide an electrical path for a power distribution network (PDN). The package 100 is coupled to a board 106 via a plurality of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0029] Package 100 includes substrate 102, integrated device 103, integrated device 105, and bridge 107. Integrated device 103 may be a first integrated device. Integrated device 105 may be a second integrated device. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 is coupled to board 106 via a plurality of solder interconnects 110. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 and a plurality of board interconnects 162.

[0030] The integrated device 103 is coupled to a first surface (e.g., top surface) of the substrate 102 through a plurality of solder interconnects 130. The plurality of solder interconnects 130 are coupled to the integrated device 103 and the plurality of interconnects 122 of the substrate 102. The integrated device 105 is coupled to a first surface (e.g., top surface) of the substrate 102 through a plurality of solder interconnects 150. The plurality of solder interconnects 150 are coupled to the integrated device 105 and the plurality of interconnects 122 of the substrate 102.

[0031] The bridge 107 is located in the substrate 102. The substrate 102 may include a cavity 109. Fig.11A Examples of cavities in substrates are further shown and described in . Bridge 107 may be located in cavity 109 of substrate 102. Bridge 107 is configured to provide multiple electrical paths for signals between integrated device 103 and integrated device 105. Bridge 107 is configured to provide at least one electrical path for a power distribution network (PDN). Bridge 107 is configured to provide at least one electrical path for power. Bridge 107 is configured to provide at least one electrical path for ground. Bridge 107 may include a front side and a back side. As will be further described below, bridge 107 is configured to provide at least one electrical path for power and / or ground through the back side of bridge 107.

[0032] As follows, at least Figure 2 As further described in , at least one passive device may be coupled to the bridge 107. For example, at least one passive device may be coupled to the back side of the bridge 107. The passive device coupled to the bridge 107 may be configured to be coupled to power and / or ground. The passive device coupled to the bridge 107 may be considered as part of the bridge 107.

[0033] The bridge 107 includes a bridge substrate 170, at least one bridge dielectric layer 172 (e.g., at least one first bridge dielectric layer), at least one bridge dielectric layer 174 (e.g., at least one second bridge dielectric layer), a plurality of bridge interconnects 171, a plurality of bridge interconnects 173 (e.g., at least one first bridge interconnect), and a plurality of bridge interconnects 175 (e.g., at least one second bridge interconnect). The bridge substrate 170 may include a silicon substrate (e.g., a silicon bridge substrate). However, the bridge substrate 170 may include different materials. At least one bridge dielectric layer 172 is coupled to a first side (e.g., front side, top side) of the bridge substrate 170. A plurality of bridge interconnects 173 are located in and on (e.g., inside and above) at least one bridge dielectric layer 172. The plurality of bridge interconnects 173 may be a plurality of front-side bridge interconnects. The at least one bridge dielectric layer 172 and the plurality of bridge interconnects 173 may be considered as part of the front side of the bridge 107. At least one bridging dielectric layer 174 is coupled to a second side (e.g., back side, bottom side) of the bridging substrate 170. A plurality of bridging interconnects 175 are located in and on (e.g., inside and above) the at least one bridging dielectric layer 174. The at least one bridging dielectric layer 174 and the plurality of bridging interconnects 175 may be considered as part of the back side of the bridge 107. The plurality of bridging interconnects 175 may be a plurality of back side bridging interconnects. The plurality of bridging interconnects 171 may extend through the front side, the bridging substrate 170, and / or the back side of the bridge 107. For example, the plurality of bridging interconnects 171 may extend (e.g., partially or completely) through the at least one bridging dielectric layer 172, the bridging substrate 170, and / or the at least one bridging dielectric layer 174. The plurality of bridging interconnects 171 may be coupled to the plurality of bridging interconnects 173 and the plurality of bridging interconnects 175. The plurality of bridging interconnects 171 may include a plurality of bridging vias (e.g., bridging via interconnects).

[0034] The bridge 107 is configured to provide multiple electrical paths for input / output signals, power, and / or ground. Figure 1 Three exemplary electrical paths are illustrated that the bridge 107 may be configured to provide. Note that the bridge 107 may be configured to provide more than three electrical paths. Thus, the bridge 107 may be configured to provide other electrical paths.

[0035] Figure 1Electrical path 101, electrical path 104, and electrical path 108 are illustrated. Electrical path 101 is an example of an electrical path between integrated device 103 and integrated device 105. Electrical path 101 is configured to provide an electrical path for input / output (I / O) signals between integrated device 103 and integrated device 105. Electrical path 101 may include: (i) at least one solder interconnect from the plurality of solder interconnects 130, (ii) at least one interconnect from the plurality of interconnects 122, (iii) at least one bridge interconnect (e.g., 171, 173) from bridge 107, (iv) at least one other interconnect from the plurality of interconnects 122, and (v) at least one solder interconnect from the plurality of solder interconnects 150. Electrical path 101 extends through the front side of bridge 107. Note that there may be multiple electrical paths similar to electrical path 101 between integrated device 103 and integrated device 105. In one example, electrical paths extending through the bridge between integrated device 103 and integrated device 105 can each be configured as an electrical path for an I / O signal.

[0036] The electrical path 104 is an example of an electrical path that extends through at least the board 106, the substrate 102, and the bridge 107. Note that the electrical path 104 may also extend to the integrated device 103 and / or the integrated device 105. In one example, the electrical path 104 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 103. In another example, the electrical path 104 is configured to provide an electrical path for ground. The electrical path 104 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, (iii) at least one interconnect from the plurality of interconnects 122, and (iv) at least one bridge interconnect (e.g., 171, 173, 175) from the bridge 107. The electrical path 104 may also include solder interconnects from the plurality of solder interconnects 130. The electrical path 104 may also include solder interconnects from a plurality of solder interconnects 150. The electrical path 104 may extend through the front and / or back of the bridge 107. In some implementations, there may be multiple electrical paths extending through the board 106, the substrate 102, and the bridge 107. The electrical path 104 may pass through the front of the bridge 107 and / or the back of the bridge 107. The electrical path 104 may extend in any direction (e.g., from left to right, from right to left, upward and / or downward). One or more currents passing through the electrical path 104 may be transmitted in any direction (e.g., from left to right, from right to left, upward and / or downward). One of the electrical paths may be configured to provide an electrical path for ground, and another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0037] The electrical path 108 is an example of an electrical path that extends through at least the board 106, the substrate 102, and the bridge 107. Note that the electrical path 108 may also extend to the integrated device 103 and / or the integrated device 105. In one example, the electrical path 108 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 103 and / or the integrated device 105. In another example, the electrical path 108 is configured to provide an electrical path for ground. The electrical path 108 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, (iii) at least one interconnect from the plurality of interconnects 122, and (iv) at least one bridge interconnect (e.g., 171, 173, 175) from the bridge 107. The electrical path 108 may also include solder interconnects from the plurality of solder interconnects 130 and / or solder interconnects from the plurality of solder interconnects 150. The electrical path 108 may extend through the front and / or back of the bridge 107. In some implementations, there may be multiple electrical paths extending through the board 106, the substrate 102, and the bridge 107. The electrical path 108 may pass through the front of the bridge 107 and / or the back of the bridge 107. The electrical path 108 may extend in any direction (e.g., from left to right, from right to left, upward and / or downward). One or more currents passing through the electrical path 108 may be transmitted in any direction (e.g., from left to right, from right to left, upward and / or downward). One of the electrical paths may be configured to provide an electrical path for ground, and another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0038] The above design and / or configuration has several advantages. First, the interconnects in / on the back side of bridge 107 help provide more interconnects to improve power delivery to integrated device 103 and / or integrated device 105. Second, providing a bridge including interconnects configured as an electrical path for ground helps improve the signal integrity of signals transmitted through bridge 107, which helps improve the performance of integrated device 103 and / or integrated device 105.

[0039] In some implementations, the interconnects on the back side of the bridge 107 may have a different thickness than the interconnects on the front side of the bridge 107. For example, the thickness (e.g., a first thickness) of the plurality of bridge interconnects 173 (which are located in / on the front side of the bridge 107) may be in a first range of about 1 to 2 microns, and the thickness (e.g., a second thickness) of the plurality of bridge interconnects 175 (which are located in / on the back side of the bridge 107) may be greater than 2 microns (e.g., in a second range of about 3 to 6 microns). Increasing the thickness of the plurality of bridge interconnects 175 (e.g., back side metal layers) helps improve power transfer and helps reduce IR drop across the bridge 107. The above thicknesses may refer to the thickness of the metal layers (e.g., M1, M2, M3, M4, M5, M6, M7) and / or metal planes of any of the bridges described in the present disclosure. As described above, in some implementations, the substrate 102 may include passive devices. Figure 2 A package 200 including a substrate having a bridge and at least one passive device is illustrated. The passive device may be coupled to a power distribution network. The passive device may be configured to help provide effective decoupling for circuits in the package, integrated device, substrate, and / or bridge. Package 200 is similar to package 100 and may therefore include components similar to package 100.

[0040] Package 200 includes substrate 102, integrated device 103, integrated device 105, and bridge 207. Bridge 207 may be similar to bridge 107. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 is coupled to board 106 through a plurality of solder interconnects 110. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 and the plurality of board interconnects 162.

[0041] The integrated device 103 is coupled to a first surface (e.g., top surface) of the substrate 102 through a plurality of solder interconnects 130. The plurality of solder interconnects 130 are coupled to the integrated device 103 and the plurality of interconnects 122 of the substrate 102. The integrated device 105 is coupled to a first surface (e.g., top surface) of the substrate 102 through a plurality of solder interconnects 150. The plurality of solder interconnects 150 are coupled to the integrated device 105 and the plurality of interconnects 122 of the substrate 102.

[0042] The bridge 207 is located in the substrate 102. The substrate 102 may include a cavity 209. The bridge 207 may be located in the cavity 209 of the substrate 102. It should be noted that a portion of the cavity 209 may also be filled with a gas (e.g., air). The bridge 207 is configured to provide multiple electrical paths for signals between the integrated device 103 and the integrated device 105. The bridge 207 is configured to provide at least one electrical path for a power distribution network (PDN). The bridge 207 is configured to provide at least one electrical path for power. The bridge 207 is configured to provide at least one electrical path for ground. The bridge 207 may include a front side and a back side. As will be further described below, the bridge 207 is configured to provide at least one electrical path for power and / or ground through the back side of the bridge 207.

[0043] The package 200 also includes a passive device 203 and a passive device 205. The passive device 203 may be a first passive device. The passive device 205 may be a second passive device. The passive device may include a capacitor. The passive device 203 and / or the passive device 205 may include a passive die. The passive device 203 may be located in the substrate 102. The passive device 205 may be located in the substrate 102. The passive device 203 is coupled to the back side of the bridge 207 through a plurality of solder interconnects 230. For example, the passive device 203 may be coupled to the bridge interconnects (e.g., 175) of the bridge 207 through a plurality of solder interconnects 230. The passive device 205 is coupled to the back side of the bridge 207 through a plurality of solder interconnects 250. For example, the passive device 205 may be coupled to the bridge interconnects (e.g., 175) of the bridge 207 through a plurality of solder interconnects 250.

[0044] Figure 2 The electrical path 101 , the electrical path 204 , and the electrical path 208 are illustrated. Figure 2 The electrical path 101 may be similar to Figure 1 The electrical path 204 may be similar to Figure 1 The electrical path 208 may be similar to Figure 1 However, as will be described further below, electrical path 204 includes passive device 203 and electrical path 208 includes passive device 205.

[0045] The electrical path 204 is an example of an electrical path that extends through at least the board 106, the substrate 102, the bridge 207, and the passive device 203. It is noted that the electrical path 204 may also extend to the integrated device 103 and / or the integrated device 105. In one example, the electrical path 204 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 103 and / or the integrated device 105. In another example, the electrical path 204 is configured to provide an electrical path for ground. The electrical path 204 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, (iii) at least one interconnect from the plurality of interconnects 122, (iv) at least one bridge interconnect (e.g., 171, 173, 175) from the bridge 207, and (v) a terminal of the passive device 203 (e.g., solder interconnect 230, interconnect). The electrical path 204 may also include solder interconnects from the plurality of solder interconnects 130 and / or solder interconnects from the plurality of solder interconnects 150. The electrical path 204 may extend through the front and / or back sides of the bridge 207. In some implementations, there may be multiple electrical paths extending through the board 106, the substrate 102, the bridge 207, and the passive devices 203. One of the electrical paths may be configured to provide an electrical path for ground, and another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0046] The electrical path 208 is an example of an electrical path that extends through at least the board 106, the substrate 102, the bridge 207, and the passive device 205. Note that the electrical path 208 may also extend to the integrated device 103 and / or the integrated device 105. In one example, the electrical path 208 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 103 and / or the integrated device 105. In another example, the electrical path 208 is configured to provide an electrical path for ground. The electrical path 208 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, (iii) at least one interconnect from the plurality of interconnects 122, (iv) at least one bridge interconnect (e.g., 171, 173, 175) from the bridge 207, and (v) a terminal of the passive device 205 (e.g., solder interconnect 250, interconnect). The electrical path 208 may also include solder interconnects from the plurality of solder interconnects 130 and / or solder interconnects from the plurality of solder interconnects 150. The electrical path 208 may extend through the front and / or back sides of the bridge 207. In some implementations, there may be multiple electrical paths extending through the board 106, the substrate 102, and the bridge 207. One of the electrical paths may be configured to provide an electrical path for ground, and another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0047] The above design and / or configuration has several advantages. First, the interconnects in / on the back side of the bridge 207 help provide more interconnects to improve power delivery to the integrated device 103 and / or the integrated device 105. Second, providing a bridge including interconnects configured as an electrical path for ground helps improve the signal integrity of the signal transmitted through the bridge 207, which helps improve the performance of the integrated device 103 and / or the integrated device 105. Third, the passive device 203 and / or the passive device 205 provide improved decoupling capabilities compared to capacitors coupled to the bottom surface of the substrate 102. Fourth, the passive device 203 and / or the passive device 205 closer to the integrated device can help improve voltage drop.

[0048] In some implementations, in order to provide a mechanically robust and stable package, additional materials and / or components can be provided to the package. Figure 3A package 300 is illustrated that includes an encapsulation layer 310 in a substrate. Package 300 is similar to package 200 and thus may include similar components to package 200. Therefore, the description of package 200 and its components also applies to package 300. Package 300 includes an encapsulation layer 310 located in substrate 102. Encapsulation layer 310 may be located in cavity 209 of substrate 102. Cavity 209 may be filled with a gas (e.g., air).

[0049] Figure 3 An encapsulation layer 310 is illustrated that encapsulates the passive device 203 and the passive device 205. The encapsulation layer 310 may be coupled to the back side of the bridge 207 and / or be a part of the back side of the bridge 207. The encapsulation layer 310 may also encapsulate the bridge 207. The encapsulation layer 310 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 310 may be a member for encapsulation. The encapsulation layer 310 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. It is noted that other materials (such as an underfill) may be used instead of the encapsulation layer 310 or in combination with the encapsulation layer. In some specific implementations, the passive device 203, the passive device 205, and / or the encapsulation layer 310 may be considered as part of the bridge 207. The encapsulation layer 310 helps provide structural stability for the bridge 207, the substrate 102, and / or the package 300.

[0050] Note that the possible electrical paths for package 300 may be similar to those for Figure 1 Package 100, Figure 2 The electrical paths described for package 200 , or any electrical paths described in this disclosure.

[0051] Figure 4A package 400 including a bridge with direct back coupling is illustrated. Package 400 is similar to package 300 and may therefore include components similar to package 300. Therefore, the description of package 300 and its components also applies to package 400. Package 400 includes a bridge 207 and an encapsulation layer 310 located in substrate 102. Encapsulation layer 310 includes a plurality of interconnects 412 configured to allow at least one electrical path through the back of bridge 207. Encapsulation layer 310 may be located in cavity 209 of substrate 102. Cavity 209 may be filled with a gas (e.g., air). In some implementations, encapsulation layer 310 and / or plurality of interconnects 412 may be considered as part of bridge 207. In some implementations, encapsulation layer 310 and / or plurality of interconnects 412 may be considered as part of substrate 102. Multiple interconnects 412 may include multiple through-mold interconnects. The plurality of interconnects 412 may be coupled to the plurality of interconnects 122. The plurality of interconnects 412 may be configured to be coupled to the plurality of bridge interconnects 171, the plurality of bridge interconnects 173, and / or the plurality of bridge interconnects 175. The plurality of interconnects 412 may include through-mold vias (TMVs). In some implementations, power may be transmitted through an electrical path including the plurality of interconnects 412. That is, power may enter through the back side of the bridge 207. Using the plurality of interconnects 412 as an electrical path for power may help improve voltage drop.

[0052] Figure 4 The electrical path 101 , the electrical path 404 , the electrical path 408 , and the electrical paths 414 and 418 are illustrated. Figure 4 The electrical path 101 may be similar to Figure 1 The electrical path 101.

[0053] The electrical path 404 is an example of an electrical path that extends through at least the board 106 and the substrate 102. Note that the electrical path 404 may also extend to the integrated device 103. In one example, the electrical path 404 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 103. In another example, the electrical path 404 is configured to provide an electrical path for ground. The electrical path 404 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, and (iii) at least one interconnect from the plurality of interconnects 122. The electrical path 404 may also include solder interconnects from the plurality of solder interconnects 130. In some implementations, there may be multiple electrical paths extending through the board 106 and the substrate 102. One of the electrical paths may be configured to provide an electrical path for ground, another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network), and another of the electrical paths may be configured to provide an electrical path for input / output (I / O) signals.

[0054] The electrical path 408 is an example of an electrical path that extends through at least the board 106 and the substrate 102. Note that the electrical path 408 may also extend to the integrated device 103. In one example, the electrical path 408 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 105. In another example, the electrical path 408 is configured to provide an electrical path for ground. The electrical path 408 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, and (iii) at least one interconnect from the plurality of interconnects 122. The electrical path 408 may also include solder interconnects from the plurality of solder interconnects 150. In some implementations, there may be multiple electrical paths extending through the board 106 and the substrate 102. One of the electrical paths may be configured to provide an electrical path for ground, another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network), and another of the electrical paths may be configured to provide an electrical path for input / output (I / O) signals.

[0055] The electrical path 414 is an example of an electrical path that extends through at least the board 106, the substrate 102, the bridge 207, and the passive device 203. Note that the electrical path 414 may also extend to the integrated device 103. In one example, the electrical path 414 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 103. In another example, the electrical path 414 is configured to provide an electrical path for ground. The electrical path 414 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, (iii) at least one interconnect from the plurality of interconnects 122, (iv) at least one interconnect from the plurality of interconnects 412, (v) at least one bridge interconnect (e.g., 171, 173, 175) from the bridge 207, and (v) a terminal (e.g., solder interconnect 230, interconnect) of the passive device 203. The electrical path 414 may also include solder interconnects from the plurality of solder interconnects 130. The electrical path 414 may extend through the encapsulation layer 310 and the back side of the bridge 207. In some implementations, there may be multiple electrical paths extending through the board 106, the substrate 102, the bridge 207, and the passive devices 203. One of the electrical paths may be configured to provide an electrical path for ground, and another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0056] The electrical path 418 is an example of an electrical path that extends through at least the board 106, the substrate 102, the bridge 207, and the passive device 203. Note that the electrical path 418 may also extend to the integrated device 105. In one example, the electrical path 418 is configured to provide an electrical path for power (as part of a power distribution network). Power may be provided to the integrated device 105. In another example, the electrical path 418 is configured to provide an electrical path for ground. The electrical path 418 may include: (i) at least one board interconnect from the plurality of board interconnects 162, (ii) at least one solder interconnect from the plurality of solder interconnects 110, (iii) at least one interconnect from the plurality of interconnects 122, (iv) at least one interconnect from the plurality of interconnects 412, (v) at least one bridge interconnect (e.g., 171, 173, 175) from the bridge 207, and (v) a terminal (e.g., solder interconnect 230, interconnect) of the passive device 203. The electrical path 418 may also include solder interconnects from the plurality of solder interconnects 150. The electrical path 418 may extend through the encapsulation layer 310 and the back side of the bridge 207. In some implementations, there may be multiple electrical paths extending through the board 106, the substrate 102, the bridge 207, and the passive devices 203. One of the electrical paths may be configured to provide an electrical path for ground, and another of the electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0057] The above design and / or configuration has several advantages. First, the interconnects in / on the back side of the bridge 207 help provide more interconnects to improve power delivery to the integrated device 103 and / or the integrated device 105. Second, providing a bridge including interconnects configured as an electrical path for ground helps improve the signal integrity of the signal transmitted through the bridge 207, which helps improve the performance of the integrated device 103 and / or the integrated device 105. Third, the passive device 203 and / or the passive device 205 provide improved decoupling capabilities compared to capacitors coupled to the bottom surface of the substrate 102. Fourth, the passive device 203 and / or the passive device 205 closer to the integrated device can help improve voltage drop. Fifth, the electrical path through the back side of the encapsulation layer 310 and / or bridge 207 can provide a more direct path to the passive devices 203 and integrated devices, thereby helping to provide improved circuit decoupling and / or a shorter path to the integrated devices (eg, 103 , 105 ).

[0058] Figure 5 An exemplary cross-sectional view of the bridge member 207 is illustrated. Figure 5As shown, the bridge 207 includes a bridge substrate 170, at least one bridge dielectric layer 172, at least one bridge dielectric layer 174, a plurality of bridge interconnects 171, a plurality of bridge interconnects 173, and a plurality of bridge interconnects 175. The bridge substrate 170 may include a silicon substrate (e.g., a silicon bridge substrate). However, the bridge substrate 170 may include different materials. At least one bridge dielectric layer 172 is coupled to a first side (e.g., front side, top side) of the bridge substrate 170. A plurality of bridge interconnects 173 are located in and on (e.g., inside and above) at least one bridge dielectric layer 172. The plurality of bridge interconnects 173 may be a plurality of front bridge interconnects. At least one bridge dielectric layer 172 and a plurality of bridge interconnects 173 may be considered as part of the front side of the bridge 207. At least one bridge dielectric layer 174 is coupled to a second side (e.g., back side, bottom side) of the bridge substrate 170. A plurality of bridge interconnects 175 are located in and on (e.g., within and above) at least one bridge dielectric layer 174. The at least one bridge dielectric layer 174 and the plurality of bridge interconnects 175 may be considered part of the back side of the bridge 207. The plurality of bridge interconnects 175 may be a plurality of back side bridge interconnects. The plurality of bridge interconnects 171 may extend through the front side, the bridge substrate 170, and / or the back side of the bridge 207. For example, the plurality of bridge interconnects 171 may extend (e.g., partially or completely) through at least one bridge dielectric layer 172, the bridge substrate 170, and / or the at least one bridge dielectric layer 174. The plurality of bridge interconnects 171 may be coupled to the plurality of bridge interconnects 173 and the plurality of bridge interconnects 175. The plurality of bridge interconnects 171 may include a plurality of bridge vias (e.g., bridge via interconnects).

[0059] The plurality of bridge interconnects 171 include at least one bridge interconnect 171a, at least one bridge interconnect 171b, at least one bridge interconnect 171c, at least one bridge interconnect 171d, at least one bridge interconnect 171e, and at least one bridge interconnect 171f. The plurality of bridge interconnects 173 include at least one bridge interconnect 173a, at least one bridge interconnect 173b, at least one bridge interconnect 173c, at least one bridge interconnect 173d, and at least one bridge interconnect 173e. The plurality of bridge interconnects 175 include at least one bridge interconnect 175a, at least one bridge interconnect 175b, at least one bridge interconnect 175c, and at least one bridge interconnect 175d.

[0060] In some implementations, at least one bridge interconnect 173a may be configured to provide at least one electrical path for input / output (I / O) signals. In some implementations, at least one bridge interconnect 173b may be configured to provide at least one electrical path for ground. In some implementations, at least one bridge interconnect 173c may be configured to provide at least one electrical path for input / output (I / O) signals. In some implementations, at least one bridge interconnect 173d may be configured to provide at least one electrical path for ground. In some implementations, at least one bridge interconnect 173e may be configured to provide at least one electrical path for ground, at least one electrical path for power, and / or at least one electrical path for input / output (I / O) signals.

[0061] In some implementations, at least one bridging interconnect 171 e can be configured to provide at least one electrical path for ground, at least one electrical path for power, and / or at least one electrical path for input / output (I / O) signals.

[0062] At least one bridging interconnect 173a may be coupled to at least one bridging interconnect 173e. At least one bridging interconnect 173e may include a pad and / or a via. At least one bridging interconnect 173c may be coupled to at least one bridging interconnect 173e. At least one bridging interconnect 173b may be coupled to at least one bridging interconnect 171b and / or at least one bridging interconnect 171e. At least one bridging interconnect 175b may be coupled to at least one bridging interconnect 171b and / or at least one bridging interconnect 171e. At least one bridging interconnect 173d may be coupled to at least one bridging interconnect 171a and / or at least one bridging interconnect 171f. At least one bridging interconnect 175c may be coupled to at least one bridging interconnect 171a and / or at least one bridging interconnect 171f. As will be described in Figure 7 As further described in , some implementations may have different paths and / or use different metal planes and / or metal layers for power, ground, and / or I / O signals. Figure 5 It is illustrated that one metal layer or one metal plane can be configured to provide at least one electrical path for an I / O signal, another metal layer or another metal plane can be configured to provide at least one electrical path for other I / O signals, and a metal layer or metal plane located between these metal layers or metal planes is configured to provide at least one electrical path for ground. The metal layer or metal layer for ground is configured to help isolate signals on different metal layers or metal planes and different signals on the same metal layer or metal plane.

[0063] Figure 6 An exemplary cross-sectional profile view of the bridge 207 is illustrated. Figure 6The bridge member 207 is similar to Figure 5 The bridge member 207. However, Figure 6 The bridge 207 of the embodiment also includes a passive device 203, a passive device 205, and an encapsulation layer 310. The passive device 203 is coupled to the back side of the bridge 207 through a plurality of solder interconnects 230. For example, the passive device 203 can be coupled to at least one bridge interconnect 175d through a plurality of solder interconnects 230. The passive device 205 is coupled to the back side of the bridge 207 through a plurality of solder interconnects 250. For example, the passive device 205 can be coupled to at least one bridge interconnect 175d through a plurality of solder interconnects 250. The encapsulation layer 310 can encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 can be coupled to the back side of the bridge 207. For example, the encapsulation layer 310 can be coupled to the back side surface of at least one bridge dielectric layer 174. Passive component 203 , passive component 205 , and / or encapsulation layer 310 may or may not be considered part of bridge 207 .

[0064] Figure 7 An exemplary cross-sectional view of the bridge member 707 is illustrated. The bridge member 707 includes Figure 6 The same or similar components as the bridge member 207. Therefore, Figure 7 The bridge member 707 may be similar to Figure 5 and / or Figure 6 The bridge member 207. However, Figure 7 The bridge 707 has different arrangements and / or configurations of electrical paths for power, ground, and I / O signals. Figure 7 As shown, the front side of the bridge 707 includes interconnects configured to provide electrical paths for I / O signals, power, and ground, and the back side of the bridge 707 is configured to provide electrical paths for power and / or ground. For example, at least a portion of a metal layer (from a plurality of bridge interconnects 173) on the front side of the bridge 707 may be configured to provide an electrical path for an I / O signal, at least a portion of another metal layer (from a plurality of bridge interconnects 173) on the front side of the bridge 707 may be configured to provide an electrical path for ground, and at least a portion of another metal layer (from a plurality of bridge interconnects 173) on the front side of the bridge 707 may be configured to provide an electrical path for power. Similarly, at least a portion of a metal layer (from a plurality of bridge interconnects 175) on the back side of the bridge 707 may be configured to provide an electrical path for ground, and at least a portion of another metal layer (from a plurality of bridge interconnects 175) on the back side of the bridge 707 may be configured to provide an electrical path for power.

[0065] The integrated device (e.g., 103, 105) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a core particle. The core particles may be manufactured using a process that provides better yields than other manufacturing processes for other types of integrated devices, which may help reduce the overall cost of manufacturing the core particles. Different core particles may have different sizes and / or shapes. Different core particles may be configured to provide different functions. Different core particles may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Using several core particles that perform several functions can reduce the overall cost of the package relative to using a single chip to perform all functions of the package.

[0066] The package (e.g., 100, 200, 300, 400) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100, 200, 300, 400) may be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 300) may be configured to support a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 100, 300) may be configured to send and receive signals having different frequencies and / or communication protocols.

[0067] Having described various packages having a substrate including a bridge, a process for manufacturing the bridge will now be described below.

[0068] Exemplary Process for Making a Bridge

[0069] In some implementations, manufacturing the bridge includes several processes. FIG. 8A to FIG. 8FAn exemplary process for providing or manufacturing a bridge member is illustrated. In some implementations, a FIG. 8A to FIG. 8F The bridge 207 can be provided or manufactured by a process. However, FIG. 8A to FIG. 8F Any of the bridges (e.g., 107, 707) described in the present disclosure may be manufactured using a process.

[0070] It should be noted that FIG. 8A to FIG. 8F The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing the bridge member. In some specific implementations, the order of each process can be changed or improved. In some specific implementations, one or more of these processes can be replaced or substituted without departing from the scope of the present disclosure.

[0071] like Fig. 8A As shown, stage 1 illustrates a state after providing the bridge substrate 170. The bridge substrate 170 may include a silicon substrate.

[0072] Stage 2 illustrates a state after forming a plurality of bridge interconnections 873a over the first surface of the bridge substrate 170. The plurality of bridge interconnections 873a may be formed over the bridge substrate 170. The plurality of bridge interconnections 873a may be formed using a plating process.

[0073] Stage 3 illustrates a state after forming a bridging dielectric layer 172a over the first surface of the bridging substrate 170 and the plurality of bridging interconnections 873a. The bridging dielectric layer 172a may be formed using a deposition process and / or a lamination process.

[0074] Stage 4 illustrates a state after forming a plurality of bridge interconnects 873b over the bridge dielectric layer 172a. The plurality of bridge interconnects 873b may be formed over the bridge dielectric layer 172a. The plurality of bridge interconnects 873b may be formed using a plating process.

[0075] like Figure 8B As shown in FIG. 5 , stage 5 illustrates a state after forming a bridging dielectric layer 172b over the plurality of bridging interconnects 873b and the bridging dielectric layer 172a. The bridging dielectric layer 172b may be formed using a deposition process and / or a lamination process.

[0076] Stage 6 illustrates a state after forming a plurality of bridge interconnects over the bridge dielectric layer 172b. A plurality of bridge interconnects 873c may be formed over the bridge dielectric layer 172b. A plating process may be used to form the plurality of bridge interconnects 873c.

[0077] Stage 7 illustrates a state after forming the bridging dielectric layer 172c over the plurality of bridging interconnections 873c and the bridging dielectric layer 172b. The bridging dielectric layer 172c may be formed using a deposition process and / or a lamination process.

[0078] Stage 8 illustrates a state after forming a plurality of bridge interconnects over the bridge dielectric layer 172c. A plurality of bridge interconnects 873d may be formed over the bridge dielectric layer 172c. A plating process may be used to form the plurality of bridge interconnects 873d.

[0079] like Figure 8C As shown in FIG. 8 , stage 9 illustrates a state after forming a bridging dielectric layer 172d over the plurality of bridging interconnects 873d and the bridging dielectric layer 172c. The bridging dielectric layer 172d may be formed using a deposition process and / or a lamination process.

[0080] Stage 10 illustrates a state after forming a plurality of cavities 710 in the bridge substrate 170 and at least one bridge dielectric layer 172. The bridge dielectric layer 172 may represent and / or include bridge dielectric layers 172a, 172b, 172c, and / or 172d. The plurality of cavities 710 may be formed by a laser ablation process.

[0081] Stage 11 illustrates a state after a plurality of bridge interconnects 171 extend through the bridge substrate 170 and the at least one bridge dielectric layer 172. The plurality of bridge interconnects 171 may be formed using a plating process.

[0082] like Fig.8D As shown in , stage 12 illustrates a state after a plurality of bridge interconnects are formed on the second surface of the bridge substrate 170. Stage 12 illustrates a state after the bridge has been flipped and the interconnects are formed on the other surface. A plurality of bridge interconnects 875a may also be formed above the bridge substrate 170 (or below it depending on the orientation of the bridge substrate). A plating process may be used to form the plurality of bridge interconnects 875a.

[0083] Stage 13 shows a state after forming a bridging dielectric layer 174a over the second surface of the bridging substrate 170 and the plurality of bridging interconnects 875a. The bridging dielectric layer 174a may be formed using a deposition process and / or a lamination process.

[0084] Stage 14 illustrates a state after forming a plurality of cavities 810 in the bridging dielectric layer 174a. These cavities may be formed using an etching process (eg, a photolithography process).

[0085] Stage 15 illustrates a state after forming a plurality of bridge interconnects 875b over the bridge dielectric layer 174a. The plurality of bridge interconnects 875b may be formed over the bridge dielectric layer 174a and the plurality of bridge interconnects 875a. The plurality of bridge interconnects 875b may be formed using a plating process.

[0086] like Fig. 8EAs shown in FIG. 1 , stage 16 illustrates a state after forming a bridging dielectric layer 174b over the plurality of bridging interconnects 875b and the bridging dielectric layer 174a. The bridging dielectric layer 174b may be formed using a deposition process and / or a lamination process.

[0087] Stage 17 illustrates a state after forming a plurality of bridge interconnects 875c over the bridge dielectric layer 174b. The plurality of bridge interconnects 875c may be formed over the bridge dielectric layer 174b. Prior to forming the plurality of bridge interconnects 875c, a plurality of cavities may be formed in the bridge dielectric layer 174b in a manner similar to that described above in stage 14. The plurality of bridge interconnects 875c may be formed using a plating process.

[0088] Stage 18 illustrates a state after forming a bridging dielectric layer 174c over the plurality of bridging interconnects 875c and the bridging dielectric layer 174b. The bridging dielectric layer 174c may be formed using a deposition process and / or a lamination process.

[0089] Stage 19 illustrates a state after forming a plurality of bridge interconnects 875d over the bridge dielectric layer 174. The bridge dielectric layer 174 may represent and / or include bridge dielectric layers 174a, 174b, and / or 174c. A plurality of bridge interconnects 875d may be formed over the bridge dielectric layer 174. Prior to forming the plurality of bridge interconnects 875d, a plurality of cavities may be formed in the bridge dielectric layer 174c in a manner similar to that described above in stage 14. A plating process may be used to form the plurality of bridge interconnects 875d.

[0090] like Fig.8F As shown in FIG. 1 , stage 20 illustrates a state after passive device 203 and passive device 205 are coupled to the plurality of bridge interconnects 175. Passive device 203 may be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 230. Passive device 205 may be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 250. Passive device 203 and / or passive device 205 may be coupled using a solder reflow process.

[0091] Stage 21 illustrates a state after the encapsulation layer 310 is formed. The encapsulation layer 310 may be coupled to the surface of the bridge 207. For example, the encapsulation layer 310 is coupled to at least one bridging dielectric layer 174. The encapsulation layer 310 may encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 310 may be a member for encapsulation. The encapsulation layer 310 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 21 illustrates an example of the bridge 207, which includes a bridge substrate 170, a plurality of bridge interconnects 171, at least one bridge dielectric layer 172, a plurality of bridge interconnects 173, at least one bridge dielectric layer 174, a plurality of bridge interconnects 175, the passive device 203, the passive device 205, and the encapsulation layer 310.

[0092] FIG. 8A to FIG. 8F A process for manufacturing a bridge is illustrated, wherein a front side of the bridge is manufactured, a bridge interconnect is subsequently manufactured in a bridge substrate, and then a back side of the bridge is manufactured. Some implementations may use different processes and / or different procedures to manufacture the bridge. For example, in some implementations, the front and back sides of the bridge may be manufactured concurrently, and bridge interconnects (e.g., through-substrate vias) extending from the front side of the bridge, the bridge substrate, and the back side of the bridge may be manufactured.

[0093] Exemplary Process for Making a Bridge

[0094] In some implementations, manufacturing the bridge includes several processes. 9A to 9D An exemplary process for providing or manufacturing a bridge member is illustrated. In some implementations, a 9A to 9D The bridge 207 can be provided or manufactured by a process. However, 9A to 9D Any of the bridges (e.g., 107, 707) described in the present disclosure may be manufactured using a process.

[0095] It should be noted that 9A to 9D The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing the bridge member. In some specific implementations, the order of each process can be changed or improved. In some specific implementations, one or more of these processes can be replaced or substituted without departing from the scope of the present disclosure. 9A to 9D It is possible to exemplify a process of manufacturing the front and back surfaces of the bridge member concurrently.

[0096] like Fig. 9A As shown, stage 1 illustrates a state after providing the bridge substrate 170. The bridge substrate 170 may include a silicon substrate.

[0097] Stage 2 illustrates a state after forming a plurality of bridging interconnects over the first surface of the bridging substrate 170 and over the second surface of the bridging substrate 170. A plurality of bridging interconnects 873a may be formed over the bridging substrate 170 (e.g., over the first surface of the bridging substrate), and a plurality of bridging interconnects 875a may be formed under the bridging substrate 170 (e.g., under the second surface of the bridging substrate). A plating process may be used to form the plurality of bridging interconnects (e.g., 873a, 875a).

[0098] Stage 3 illustrates a state after forming a bridging dielectric layer 172a over the first surface of the bridging substrate 170 and the plurality of bridging interconnects 873a. Stage 3 also illustrates a state after forming a bridging dielectric layer 174a over the second surface of the bridging substrate 170 and the plurality of bridging interconnects 875a. The bridging dielectric layers (e.g., 172a, 174a) may be formed using a deposition process and / or a lamination process.

[0099] Stage 4 illustrates a state after forming a plurality of bridge interconnects over the bridge dielectric layer 172a and over the bridge dielectric layer 174a. For example, a plurality of bridge interconnects 873b may be formed over the bridge dielectric layer 172a, and a plurality of bridge interconnects 875b may be formed under the bridge dielectric layer 174a. A plating process may be used to form the plurality of bridge interconnects (e.g., 873b, 875b).

[0100] like Fig. 9B As shown in FIG. 5 , stage 5 illustrates a state after forming a bridging dielectric layer 172 b over the plurality of bridging interconnects 873 b and the bridging dielectric layer 172 a. Stage 5 also illustrates a state after forming a bridging dielectric layer 174 b over the plurality of bridging interconnects 875 b and the bridging dielectric layer 174 a. The bridging dielectric layers (e.g., 172 b, 174 b) may be formed using a deposition process and / or a lamination process.

[0101] Stage 6 illustrates a state after forming a plurality of bridge interconnects over the bridge dielectric layer 172b and over the bridge dielectric layer 174b. A plurality of bridge interconnects 873c may be formed over the bridge dielectric layer 172b, and a plurality of bridge interconnects 875c may be formed under the bridge dielectric layer 174b. A plating process may be used to form the plurality of bridge interconnects (e.g., 873c, 875c).

[0102] Stage 7 illustrates a state after forming a bridging dielectric layer 172c over the plurality of bridging interconnects 873c. Stage 7 also illustrates a state after forming a bridging dielectric layer 174c over the plurality of bridging interconnects 875c. The bridging dielectric layers (eg, 172c, 174c) may be formed using a deposition process and / or a lamination process.

[0103] Stage 8 illustrates a state after forming a plurality of bridge interconnects over the bridge dielectric layer 172c and over the bridge dielectric layer 174c. A plurality of bridge interconnects 873d may be formed over the bridge dielectric layer 172c, and a plurality of bridge interconnects 875d may be formed under the bridge dielectric layer 174c. A plating process may be used to form the plurality of bridge interconnects (e.g., 873d, 875d).

[0104] like Fig. 9C As shown in FIG. 8 , stage 9 illustrates a state after forming a bridging dielectric layer 172d over the plurality of bridging interconnects 873d and the bridging dielectric layer 172c. The bridging dielectric layer (eg, 172d) may be formed using a deposition process and / or a lamination process.

[0105] Stage 10 illustrates a state after forming a plurality of cavities 710 in the bridge substrate 170, at least one bridge dielectric layer 172, and / or at least one bridge dielectric layer 174. The plurality of cavities 710 may be formed by a laser ablation process. The bridge dielectric layer 172 may represent and / or include bridge dielectric layers 172a, 172b, 172c, and / or 172d. The bridge dielectric layer 174 may represent and / or include bridge dielectric layers 174a, 174b, and / or 174c.

[0106] Stage 11 illustrates a state after forming a plurality of bridge interconnects 171 extending through the bridge substrate 170, the at least one bridge dielectric layer 172, and / or the at least one bridge dielectric layer 174. The plurality of bridge interconnects 171 may be formed using a plating process.

[0107] like Fig.9D As shown in FIG. 1 , stage 12 illustrates a state after the passive device 203 and the passive device 205 are coupled to the plurality of bridge interconnects 175. The passive device 203 may be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 230. The passive device 205 may be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 250. The passive device 203 and / or the passive device 205 may be coupled using a solder reflow process.

[0108] Stage 13 illustrates a state after forming the encapsulation layer 310. The encapsulation layer 310 may be coupled to a surface of the bridge 207. For example, the encapsulation layer 310 may be coupled to a surface of at least one bridging dielectric layer 174. The encapsulation layer 310 may encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 310 may be a member for encapsulation. The encapsulation layer 310 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 13 illustrates an example of the bridge 207, which includes a bridge substrate 170, a plurality of bridge interconnects 171, at least one bridge dielectric layer 172, a plurality of bridge interconnects 173, at least one bridge dielectric layer 174, a plurality of bridge interconnects 175, the passive device 203, the passive device 205, and the encapsulation layer 310.

[0109] Exemplary flow chart of a method for manufacturing a bridge

[0110] In some implementations, manufacturing the bridge includes several processes. Fig.10 An exemplary flow chart of a method 1000 for providing or manufacturing a bridge member is illustrated. In some implementations, Fig.10 The method 1000 may be used to provide or manufacture the bridge 207 described in the present disclosure. However, the method 1000 may be used to provide or manufacture any of the bridges (eg, 107, 707) described in the present disclosure.

[0111] It should be noted that Fig.10 The method 1000 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a bridge member. In some implementations, the order of the processes may be changed or modified.

[0112] The method provides (at 1005) a bridging substrate (eg, 170). The bridging substrate 170 may include a silicon substrate. Fig. 9A Stage 1 of the present invention illustrates and describes an example of providing a bridging substrate.

[0113] The method forms (at 1010) bridging interconnects (e.g., 173, 175) and bridging dielectric layers (e.g., 172, 174) over the surface of the bridging substrate. For example, a plurality of bridging interconnects may be formed over the first surface of the bridging substrate 170 and over the second surface of the bridging substrate 170. A plurality of bridging interconnects 873a may be formed over the bridging substrate 170, and a plurality of bridging interconnects 875a may be formed under the bridging substrate 170. A plating process may be used to form the plurality of bridging interconnects (e.g., 873a, 875a). In another example, a bridging dielectric layer 172a may be formed over the first surface of the bridging substrate 170 and the plurality of bridging interconnects 873a. In another example, a bridging dielectric layer 174a may be formed over the second surface of the bridging substrate 170 and the plurality of bridging interconnects 875a. A deposition process and / or a lamination process may be used to form the bridging dielectric layers (e.g., 172a, 174a). The above process may be repeatedly performed to form several bridging interconnects and / or bridging dielectric layers. 9A to 9C Stages 2 through 9 of exemplify and describe examples of forming a bridging interconnect and a bridging dielectric layer.

[0114] The method forms (at 1015) a plurality of cavities (e.g., 710) in the bridging substrate 170, the at least one bridging dielectric layer 172, and / or the at least one bridging dielectric layer 174. The plurality of cavities 710 may be formed by a laser ablation process. The plurality of cavities 710 may extend through the at least one bridging dielectric layer 172, the bridging substrate 170, and / or the at least one bridging dielectric layer 174. Fig. 9C Stage 10 of the present invention illustrates and describes an example of forming a cavity.

[0115] The method forms (at 1020) a plurality of bridge interconnects (e.g., 171) in the plurality of cavities 710. The plurality of bridge interconnects 171 may extend through at least one bridge dielectric layer 172, the bridge substrate 170, and / or at least one bridge dielectric layer 174. A plating process may be used to form the plurality of bridge interconnects 171. The plurality of bridge interconnects 171 may be coupled to a plurality of bridge interconnects 173 and / or a plurality of bridge interconnects 175. Fig. 9C Stage 11 of the present invention illustrates and describes an example of forming a bridging interconnect.

[0116] The method couples (at 1025) one or more passive devices (e.g., 203, 205) to the bridging interconnects. For example, the passive device 203 may be coupled to the plurality of bridging interconnects 175 via a plurality of solder interconnects 230, and the passive device 205 may be coupled to the plurality of bridging interconnects 175 via a plurality of solder interconnects 250. The passive device 203 and / or the passive device 205 may be coupled using a solder reflow process. Fig.9DStage 12 of the present invention illustrates and describes an example of coupling a passive device to a bridge interconnect.

[0117] The method forms (at 1030) an encapsulation layer (e.g., 310). For example, the encapsulation layer 310 may be coupled to a surface of the bridge 207. The encapsulation layer 310 may encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 310 may be a member for encapsulation. The encapsulation layer 310 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Fig.9D Stage 13 of the present invention illustrates and describes an example of forming an encapsulation layer.

[0118] It should be noted that Fig.10 The method 1000 may be modified to follow FIG. 8A to FIG. 8F The bridge may be fabricated in the manner described in . In such a specific implementation, the method may form a bridging dielectric layer and a bridging interconnect for the front side of the bridge, then form an interconnect in the bridge substrate, and then form a bridging dielectric layer and a bridging interconnect for the back side of the bridge. Once the front side bridging interconnect and the back side bridging interconnect are fabricated, passive devices may be coupled to the bridge and an encapsulation layer may be formed.

[0119] Exemplary process for making a package including a bridge

[0120] In some implementations, manufacturing the package includes several processes. FIG. 11A to FIG. 11D An exemplary process for providing or manufacturing a package including a bridge is illustrated. In some implementations, a FIG. 11A to FIG. 11D The package 400 can be provided or manufactured using a process. FIG. 11A to FIG. 11D Any of the packages described in this disclosure that include a bridge may be manufactured using a process described herein.

[0121] It should be noted that FIG. 11A to FIG. 11D The process of the present invention may combine one or more stages to simplify and / or clarify the process for providing or manufacturing a package including a bridge. In some specific implementations, the order of the processes may be changed or improved. In some specific implementations, one or more of these processes may be replaced or substituted without departing from the scope of the present disclosure.

[0122] Fig.11A Stage 1 of FIG. 1 illustrates a state after providing a substrate 102 and a carrier 1100. The substrate 102 may be coupled to and located on the carrier 1100. The substrate 102 may include at least one dielectric layer 120 and a plurality of interconnects 122. FIG. 13A to FIG. 13B An example of manufacturing a substrate including at least one dielectric layer and a plurality of interconnects is illustrated.

[0123] Stage 2 illustrates a state after forming a cavity 209 in the substrate 102. The cavity 209 may be formed using a laser ablation process and / or an etching process. The cavity 209 may extend (e.g., partially or completely) through the substrate 102 (e.g., through at least one dielectric layer 120 of the substrate 102). The surface of the carrier 1100 may be exposed through the cavity 209.

[0124] Stage 3 illustrates a state after the bridge 207 is placed in the cavity 209 and on the carrier 1100. A pick-and-place process may be used to position the bridge 207 in the cavity 209. Different tools may position different bridges (e.g., 107, 707) in the cavity 209. The bridge 207 may or may not include an encapsulation layer. The bridge 207 may or may not include one or more passive devices. The bridge 207 may be located on the carrier 1100 and / or coupled to the carrier.

[0125] Fig. 11B Stage 4 of exemplifies a state after a dielectric layer 1120 is formed over the bridge 207. The dielectric layer 1120 may be similar to at least one dielectric layer 120. The dielectric layer 1120 may be formed along a portion of the face of the bridge 207 located in the cavity 209. The dielectric layer 1120 may fill a portion of the cavity 209 of the substrate 102. In some implementations, some portions of the cavity 209 are filled with the dielectric layer 1120. In some implementations, most of the space in the cavity 209 not occupied by the bridge 207, if not all of the space, may be filled with the dielectric layer 1120. The dielectric layer 1120 may be formed using a deposition process and / or a lamination process. In some implementations, an encapsulation layer similar to the encapsulation layer 310 may be used instead of the dielectric layer 1120. The encapsulation layer provided over the bridge 207 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0126] Stage 5 illustrates a state after a plurality of cavities 1121 are formed in the dielectric layer 1120. The plurality of cavities 1121 may be formed using a laser ablation process and / or an etching process (e.g., a photolithography process). The dielectric layer 1120 may be considered as a portion of the dielectric layer 120. Therefore, the dielectric layer 120 may include the dielectric layer 1120. It may be considered that a plurality of cavities 1121 are formed in the dielectric layer 120. The plurality of cavities 1121 may expose a portion of the bridge 207. For example, the plurality of cavities 1121 may expose a bridge interconnect of the bridge 207.

[0127] Stage 6 illustrates after forming a plurality of bridging interconnects 1123 over at least one dielectric layer 120 and / or dielectric layer 1120. Dielectric layer 1120 may be considered a portion of at least one dielectric layer 120. The plurality of bridging interconnects 1123 may be coupled to the bridging interconnects (e.g., 173) of the plurality of interconnects 122 and bridge 207. The plurality of bridging interconnects 1123 may be formed using a plating process.

[0128] Fig. 11C Stage 7 of FIG. 1 illustrates a state after the carrier 1100 is decoupled from the substrate 102 and the bridge 207. The carrier 1100 may be removed and / or separated from the substrate 102 and / or the bridge 207.

[0129] Stage 8 illustrates a state after a plurality of cavities 1143 are formed in the encapsulation layer 310. The plurality of cavities 1143 may be formed using a laser ablation process and / or an etching process.

[0130] Stage 9 illustrates a state after forming a plurality of interconnects 1145. The plurality of interconnects 1145 may be formed in and on the encapsulation layer 310. The plurality of interconnects 1145 may be formed on at least one dielectric layer 120. The plurality of interconnects 1135 may include interconnects that are considered part of the substrate 102 and / or bridge interconnects that are considered part of the bridge 207. Some or all of the plurality of interconnects 1145 may be considered part of the plurality of interconnects 122.

[0131] Stage 10 illustrates a state after a dielectric layer 1160 is formed on at least one dielectric layer 120 and / or encapsulation layer 310. A deposition process and / or a lamination process may be used to form dielectric layer 1160. Dielectric layer 1160 may be similar to at least one dielectric layer 120. Dielectric layer 1160 may be considered as a part of at least one dielectric layer 120.

[0132] Stage 11 illustrates a state after the integrated devices are coupled to substrate 102. For example, integrated device 103 is coupled to substrate 102 through a plurality of solder interconnects 130, and integrated device 105 is coupled to substrate 102 through a plurality of solder interconnects 150. A solder reflow process may be used to couple the integrated devices (e.g., 103, 105) to substrate 102.

[0133] Stage 12 illustrates a state after the plurality of solder interconnects 110 are coupled to the substrate 102. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 of the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the substrate 102. Stage 12 illustrates an example of a package 400 that includes the substrate 102, the bridge 207, the integrated device 103, and the integrated device 105.

[0134] Exemplary flow chart of a method for manufacturing a package including a bridge

[0135] Fig.12 An exemplary flow chart of a method 1200 for providing or manufacturing a package including a bridge is illustrated. In some implementations, Fig.12 The method 1200 may be used to provide or manufacture the package 400 described in the present disclosure. However, the method 1200 may be used to provide or manufacture any of the packages described in the present disclosure.

[0136] It should be noted that Fig.12 The method 1200 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0137] The method provides (at 1205) a substrate (eg, 102) including at least one dielectric layer (eg, 120) and a plurality of interconnects (eg, 122). The substrate 102 may be coupled to a carrier 1100. The substrate may be a laminate substrate. FIG. 13A to FIG. 13B An example of manufacturing a substrate including at least one dielectric layer and a plurality of interconnects is illustrated. Fig.11A Stage 1 of the present invention illustrates and describes an example of providing a substrate and a carrier.

[0138] The method forms (at 1210) a cavity (e.g., 209) in the substrate 102. The cavity 209 may be formed using a laser ablation process and / or an etching process. The cavity 209 may extend (e.g., partially or completely) through the substrate 102 (e.g., through at least one dielectric layer 120 of the substrate 102). A surface of the carrier 1100 may be exposed through the cavity 209. Fig.11A Stage 2 of the present invention illustrates and describes an example of forming a cavity in a substrate.

[0139] The method places (at 1215) a bridge (e.g., 207) in the cavity 209 of the substrate 102 and on the carrier 1100. The bridge 207 may be positioned in the cavity 209 of the substrate 102 using a pick-and-place process. Different tools may place different bridges (e.g., 107, 207) in the cavity 209. The bridge 207 may or may not include at least one passive device. The bridge 207 may or may not include an encapsulation layer. The bridge 207 may be located on the carrier 1100 and / or coupled to the carrier. Fig.11A Stage 3 of the present invention illustrates and describes an example of placing a bridge member in a cavity of a substrate.

[0140] The method forms (at 1220) dielectric layers and interconnects (e.g., bridge interconnects) over the bridge and / or substrate. For example, dielectric layer 1120 may be formed over bridge 207. Dielectric layer 1120 may be similar to at least one dielectric layer 120. Dielectric layer 1120 may be formed along a portion of a face of bridge 207 that is located in cavity 209. Dielectric layer 1120 may fill a portion of cavity 209 of substrate 102. Dielectric layer 1120 may be formed using a deposition process and / or a lamination process. In some implementations, dielectric layer 1120 may be an encapsulation layer similar to encapsulation layer 310. The encapsulation layer provided over bridge 207 may be provided using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0141] Forming the interconnects may include forming cavities in the dielectric layer and performing a plating process. For example, a plurality of cavities 1121 may be formed in the dielectric layer 1120. The plurality of cavities 1121 may be formed using a laser ablation process and / or an etching process (e.g., a photolithography process). A plurality of bridging interconnects 1123 may be formed on at least one dielectric layer 120 and / or on the dielectric layer 1120. The dielectric layer 1120 may be considered as a portion of at least one dielectric layer 120. The plurality of bridging interconnects 1123 may be coupled to the plurality of interconnects 122 and the bridging interconnects (e.g., 173) of the bridge 207. The plurality of bridging interconnects 1123 may be formed using a plating process.

[0142] The carrier 1100 is decoupled from the substrate 102 and the bridge 207. The carrier 1100 may be removed and / or separated from the substrate 102 and / or the bridge 207. A plurality of cavities 1143 may be formed in the encapsulation layer 310. The plurality of cavities 1143 may be formed using a laser ablation process and / or an etching process. A plurality of interconnects 1145 may be formed. The plurality of interconnects 1145 may be formed in and on the encapsulation layer 310. The plurality of interconnects 1145 may be formed on at least one dielectric layer 120. The plurality of interconnects 1135 may include interconnects that are considered part of the substrate 102 and / or bridge interconnects that are considered part of the bridge 207. Some or all of the plurality of interconnects 1145 may be considered part of the plurality of interconnects 122. A dielectric layer 1160 may be formed on at least one dielectric layer 120 and / or the encapsulation layer 310. The dielectric layer 1160 may be formed using a deposition process and / or a lamination process. The dielectric layer 1160 can be similar to the at least one dielectric layer 120. The dielectric layer 1160 can be considered as a part of the at least one dielectric layer 120. FIG. 11B to FIG. 11C Stages 4 to 10 of the present invention illustrate examples of forming a dielectric layer, forming a cavity, and forming an interconnect.

[0143] The method couples (at 1025) at least one integrated device to the substrate. For example, the integrated device 103 may be coupled to the substrate 102 via a plurality of solder interconnects 130, and the integrated device 105 may be coupled to the substrate 102 via a plurality of solder interconnects 150. A solder reflow process may be used to couple the integrated devices (e.g., 103, 105) to the substrate 102. Fig.11D Stage 11 of the present invention illustrates and describes an example of coupling an integrated device to a substrate.

[0144] The method couples (at 1230) a plurality of solder interconnects to the substrate. For example, a plurality of solder interconnects 110 may be coupled to the substrate 102. The plurality of solder interconnects 110 may be coupled to a plurality of interconnects 122 of the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the substrate 102. Fig.11D Stage 12 of the present invention illustrates and describes an example of coupling a solder interconnect to a substrate.

[0145] Exemplary Process for Making a Substrate

[0146] In some implementations, manufacturing the substrate includes several processes. FIG. 13A to FIG. 13B An exemplary process for providing or manufacturing a substrate is illustrated. In some implementations, a substrate may be used. FIG. 13A to FIG. 13B The substrate 102 may be provided or manufactured using a process. FIG. 13A to FIG. 13B A process for manufacturing any of the substrates described in this disclosure.

[0147] It should be noted that FIG. 13A to FIG. 13B The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing a substrate. In some specific implementations, the order of each process can be changed or improved. In some specific implementations, one or more of these processes can be replaced or substituted without departing from the scope of the present disclosure.

[0148] like Fig.13A As shown in , stage 1 illustrates a state after providing a carrier 1300. A seed layer 1301 and an interconnect 1302 may be located on the carrier 1300. The interconnect 1302 may be located on the seed layer 1301. The interconnect 1302 may be formed using a plating process and an etching process. In some implementations, the carrier 1300 may be provided with a seed layer 1301 and a metal layer that is patterned to form the interconnect 1302. The interconnect 1302 may represent at least some of the interconnects from the plurality of interconnects 142.

[0149] Stage 2 illustrates a state after a dielectric layer 1320 is formed over the carrier 1300, the seed layer 1301, and the interconnect 1302. The dielectric layer 1320 may be formed using a deposition process and / or a lamination process. The dielectric layer 1320 may include prepreg and / or polyimide. The dielectric layer 1320 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0150] Stage 3 illustrates a state after a plurality of cavities 1310 are formed in the dielectric layer 1320. The plurality of cavities 1310 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0151] Stage 4 illustrates a state after interconnects 1312 are formed in and on dielectric layer 1320 (including in and on plurality of cavities 1310). For example, vias, pads, and / or traces may be formed. The interconnects may be formed using a plating process.

[0152] Stage 5 illustrates a state after dielectric layer 1322 is formed over dielectric layer 1320 and interconnect 1312. Dielectric layer 1322 may be formed using a deposition process and / or a lamination process. Dielectric layer 1322 may include prepreg and / or polyimide. Dielectric layer 1322 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0153] like Fig. 13B As shown in FIG. 1 , stage 6 illustrates a state after a plurality of cavities 1330 are formed in the dielectric layer 1322. The plurality of cavities 1330 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0154] Stage 7 illustrates a state after interconnects 1314 are formed in and on dielectric layer 1322, including in and on plurality of cavities 1330. For example, vias, pads, and / or traces may be formed. The interconnects may be formed using a plating process.

[0155] Stage 8 illustrates a state after the carrier 1300 is decoupled (e.g., separated, removed, ground away) from the at least one dielectric layer 140 and the seed layer 1301, and portions of the seed layer 1301 are removed (e.g., etched away), leaving the substrate 102 including the at least one dielectric layer 120 and the plurality of interconnects 122.

[0156] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0157] In some implementations, manufacturing the substrate includes several processes. Fig.14 An exemplary flow chart of a method 1400 for providing or manufacturing a substrate is illustrated. In some implementations, Fig.14The method 1400 can be used to provide or manufacture a substrate of the present disclosure. For example, Fig.14 The method 1400 is used to manufacture the substrate 102.

[0158] It should be noted that Fig.14 The method 1400 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0159] The method provides (at 1405) a carrier (e.g., 1300). Different implementations may use different materials for the carrier 1300. The carrier 1300 may include a seed layer (e.g., 1301). The seed layer 1301 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Fig.13A Stage 1 of the present invention illustrates and describes an example of a provided carrier having a seed layer.

[0160] The method forms (at 1410) interconnects over the carrier 1300 and the seed layer 1301 and patterns them. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is located over the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 1302). Fig.13A Stage 1 of FIG. 1 illustrates and describes an example of forming and patterning interconnects over a seed layer and a carrier.

[0161] The method forms (at 1415) a dielectric layer 1320 over the seed layer 1301, the carrier 1300, and the interconnect 1302. The dielectric layer 1320 may be formed using a deposition process and / or a lamination process. The dielectric layer 1320 may include a prepreg and / or a polyimide. The dielectric layer 1320 may include a photoimageable dielectric. Forming the dielectric layer 1320 may also include forming a plurality of cavities (e.g., 1310) in the dielectric layer 1320. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Fig.13A Stages 2 to 3 of exemplify and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0162] The method forms (at 1420) interconnects in and on the dielectric layer. For example, interconnect 1312 may be formed in and on dielectric layer 1320. The interconnect may be formed using a plating process. Forming the interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity of the dielectric layer. Fig.13A Stage 4 of FIG. 1 illustrates and describes an example of forming interconnects in and over a dielectric layer.

[0163] The method forms (at 1425) a dielectric layer 1322 over the dielectric layer 1320 and the interconnect 1312. The dielectric layer 1322 may be formed using a deposition process and / or a lamination process. The dielectric layer 1322 may include a prepreg and / or a polyimide. The dielectric layer 1322 may include a photoimageable dielectric. Forming the dielectric layer 1322 may also include forming a plurality of cavities (e.g., 1330) in the dielectric layer 1322. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. FIG. 13A to FIG. 13B Stages 5 to 6 of exemplify and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0164] The method forms (at 1430) interconnects in and on the dielectric layer. For example, interconnect 1314 may be formed in and on dielectric layer 1322. The interconnect may be formed using a plating process. Forming the interconnect may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity of the dielectric layer. Forming the interconnect may include forming a pillar-shaped interconnect. Fig. 13B Stage 7 of exemplifies and describes an example of forming interconnects in and over a dielectric layer, including forming pillar-shaped interconnects.

[0165] The method (at 1435) decouples the carrier (e.g., 1300) from the seed layer (e.g., 1301). The carrier 1300 may be separated and / or ground away. The method (at 1435) may also remove portions of the seed layer (e.g., 1301). An etching process may be used to remove portions of the seed layer 1301. Fig. 13B Stage 8 of the present invention illustrates and describes an example of decoupling the carrier and removing the seed layer.

[0166] Exemplary Electronic Devices

[0167] Fig.15 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-level packages (SiP), or systems on a chip (SoC) are illustrated. For example, a mobile phone device 1502, a laptop computer device 1504, a fixed location terminal device 1506, a wearable device 1508, or a motor vehicle 1510 may include a device 1500 as described herein. For example, the device 1500 may be any of the devices and / or integrated circuit (IC) packages described herein. Fig.15The devices 1502, 1504, 1506, and 1508 and the vehicle 1510 illustrated in the figure are merely exemplary. Other electronic devices may also feature the device 1500, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0168] Figures 1 to 7 , FIG. 8A to FIG. 8F , 9A to 9D , Fig.10 , FIG. 11A to FIG. 11D , Fig.12 , FIG. 13A to FIG. 13B as well as Figure 14 to Figure 15 One or more of the components, processes, features, and / or functions illustrated in the present disclosure may be rearranged and / or combined into a single component, process, feature, or function, or may be implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1 to 7 , FIG. 8A to FIG. 8F , 9A to 9D , Fig.10 , FIG. 11A to FIG. 11D , Fig.12 , FIG. 13A to FIG. 13B as well as Figure 14 to Figure 15 and its corresponding description in this disclosure are not limited to die and / or IC. In some specific implementations, Figures 1 to 7 , FIG. 8A to FIG. 8F , 9A to 9D , Fig.10 , FIG. 11A to FIG. 11D , Fig.12 , FIG. 13A to FIG. 13B as well as Figure 14 to Figure 15 The invention and its corresponding description may be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0169] It should be noted that the drawings in the present disclosure may represent actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size and / or shape of various parts and / or components in the drawings may be exemplary. In some implementations, various components and / or parts in the drawings may be optional.

[0170] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other, even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can be transmitted between the two objects. Two electrically coupled objects may or may not have an electric current flowing between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything above the fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. The component located at the top may be located above the component at the bottom. The top component may be considered as the bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be located above (e.g., above) a first surface of the second component, and the third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. It should also be noted that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is above (e.g., on a surface of) the second component; and / or (3) the first component is in (e.g., embedded in) the second component. A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X to XX may refer to a value between X and XX, inclusive. The values ​​between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within 10 percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0171] In some implementations, an interconnect is an element or component in a device or package that allows or facilitates electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a column, a metallization layer, a redistribution layer, and / or an under-bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or procedures to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process may be used to form an interconnect.

[0172] It should also be noted that the various disclosures contained herein may be described as processes depicted as job diagrams, flow charts, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many of the operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0173] Further examples are described below to facilitate understanding of the present disclosure.

[0174] Aspect 1: A package, the package comprising: a substrate; a bridge, the bridge being located in the substrate; a first integrated device, the first integrated device being coupled to the substrate; and a second integrated device, the second integrated device being coupled to the substrate. The bridge comprises: a bridge substrate; at least one first bridge dielectric layer, the at least one first bridge dielectric layer being coupled to a first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect being located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer being coupled to a second surface of the bridge substrate; at least one second bridge interconnect, the at least one second bridge interconnect being located in the at least one second bridge dielectric layer; and at least one bridge interconnect, the at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0175] Aspect 2: A package according to aspect 1, wherein the at least one first bridging interconnect is configured to provide a first electrical path for input / output (I / O) signals, and wherein the at least one second bridging interconnect is configured to provide a second electrical path for power.

[0176] Aspect 3: The package of aspect 1, wherein the at least one first bridging interconnect is configured to provide a first electrical path for an input / output (I / O) signal, and wherein the at least one second bridging interconnect is configured to provide a second electrical path for a ground.

[0177] Aspect 4: The package of aspect 3, wherein the at least one second bridging interconnect is configured to provide another electrical path for power.

[0178] Aspect 5: The package according to aspects 1 to 4, further comprising a passive device coupled to the at least one second bridge interconnect.

[0179] Aspect 6: The package according to aspect 5, further comprising an encapsulation layer encapsulating the passive device.

[0180] Aspect 7: The package of any one of aspects 5 to 6, wherein the bridge comprises a front side and a back side, and wherein the passive device is coupled to the back side of the bridge.

[0181] Aspect 8: The package of aspect 7, wherein the bridge is configured to provide at least one electrical path for power, and wherein power transmitted through the bridge is transmitted through the back surface of the bridge.

[0182] Aspect 9: The package of any of aspects 1 to 8, wherein the first integrated device is configured to be electrically coupled to the bridge.

[0183] Aspect 10: The package of any of aspects 1 to 9, wherein the first integrated device is configured to be electrically coupled to the second integrated device through the substrate and the bridge.

[0184] Aspect 11: A package according to Aspect 10, wherein input and / or output (I / O) signals are configured to be transmitted between the first integrated device and the second integrated device via an electrical path, the electrical path comprising an interconnect from the substrate and a bridge interconnect from the bridge.

[0185] Aspect 12: The package of aspects 1 to 11, wherein the first integrated device comprises a first die and the second integrated device comprises a second die.

[0186] Aspect 13: The package of aspects 1 to 12, wherein the at least one first bridging interconnect comprises a first thickness, wherein the at least one second bridging interconnect has a second thickness, and wherein the second thickness is greater than the first thickness.

[0187] Aspect 14: The package of aspect 13, wherein the first thickness is in a first range of approximately 1 to 2 microns, and wherein the second thickness is in a second range of approximately 3 to 6 microns.

[0188] Aspect 15: A device including a package, the package including: a substrate; a bridge, the bridge being located in the substrate; a first integrated device, the first integrated device being coupled to the substrate; and a second integrated device, the second integrated device being coupled to the substrate. The bridge includes: a bridge substrate; at least one first bridge dielectric layer, the at least one first bridge dielectric layer being coupled to a first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect being located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer, the at least one second bridge dielectric layer being coupled to a second surface of the bridge substrate; at least one second bridge interconnect, the at least one second bridge interconnect being located in the at least one second bridge dielectric layer; and at least one bridge interconnect, the at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0189] Aspect 16: The device of aspect 15, wherein the first integrated device is configured to be electrically coupled to the second integrated device through the substrate and the bridge.

[0190] Aspect 17: A device according to Aspect 16, wherein input and / or output (I / O) signals are configured to be transmitted between the first integrated device and the second integrated device via an electrical path, the electrical path comprising an interconnect from the substrate and a bridge interconnect from the bridge.

[0191] Aspect 18: The device of aspects 15 to 17, wherein the first integrated device comprises a first core-die and the second integrated device comprises a second core-die.

[0192] Aspect 19: The device according to aspects 15 to 18, further comprising a passive device coupled to the at least one second bridging interconnect.

[0193] Aspect 20: The device according to aspect 19, further comprising an encapsulation layer encapsulating the passive device.

[0194] Aspect 21: The device of any of aspects 19 to 20, wherein the bridge comprises a front side and a back side, and wherein the passive device is coupled to the back side of the bridge.

[0195] Aspect 22: The device of aspect 21, wherein the bridge is configured to provide at least one electrical path for power, and wherein power transmitted through the bridge is transmitted through the back surface of the bridge.

[0196] Aspect 23: A device according to Aspects 15 to 22, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0197] Aspect 24: A method for manufacturing a package. The method provides a substrate. The method places a bridge in the substrate. The bridge includes: a bridge substrate; at least one first bridge dielectric layer, the at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect, the at least one first bridge interconnect is located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer, the at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect, the at least one second bridge interconnect is located in the at least one second bridge dielectric layer; and at least one bridge interconnect, the at least one bridge interconnect extends through the at least one first bridge dielectric layer and the bridge substrate. The method couples a first integrated device to the substrate. The method couples a second integrated device to the substrate.

[0198] Aspect 25: The method of aspect 24, wherein the package comprises a passive device coupled to the at least one second bridging interconnect.

[0199] Aspect 26: The method of aspect 25, wherein the package comprises an encapsulation layer encapsulating the passive device.

[0200] Aspect 27: The method of any of aspects 25 to 26, wherein the bridge comprises a front side and a back side, and wherein the passive device is coupled to the back side of the bridge.

[0201] Aspect 28: The method of aspect 27, wherein the bridge is configured to provide at least one electrical path for power, and wherein power transmitted through the bridge is transmitted through the back surface of the bridge.

[0202] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be interpreted as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, rather than limiting the scope of the appended claims. Thus, the present teachings can be easily applied to other types of devices, and many replacements, modifications and variations will be apparent to those skilled in the art.

Claims

1. A package, comprising: substrate; A bridge member, the bridge member being located in the substrate, wherein the bridge member comprises: bridge substrate; at least one first bridging dielectric layer coupled to a first surface of the bridging substrate; at least one first bridging interconnect, the at least one first bridging interconnect being located in the at least one first bridging dielectric layer; at least one second bridging dielectric layer coupled to a second surface of the bridging substrate; at least one second bridging interconnect, the at least one second bridging interconnect being located in the at least one second bridging dielectric layer; and at least one bridging interconnect extending through the at least one first bridging dielectric layer and the bridging substrate; a first integrated device coupled to the substrate; and A second integrated device is coupled to the substrate.

2. The package according to claim 1, wherein the at least one first bridging interconnect is configured to provide a first electrical path for an input / output (I / O) signal, and Wherein the at least one second bridging interconnect is configured to provide a second electrical path for power.

3. The package according to claim 1, wherein the at least one first bridging interconnect is configured to provide a first electrical path for an input / output (I / O) signal, and Wherein the at least one second bridging interconnect is configured to provide a second electrical path for grounding. The package of claim 3 , wherein the at least one second bridging interconnect is configured to provide another electrical path for power. 5 . The package of claim 1 , further comprising a passive device coupled to the at least one second bridge interconnect. The package according to claim 5 , further comprising an encapsulation layer encapsulating the passive device.

7. The package according to claim 5, wherein the bridge comprises a front face and a back face, and The passive device is coupled to the back side of the bridge.

8. The package according to claim 7, wherein the bridge is configured to provide at least one electrical path for electrical power, and The power transmitted through the bridge member is transmitted through the back surface of the bridge member. 9 . The package of claim 1 , wherein the first integrated device is configured to be electrically coupled to the bridge. 10 . The package of claim 1 , wherein the first integrated device is configured to be electrically coupled to the second integrated device through the substrate and the bridge.

11. The package of claim 10, wherein input and / or output (I / O) signals are configured to be transmitted between the first integrated device and the second integrated device via an electrical path comprising an interconnect from the substrate and a bridge interconnect from the bridge. 12 . The package of claim 1 , wherein the first integrated device comprises a first die and the second integrated device comprises a second die.

13. The package according to claim 1, wherein the at least one first bridging interconnect comprises a first thickness, wherein the at least one second bridging interconnect has a second thickness, and The second thickness is greater than the first thickness.

14. The package according to claim 13, wherein the first thickness is within a first range of about 1 to 2 microns, and Wherein the second thickness is in a second range of about 3 to 6 microns.

15. A device, comprising: A package, the package comprising: substrate; A bridge member, the bridge member being located in the substrate, wherein the bridge member comprises: bridge substrate; at least one first bridging dielectric layer coupled to a first surface of the bridging substrate; at least one first bridging interconnect, the at least one first bridging interconnect being located in the at least one first bridging dielectric layer; at least one second bridging dielectric layer coupled to a second surface of the bridging substrate; at least one second bridging interconnect, the at least one second bridging interconnect being located in the at least one second bridging dielectric layer; and at least one bridging interconnect extending through the at least one first bridging dielectric layer and the bridging substrate; a first integrated device coupled to the substrate; and A second integrated device is coupled to the substrate. 16 . The device of claim 15 , wherein the first integrated device is configured to be electrically coupled to the second integrated device through the substrate and the bridge.

17. The device of claim 16, wherein input and / or output (I / O) signals are configured to be transmitted between the first integrated device and the second integrated device via an electrical path comprising an interconnect from the substrate and a bridge interconnect from the bridge.

18. The device of claim 15, wherein the first integrated device comprises a first core-die and the second integrated device comprises a second core-die.

19. The device of claim 15, further comprising a passive device coupled to the at least one second bridging interconnect.

20. The device of claim 19, further comprising an encapsulation layer encapsulating the passive device.

21. The device according to claim 19, wherein the bridge comprises a front face and a back face, and The passive device is coupled to the back side of the bridge.

22. The device according to claim 21, wherein the bridge is configured to provide at least one electrical path for electrical power, and The power transmitted through the bridge member is transmitted through the back surface of the bridge member.

23. The device of claim 15, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

24. A method for manufacturing a package, the method comprising: providing a substrate; A bridge is disposed in the substrate, wherein the bridge comprises: bridge substrate; at least one first bridging dielectric layer coupled to a first surface of the bridging substrate; at least one first bridging interconnect, the at least one first bridging interconnect being located in the at least one first bridging dielectric layer; at least one second bridging dielectric layer coupled to a second surface of the bridging substrate; at least one second bridging interconnect, the at least one second bridging interconnect being located in the at least one second bridging dielectric layer; and at least one bridging interconnect extending through the at least one first bridging dielectric layer and the bridging substrate; coupling a first integrated device to the substrate; and A second integrated device is coupled to the substrate.

25. The method of claim 24, wherein the package comprises a passive device coupled to the at least one second bridging interconnect.

26. The method of claim 25, wherein the package comprises an encapsulation layer encapsulating the passive device.

27. The method according to claim 25, wherein the bridge comprises a front face and a back face, and The passive device is coupled to the back side of the bridge.

28. The method according to claim 27, wherein the bridge is configured to provide at least one electrical path for electrical power, and The power transmitted through the bridge member is transmitted through the back surface of the bridge member.

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