Surface emitting laser, method of manufacturing surface emitting laser

Abstract

The vertical cavity surface emitting laser includes: an oxide substrate having a first surface and a second surface on an opposite side of the first surface; a semiconductor portion disposed on the first surface; a dielectric filter layer disposed between the semiconductor portion and the first face, and having a dielectric filter layer configured to provide an optical window; a first DBR mirror; and a second DBR mirror disposed at the curved surface of the second face. The first DBR mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate, and the second DBR mirror are arranged in a first axial direction to form an expanded cavity. The semiconductor portion is disposed between the dielectric filter layer and the first DBR mirror, and includes a p-type Group III nitride region, an n-type Group III nitride region, and a Group III nitride active region between the p-type and n-type Group III nitride regions.

Description

Technical Field

[0001] The present invention relates to an extended cavity III-nitride vertical cavity surface emitting laser (VCSEL) and a method of manufacturing the extended cavity III-nitride VCSEL. Background Art

[0002] Surface emitting lasers are called vertical cavity surface emitting lasers (VCSELs). VCSELs include a semiconductor active region disposed between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors (referred to as multiple DBRs) used as high reflective mirrors. The semiconductor active region, also known as a gain medium, is disposed between the two DBRs so that the two DBRs and the semiconductor active region form an optical cavity. The n-side and p-side regions inject their respective carriers, i.e., electrons and holes, into the active region, and these carriers recombine in the active region to generate light. The light or electromagnetic radiation thus generated is reflected multiple times by the multiple DBRs and propagates in the optical cavity, thereby generating laser light. VCSELs provide one of the multiple DBRs with a mirror with lower reflectivity for emitting a laser beam.

[0003] This application cites many patents or non-patent publications, as indicated by their reference numbers in brackets (i.e. []) throughout the specification. A list of publications sorted by these reference numbers can be found in the section entitled "Non-Patent Literature" or "Patent Literature" below. Reference List Non-patent literature

[0004] NPL 1:Appl.Phys.Express 12,044004(2019) NPL2:Sci.Rep.8,10350(2018) NPL 3:Applied Phys.Lett.83,2121(2003) NPL4:Appl.Phys.Express 2008,1,121102. NPL5:Appl.Phys.Express 2012,5,092104 NPL 6:Optics Express,27,24717(2019) NPL 7:Appl.Phys.Express,13,041003(2020) NPL8:Appl.Phys.Express,14,031002(2021) NPL 9:Applied Phys.Lett.119,142103(2021) NPL10:Crystals,11(12)1563,(2021) NPL11: MBStern and TRJay, "Dry etching for coherent refractivemicro-lens arrays," Opt.Eng.33,3547-3551(1994) Summary of the invention Technical issues

[0005] The optical cavity defined by two flat DBR mirrors in a VCSEL suffers from excessive diffraction losses as the cavity length increases. Using curved mirrors or lenses in a VCSEL allows the VCSEL to have a longer optical cavity. As shown in references [NPL1] and [NPL2], the curved mirrors or lenses focus the electric field of the laser into the gain medium to reduce the diffraction losses arising from the longer cavity length. High efficiency operation can be achieved by aligning the cavity modes to the gain spectrum in the VCSEL. Using very short cavity lengths, for example, one or two laser wavelengths in a VCSEL, allows the spacing of the cavity modes to be larger. Due to the larger spacing, at least one cavity mode is less likely to fall within the gain spectrum of the VCSEL, thereby reducing the yield and lasing efficiency of the VCSEL. Conversely, increasing the cavity length narrows the mode spacing. Due to the narrower spacing, one of the cavity modes is more likely to fall within the gain spectrum of the VCSEL, thereby increasing the yield of lasing.

[0006] However, in VCSELs with long cavities, it is a challenging task that all device layers except the active region are made of materials that are transparent to the electromagnetic radiation propagating in the VCSEL. One of the DBR mirrors can be set on the curved back side of the III-nitride semiconductor host substrate, which is formed into a lens structure. Therefore, the VCSEL of this structure does not use substrate removal, which results in that the III-nitride host substrate may introduce moderate losses in the cavity. This curved mirror approach, as proposed in references [NPL1] and [NPL2], still provides a mostly native host substrate for the cavity, where the lens structure is formed by etching a curved n-side DBR mirror thereon. This method is designed for GaN homoepitaxial growth. In addition, the dopant concentration of the host substrate contained in the long cavity should be as low as the level of pin absorption losses. Therefore, the host substrate is first thinned to reduce the light absorption losses in the cavity. Thinning the substrate is a difficult process to control thickness and can damage the substrate, as it must be thinned from an initial thickness of 300 to 400 microns to a target thickness of 10 to 30 microns to provide the required cavity length for the VCSEL.

[0007] Otherwise, including the host substrate in the cavity may result in unintentional absorption losses for each round trip of the electromagnetic radiation, thus preventing the lasing threshold from being reduced. However, the authors of [NPL3] demonstrated the operation of a GaN-based VCSEL in an extended cavity scheme, which was fabricated by growing the GaN-based device layers directly on a less absorptive sapphire substrate. In this scheme, the lattice mismatch between the sapphire substrate and the device layers still limits the crystal quality of the device layers, and therefore the lifetime and yield of such devices will become an issue.

[0008] It is best to keep the absorption source as thin as possible while maintaining stable laser operation, and the bottom mirror must be positioned to form the cavity so that the top and bottom mirrors are close to each other to remove the native substrate. In the heteroepitaxial approach, the III-nitride device layers are grown on a foreign substrate (such as sapphire or silicon), and the foreign substrate of the III-nitride VCESL device can be easily removed by chemical etching or laser lift-off (called "LLO"), as described in reference [NPL4], while heteroepitaxial GaN on sapphire substrates cannot improve its crystal quality. However, the conventional LLO process is not suitable for GaN homoepitaxial. Among other methods, reference [NPL5] reports the removal of III-nitride device layers from GaN homoepitaxial structures, and it is still very interesting as in references [NPL6] to [NPL10].

[0009] The longer the cavity, the better the stability in terms of lasing and thermal drift. Alternatively, extended cavity VCSEL designs can be achieved by carefully removing the VCSEL device layers from the native growth substrate or a foreign substrate and then reattaching lossless transparent oxide (called "TO") materials such as ZnO and group III oxides, where group III oxides may include Al 2 O 3 and Ga 2 O 3 . This design requires surface treatment in the connected TO substrate and the removed device layer, which must be performed to sub-nanometer level and leads to potential unwanted reflections due to the difference in refractive index at the GaN / oxide interface formed during reconnection. If such reflections lead to degradation of device performance, the unwanted reflections can be suppressed by anti-reflection coatings at the interface. All of these procedures are time-consuming and lead to additional cost issues.

[0010] In view of all these disadvantages, an object of the present disclosure is to provide a structure of a III-VCSEL with extended cavity features and a method for manufacturing a VCSEL with extended cavity features. Another object of the present disclosure is to provide a single-step integration solution that allows the formation of an extended cavity without involving complex bonding and substrate removal procedures. Problem Solving

[0011] One configuration of the present disclosure is a VCSEL, which includes: an oxide substrate having a first face and a second face located on an opposite side of the first face, the second face including a curved surface; a semiconductor portion disposed on the first face of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first face of the oxide substrate and having a reflective spectrum, the reflective spectrum being configured to provide an optical window; a first distributed Bragg reflector (DBR), the semiconductor portion being disposed between the dielectric filter layer and the first DBR mirror; and a second DBR mirror disposed at the curved surface of the oxide substrate, the first DBR mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate, and the second DBR mirror being arranged along a first axial direction to form an extended cavity, the semiconductor portion including a p-type III-nitride region, a III-nitride region, and a III-nitride active region located between the p-type III-nitride region and the III-nitride region, the p-type III-nitride region, the III-nitride active region, and the III-nitride region being arranged along the first axial direction, and the III-nitride region including an n-type III-nitride region.

[0012] Another configuration of the present invention is a method for manufacturing a VCSEL, the method comprising: preparing a starting substrate, the starting substrate comprising an oxide substrate, a III-nitride template plug and a dielectric filter layer, the oxide substrate having a first surface and a second surface located on the opposite side of the first surface of the oxide substrate, the dielectric filter layer and the III-nitride template plug are located on the first surface of the oxide substrate, the dielectric filter layer has a reflection spectrum, and the reflection spectrum is configured to provide an optical window; growing a III-nitride region from the III-nitride template plug on the dielectric filter layer; after growing the III-nitride region, growing a semiconductor stack including an n-type III-nitride region, a III-nitride active region and a p-type III-nitride region; processing the second surface of the oxide substrate to form an oxide substrate having a curved surface, the curved surface being located on the opposite side of the first surface of the oxide substrate; after growing the semiconductor stack, forming a first distributed Bragg reflector (DBR) stack on the first surface of the oxide substrate; forming a second DBR stack on the curved surface of the oxide substrate. Effects of the Invention

[0013] The above configuration may provide a structure of a IIIVCSEL having extended cavity features and a method for manufacturing a VCSEL having extended cavity features. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] [like Figure 1 ] Figure 1is a schematic cross-sectional view showing an extended cavity VCSEL according to one embodiment of the present disclosure, which includes two reflectors and a Fabry-Perot filter. [like Figure 2 ] Figure 2 is a schematic top view showing a VCSEL according to an embodiment of the present disclosure. [like Figure 3A ] Figure 3A Schematic diagram showing the process steps of a method for manufacturing an extended cavity VCSEL according to an embodiment of the present disclosure. [like Figure 3B ] Figure 3B Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3C ] Figure 3C Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3D ] Figure 3D Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3E ] Figure 3E Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3F ] Figure 3F Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3G ] Figure 3G Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3H ] Figure 3H Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Fig. 3I ] Fig. 3I Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3J ] Figure 3J Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3K ] Figure 3K Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3L ] Figure 3L Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3M ] Figure 3M Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3N ] Figure 3N Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Fig.3O ] Fig.3O Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3P ] Figure 3P Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3Q ] Figure 3Q Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 3R ] Figure 3R Schematic diagram showing process steps in the method for manufacturing a VCSEL according to the present embodiment. [like Figure 4A ] Figure 4A : is a schematic perspective view showing main elements of a VCSEL product manufactured according to the manufacturing method of this embodiment. [like Figure 4B ] Figure 4B is a schematic top view showing main elements of a VCSEL product according to the present embodiment. [like Figure 5 ] Figure 5 1 is a schematic top view showing an arrangement of device parts in a VCSEL product in the VCSEL manufacturing method according to the present embodiment. [like Figure 6 ] Figure 6 FIG. 4 is a schematic top view showing another arrangement of device parts in a VCSEL product in the VCSEL manufacturing method according to the present embodiment. [like Figure 7 ] Figure 7 FIG. 4 is a schematic top view showing still another arrangement of device parts in a VCSEL product in the VCSEL manufacturing method according to the present embodiment. [like Figure 8 ] Figure 8 is a schematic cross-sectional view showing an exemplary device structure of a VCSEL according to the present embodiment. [like Fig. 9 ] Fig. 9 is a schematic cross-sectional view showing an exemplary device structure of a VCSEL according to the present embodiment. [like Fig.10 ] Fig.10 is a schematic cross-sectional view showing an exemplary device structure of a VCSEL according to the present embodiment. Example Description

[0015] The teachings of the present disclosure may be readily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. With reference to the accompanying drawings, schematic diagrams of vertical cavity surface emitting lasers (VCSELs) and methods of manufacturing VCSELs according to the present disclosure will be described below. To facilitate understanding, the same reference numerals are used, where possible, to represent the same elements common to the drawings.

[0016] Figure 1 is a schematic diagram showing the layer structure of the VCSEL according to the present embodiment. Figure 2 is a schematic top view showing a VCSEL according to this embodiment. Specifically, Figure 1 Shown along Figure 2 The cross section is taken along line II. Figure 1 and Figure 2 A VCSEL 11 is shown bonded to a submount 10a on the curved DBR side of the VCSEL 11 using solder bumps 10b. Figure 1 In parts (1), (2) and (3) of FIG. 1 , the vertical axis represents reflectivity (R) and the horizontal axis represents wavelength (W).

[0017] The VCSEL 11 includes a first distributed Bragg reflector (DBR) mirror 13, a semiconductor portion 15, a dielectric filter layer 17, a second DBR mirror 19, and an oxide substrate 21. The dielectric filter layer 17 is disposed between the first DBR mirror 13 and the second DBR mirror 19. The oxide substrate 21 has a first face 21a and a second face 21b located on the opposite side of the first face 21a, and the second face 21b includes a curved surface 21c. The semiconductor portion 15 is disposed on the first face 21a of the oxide substrate 21 and is located between the first DBR mirror 13 and the dielectric filter layer 17. The first DBR mirror 13, the semiconductor portion 15, the dielectric filter layer 17, the oxide substrate 21, and the second DBR mirror 19 are arranged along the first axial direction Ax1 to form an extended optical cavity CAV. The first DBR mirror 13 is disposed on the semiconductor portion 15, and the second DBR mirror 19 is disposed on the curved surface 21c of the oxide substrate 21. The dielectric filter layer 17 is disposed in the extended optical cavity CAV formed by the first DBR mirror 13 and the second DBR mirror 19, and has a reflection wavelength region and an optical window WIN defined by the reflection wavelength region as a wavelength. The optical window WIN allows the light beam to travel in the optical cavity CAV at the laser wavelength, and the reflection wavelength region can block the light of the wavelength outside the optical window WIN.

[0018] The semiconductor portion 15 includes a p-type III-nitride region 23, a III-nitride active region 27, and a III-nitride region 29, and the III-nitride region 29 includes an n-type III-nitride region 25. The III-nitride active region 27 is disposed between the p-type III-nitride region 23 and the III-nitride region 29 (n-type III-nitride region 25). The p-type III-nitride region 23, the III-nitride active region 27, and the III-nitride region 29 (n-type III-nitride region 25) are arranged along the first axis direction Ax1. In VCSEL11, group III nitrides may include any compounds of nitrogen and group III elements, such as aluminum, gallium, and indium, and specifically, binary alloys such as gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN); ternary alloys such as aluminum gallium nitride (GaAlN), aluminum indium nitride (InAlN), and gallium indium nitride (GaInN), and quaternary alloys such as gallium nitride aluminum nitride (InGaAlN), which may contain any trace impurities. Group III nitrides may be doped with p-type dopants such as magnesium, carbon, and beryllium to form p-type regions, and may be doped with n-type dopants such as silicon and tellurium to form n-type regions. Group III nitrides may also be doped with p-type and n-type dopants.

[0019] The oxide substrate 21 includes one or more oxide materials, specifically aluminum oxide (eg, Al 2 O 3 , which has a band gap of about 8.8 electron volts (eV), zinc oxide (such as ZnO, which has a band gap of about 3.37 eV), or gallium oxide (such as Ga 2 O 3 , whose band gap is about 4.6 to 4.7 eV). These oxide materials, such as aluminum oxide, zinc oxide and gallium oxide, are transparent to light of visible, infrared or ultraviolet wavelengths, which can pass through the oxide substrate 21.

[0020] The VCSEL 11 further includes a III-nitride template plug 18 extending from the first face 21a of the oxide substrate 21 to the semiconductor portion 15 in the through hole 17a in the dielectric filter layer 17. The through hole 17a extends along the first axis direction Ax1. The III-nitride template plug 18 has an embedded portion 18a (also Figure 3D ) and protrusion 18b (also shown in Figure 3D ). The embedded portion is located in the through hole 17 a and is disposed in contact with the first face 21 a of the oxide substrate 21 , and the protruding portion protrudes into the semiconductor portion 15 .

[0021] like Figure 1As shown, the curved surface 21 c of the oxide substrate 21 has a center line CNT, and the center lines CNT of the III-nitride template plug 18 and the curved surface 21 c are not aligned with each other.

[0022] The dielectric filter layer 17 has a reflection spectrum R3, and the reflection spectrum R3 is configured to provide an optical window WIN, such as Figure 1 See section (2) of Figure 1 The dielectric filter layer 17 specifically includes a plurality of dielectric layers 30, and the plurality of dielectric layers 30 are disposed on the oxide substrate 21. The plurality of dielectric layers 30 are arranged to configure a Fabry-Perot filter that can provide a reflection spectrum R3, and the reflection spectrum R3 has an optical window WIN.

[0023] The first DBR mirror 13 has a reflection spectrum R1, such as Figure 1 The second DBR mirror 19 has a reflection spectrum R2, as shown in part (1). Figure 1 As shown in part (3) of . The reflection spectra R1 and R2 each have a reflection wavelength bandwidth including the wavelength λ0.

[0024] The magnitude relationship among the reflection spectra R1 , R2 , and R3 is as follows: the reflectivity value of each of the reflection spectra R1 , R2 is much greater than the reflectivity value of the reflection spectrum R3 ; and the reflectivity value of the reflection spectrum R2 may be greater than the reflectivity value of the reflection spectrum R1 .

[0025] The III-nitride active region 27 has a quantum well structure to generate light having a wavelength within the first reflection spectrum R1, the second reflection spectrum R2, and the optical window WIN of the dielectric filter layer 17. Laser light can be emitted through the first DBR mirror 13 having a reflectivity lower than that of the second DBR mirror 19, for example.

[0026] Specifically, the first DBR mirror 13 includes a first dielectric layer 13a and a second dielectric layer 13b, which are alternately arranged along the first axial direction Ax1 to serve as, for example, a top mirror. The second DBR mirror 19 also includes a third dielectric layer 19a and a fourth dielectric layer 19b, which are also alternately arranged on the first axial direction Ax1 to serve as, for example, a bottom mirror. The dielectric filter layer 17 extends between the semiconductor portion 15 and the first face 21a of the oxide substrate 21.

[0027] In the VCSEL 11 , the length of the extended optical cavity CAV may be greater than 50 micrometers (>50 micrometers). The curved surface 21 c has a radius of curvature greater than 50 micrometers (>50 micrometers).

[0028] In the VCSEL 11, the first DBR mirror is planar, the second DBR mirror is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 may be greater than 50 micrometers. The semiconductor portion 15 may have a thickness greater than 0.5 micrometers.

[0029] The VCSEL 11 further includes a conductive layer 35 disposed on the semiconductor portion 15. The conductive layer 35 may include a group III nitride semiconductor (e.g., n-type GaN) or a conductive inorganic material (e.g., indium tin oxide (ITO)) or both. A portion of the conductive layer 35 is disposed between the first DBR mirror 13 and the semiconductor portion 15.

[0030] In VCSEL11, semiconductor portion 15 has an aperture structure 39 to limit electric particles and laser. If necessary, semiconductor portion 15 may also include a tunnel structure located at the topmost layer of semiconductor portion 15 to supplement or replace aperture structure 39. The tunnel structure changes the conductivity type, that is, one of electrons or holes becomes another. The tunnel structure may be one of a tunnel junction or a buried tunnel junction. The tunnel junction may limit the path of carriers through the aperture structure 39, while the buried tunnel junction may limit the path of carriers without the aperture structure 39.

[0031] Reference Figure 1 and Figure 2 , the semiconductor portion 15 has a mesa structure 37. The mesa structure 37 includes a base region 37a and a mesa region 37b disposed on the base region 37a. The mesa region 37b is also provided with a p-type III-nitride region 23, a III-nitride active region 27, and a portion of an n-type III-nitride region of the III-nitride region 25. The base region 37a includes the remaining portion of the n-type III-nitride region of the III-nitride region 25, and at the bottom of the mesa region 37b, the mesa region 37b may be surrounded by the n-type III-nitride front side 25a at the top of the base region 37a.

[0032] The VCSEL 11 also includes a first electrode 31, such as an anode electrode, located on the mesa region 37b, and a second electrode 33, such as a cathode electrode, located outside the mesa region 37b. In the exemplary VCSEL 11, the anode electrode is arranged to contact the ITO or the extended semiconductor layer, and the cathode electrode is arranged to contact the top surface 25a of the n-type III-nitride region 25 of the base region 37a. The first electrode 31 is arranged on the conductive layer 35 or the semiconductor portion 15 outside the first DBR mirror 13, and can be in contact with the conductive layer 35 or the semiconductor portion 15. The cathode electrode 33 can be arranged on the n-type III-nitride front surface 37c (25a) of the base region 37a outside the mesa region 37b.

[0033] In VCSEL 11 including conductive layer 31, semiconductor portion 15 has first face 15a and second face 15b opposite to first face 15a. Dielectric filter layer 17 is provided in contact with first face 15a of semiconductor portion 15, and conductive layer 31 is provided in contact with second face 15b thereof.

[0034] Reference Figure 1 , which shows the profile of a VCSEL 11, which is provided with two highly reflective DBR mirrors 13 and 19, wherein one of these mirrors is placed on a curved surface of an oxide substrate 21, and the oxide substrate 21 separates the two DBR mirrors 13 and 19 from each other to allow the extended optical cavity to be integrated in a single step. In view of the fabrication of the VCSEL 11, the semiconductor portion 15 is grown along the dielectric filter layer 17 by epitaxial lateral overgrowth (ELO) derived from a III-nitride template plug 18, and the dielectric filter layer 17 may have a Fabry-Perot multilayer film, allowing both a narrow optical bandpass within the wavelength and a large optical suppression region outside the narrow bandpass. The reflectivity of the dielectric filter layer 17 is designed to be very small at the laser wavelength compared to the reflectivity of each DBR mirror 13 and 19.

[0035] The oxide substrate 21 separates the DBR mirrors 13 and 19 forming the extended cavity further apart, so that the longitudinal mode spacing of the extended cavity is very small, and this very small spacing is conducive to at least one longitudinal mode being located within the narrow bandpass window WIN of the dielectric filter layer 17. In contrast, since the semiconductor portion 15 separates the DBR mirror 13 that may form the parasitic cavity from the dielectric filter layer 17 at a shorter spacing, the longitudinal mode spacing of the parasitic cavity is larger, and this larger spacing is conducive to most or all of the longitudinal modes of the parasitic cavity being located outside the narrow bandpass window WIN. All longitudinal modes of the parasitic cavity are likely to be located outside the narrow bandpass window WIN. The narrower bandpass window of the dielectric filter layer 17 is combined with the wider reflection wavelength range of the highly reflective DBR mirrors 13 and 19 to demonstrate the extended optical cavity. The active region (i.e., the gain dielectric) can be aligned with the DBR mirrors 13 and 19 so that the field maximum of the widely separated longitudinal modes to be suppressed is not aligned with the position of the gain medium. Although VCSEL11 includes multiple cavities, at least one single longitudinal mode is selected from the extended cavity in the narrow bandpass window WIN, and light of the selected mode in the narrow bandpass window WIN can propagate in the extended cavity between the plane mirror and the curved mirror to generate laser light. Therefore, the small mode spacing makes it less complicated to align the selected mode with the gain spectrum, and the long cavity also makes it less complicated to align the selected mode with the gain medium.

[0036] VCSEL11 involves the placement of a curved mirror on an oxide substrate 21, and a dielectric filter layer 17, such as a Fabry-Perot filter, embedded between the plane mirror and the curved mirror of VCSEL11. The curved mirror can return the incident electromagnetic radiation to the gain medium with a reflectivity of nearly 90% by refocusing, thereby providing lower diffraction losses for the extended optical cavity of VCSEL11. In addition, the oxide substrate 21 is made of a transparent oxide (TO) material, which includes ZnO, Ga 2 O 3 or Al 2 O 3 , transparent oxide materials and curved mirrors can make the light absorption therein negligible, thus achieving lossless light transmission in the substantial part of the VCSEL11 optical cavity. The current device structure allows the VCSEL11 to have a long cavity and better thermal performance.

[0037] Reference Figure 1 , the VCSEL 11 is equipped with a curved DBR mirror, which is arranged on the back side of the substrate 21 as a bottom mirror. In view of the manufacture of the VCSEL 11, the curved DBR mirror is designed to be integrated with a simple manufacturing step, for example, a patterned dielectric stack is formed along the curved back side of the substrate 21, that is, the DBR reflector 19. The VCSEL 11 is also equipped with a flat DBR mirror, which is located on the front side of the substrate 21 as a top mirror. In view of the manufacture of the VCSEL 11, the flat DBR mirror is designed to be integrated with a simple manufacturing step, for example, a patterned dielectric stack is formed along the plane of the semiconductor part 15, that is, the DBR mirror 13 as a top mirror. The flat DBR mirror 13 and the curved DBR mirror 19 form an extended cavity, in which a dielectric filter layer 17 is embedded. The dielectric filter layer 17 preferably includes an anti-reflection coating or a Fabry-Perot structure, which includes a dielectric material to exhibit a narrow passband characteristic near a desired wavelength and reflect light of a wavelength other than the passband wavelength. In view of the manufacture of the VCSEL 11, the semiconductor portion 15 formed by epitaxial lateral overgrowth (ELO) originates from the template plug 18, which can be manufactured by deposition and etching on the oxide substrate 21. The semiconductor portion 15 includes a light emitting structure provided with a p-type III-nitride region 23, an n-type III-nitride region 25 of the III-nitride region 29, and a III-nitride active region 27 located between the p-type III-nitride region 23 and the n-type III-nitride region 25.

[0038] The filter layer 17 can preferably be a Fabry-Perot structure made of all dielectric. In view of the manufacture of VCSEL 11, the dielectric filter layer 17 can be used as an ELO mask, which allows the III-nitride to be overgrown laterally epitaxially from the III-nitride template plug 18 to prevent the III-nitride from being deposited thereon, and as a support structure for the III-nitride thus grown on the oxide substrate 21 by ELO. The ELO deposition of the III-nitride for the semiconductor portion 15 is embedded in a portion of the dielectric filter layer 17. Therefore, the filter layer 17 laminated with the ELO mask structure is designed to provide a simple step integration of the thin semiconductor portion 15 on the TO substrate 21 without removing the substrate and bonding. The filter layer 17 has optical properties that provide a narrow passband and a stopband, the narrow passband allows lasing in the mode of the main optical cavity, and the stopband can prevent one or more modes of the parasitic optical cavity from lasing.

[0039] The VCSEL 11 is provided with a first DBR mirror 13 on a semiconductor portion 15, which extends over a filter layer 17. The first DBR mirror 13 is provided with first dielectric layers 13a and second dielectric layers 13b alternately arranged along a first axial direction Ax1, and the material of the first layer 13a is different from that of the second layer 13b.

[0040] The VCSEL 11 is equipped with a second DBR mirror 19 separated from the first DBR mirror 13 by a semiconductor portion 15 and an oxide substrate 21. The second DBR mirror 19 includes third and fourth dielectric layers 19a and 19b alternately arranged along the first axial direction Ax1, and the material of the third layer 19a is different from that of the fourth layer 19b.

[0041] VCSEL 11 further includes an omnidirectional reflection layer 40. Omnidirectional reflection layer 40 covers semiconductor portion 15 and dielectric filter layer 17 to reflect stray light of the emission laser wavelength outward, thereby preventing stray light from interfering with the laser in the cavity. Omnidirectional reflection layer 40 also serves as a passivation layer between cathode electrode 33 and anode electrode 31.

[0042] The cavity CAV has a total cavity length, which can be defined as the distance between the curved surface 21c and a substantially flat surface disposed in contact with the first DBR mirror 19. In an exemplary structure of the VCSEL 11, the distance between the curved surface 21c and the flat top surface 21a of the TO substrate 21 may be 50 to 1000 microns, which serves as an extended cavity, and the thickness of the semiconductor portion 15 is approximately 0.5 to 4 microns, also serving as an extended cavity.

[0043] The semiconductor portion 15 is provided with an aperture structure 39. The aperture structure 39 has a conductive aperture portion 39a and a low conductive portion 39b surrounding the aperture conductive portion 39a. The aperture conductive portion 39a provides an electrical path formed between the anode electrode 31 and the cathode electrode 33 for the VCSEL 11. Carriers such as electrons and holes flow through the electrical path and recombine in the III-nitride active region 27 to generate light, which is emitted from one of the DBR mirrors (e.g., the first DBR mirror 13). The conductive aperture portion 39a is located laterally away from the template plug 18 to reduce optical interference that may be caused by the template plug 18. Preferably, the conductive aperture portion 39a can be separated from the sidewall of the template plug 18 by at least about 3 microns, which is measured along the dielectric filter layer 17. The main part of the extended cavity is composed of the oxide substrate 21, and its size is designed so that the template plug 18 is located outside the main part of the cone associated with the curved DBR mirror 19.

[0044] Reference Figure 2 , the III-nitride template plug 18, the curved surface 21c and the aperture structure 39 are depicted by dotted lines. In addition to the first axial direction Ax1, the second axial direction Ax2 and the third axial direction Ax3 are also shown, and these three axial directions are perpendicular to each other. For example, the conductive hole portion 39a is asymmetrically positioned relative to the liner template plug 18, and the asymmetrical design is conducive to the arrangement of the anode electrode and the cathode electrode on the front side and the arrangement of the position of the curved DBR mirror 19 on the back side. The semiconductor portion 15 is formed by the exposed sidewall surface and the top surface of the III-nitride template plug 18 growing laterally outward on the dielectric filter layer. This formation allows the III-nitride template plug 18 to connect the semiconductor portion 15 to the TO substrate 21, and the template plug 18 forms a thermal path for the III-nitride, which allows heat dissipation from the active area 27 to the oxide substrate 21. This structure that provides a thermal path for the VCSEL 11 ensures that thermal energy is absorbed by the better thermally conductive TO substrate 21 through the template plug 18.

[0045] Will refer to Figures 3A to 3R An example of a method of manufacturing the VCSEL according to the present embodiment is described. FIG. 3A to FIG. 3R are cross-sectional views showing process steps in the manufacturing method, and the cross-sectional views are taken along Figure 2 In order to avoid repeated descriptions below, the following text will use Figure 1 and Figure 2 In the following description, the group III nitrides may be deposited by, for example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0046] See also Figure 3A, prepare an oxide wafer 41 corresponding to the oxide substrate 21 of the VCSEL 11, which includes a transparent material such as ZnO, Al 2 O 3 , Ga 2 O 3 , a Group III nitride film 43 , such as gallium nitride (GaN), is then deposited on the top surface of the oxide wafer 41 .

[0047] Reference Figure 3B , a resist mask 45 is formed on the III-nitride film 43, and the III-nitride film 43 is etched with the mask 45 to form one or more III-nitride template plugs 18, each of which has a width "W" and a height "H". The III-nitride template plugs 18 each include a single crystal III-nitride with a very low defect density. For example, the III-nitride template plugs 18 can extend linearly along the top surface of the oxide wafer 41 and can be arranged in parallel at a pitch of "P".

[0048] Reference Figure 3C , a dielectric multilayer film 47 is deposited on the oxide wafer 41 and above the III-nitride template plug 18. The thickness of the dielectric multilayer film 47 is less than the height of the III-nitride template plug 18 and the thickness of the III-nitride film 43, and may have a structure capable of forming a Fabry-Perot filter.

[0049] The dielectric multilayer film 47 for the exemplary dielectric Fabry-Perot structure has the following exemplary layer structure: "(HL)m2nH(LH)m", where "H" and "L" represent respective layers having high and low refractive indices, which have a quarter-wavelength optical thickness, and "m" and "n" are integers. Specifically, "(HL)m" means that the high refractive index layer and the low refractive index layer alternate m times; "2nH" means that the high refractive index layer is 2n times thick; "(LH)m" means that the low refractive index layer and the high refractive index layer alternate m times. By designing the Fabry-Perot spectrum (R3) according to the refractive index and layer thickness of the dielectric material, a high transmission optical window can be realized at the central wavelength λ0, and high reflection spectral regions can be realized on both sides of the high transmission optical window.

[0050] Reference Figure 3DThe dielectric multilayer film 47 is processed by etching to form the dielectric filter layer 17. During the etching process, a mask (not shown in the figure) may be used. The mask is formed on the dielectric multilayer film 47 and has corresponding openings at the III-nitride template plugs 18. Each III-nitride template plug 18 is located at the corresponding opening of the dielectric filter layer 17 thus formed, and has a lower portion and an upper portion. The lower portion 18a of the III-nitride template plug 18 is embedded in the opening of the dielectric filter layer 17, and the upper portion 18b of the III-nitride template plug 18 protrudes from the top surface of the dielectric filter layer 17.

[0051] In obtaining Figure 3D In the process of the intermediate product shown, a starting substrate 51 has been prepared, which is equipped with an oxide substrate as an oxide wafer 41, an arrangement of a III-nitride template plug 18, and a dielectric filter layer 17. The oxide wafer 41 has a first face 41a and a second face 41b located on the opposite side of the first face 41a. The dielectric filter layer 17 and the III-nitride template plug 18 are arranged in the first face 41a. The reflection spectrum (R3) of the dielectric filter layer 17 extending along the first face 41a is configured to provide an optical window (WIN). The light travels in the extended optical cavity between the flat DBR reflector 13 and the curved DBR reflector 19 to pass through the dielectric Fabry-Perot filter twice in each optical round trip. The dielectric filter layer 17 is provided with a Fabry-Perot filter structure, which provides a narrow passband and a stopband on both sides of the narrow passband. If necessary, a dielectric multilayer film 47 may be deposited and then patterned to form periodically arranged stripe-shaped openings on the first face 41 a of the oxide wafer 41 , and group III nitride may be selectively grown in the stripe-shaped openings to form group III nitride template plugs 18 .

[0052] Reference Figure 3E After forming a starting substrate 51 including an arrangement of a dielectric filter layer 17 and a III-nitride template plug 18, a III-nitride region 52 is epitaxially grown on the starting substrate 51, starting from the III-nitride template plug 18, along the dielectric filter layer 17. The III-nitride region 52 is grown from the side and top of the III-nitride template plug 18 by ELO to form a wing-shaped III-nitride island, and adjacent III-nitride regions 52 are isolated from each other. The III-nitride island is formed by depositing the III-nitride material from the template plug 18 by ELO, and defines a cutting street "D" extending between adjacent III-nitride islands. The cutting street "D" also defines a separate VCSEL portion, which corresponds to the VCSEL chip. The III-nitride region 52 may be partially or fully doped with an n-type dopant and extends outward from the template plug 18.

[0053] Reference Figure 3FIf necessary, before growing a subsequent semiconductor stack, the III-nitride region 52 is planarized by at least one of polishing or etching to form a III-nitride region 53 having a planar top surface 53 a.

[0054] Reference Figure 3G After the III-nitride region 53 is grown, a semiconductor stack 55 including a III-nitride device layer is epitaxially formed. The III-nitride device layer is provided with an n-type III-nitride region 25, a III-nitride active region 27, and a p-type III-nitride region 23. Specifically, the n-type III-nitride region 25, the III-nitride active region 27, and the p-type III-nitride region 23 are sequentially grown on the plane of the III-nitride region 53.

[0055] Specifically, the nitride region 25 may include a GaN-based material or an AlN-based material doped with an n-type dopant, which allows electrons to be supplied to the III-nitride active region 27, and the p-type III-nitride region 23 may include a GaN-based material or an AlN-based material doped with a p-type dopant, so that holes can be supplied to the III-nitride active region 27. The III-nitride active region 27 may include a GaN-based material or an AlN-based material, such as GaN, InGaN, AlN, AlGaN, or AlInGaN. The III-nitride active region 27 may be equipped with a single well layer or a quantum well structure, such as a single quantum well (SQW) or multiple quantum wells (MQWs). If necessary, a buried tunnel junction layer or a tunnel bonding layer may be grown after the p-type III-nitride region 23 is deposited.

[0056] Reference Figure 3H After the semiconductor stack 55 is grown, the oxide wafer 41 is processed at the second face 41b to form a curved surface 41c generated from the second face 41b and a newly generated back face 41d, and if necessary, the second face 41b may be a polished face. Specifically, the curved surface 41c of the oxide wafer 41 is used as the microlens 45a. The curved surface 41c of the oxide wafer 41 has a central axis CNT, and as shown in FIG. Figure 3H As shown, the center axes CNT of the III-nitride template plug 18 and the curved surface 41c are not aligned with each other. The polished surface of the oxide wafer 41, such as a sapphire wafer, is processed to produce the curved surface 41c and the back surface 41d, such as the microlens 45a. The curved surface 41c can be positioned at a predetermined position, which is aligned so that the focus of the microlens 45a helps determine the position of the aperture structure that confines the carriers. The aperture structure will be described later.

[0057] Reference Figures 3H to 3J, the curved surface 41c used as a microlens can be manufactured using the thermal reflow technology mentioned in reference [NPL11]. Specifically, Fig. 3I As shown, a resist film may be formed on the back side of the oxide wafer 41 and processed by standard photolithography techniques to form a patterned resist 57, such as a photoresist microdisk 45a. Figure 3J As shown, the patterned resist 57 is subjected to a high temperature heat treatment, for example, using a hot plate, and the high temperature heat treatment causes the patterned resist 57 to be deformed into a lens shape, which can be used as a sacrificial photoresist mask 58. Further, as Figure 3H As shown, the lens-shaped resist 58 and the back side 41b of the oxide wafer 41 can be processed by reactive ion etching (RIE) so that the shape of the lens-shaped resist 58 is transferred to the oxide wafer 41. Specifically, the oxide wafer 41 is thinned, and a curved surface 41c such as a microlens 45a is left at the back side 41d of the thinned oxide wafer, which will be referred to as an oxide substrate 42. Thinning the oxide wafer 41 can adjust the length of the extended optical cavity. Therefore, through this process, not only can the curved surface 41c be formed, but also the cavity length can be adjusted.

[0058] refer to Figure 3K , a photoresist film 59 is formed on the front surface of the oxide substrate 42 to cover the semiconductor stack 55 and the dielectric filter layer 17. Then, the curved surface 41c of the back surface 41d of the oxide substrate 42 is irradiated with the photomask 56 through which the exposure light 60 passes, and the exposure light 60 passes through the curved surface 41c to focus on, for example, a point in the portion of the photoresist film 59 covering the top surface of the semiconductor stack 55, thereby forming an exposed portion 59a of the photoresist film 59.

[0059] Reference Figure 3L , the exposed photoresist film 59 is developed to form a resist mask 61 having a patterned opening 61a. Then, a film 63 is deposited on the resist mask 61 and in the patterned opening 61a, and the resist mask 61 is removed to leave a mask 64 produced by the film 63. The film 63 may be made of Ti / Au or a dielectric layer.

[0060] Reference Figure 3M, the manufacture of VCSEL 11 that does not include a buried tunnel junction requires the formation of an aperture structure 65. Specifically, ion implantation is performed using a mask 64 to form an aperture structure 65. The aperture structure 65 formed in this way includes an aperture region 65a and an isolation region 65b surrounding the aperture region 65a. Ions such as hydrogen atoms, n-type dopant atoms and / or p-type dopant atoms are implanted into the semiconductor stack 51 using a mask 64 to form an aperture structure 65 in the semiconductor stack 55. The aperture structure 65 is provided with a semiconductor aperture region 65a and an isolation region 65b, the semiconductor aperture region 65a can form an electrical path for carriers to flow, and the isolation region 65b can confine light and carriers within the semiconductor aperture region 65a. After the ion implantation, the mask 64 is removed.

[0061] Alternatively, when manufacturing a VCSEL 11 in which the semiconductor stack 55 includes a buried tunnel junction, it is necessary to perform a tunneling operation on the tunnel layer (eg, p ++ GaN layer and n ++ The GaN layer is patterned. Specifically, the tunnel layer can be etched with mask 64 to form a buried tunnel junction. After etching, the mask 64 is removed, and then the III-nitride is regrown to deposit a doped semiconductor layer, which serves as a current spreader and covers the buried tunnel junction.

[0062] Reference Figure 3N , after removing the mask 64 when manufacturing the VCSEL 11 that does not include a buried tunnel junction, a conductive layer 67 is deposited on the semiconductor stack 55 to cover the semiconductor aperture region 65a and the isolation region 65b. The conductive layer 67 may include a heavily doped III-nitride semiconductor layer (e.g., GaN or AlGaN) and / or an inorganic layer (e.g., indium tin oxide (ITO)), and is transparent to light from the III-nitride active region 27. For example, the conductive layer 67 may be deposited on the oxide substrate 42 without a mask.

[0063] Reference Fig.3O , a mesa structure 69 is generated by the semiconductor stack 55. Specifically, a photoresist is formed on the oxide substrate 42a to cover the semiconductor stack 55, and then patterned to form a resist mask 71. Using the resist mask 71, the lower n-type GaN region of the semiconductor stack 55 is exposed by etching, thereby forming a mesa structure 69 including the group III nitride active region 27 and the p-type group III nitride region 23. On the outside of the mesa structure 69, an etched surface 69a of the n-type group III nitride region is generated by the semiconductor stack 55.

[0064] Referring to 3P and 3Q, after forming the mesa structure 69 with the resist mask 71 remaining on the oxide substrate 42, an omnidirectional reflection (ODR) layer 73 is formed by depositing an omnidirectional reflection film 73 over the oxide substrate 42 and the resist mask 71 and then removing the resist mask 71 (i.e., by lift-off). Figure 3P As shown, the formed ODR layer 73 covers the side of the mesa structure 69 and the top of the dielectric filter layer 17, and has an opening at the top of the mesa structure 69. The ODR layer 71 serves as a reflector of stray light of the laser wavelength of the VCSEL 11, and also serves as a passivation layer between the anode electrode and the cathode electrode to be formed in the subsequent process steps.

[0065] Refer again Figure 3Q After forming the ODR layer 73, a first distributed Bragg reflector (DBR) stack 75 and a first electrode 77 are formed on the conductive layer 67 by lift-off, and a second electrode 79 is formed on the etched surface 69a of the n-type III-nitride region 25 outside the mesa structure 69 by lift-off.

[0066] Specifically, the first DBR stack 75 can be formed by lift-off and aligned with the aperture structure 65 or the buried tunnel junction. The first electrode 77, such as an anode electrode, can be located outside the first DBR stack 75 and is arranged to contact the conductive layer 67 or the regrown semiconductor layer. After patterning the ODR layer 73 to form an opening of the ODR layer 73, the second electrode 79, such as a cathode electrode, can be located outside the mesa structure 69. The opening of the ODR layer 73 allows the second electrode 79 to be arranged to contact the etched n-type III-nitride face 69a of the III-nitride region 25.

[0067] Reference Figure 3R , a second DBR mirror stack 81 is formed on the curved surface 41c of the oxide substrate 42. If necessary, the second DBR mirror stack 81 may be patterned to expose a portion of the back side 41d of the oxide substrate 42, and then a bonding material such as a solder ball may be formed on the exposed back side 41d of the oxide substrate 42.

[0068] These processes complete a VCSEL, such as VCSEL 11. This structure allows the VCSEL 11 thus manufactured to be bonded to a submount on the curved DBR side using solder bumps.

[0069] Figure 4A is a schematic perspective view showing one chip portion including the template plug 18 , the curved surface 41 c as a lens structure, and the aperture structure 65 in the mesa structure 69 . Figure 4B is a plan view showing two chip portions on an oxide substrate 42 to which the above-described manufacturing process has been applied.

[0070] In the above-mentioned manufacturing method, the oxide substrate thus manufactured is separated into VCSEL chips by a separation process such as cutting and / or etching. Please note that the oxide substrate of the present invention is provided with an arrangement of mesa structures and cutting roads extending between adjacent mesa structures. The cutting roads of the present product thus manufactured do not include semiconductor structures. The omnidirectional filter layer covers the top surface of the oxide substrate except the top of the mesa structure, and can be removed at the cutting road by photolithography and etching if necessary. Since the second DBR stack can be patterned to be located on and around the curved surface 41c, no material covers the cutting road at the back side of the oxide substrate.

[0071] In the VCSEL 11 manufactured in this way, the length of the extended optical cavity CAV may be greater than 50 micrometers (>50 micrometers). The curved surface 41c has a radius of curvature greater than 50 micrometers (>50 micrometers).

[0072] In the VCSEL 11, the first DBR mirror 13 is planar, the second DBR mirror 19 is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 is greater than 50 micrometers. The thickness of the semiconductor portion 15 is greater than 0.5 micrometers.

[0073] exist Figure 4A and Figure 4B , a hemispherical circle 44 is drawn to show a virtual sphere extending along the curved surface 41c. For example, when the radius of curvature R0 of the curved mirror 21c is about 100 microns, the hemispherical circle 44 has a diameter "DIA" of 200 microns on the top surface 21a.

[0074] The spacing between adjacent template plugs 18 is related to the fill rate, which represents the ratio of the total area of ​​the device portion on a single wafer to the top area of ​​the wafer. The dicing streets define the arrangement of chip areas, each of which is prepared for a single VCSEL device. The template plugs 18 can be arranged periodically in one direction, or can be long microstrips spanning the entire wafer, or can be microstrips that terminate longitudinally within a single chip size, or can be terminated strips arranged in a checkerboard pattern and, if desired, staggered at their ends to obtain an increased benefit, namely reduced edge effects.

[0075] The arrangement of the template plug 18 is associated with the location of the scribe line. Due to the ELO, the semiconductor parts grown from the template plug cannot be made very large, and the ELO of the semiconductor parts is terminated before they reach the adjacent parts.

[0076] Preferably, the size of the semiconductor portion should be wider than the size of the designed hole portion of the aperture structure and smaller than the size of the period of arrangement of the template plugs 18 .

[0077] Preferably, the scribe line should exclude the III-nitride material to be diced. The slicing of the oxide substrate can be performed at the scribe line by a dicing blade, laser scribing and / or plasma etching. One of the benefits of excluding the III-nitride material in the scribe line is that the semiconductor layer can be avoided from being wasted.

[0078] The conductive hole portion of the aperture structure can be placed near the edge of a wing-shaped semiconductor island that is grown outward from a template plug by ELO. The device has the advantage of accommodating electrical pads on the chip surface and reducing crystal defects or irregularities that may be contained in the area immediately adjacent to the template plug. Another benefit is the separation of the aperture structure from a reference plane that extends perpendicular to the top surface of the oxide substrate at the center of the template plug, thereby eliminating optical losses.

[0079] Narrower scribe lines allow more device components to be placed on a single wafer.

[0080] Figures 5 to 7 Schematic diagrams showing exemplary arrangements of device parts on a TO substrate. Figures 5 to 7 , shows a typical arrangement of device parts on a TO substrate. The device parts are arranged to form a two-dimensional array, and the dicing lanes D extend to define the array. Figure 5 and Figure 6 In the embodiment, the hemispherical circles 44 are separated from each other. Figure 7 In FIG. 4 , the hemispherical circles 44 partially overlap, while the curved surfaces 21 are separated from each other. The boundary of the device portion 46 is depicted by a dotted line.

[0081] A person skilled in the art may appreciate various modifications from the above arrangement, such as a filled or less filled version of the arrangement of the VCSEL device portion.

[0082] Figure 8 Schematic diagram of a VCSEL according to an embodiment of the present invention. The VCSEL 11 is provided with a conductive layer 35 and an aperture structure 39 for confining carriers and laser light. The conductive layer 35 forms an electrical path from the first electrode 31 located beside the first DBR mirror 13 to a conductive aperture portion 39a of the aperture structure 39, wherein the conductive aperture portion 39a is located directly below the first DBR mirror 13 to be aligned with the cavity.

[0083] A description will be given of an exemplary process flow in a method for manufacturing the VCSEL 11 including a conductive layer serving as a current spreading layer.

[0084] The method comprises the following steps. 1. Prepare a starting substrate, wherein the preparation of the starting substrate includes forming a GaN template plug, which extends straight on the TO wafer along a second axial direction Ax2 perpendicular to the first axial direction Ax1; forming a dielectric Fabry-Perot filter structure on the entire TO wafer, wherein the side wall of the template plug is partially exposed and the top surface of the template plug is completely exposed. 2. Using ELO, an unintentionally doped GaN layer (n-GaN) is grown from the exposed GaN of the template plug along the top surface of the Fabry-Perot filter structure to form a semiconductor base region having a total width of approximately 30 to 50 microns in a third axial direction Ax3 perpendicular to the first and second axial directions Ax1 and Ax2. 3. Planarize the semiconductor base region to form a planarized n-GaN layer. 4. Growing a semiconductor stack on the planarized n-GaN layer, the semiconductor stack including device layers such as n-GaN for cladding and n-contact, InGaN multiple quantum wells, AlGaN electron blocking layer and p-GaN layer, and if necessary, p ++ GaN layer. 5. Polishing of TO wafer backside. 6. The resist pattern formed by reflow is transferred to the back side of the TO wafer by reactive ion etching to form a monolithic microlens. 7. A resist mask is produced from a resist film covering the device layer by backside exposure, in which a monolithic microlens is used to focus the exposure light at a focal point located around the resist film. 8. Use a resist mask to form a mask on the device layer. 9. Ion implantation is performed using a mask to define the aperture structure. 10. Deposition of transparent conductive oxide (TCO). 11. Fabricate mesa structures in semiconductor stacks. 12. Deposit a passivation film of omnidirectional reflector (ODR) material with openings on top of the mesa structures. 13. Deposit a dielectric distributed Bragg reflector stack on top of the flat top of the device layer of the mesa structure. 14. Depositing electrode metal pads on the semiconductor stack including the mesa structure. 15. Deposit a dielectric distributed Bragg reflector stack on the curved surface of the TO substrate. 16. Place bonding material on the back side of the TO substrate. 17. The TO wafer thus fabricated is separated to form VCSEL chips. 18. Bond the VCSEL chip to the substrate.

[0085] VCSEL chips can be used for user-defined applications such as light sources, sensors, or both.

[0086] Fig. 9 Schematic diagram of a VCSEL of another embodiment of the present invention. VCSEL 11a is provided with a tunnel junction structure 36 and an aperture structure 39. Tunnel junction 36 forms a circuit line from the first electrode 31 located next to the first DBR mirror 13 to the conductive hole portion 39a, and the conductive hole portion 39a is located directly below the first DBR mirror 13 and confines carriers and laser light. The tunnel junction structure 36 includes a p-type conductive hole in the aperture structure 39. ++ The group III nitride layer 36a and the n-type layer 36 on the mesa structure 36 ++ The group III nitride layer 36b, and p ++ The group III nitride layers 36a and 36n ++ The III-nitride layers 36b contact each other to form a tunnel junction. The tunnel junction is embedded by an additional III-nitride layer 36c.

[0087] An exemplary process flow of a method for manufacturing a VCSEL 11a including a heavily doped n ++ layer and an n-type semiconductor layer used as a current spreading layer. ++ The semiconductor layer and the top p ++ The semiconductor layers contact to form a tunnel junction 36 .

[0088] The method comprises the following steps. 1. Prepare a starting substrate, wherein the preparation of the starting substrate includes forming a GaN template plug, which extends straight on the TO wafer along a second axial direction Ax2 perpendicular to the first axial direction Ax1; forming a dielectric Fabry-Perot filter structure on the entire TO wafer, wherein the side wall of the template plug is partially exposed and the top surface of the template plug is completely exposed. 2. Using ELO, an unintentionally doped GaN layer (n-GaN) is grown from the exposed GaN of the template plug along the top surface of the Fabry-Perot filter structure to form a semiconductor base region having a total width of approximately 30 to 50 microns in a third axial direction Ax3 perpendicular to the first and second axial directions Ax1 and Ax2. 3. Planarize the semiconductor base region to form a planarized n-GaN layer. 4. Growing a semiconductor stack on the planarized n-GaN layer, the semiconductor stack including device layers, such as n-GaN for cladding and n-contact, InGaN multiple quantum wells, AlGaN electron blocking layer, p-GaN layer and p ++ GaN layer. 5. Polishing of TO wafer backside. 6. The resist pattern formed by reflow is transferred to the back side of the TO wafer by reactive ion etching to form a monolithic microlens. 7. A resist mask is made on the device layer by backside exposure, where a monolithic microlens is used to focus the exposure light at a focal point located around the resist film. 8. Use a resist mask to form a mask on the device layer. 9. Ion implantation is performed using a mask to define the aperture structure. 10. After the aperture structure is formed, re-grow n ++ GaN layer to complete the tunnel junction and ++ An n-GaN layer is further deposited on the GaN layer for contact and current spreading. 11. Produce a mesa structure from a semiconductor stack including device layers and tunnel junctions. 12. Deposit a passivation film of omnidirectional reflector (ODR) material with openings for contact areas on the top surface of the mesa structures. 13. Deposit a dielectric distributed Bragg reflector stack on top of the flattened device layer. 14. Depositing electrode metal pads on the semiconductor stack including the mesa structure. 15. Deposit a dielectric distributed Bragg reflector stack on the curved surface of the TO substrate. 16. Place bonding material on the back of the TO wafer. 17. The TO wafer thus fabricated is separated to form VCSEL chips. 18. Bond the VCSEL chip to the substrate.

[0089] VCSEL chips can be used for user-defined applications such as light sources, sensors, or both.

[0090] Fig.10 Schematic diagram of a VCSEL according to another embodiment of the present invention. VCSEL 11b is equipped with a buried tunnel junction structure 38 without an aperture structure 39. The buried tunnel junction 38 is located directly below the first DBR mirror 13, aligned with the cavity, and covered with a current spreading layer, thereby limiting the electrical path from the first electrode 31 adjacent to the first DBR mirror 13 to the buried tunnel junction 38, and the buried tunnel junction 38 is used to confine carriers and lasers.

[0091] An exemplary process flow in a method of manufacturing a VCSEL 11b will be described. The method includes a method of manufacturing a VCSEL having a heavily doped n ++ and p ++ The buried tunnel junction structure 38 includes a patterned p-type semiconductor layer disposed on the mesa structure 36.++ The III-nitride layer 38a and the patterned n ++ Group III nitride layer 38b. ++ The group III nitride layers 38a and n ++ The III-nitride layers 38b are in contact with each other to form a tunnel interface and are embedded by an additional III-nitride layer 38c. The additional III-nitride layer 38c is grown on the mesa structure 37 to form a substantially planarized top surface thereof. The first electrode 31 is disposed in contact with the III-nitride layer 38c, and the first DBR mirror 13 is disposed on top of the III-nitride layer 38c.

[0092] The method comprises the following steps. 1. Prepare a starting substrate, wherein the preparation of the starting substrate includes forming a GaN template plug, which extends straight on the TO wafer along a second axial direction Ax2 perpendicular to the first axial direction Ax1; forming a dielectric Fabry-Perot filter structure on the entire TO wafer, wherein the side wall of the template plug is partially exposed and the top surface of the template plug is completely exposed. 2. Using ELO, an unintentionally doped GaN layer (n-GaN) is grown from the exposed GaN of the template plug along the top surface of the Fabry-Perot filter structure to form a semiconductor base region having a total width of approximately 30 to 50 microns in a third axial direction Ax3 perpendicular to the first and second axial directions Ax1 and Ax2. 3. Planarize the semiconductor base region to form a planarized n-GaN layer. 4. Growing a semiconductor stack on the planarized n-GaN layer, the semiconductor stack including device layers, such as n-GaN for cladding and n-contact, InGaN multiple quantum wells, AlGaN electron blocking layer, p-GaN layer and p ++ GaN layer. 5. Polishing of TO wafer backside. 6. The resist pattern formed by reflow is transferred to the back side of the TO wafer by reactive ion etching to form a monolithic microlens. 7. In p ++ The GaN layer is regrown with n ++ GaN layer to complete the tunnel junction. 8. A resist mask is produced from the resist film on the device layer by backside exposure, in which a monolithic microlens is used to focus the exposure light at a focal point located around the resist film. 9. Pattern the tunnel junction using a resist mask to complete the buried tunnel junction on the device layer. 10. After forming the buried tunnel junction, deposit an n-GaN layer covering the buried tunnel junction to form a planarized n-GaN top surface. 11. Producing mesa structures from semiconductor stacks. 12. Deposit a passivation film of omnidirectional reflector (ODR) material with openings for contact areas on the mesa structures. 13. Deposit a dielectric distributed Bragg reflector stack on top of the flattened device layer. 14. Depositing electrode metal pads on the semiconductor stack including the mesa structure. 15. Deposit a dielectric distributed Bragg reflector stack on the curved surface of the TO substrate. 16. Place bonding material on the back of the TO wafer. 17. The TO wafer thus fabricated is separated to form VCSEL chips. 18. Bond the VCSEL chip to the substrate.

[0093] VCSEL chips can be used for user-defined applications such as light sources, sensors, or both.

[0094] In addition, the production of semiconductor chips in the background art certainly includes growing epitaxial device layers on a wafer, and cutting the device layers and the wafer. The cutting and chip singulation area may require at least 10% of the processing area of ​​the wafer.

[0095] There may be three methods of manufacturing a semiconductor chip, such as an extended cavity VCSEL.

[0096] Method 1 First, the entire device layer is epitaxially grown on a flat GaN substrate. After growth, the GaN substrate is thinned by polishing its backside, and then a curved surface for an optical cavity, such as a microlens, is formed on the polished backside.

[0097] Method 2 First, the entire device layer is epitaxially grown on a planar GaN substrate. After growth, the GaN substrate is removed to form a device stack including the device layer, and then the device stack is bonded to a foreign substrate with a curved surface on its back side for an optical cavity, such as a microlens.

[0098] Method 3 Method 3 includes a manufacturing process according to the present disclosure. Compared with methods 1 and 2, the integration of the extended cavity in method 3 is a simple one-step process without removing and thinning the substrate. The dicing lanes can be arranged between semiconductor parts. The manufacturing process according to the present disclosure allows various arrangements of device parts, such as high packaging density of device parts on a wafer.

[0099] Example

[0100] Transparent Oxide (TO) Substrate Materials The microlens is integrated with the device layer on the TO substrate. The device layer is also grown on the TO substrate. The material of the TO substrate can include ZnO, Ga 2 O 3 , Al 2 O 3 and other materials transparent to infrared, visible, near-ultraviolet and / or deep-ultraviolet wavelengths, depending on the material. A VCSEL device according to the present structure is equipped with a cavity dominated by a less absorbing TO substrate. This enables the manufacture of VCSEL devices to use large-size TO wafers, such as sapphire wafers with a size of more than 6 inches, thereby producing more devices at a single time.

[0101] Template plug First, a III-nitride template plug is installed on the TO wafer, and the height of the III-nitride template plug can be 1 micron to 10 microns. The crystalline quality of the III-nitride layer used for the template plug increases with its thickness. Increasing the thickness of the III-nitride layer can terminate the threading dislocations therein, which originate from the lattice mismatch at the substrate interface. In addition, the larger thickness can provide a thicker Fabry-Perot filter structure for the dielectric filter layer, which helps to characterize and form a very narrow bandpass and a better suppression area outside the bandpass. The thicker Fabry-Perot filter is embedded in the lower sidewall portion of the template plug, where most defects may include.

[0102] For example, the template plugs may be in the form of strips parallel to the <11-20> axis of a hexagonal III-nitride (e.g., GaN). In forming the template plugs, etching the III-nitride film with a (0001) polarity orientation of the III-nitride film may provide template plug strips formed therefrom with (11-22) sidewalls. Such sidewall orientation may enhance subsequent lateral growth. If desired, the III-nitride template plug sidewalls may be provided with another orientation that would enhance lateral growth. Alternatively, the template plug may be provided with a desired orientation that allows for enhanced growth of the III-nitride layer along the dielectric filter layer.

[0103] Fabry-Perot Filters / Anti-Reflection One of the ideal designs for producing narrow bandpass filters is the use of a Fabry-Perot filter structure. A Fabry-Perot filter provides a narrow passband and stopbands on either side of the passband. A Fabry-Perot filter can be set up in a single laser cavity and includes a central spacer with a certain thickness, generally half the laser wavelength, and two identical mirrors, the same as the DBR mirror structure, sandwiched between the central spacer.

[0104] A typical all-dielectric structure is as follows: "Substrate 1 / (HL)m / 2nH / (LH)m / Substrate 2". Substrate 1 and Substrate 2 can be a GaN layer and a TO substrate, i.e., sapphire, respectively. "H" and "L" represent layers with high and low refractive indices, respectively, and their quarter-wavelength optical thicknesses, and "m" and "n" are integers. The overall thickness of the entire structure at an exemplary operating wavelength of 450 nm can be in the range of 1 to 2 microns or even thicker. The Fabry-Perot structure in an optimized design allows for very narrow bandpasses, for example, around the central operating wavelength The optical window "WIN" can have a thickness of more than 2 microns. The "WIN" can be further reduced by increasing the number of dielectric layers and fine-tuning the thickness of each layer. The Fabry-Perot structure can have a surface roughness of less than 1 nanometer, preferably, the roughness can be 0.1 to 1 nanometer root mean square (RMS). The dielectric layer of the Fabry-Perot structure can be deposited by sputtering, atomic layer deposition, ion beam deposition and the like. The Fabry-Perot filter includes two reflectors and a central layer of a high refractive index material. Each of the two reflectors includes alternating deposition of high refractive index material and low refractive index material, such as SiO 2 and HfO 5 , each material has a thickness of one quarter wavelength. A central layer of high refractive index material has a thickness of half the central operating wavelength and is disposed between these reflectors.

[0105] Epitaxial lateral overgrowth The III-nitride template plug arranged on the TO substrate can be formed into a strip shape, and the lower side wall of the template plug is embedded with a Fabry-Perot filter structure, which is made of materials such as SiO2, Ta2O5, HfO 5 The template plug is made of all-dielectric materials such as FETs, and the top surface defects of the template plug are relatively few. Preferably, the thickness of the plug is designed to enable a thick Fabry-Perot filter, which produces a very narrow bandpass extension "WIN". The sidewalls of the plug are exposed by about 1 or 2 microns, and the top surface width of the plug is about 1 to 10 microns. The strips are arranged at a period of 50 to 200 microns. The length of the strip can match the length of the device portion or can be longer. The polar template plug is equipped with a top surface orientation of the c-plane (0001), so the strips of the template plug can be oriented along the <11-20> axis. Alternatively, the non-polar template plug is provided with a top surface orientation of the a-plane (11-20) or the m-plane (1100), so the strips of the template plug are along <0001> Axis orientation. Further, the semi-polar template plug has a top surface orientation of the (20-21) or (20-2-1) plane, and correspondingly, the strips of the template plug are oriented along the direction parallel to [-1014] or [10-14], respectively. Other orientations can also be used, in which the strips are oriented in the corresponding directions.

[0106] A TO wafer with a template plug installed with partially exposed sidewalls is loaded into a MOCVD reactor to grow a III-nitride island. In one embodiment, the growth pressure ranges from 50 to 760 Torr, although the growth pressure preferably ranges from 100 to 300 Torr to provide an island-shaped III-nitride semiconductor layer with a large width; the growth temperature ranges from 900 to 1200 degrees Celsius; the V / III ratio ranges from 10 to 30,000; the TMG flow rate ranges from 2 to 20 standard cubic centimeters per minute (sccm); the NH3 flow rate ranges from 0.1 to 10 standard liters per minute (slm); and only hydrogen or hydrogen and nitrogen are used as carrier gases. In order to obtain a smooth surface, the growth conditions of the III-nitride island can be optimized. Finally, a III-nitride layer, such as a GaN layer 25, is grown by ELO to complete each island so that the GaN layer 25 has a thickness of about 1 to 10 microns and a width of 50 microns, and the III-nitride islands so grown are spaced about 15 microns from each other.

[0107] The TO wafer with the template plug sidewall partially exposed has a III-nitride interface (exposed template plug) and a dielectric interface (Fabry-Perot filter layer) on its top, and the ratio of these two interfaces is the "filling factor". In the reactor, III-nitride can be deposited on the III-nitride interface but not on the dielectric interface, which is expressed by the "filling factor". In current TO wafers, the filling factor is lower than 1. Deposition with a filling factor deviating from 1 may cause the III-nitride atoms in the reactor to gather more at the edge of the growth surface. This is because there are a large number of III-nitride atoms around the boundary between the growth and non-growth interfaces. Therefore, the edge of the III-nitride island may produce a thicker GaN layer compared to the central area.

[0108] Polishing Due to the abundance of III-nitride atoms, the III-nitride islands grown from each template plug can have a concave shape on their top. In order to obtain a flat device layer, the III-nitride islands are first grown to a thickness of 5 to 10 microns and then flattened by polishing or etching to form a III-nitride substrate with a flat top surface. On this flat top surface, the device layer including p-GaN, n-GaN, InGaN and AlGaN layers is regrown. Specifically, since the thickness of the device layer and / or tunnel junction layer including n-GaN, MQW and p-GaN may not exceed 700nm in total, the edge growth caused by the abundant III-nitride atoms may be negligibly small in this re-growth.

[0109] Device layer growth The III-nitride-based semiconductor layer and the tunnel junction or buried tunnel junction layer are regrown on the polished surface of the III-nitride substrate. The semiconductor stack and the semiconductor portion 15 both include semiconductor device layers of III-nitride compounds, which may include In, Al and / or B and dopants or impurities such as Mg, Si, Zn, O, C and H. The device layer of the III-nitride-based semiconductor generally includes more than three layers, including an n-type layer, an undoped layer and a p-type layer. The device layer specifically includes gallium nitride-based materials such as GaN layers, AlGaN layers, InGaN layers and AlGaInN layers. For example, the epitaxial growth of these device layers is carried out in an MOCVD or MBE reactor. The device region includes a thick n-GaN layer, multiple quantum wells (e.g., MQWs with 3 nm thick wells and 7 nm thick barriers), a 10 nm thick p-AlGaN electron blocking layer (EBL), a 100 nm thick p-GaN layer and a 10 nm thick p-AlGaN layer. ++ GaN layer.

[0110] When ITO is used as the current spreading layer, the top device layer can be p ++ GaN. In addition, in p ++ An additional 10nm thick n ++ For buried tunnel junction and tunnel junction designs, a 50nm thick n-GaN current spreading layer is deposited on top of the additional n ++ On the GaN layer.

[0111] Specifically, in the tunnel junction design, when growing p ++ The growth of the semiconductor stack is stopped after the GaN layer, and then ion implantation is performed to form an aperture structure, followed by n ++ A GaN layer and an n-type GaN layer are deposited on the aperture structure.

[0112] Specifically, in the buried tunnel junction design, the p ++ The GaN layer is grown on top of the ++ After the GaN layer, the growth of the semiconductor stack is stopped, and then the n ++ GaN and p ++ The GaN layer is patterned to form a patterned tunnel junction, and then an n-type GaN layer is deposited on the patterned tunnel junction. Regrowth can be performed using either MOCVD or MBE (Molecular Beam Epitaxy) reactors. Using MBE instead of MOCVD eliminates hydrogen repassivation of p-GaN during tunnel junction regeneration.

[0113] Alternatively, the present design described in the embodiments may include processing the island III-nitride device layer. To restore hydrogen repassivation, the p-type gallium nitride substrate material, such as p-GaN, may be activated by lateral diffusion and the p-GaN layer embedded with the tunnel junction or current spreading layer (n-GaN) may be activated. Thus, the design of a particular device layer may select MBE or MOCVD based on manufacturing parameters such as cost and yield.

[0114] Microlens formation The monolithic microlens is used in the aperture manufacturing process. Specifically, the monolithic lens on the back focuses the exposure light at the position of the aperture structure through the lens effect of the curved surface, which is used to form the curved second DBR mirror in the VCSEL product.

[0115] The TO substrate can be a double-sided polished substrate, so the microlens pattern on the back side is positioned so that the final position and shape of the lens can be used to accurately align with the position of the aperture portion on the top surface of the semiconductor portion. The monolithic microlens is manufactured by a photoresist (PR) reflow and dry etching process. For example, the double-sided polished sapphire substrate can be a 2-inch wafer with a (0001) orientation, and if possible, a larger diameter wafer can also be used. Specifically, a row of circular PR disks are patterned on the back side of the polished sapphire substrate by standard photolithography. The PR pattern is then baked at high temperature using a hot plate. After reaching the PR transition temperature, the PR pattern begins to reflow, forming a convex shape, with the center of each pattern being the thickest. Then, the convex shape is transferred to the sapphire substrate, for example, using an inductively coupled plasma (ICP) system. Optimized etching conditions can achieve a surface roughness of less than 1 nanometer, and preferably, the etched surface of the sapphire can have a surface roughness between 0.1 nanometers and 0.5 nanometers to avoid optical scattering and corresponding optical losses.

[0116] Ion implantation Ion implantation is used to form electrical and optical apertures in the GaN substrate by damaging these GaN substrates outside the apertures, and the damaged GaN substrate material is no longer conductive. This method can keep the top surface flat and can produce very slight refractive index guidance between the aperture area and the damaged area. The absorption value of the damaged area may be higher than the absorption value of the non-implanted material in the aperture area, but it will cause increased optical losses in the cavity. Heavy ions such as aluminum (Al), boron (B), etc. can be used in the ion implantation process. The basic idea of ​​ion implantation is to create a conductive hole.

[0117] Transparent conductive layer After ion implantation, a transparent conductive layer can be stacked on the device layer, or a III-nitride regrowth for a tunnel junction can be performed on the device layer with or without an ion implantation process. ITO can be used as a commonly used transparent current spreading layer. The inclusion of ITO in VCSELs may result in additional absorption, but this absorption can be reduced by reducing the intensity of electromagnetic waves around the ITO layer. Alternative methods (such as tunnel junctions) can also be used to spread the current and reduce light absorption.

[0118] Tunnel knot The tunnel junction method allows hole carriers to be injected into the active layer of the device through the n-type semiconductor. This is because the junction between the highly doped n-type region and the highly doped p-type region allows electrons to tunnel from the valence band of the p-type region to the conduction band of the n-type region under reverse bias, thereby causing a change in the type of conductive carriers. Since the tunneling probability is exponentially related to the tunneling distance, the highly doped region (~10 19 / cm 3 or more) to produce a thin depletion width, thereby achieving efficient operation. After the aperture structure is formed by ion implantation, the top p ++ The epitaxial growth of GaN layer ++ / n-GaN layer (thickness is 10 / 50nm) to form a tunnel junction and current spreading layer.

[0119] Buried Tunnel Junction: The buried tunnel junction can be used as both a carrier-type converter and a current aperture. ++ / n ++ The buried tunnel junction is formed by forming a planar tunnel junction of a layer (thickness of 10 / 10nm); using a microlens of a TO substrate to form a mask on the high-doped junction layer at the desired aperture position; etching the high-doped junction layer using the mask. The buried tunnel junction is not always combined with a current aperture formed by ion implantation, and can be combined with a current aperture if necessary.

[0120] DBR mirror The DBR mirrors of the present invention each include alternating dielectric layers bonded together to form a reflector and are disposed at the top and bottom of the VCSEL to form an optical cavity. The dielectric DBR mirror may include, for example, a quarter-wavelength thick dielectric SiO 2 / Ta 2 O 5 The number of DBR mirror pairs is related to their reflectivity, and the reflectivity of the DBR mirror located on the VCSELp side may be smaller than the reflectivity of the DBR mirror located on the curved surface to promote light emission.

[0121] Omnidirectional Reflector (ODR): The ODR is arranged outside the optical cavity and can reflect the light leaked from the propagation path. The ODR is also arranged between the anode electrode and the cathode electrode and plays a role in protecting and / or passivating the device layer from possible contaminants and direct contact.

[0122] Metal pad In the manufacture of VCSEL, gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), titanium (Ti), indium (In) and other metals can be used as the material of the metal pad. The metal layer can be formed by sputtering, evaporation or electroplating.

[0123] application

[0124] Data Center As cloud computing and streaming services increase, the demand for data communications has increased the need for information transmission hardware, such as edge-emitting lasers and VCSELs, which provide server data transmission for servers in data centers. In most data communications, VCSELs operate at infrared (IR) wavelengths. The III-nitride VCSELs according to the aforementioned embodiments can be used for data communications associated with data centers.

[0125] illumination: GaN-based light sources such as LEDs have enabled a dramatic shift in residential and automotive lighting. The combination of lighting and communication services is highly desirable in future smart cities and smart infrastructure. VCSELs may be a better alternative to LEDs and edge-emitting laser diodes. The procedures developed in the preceding examples can be used to fabricate VCSEL units suitable for lighting applications.

[0126] Visible Light Communication Lasers can be used for data transmission and communication applications through Light Fidelity (LiFi). With the rapid increase in Internet of Things (IoT) devices, the demand for data transmission continues to expand. The radio frequency spectrum is becoming saturated and new frequencies are needed to meet the growing demand. It is simpler to adopt GaN-based VCSELs into existing LED architectures than to replace them with edge-emitting lasers. The III-nitride VCSEL according to the above embodiment can be applied in visible light communication.

[0127] Near Eye Display Near-eye displays will represent the next major wave of consumer electronics and are the basis of virtual reality (VR) and augmented reality (AR) technologies. Currently, micro-LEDs are the main choice for displays, however, despite the current limited progress in VCSEL research, VCSELs may be introduced as micro-displays and near-eye displays. VCSELs can provide relatively low optical power, which is beneficial for maintaining eye safety, and the low divergence and circular symmetry can reduce the number of additional optical elements, making the device compact. 2D array integration of VCSELs is simpler than edge-emitting lasers. The III-nitride VCSELs according to the aforementioned embodiments can be used in these applications.

[0128] The beneficial effects of the above embodiments are as follows: Using a cavity long enough without excessive diffraction losses, two mirrors define the VCSEL cavity, and a Fabry-Perot filter is added to narrow the single-mode operation range; Better thermal management due to sufficiently long cavities and / or electrical contacts on the III-nitride layer; The GaN template plug connected to the TO substrate provides better thermal conductivity for the device, thus improving thermal performance; Use low-cost, large-scale template substrates, such as GaN on sapphire; Minimize semiconductor layer waste by using island-shaped III-nitrides; Eliminate substrate removal and bonding steps in the manufacturing process, thereby improving production parameters; and Unlocking the use of heterogeneous substrates in VCSELs production using ELO technology; The above-described embodiments are expected to significantly improve performance, reduce manufacturing costs, and eliminate complex procedures. The above-mentioned embodiments propose to integrate a Fabry-Perot filter into a VCSEL, which enables epitaxial lateral overgrowth to improve the crystal quality of the device layer. Using a template TO material substrate containing a GaN / sapphire structure similar to that of GaN allows the device layers to be grown on the wings of epitaxial lateral overgrowth, which generally provides no or few defects, resulting in high crystalline quality.

[0129] Aspect 1 The VCSEL includes: an oxide substrate having a first surface and a second surface located on the opposite side of the first surface, the second surface including a curved surface; a semiconductor portion disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first surface of the oxide substrate and having a reflection spectrum, the reflection spectrum being configured to provide an optical window; a first distributed Bragg reflector (DBR) mirror, the semiconductor portion being disposed between the dielectric filter layer and the first DBR mirror; and a second DBR mirror disposed at the curved surface of the oxide substrate, the first DBR mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate, and the second DBR mirror being arranged along a first axial direction to form an extended cavity, the semiconductor portion including a p-type III-nitride region, a III-nitride region, and a III-nitride active region located between the p-type III-nitride region and the III-nitride region, the p-type III-nitride region, the III-nitride active region, and the III-nitride region being arranged along the first axial direction, and the III-nitride region including an n-type III-nitride region.

[0130] Aspect 2 In the VCSEL according to aspect 1, the dielectric filter layer has a through hole extending along the first axial direction. The VCSEL further includes a III-nitride template plug disposed in the through hole and extending from the first face of the oxide substrate to the semiconductor portion in the through hole.

[0131] Aspect 3 In the VCSEL according to aspect 2, the III-nitride template plug includes an embedded portion in the through hole and a protruding portion protruding into the semiconductor portion, and the embedded portion of the III-nitride template plug is provided in contact with the first face of the oxide substrate.

[0132] Aspect 4 In the VCSEL according to any one of aspects 1 to 3, the curved surface of the oxide substrate has a center line, and the center lines of the III-nitride template plug and the curved surface are not aligned with each other.

[0133] Aspect 5 In the VCSEL according to any one of aspects 1 to 4, the length of the extended cavity is greater than 50 micrometers.

[0134] Aspect 6 In the VCSEL according to any one of aspects 1 to 5, the curved surface has a radius of curvature greater than 50 micrometers.

[0135] Aspect 7 In the VCSEL according to any one of aspects 1 to 6, the second DBR mirror is curved, and the first DBR mirror is planar, and a distance between the first DBR mirror and the second DBR mirror is greater than 50 micrometers.

[0136] Aspect 8 In the VCSEL according to any one of aspects 1 to 7, the semiconductor portion includes a mesa structure, and the mesa structure includes a base region and a mesa region disposed on the base region. The VCSEL further includes: a conductive layer disposed on the semiconductor portion, a portion of the conductive layer disposed between the first DBR mirror and the semiconductor portion; a first electrode disposed on the conductive layer outside the DBR mirror, the first electrode disposed in contact with the conductive layer; and a second electrode disposed at a surface of the base region of the mesa structure.

[0137] Aspect 9 In the VCSEL according to aspect 8, the semiconductor portion has a first face and a second face located on an opposite side of the first face of the semiconductor portion, the dielectric filter layer is provided at the first face of the semiconductor portion, and the conductive layer is provided at the second face of the semiconductor portion.

[0138] Aspect 10 In the VCSEL according to any one of aspects 1 to 9, the semiconductor portion includes an aperture structure, the aperture structure including an aperture region extending along a first axial direction, and an isolation region surrounding the aperture region, and the first DBR mirror, the aperture region, and the second DBR mirror are arranged along an axis that does not pass through the III-nitride template plug.

[0139] Aspect 11 In the VCSEL according to any one of aspects 1 to 10, the total thickness of the semiconductor portion is greater than 0.5 micrometer.

[0140] Aspect 12 In the VCSEL according to any one of aspects 1 to 11, the dielectric filter layer comprises a Fabry-Perot filter configured to provide a reflection spectrum to the optical window.

[0141] Aspect 13 In the VCSEL according to any one of aspects 1 to 12, the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

[0142] Aspect 14 In the VCSEL according to any one of aspects 1 to 13, the first DBR mirror has a reflectivity lower than a reflectivity of the second DBR mirror.

[0143] Aspect 15 In the VCSEL according to any one of aspects 1 to 14, the III-nitride active region includes a quantum well structure configured to generate light having a first reflection spectrum of the first DBR mirror, a second reflection spectrum of the second DBR mirror, and a wavelength in the optical window of the dielectric filter layer.

[0144] Aspect 16 A method for manufacturing a VCSEL includes: preparing a starting substrate, the starting substrate including an oxide substrate, a III-nitride template plug and a dielectric filter layer, the oxide substrate having a first surface and a second surface located on the opposite side of the first surface of the oxide substrate, the dielectric filter layer and the III-nitride template plug are located on the first surface of the oxide substrate, the dielectric filter layer has a reflection spectrum, and the reflection spectrum is configured to provide an optical window; growing a III-nitride region from the III-nitride template plug on the dielectric filter layer; after growing the III-nitride region, growing a semiconductor stack including an n-type III-nitride region, a III-nitride active region and a p-type III-nitride region; processing the oxide substrate at the second surface of the oxide substrate to form an oxide substrate having a curved surface, the curved surface being located on the opposite side of the first surface of the oxide substrate; after growing the semiconductor stack, forming a first distributed Bragg reflector (DBR) stack on the first surface of the oxide substrate; and forming a second DBR stack on the curved surface of the oxide substrate.

[0145] Aspect 17 The method according to aspect 16 further includes planarizing the Group III nitride region by at least one of polishing or etching prior to growing the semiconductor stack.

[0146] Aspect 18 The method according to clause 16 or 17 further comprises: depositing a conductive layer on the first side of the oxide substrate after growing the semiconductor stack and before forming the first DBR stack; and forming a first electrode on the conductive layer.

[0147] Aspect 19 The method according to any one of aspects 16 to 18, further comprising: generating a mesa structure from the semiconductor stack by etching to form an etched surface of the n-type group III-nitride region, the mesa structure comprising the group III-nitride active region;

[0148] Aspect 20 The method according to aspect 19 further includes forming a second electrode on the etched surface of the n-type III-nitride region outside the mesa structure.

[0149] Aspect 21 In the method according to any one of aspects 16 to 20, the semiconductor stack further comprises one of a tunnel junction or a buried tunnel junction.

[0150] Aspect 22 In the method according to any one of aspects 16 to 21, the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

[0151] Aspect 23 In the method according to any one of aspects 16 to 22, preparing a starting substrate includes: depositing a Group III nitride layer on a first surface of an oxide substrate; patterning the Group III nitride layer to form a Group III nitride template plug; depositing multiple dielectric layers to cover the first surface of the oxide substrate and the Group III nitride template plug; and processing the multiple layers to form a dielectric filter layer, so that the Group III nitride template plug is located in a through hole of the dielectric filter layer, and the height of the Group III nitride template plug is greater than the thickness of the dielectric filter layer.

[0152] Aspect 24 In the method according to clause 23, multiple dielectric layers are grown to form a Fabry-Perot filter configured to provide a reflective spectrum to the optical window.

[0153] Aspect 25 In the method according to any one of aspects 16 to 24, the III-nitride region is grown from the III-nitride template plug by epitaxial lateral overgrowth to form the III-nitride island.

[0154] Aspect 26 According to the method of clause 25, the III-nitride islands extend outward from the III-nitride template plug along a top surface of the dielectric filter layer, and the top surface of the dielectric filter layer has a roughness of less than 1 nanometer.

[0155] Aspect 27 In the method according to any one of aspects 16 to 26, a Group III nitride active region is grown to form a quantum well structure configured to generate light having a first reflection spectrum of the first DBR stack, a second reflection spectrum of the second DBR stack, and a wavelength in the optical window of the dielectric filter layer.

[0156] Aspect 28 According to the method of any one of aspects 16 to 27, the oxide substrate is processed at the second side of the oxide substrate to form an oxide substrate, including: forming a patterned resist layer on the second side of the oxide substrate; heat treating the patterned resist layer to form a raised resist area; and transferring the shape of the raised resist area to the oxide substrate by etching the raised resist area and the oxide substrate to form a curved surface. Etching the raised resist area and the oxide substrate is stopped to meet the condition that after forming the first DBR stack and the second DBR stack, the distance between the second DBR stack and the first DBR stack is greater than 50 microns.

[0157] Aspect 29 In the method according to any one of aspects 16 to 28, the curved surface has a radius of curvature greater than 50 microns.

[0158] Aspect 30 The method according to any one of aspects 16 to 29 also includes: forming a resist film on the first surface of the oxide substrate after growing the semiconductor laminate and before forming the conductive layer; irradiating the resist layer through the curved surface of the oxide substrate to produce a patterned mask from the resist film; and performing ion implantation using the patterned mask to form an aperture structure including an aperture region and an isolation region surrounding the aperture region.

[0159] Having described and illustrated the principle of the present invention in the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that the arrangement and details of the present invention may be modified without departing from these principles. Therefore, we require that all modifications and changes fall within the scope and revelation of the appended claims. Reference Mark List

[0160] 11, 11a, 11b, 11c VCSEL 13.19 Distributed Bragg reflector (DBR) 15 Semiconductor 17 Dielectric filter layer 23p-type III-nitride region 25n-type III-nitride region 27III-nitride active region CAV Optical Cavity 31 Anode electrode 33 Cathode electrode 35 Conductive layer 37 Table structure Ax1, Ax2, Ax3 Axial

Claims

1. Vertical Cavity Surface Emitting Laser (VCSEL), including: an oxide substrate having a first surface and a second surface located on an opposite side of the first surface, the second surface including a curved surface; a semiconductor portion, the semiconductor portion being disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first side of the oxide substrate, and having a reflection spectrum configured to provide an optical window; a first distributed Bragg reflector (DBR) mirror, the semiconductor portion being disposed between the dielectric filter layer and the first DBR mirror; and a second DBR mirror, the second DBR mirror being disposed on the curved surface of the oxide substrate, the first DBR mirror, the semiconductor portion, the dielectric filter layer, the oxide substrate and the second DBR mirror being arranged along a first axial direction to form an extended cavity, The semiconductor portion includes a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region located between the p-type Group III nitride region and the Group III nitride region, the p-type Group III nitride region, the Group III nitride active region, and the Group III nitride region are arranged along the first axial direction, and the Group III nitride region includes an n-type Group III nitride region.

2. The VCSEL according to claim 1, wherein: The dielectric filter layer has a through hole extending along the first axial direction, The VCSEL further includes a Group III-nitride template plug disposed in the through-hole and extending from the first side of the oxide substrate to the semiconductor portion in the through-hole.

3. The VCSEL according to claim 2, wherein: The III-nitride template plug includes an embedded portion located in the through hole and a protruding portion protruding into the semiconductor portion, and the embedded portion of the III-nitride template plug is disposed in contact with the first face of the oxide substrate.

4. The VCSEL according to any one of claims 1 to 3, wherein: The curved surface of the oxide substrate has a center line, and the III-nitride template plug and the center line of the curved surface are not aligned with each other.

5. The VCSEL according to any one of claims 1 to 3, wherein: The length of the expansion cavity is greater than 50 microns.

6. The VCSEL according to any one of claims 1 to 3, wherein: The curved surface has a radius of curvature greater than 50 microns.

7. The VCSEL according to any one of claims 1 to 3, wherein: The second DBR mirror is curved, the first DBR mirror is planar, and a distance between the first DBR mirror and the second DBR mirror is greater than 50 micrometers.

8. A VCSEL according to any one of claims 1 to 3, wherein: The semiconductor portion includes a mesa structure, and the mesa structure includes a base region and a mesa region disposed on the base region, The VCSEL further comprises: a conductive layer, the conductive layer being disposed on the semiconductor portion, and a portion of the conductive layer being disposed between the first DBR mirror and the semiconductor portion; a first electrode, the first electrode being disposed on the conductive layer outside the DBR mirror, the first electrode being disposed in contact with the conductive layer; and A second electrode is disposed at a surface of the base region of the mesa structure.

9. The VCSEL according to claim 8, wherein: The semiconductor portion has a first surface and a second surface located on an opposite side of the first surface of the semiconductor portion, the dielectric filter layer is disposed at the first surface of the semiconductor portion, and the conductive layer is disposed at the second surface of the semiconductor portion.

10. The VCSEL according to any one of claims 1 to 3, wherein: The semiconductor portion includes an aperture structure including an aperture region extending along the first axial direction and an isolation region surrounding the aperture region, and the first DBR mirror, the aperture region and the second DBR mirror are arranged along an axis that does not pass through the III-nitride template plug.

11. The VCSEL according to any one of claims 1 to 3, wherein: The total thickness of the semiconductor portion is greater than 0.5 micrometers.

12. The VCSEL according to any one of claims 1 to 3, wherein: The dielectric filter layer comprises a Fabry-Perot filter configured to provide the reflection spectrum to the optical window.

13. The VCSEL according to any one of claims 1 to 3, wherein: The oxide substrate includes one of aluminum oxide, zinc oxide or gallium oxide.

14. The VCSEL according to any one of claims 1 to 3, wherein: The first DBR mirror has a reflectivity lower than a reflectivity of the second DBR mirror.

15. The VCSEL according to any one of claims 1 to 3, wherein: The III-nitride active region includes a quantum well structure configured to generate light having a first reflection spectrum of the first DBR mirror, a second reflection spectrum of the second DBR mirror, and a wavelength in the optical window of the dielectric filter layer.

16. A method for manufacturing a vertical cavity surface emitting laser (VCSEL), the method comprising: Prepare a starting substrate, the starting substrate comprising an oxide substrate, a group III nitride template plug and a dielectric filter layer, the oxide substrate having a first surface and a second surface located on an opposite side of the first surface of the oxide substrate, the dielectric filter layer and the group III nitride template plug are located on the first surface of the oxide substrate, the dielectric filter layer has a reflection spectrum, and the reflection spectrum is configured to provide an optical window; growing a group III nitride region on the dielectric filter layer from the group III nitride template plug; After growing the Group III nitride region, growing a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region, and a p-type Group III nitride region; processing the oxide substrate at the second side of the oxide substrate to form an oxide substrate having a curved surface, the curved surface being located on an opposite side of the first side of the oxide substrate; After growing the semiconductor stack, forming a first distributed Bragg reflector (DBR) stack on the first surface of the oxide substrate; A second DBR stack is formed on the curved surface of the oxide substrate.

17. The method according to claim 16, further comprising: Prior to growing the semiconductor stack, the III-nitride region is planarized by at least one of polishing or etching.

18. The method according to claim 16 or 17, further comprising: After growing the semiconductor stack and before forming the first DBR stack, depositing a conductive layer on the first face of the oxide substrate; and A first electrode is formed on the conductive layer.

19. The method of claim 16 or 17, further comprising generating a mesa structure from the semiconductor stack by etching to form an etched surface of the n-type III-nitride region, the mesa structure comprising the III-nitride active region.

20. The method of claim 19, further comprising forming a second electrode on the etched face of the n-type III-nitride region outside the mesa structure.

21. The method of claim 16 or 17, wherein the semiconductor stack further comprises one of a tunnel junction or a buried tunnel junction.

22. The method according to claim 16 or 17, wherein: The oxide substrate includes one of aluminum oxide, zinc oxide or gallium oxide.

23. The method according to claim 16 or 17, wherein: Preparing a starting substrate includes: depositing a group III nitride layer on the first surface of the oxide substrate; patterning the group III nitride layer to form the group III nitride template plug; depositing multiple dielectric layers to cover the first surface of the oxide substrate and the group III nitride template plug; and processing the multiple layers to form the dielectric filter layer, so that the group III nitride template plug is located in the through hole of the dielectric filter layer, and the height of the group III nitride template plug is greater than the thickness of the dielectric filter layer.

24. The method according to claim 23, wherein: The plurality of dielectric layers are grown to form a Fabry-Perot filter configured to provide the reflection spectrum to the optical window.

25. The method according to claim 16 or 17, wherein: The III-nitride region is grown from the III-nitride template plug by epitaxial lateral overgrowth to form a III-nitride island.

26. The method according to claim 25, wherein: The III-nitride islands extend outward from the III-nitride template plug along the top surface of the dielectric filter layer, and the top surface of the dielectric filter layer has a roughness of less than 1 nanometer.

27. The method according to claim 16 or 17, wherein: The III-nitride active region is grown to form a quantum well structure configured to generate light having a wavelength in a first reflection spectrum of the first DBR stack, a second reflection spectrum of the second DBR stack, and the optical window of the dielectric filter layer.

28. The method according to claim 16 or 17, wherein: Processing the oxide substrate at the second face of the oxide substrate to form an oxide substrate, comprising: forming a patterned resist layer on the second face of the oxide substrate; thermally treating the patterned resist layer to form a raised resist region; and transferring the shape of the raised resist region to the oxide substrate by etching the raised resist region and the oxide substrate to form the curved surface; and The etching of the raised resist region and the oxide substrate is stopped to satisfy a condition that a distance between the second DBR stack and the first DBR stack is greater than 50 μm after the first DBR stack and the second DBR stack are formed.

29. The method according to claim 16 or 17, wherein: The curved surface has a radius of curvature greater than 50 microns.

30. The method according to claim 16 or 17, characterized in that Also includes: After growing the semiconductor stack and before forming the conductive layer, forming a resist film on the first surface of the oxide substrate; irradiating the resist layer through the curved surface of the oxide substrate to produce a patterned mask from the resist film; and Ion implantation is performed using the patterned mask to form an aperture structure including an aperture region and an isolation region surrounding the aperture region.

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