Power conversion device

Abstract

In a power conversion device that performs conversion between DC and AC by driving a semiconductor switching element by means of PWM control, the pulse width of the PWM control is set using a PWM carrier wave, and the pulse width of the PWM control is set at a predetermined update timing with respect to a carrier frequency, a gate voltage, and a gate resistance of the semiconductor switching element, which are driving conditions of the semiconductor switching element. According to a current driving condition, the loss of the semiconductor switching element in a predetermined loss calculation period is calculated by calculation, and a process for changing the driving condition and calculating the loss in the loss calculation period is repeated by a predetermined number of times, thereby determining a driving condition in which the loss is the minimum. The semiconductor switching element is driven under the determined driving condition.

Description

Technical Field

[0001] The present application relates to a power conversion device. Background Art

[0002] As a power conversion device having an inverter composed of a plurality of semiconductor switching elements, there is a power conversion device that converts direct current into alternating current by turning on / off the plurality of semiconductor switching elements using a pulse width modulation method, and then supplies power to a three-phase AC motor. In this power conversion device, the total loss amount of the semiconductor switching element per predetermined time is calculated as the sum of the switching loss and the steady-state loss, and the total loss amount reduction method is switched according to the relationship between the amount of reduction in switching loss and the amount of increase in steady-state loss to reduce the loss (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2006-020418 Summary of the invention

[0005] The gate voltage and gate resistance, which are driving variables of the semiconductor switching element, are fixed to meet the restriction conditions under the current and voltage conditions where the surge voltage or noise is maximized. Therefore, in the power conversion device described in Patent Document 1, when the current and voltage conditions change, the gate voltage and gate resistance cannot be adjusted to reduce the loss.

[0006] The present application has been made to solve the above-mentioned problems, and an object of the present application is to provide a power conversion device capable of reducing loss when current and voltage conditions change.

[0007] The power conversion device disclosed in the present application is provided with a drive controller for controlling a semiconductor switching element through PWM control to perform conversion between direct current and alternating current, wherein the drive controller uses a PWM carrier to set the pulse width of the PWM control, and with respect to a carrier frequency as the frequency of the PWM carrier, a gate voltage of the semiconductor switching element, and a gate resistance of the semiconductor switching element, which are driving conditions of the semiconductor switching element, at a predetermined update timing, according to the current driving conditions, calculates the current loss of the semiconductor switching element during a predetermined loss calculation period by calculation, repeats the process of changing the driving conditions and calculating the loss during the loss calculation period by calculation a predetermined number of times, determines the driving conditions that minimize the loss, and controls the semiconductor switching element with the determined driving conditions.

[0008] In addition, a power conversion device includes a drive controller that controls a semiconductor switching element through PWM control to perform conversion between direct current and alternating current, wherein the drive controller uses a PWM carrier to set the pulse width of the PWM control, and with respect to a carrier frequency as the frequency of the PWM carrier, a gate voltage of the semiconductor switching element, and a gate resistance of the semiconductor switching element, which are driving conditions of the semiconductor switching element, at a predetermined update timing, based on the current driving conditions, calculates the loss of the semiconductor switching element during a predetermined loss calculation period, and when the loss is greater than a predetermined value, the process of changing the driving conditions and calculating the loss during the loss calculation period by calculation is repeated a predetermined number of times to determine the driving conditions that minimize the loss, and control the semiconductor switching element under the determined driving conditions.

[0009] According to the power conversion device disclosed in the present application, it is possible to provide a power conversion device that can set the gate resistance and gate voltage of a semiconductor switch element to appropriate values ​​when current and voltage conditions change, thereby further reducing loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic block diagram showing the configuration of the power conversion device according to the first embodiment.

[0011] Figure 2 This is a block diagram showing the configuration of a drive controller of the power conversion device according to the first embodiment.

[0012] Figure 3 This is a block diagram showing the configuration of a gate drive unit of the power conversion device according to the first embodiment.

[0013] Figure 4 This is a block diagram showing the configuration of a drive condition setting unit of the power conversion device according to the first embodiment.

[0014] Figure 5 This is a diagram for explaining the update timing of the driving conditions in the driving condition setting unit of the power conversion device according to the first embodiment.

[0015] Figure 6 This is a diagram showing a processing flow of updating the driving conditions in the driving condition setting unit of the power conversion device according to the first embodiment.

[0016] Figure 7 This is a diagram showing an example of a variation range of each driving condition in a driving condition setting unit of the power conversion device according to the first embodiment.

[0017] Fig. 8A as well as Figure 8B This is a diagram showing an example of a setting function of a carrier frequency in a drive condition setting unit of the power conversion device according to the first embodiment.

[0018] Fig. 9A as well as Fig. 9B This is a diagram showing an example of a setting function of a gate voltage in a drive condition setting unit of the power conversion device according to the first embodiment.

[0019] Fig. 10A as well as Fig. 10B This is a diagram showing an example of a setting function of a gate resistance in a drive condition setting unit of the power conversion device according to the first embodiment.

[0020] Fig.11 This is a diagram for explaining the carrier wave of the power conversion device according to the first embodiment and the timing for changing each driving condition.

[0021] Fig.12 This is a diagram for explaining whether or not each setting function in the drive condition setting unit of the power conversion device according to the first embodiment is updated.

[0022] Fig.13 This is a block diagram showing the configuration of a drive condition setting unit of the power conversion device according to the second embodiment.

[0023] Fig.14 This is a diagram showing the flow of step ST4 of the process flow of updating the drive condition in the drive condition setting unit of the power conversion device according to the second embodiment.

[0024] Fig.15 This is a diagram showing the flow of step ST43 of the process flow of updating the drive condition in the drive condition setting unit of the power conversion device according to the second embodiment.

[0025] Fig.16 This is a diagram for explaining the flow of step ST436 in the flow of processing for updating the drive conditions in the drive condition setting unit of the power conversion device according to the second embodiment.

[0026] Fig.17 This is a diagram showing an example of a variation range of gate resistance in a drive condition setting unit of the power conversion device according to the second embodiment.

[0027] Fig.18 This is a diagram showing a processing flow of updating the driving conditions in the driving condition setting unit of the power conversion device according to the third embodiment.

[0028] Fig.19 This is a diagram showing an example of the hardware configuration of the drive controller. DETAILED DESCRIPTION

[0029] Implementation method 1.

[0030] Figure 1 1 is a block diagram showing the structure of the power conversion device according to Embodiment 1. The power conversion device 10 converts the DC power of the DC power supply 20 into a three-phase AC power and supplies the power to the motor 21. Conversely, the AC power generated by the motor 21 can also be converted into DC power and regenerated in the DC power supply 20. The power conversion device 10 has Figure 2 The drive controller 11 shown controls the semiconductor switching elements 41 to 46 constituting the power conversion device 10. A smoothing capacitor 31 for smoothing power pulsation is generally provided on the DC side of the power conversion device 10. Here, the motor 21 is connected to the AC side of the power conversion device 10, but the device connected to the AC side is not limited to the motor, and any device that can operate with AC can be used.

[0031] The drive controller 11 determines the gate signals 8i1 (i=1-6), gate voltage command values ​​8i2 (i=1-6), and gate resistance command values ​​8i3 (i=1-6) of the semiconductor switch elements 41-46 (also recorded as 4i (i=1-6). The numbers of the values ​​and signals corresponding to the semiconductor switch elements 4i are sometimes recorded in the same way), and outputs them to the gate drive unit 8i (i=1-6) of each semiconductor switch element 4i (i=1-6). The gate drive unit 8i (i=1-6) generates the gate voltage signal 8i4 (i=1-6) for controlling the semiconductor switch element 4i (i=1-6) according to the command from the drive controller 11. In addition, the power conversion device 10 includes: a voltage sensor 51 for detecting the DC voltage of the DC power supply; a current sensor 61 for detecting the AC current supplied to the motor 21; and a temperature sensor 7i (i=1-6) for detecting the temperature of each semiconductor switch element 4i (i=1-6).

[0032] According to the above structure, the power conversion device 10 converts the DC power of the DC power supply 20 into AC power to drive the motor 21 by turning on / off the semiconductor switch elements 4i (i=1 to 6) according to the gate signal 8i1 (i=1 to 6). Conversely, by turning on / off the semiconductor switch elements 4i (i=1 to 6) according to the gate signal 8i1 (i=1 to 6), the AC power generated by the motor 21 can also be converted into DC power and regenerated in the DC power supply 20. Here, the on / off control of the semiconductor switch elements is performed using the gate signal 8i1 (i=1 to 6) described later. Fig.11 PWM control is a method of controlling the pulse width using a PWM (Pulse Width Modulation) carrier as shown in FIG. Figure 1The figure shows an electric power conversion device in which the AC side becomes a three-phase full-bridge circuit of three-phase AC, but in the technology disclosed in the present application, as long as it is a DC and AC conversion circuit based on PWM control, it can be applied regardless of whether the AC side is single-phase or multi-phase other than three-phase.

[0033] like Figure 2 As shown, the drive controller 11 includes an AD conversion unit 111, a drive condition setting unit 112, a duty cycle calculation unit 113, and a gate signal output unit 114. The AD conversion unit 111 converts the DC voltage detection value 511 of the voltage sensor 51, the current detection value 611 of the AC current of the current sensor 61, and the temperature detection values ​​7i1 (i=1~6) of the temperature sensor 7i (i=1~6) into a DC voltage detection signal 5112, a current detection signal 6112, and each temperature detection signal 7i11 (i=1~6) as digital signals by sampling, etc. The drive condition setting unit 112 uses the signal from the AD conversion unit 111, etc. to determine the drive conditions of the semiconductor switch element. Here, the determined drive conditions are carrier frequency, gate voltage, and gate resistance. The duty cycle calculation unit 113 generates a voltage peak command value 921 using the current detection signal 6112 and the DC voltage detection signal 5112, and adjusts the proportional duty cycle D of the on period of each semiconductor switch element 4i (i=1 to 6) using the repetition frequency of the PWM carrier determined by the drive condition setting unit 112, that is, the carrier frequency command value 911, and outputs the duty cycle D, the carrier frequency command value 911, and the voltage peak command value 921. In addition, the voltage peak command value 921 generated by the duty cycle calculation unit 113 is also used in the operation waveform estimation unit 1121 in the drive condition setting unit 112 described later. The gate signal output unit 114 uses the carrier frequency command value 911 and the voltage peak command value 921 from the duty cycle calculation unit 113 to output the gate signal 8i1 (i=1 to 6) for driving each semiconductor switch element that satisfies the duty cycle D.

[0034] Figure 3This is a block diagram showing the structure of a gate driving unit 8i (i=1~6) that drives the gate of each semiconductor switch element 4i (i=1~6). Each gate driving unit 8i (i=1~6) has the same structure. In each gate driving unit 8i (i=1~6), a gate signal 8i1 (i=1~6), a gate voltage command value 8i2 (i=1~6), and a gate resistance command value 8i3 (i=1~6) are input and a gate voltage signal 8i4 (i=1~6) is output to drive the semiconductor switch element 4i (i=1~6). In the voltage adjustment circuit 810i (i=1~6), the gate voltage command value 8i2 (i=1~6) and the current gate voltage value are input, and the gate voltage value is output to match the command value, for example, through feedback control. The gate drive circuit 811i (i=1~6) amplifies the gate signal 8i1 (i=1~6) to the gate voltage command value set in the voltage adjustment circuit 810i (i=1~6) and outputs it to the gate resistance switching circuit. The gate resistance switching circuit 812i (i=1~6) is a circuit that selects a gate resistance value from a predetermined gate resistance candidate according to the gate resistance command value 8i3 (i=1~6), and outputs a gate voltage signal 8i4 (i=1~6) based on the gate voltage command value 8i2 (i=1~6) input from the gate drive circuit 811i (i=1~6) by setting the gate resistance to the selected gate resistance value. In addition, Figure 1 , the structure in which each gate driving unit 8i (i=1~6) is arranged outside the driving controller 11 is shown, but part of the function of each gate driving unit 8i (i=1~6) or each gate driving unit 8i (i=1~6) may also be arranged in the driving controller 11.

[0035] Figure 4 1 is a block diagram showing the structure of the driving condition setting unit 112. In the driving condition setting unit 112, the carrier frequency, gate voltage, and gate resistance as driving conditions are set as a function in one AC cycle. This function is called a setting function. In the driving condition setting unit 112, in addition to the current carrier frequency setting function 911f (hereinafter, the symbol f is added when the parameter is a function), the gate voltage setting function 8i2f (i=1~6) and the gate resistance setting function 8i3f (i=1~6) of each semiconductor switch element, the voltage peak command value 921, the voltage frequency command value 931, and the static characteristics 941 of the semiconductor switch element and the dynamic characteristics 942 of the semiconductor switch element stored in the memory, the DC voltage detection signal 5112 converted by the AD conversion unit 111 and the temperature detection signal 7i11 (i=1~6) of each semiconductor switch element are also input.

[0036] The current carrier frequency setting function 911f, the gate voltage setting function 8i2f (i=1 to 6) and the gate resistance setting function 8i3f (i=1 to 6) of each semiconductor switch element, the voltage peak command value 921, and the voltage frequency command value 931 are read in the setting value reading unit 1125. The gate signal pattern 951 and the operating current waveform 961 of one cycle of the voltage frequency command value 931 are estimated in the operation waveform estimation unit 1121. The static characteristics 941 of the semiconductor switch element and the dynamic characteristics 942 of the semiconductor switch element which are stored as data in advance in the memory are read in the semiconductor characteristic derivation unit 1124. Based on the static characteristics and dynamic characteristics of the semiconductor switch element stored in these, the conduction loss characteristics 9411 of the semiconductor switch element and the switching loss characteristics 9421 of the semiconductor switch element are generated as approximate expressions or approximate data depending on five variables of the applied voltage, the flowing current, the gate resistance, the gate voltage, and the temperature in each semiconductor switch element.

[0037] Here, the static characteristic 941 of the semiconductor switch element on the input side of the semiconductor characteristic derivation unit 1124 is provided as characteristic data with the flow current, temperature, and gate voltage as parameters for the forward voltage drop and the reverse voltage drop of the target semiconductor switch element. In addition, the dynamic characteristic 942 of the semiconductor switch element is provided as characteristic data with the flow current, temperature, gate voltage, gate resistance, and DC applied voltage as parameters for the turn-on loss (loss when the semiconductor switch element is turned on) and the turn-off loss (loss when the semiconductor switch element is turned off) of the target semiconductor switch element.

[0038] In the semiconductor characteristic derivation unit 1124, the static characteristic 941 of the input semiconductor switch element is used to generate the conduction loss characteristic 9411 of the semiconductor switch element as an approximate expression or approximate data with the gate voltage, junction temperature, and flow current as parameters. In addition, the dynamic characteristic 942 of the input semiconductor switch element is used to generate the switching loss characteristic 9421 of the semiconductor switch element as an approximate expression or approximate data with the gate voltage, gate resistance, junction temperature, DC applied voltage, and flow current as parameters. In addition, if the conduction loss characteristic 9411 of the semiconductor switch element and the switching loss characteristic 9421 of the semiconductor switch element generated as these approximate expressions or approximate data are generated externally and stored in the memory, the semiconductor characteristic derivation unit 1124 can be omitted.

[0039] In the loss calculation unit 1122, the gate signal pattern 951 and the operating current waveform 961 output from the operating waveform estimation unit 1121, the DC voltage detection signal 5112 output from the AD conversion unit 111 and the temperature detection signal 7i11 (i=1 to 6) of each semiconductor switch element, each gate voltage setting function 8i2f (i=1 to 6) and each gate resistance setting function 8i3f (i=1 to 6) are applied to the conduction loss characteristic 9411 of the semiconductor switch element and the switching loss characteristic 9421 of the semiconductor switch element output from the semiconductor characteristic derivation unit 1124, thereby calculating the loss 97i which is the sum of the conduction loss and the switching loss of each semiconductor switch element 4i (i=1 to 6) in one cycle of the voltage frequency command value 931, that is, one AC cycle. In addition, as one of the parameters set in the characteristics of the semiconductor switch element, there is a junction temperature, and the junction temperature of each semiconductor switch element can be estimated from each temperature detection signal 7i11 (i=1 to 6). In the above description, the loss of one AC cycle is calculated, but the loss of two AC cycles may be calculated, and the loss during the loss calculation period, which is a predetermined period, may be calculated. The loss calculation period is preferably set to at least one AC cycle.

[0040] In the driving condition updating unit 1123, each setting function of the carrier frequency, gate voltage, and gate resistance is updated to a setting function with reduced loss. Therefore, each setting function of the carrier frequency, gate voltage, and gate resistance is changed, and the loss calculation unit 1122 repeats the process of calculating the loss based on the changed setting functions of the carrier frequency, gate voltage, and gate resistance, thereby determining each setting function of the carrier frequency, gate voltage, and gate resistance with less loss of the semiconductor switching element. The driving condition updating unit 1123 outputs the carrier frequency command value 911, each gate voltage command value 8i2 (i=1~6), and each gate resistance command value 8i3 (i=1~6) according to each determined setting function. For example, for each Tsw described later, these command values ​​are output as the values ​​of each setting function corresponding to the phase of the AC at that time point.

[0041] exist Figure 5 In FIG. 1 , the update timing of each setting function of the carrier frequency, gate voltage, and gate resistance as the driving conditions in the driving condition setting unit 112 is shown using the relationship with the AC cycle. Figure 5As shown, in this embodiment, one cycle of the sinusoidal current of each phase flowing through the motor 21 connected to the AC side of the inverter is a period Trot that becomes the basis for updating, and a process for updating the driving condition with a cycle of an integer multiple (n times) of Trot is performed. After the process for updating the driving condition is performed, the semiconductor switching element is driven to operate in a period of n times of Trot (also referred to as a predetermined driving period) under the updated driving condition.

[0042] Figure 6 It is shown in Figure 4 This is a flowchart of the processing in the drive condition setting unit 112 described in FIG. Figure 5 The update timing shown is executed Figure 6 That is, the update timing is executed Figure 6 The processing is performed to determine and update the setting functions of the carrier frequency, gate voltage, and gate resistance within one AC cycle Trot. In addition, each setting function may be set as a function of at least one AC cycle, for example, it may be set as a function of two AC cycles, or a function of a longer period. The following is an example in which each setting function is set as a function of one AC cycle.

[0043] First, the current setting functions of the carrier frequency, gate voltage, and gate resistance are read (step ST1 ). Using these setting functions, the loss of the semiconductor switching elements 41 to 46 per AC cycle is calculated as the current loss of the semiconductor switching elements (step ST2 ).

[0044] The setting function 8i2f (i=1~6) of the current gate voltage and the setting function 8i3f (i=1~6) of the gate resistance stored in the memory, the gate signal pattern 951 and the action current waveform 961 output from the action waveform estimation unit 1121, the temperature detection signal 7i11 (i=1~6) of each semiconductor switch element, and the DC voltage detection signal 5112 are applied to the conduction loss characteristic 9411 of the semiconductor switch element and the switching loss characteristic 9421 of the semiconductor switch element, and the loss of the semiconductor switch element is calculated.

[0045] Next, in step ST4, the carrier frequency variation range, gate voltage variation range, and gate resistance variation range for determining each setting function of the carrier frequency, gate voltage, and gate resistance to be updated are determined. These variation ranges are determined as functions of one AC cycle of upper and lower limits as ranges to be determined so that the setting functions of each parameter converge within their variation ranges. Figure 7 An example of the variation range of the carrier frequency fsw, the gate resistance Rg, and the gate voltage Vg is shown.

[0046] Regarding the variation range of the carrier frequency fsw, the upper limit fswu and the lower limit fswl are determined based on the control characteristics or the processing speed of the CPU used for control, which are different from the loss calculation. The upper limit Rgu of the gate resistance Rg is mainly determined by the element withstand voltage, and the lower limit Rgl is mainly determined by the surge voltage of the semiconductor switch element, which are different from the loss. The upper limit Vgu of the gate voltage Vg is determined based on the limitation caused by the surge voltage, and the lower limit Vgl is determined based on the saturation characteristics of the semiconductor switch element, according to the limitation different from the loss.

[0047] Next, within the carrier frequency variation range (fswu-fswl), the gate voltage variation range (Vgu-Vgl) and the gate resistance variation range (Rgu-Rgl), the respective setting functions of the carrier frequency, the gate voltage and the gate resistance are set (ST5).

[0048] Fig. 8A as well as Figure 8B FIG. 2 shows an example of a setting function fsws of a carrier frequency fsw. A bold line indicates the setting function fsws. Fig. 8A In FIG. 1 , an example of setting function fsws is shown in which the frequency is linearly decreased toward the phase (Trot / 4, 3Trot / 4) where the output current reaches a peak value to reduce the switching loss. In addition, Figure 8B An example of a setting function fsws that is set to a constant value and does not change the setting value is shown. The setting value may not be changed at the update timing, or the carrier frequency may be changed at the update timing and kept constant at its setting value only in one AC cycle (Trot period). In addition, the carrier frequency may be changed stepwise within one AC cycle.

[0049] Fig. 9A as well as Fig. 9B An example of a setting function for gate voltage Vg is shown. The bold line represents the setting function Vgs. Fig. 9A In FIG. 1 , an example of setting function Vgs is shown, which is determined to reduce the gate voltage near the phase (Trot / 4, 3Trot / 4) where the output current reaches the peak value. In this setting, considering that the surge voltage increases as the switching current increases, the gate voltage is intended to be reduced during a predetermined period to maintain the surge voltage below the allowable voltage value. In addition, Fig. 9BAn example of a function set to a constant value is shown. The set value may not be changed at the update timing, or the gate voltage may be changed only at the update timing and kept constant at its set value during one AC cycle (Trot period). The switching of the gate voltage requires the response time of the capacitor load, so it is not a gradual change but a step-like change.

[0050] Fig. 10A as well as Fig. 10B An example of setting function Rgs of gate resistance Rg is shown. Fig. 10A In FIG. 1 , an example of a setting function Rgs that changes according to the phase is shown. In this example, the gate resistance is set to be increased near the phase (Trot / 4, 3Trot / 4) where the output current reaches a peak. In this setting, considering that the surge voltage increases as the switching current increases, the intention is to increase the gate resistance for each predetermined period to maintain the surge voltage below the allowable voltage value. On the other hand, when the gate resistance is increased, the switching loss increases, so the gate resistance is set to be as small as possible within the above-mentioned surge voltage limit. In addition, Fig. 10B An example of a function set to a constant value is shown. The setting function Rgs can be set so that the setting value itself is not changed at the update timing, or the gate resistance value can be changed at the update timing and kept constant at its setting value only during one AC cycle (Trot period). The gate resistance switching circuit 812i (i=1 to 6) is configured to switch the fixed resistance value using a switch or the like. Therefore, the switching of the gate resistance value is not a gradual switching but a step-by-step switching.

[0051] Using the respective setting functions of the carrier frequency, gate voltage, and gate resistance determined as described above, the losses of the semiconductor switch elements 41 to 46 are calculated and stored (step ST6). Steps ST5 and ST6 are repeated a predetermined number of times (N times). That is, including the current settings, N+1 combinations of carrier frequency setting functions, gate voltage setting functions, and gate resistance setting functions and the losses of the semiconductor switch elements are stored. The combination of the carrier frequency setting function, gate voltage setting function, and gate resistance setting function that minimizes the losses among the N+1 losses is determined (step ST6), and the semiconductor switch elements 41 to 46 are driven based on these setting functions.

[0052] In this way, the combination of the setting functions that minimizes the loss can be obtained from the combination of the wide range of setting functions set within the range of changes of the carrier frequency, gate voltage, and gate resistance determined in step ST4. Therefore, even if the current and voltage conditions on the AC side or the voltage on the DC side change, it is possible to set the driving conditions including the gate voltage and gate resistance that minimize the loss of the semiconductor switching element, so that a power conversion device with smaller loss can be achieved.

[0053] As described above, the carrier frequency, the gate voltage, and the gate resistance are set as a setting function of one AC cycle, that is, a function of the phase of the AC. For each phase of the AC, the output of the drive controller 11, that is, each gate signal 8i1 (i=1 to 6), the gate voltage command value 8i2 (i=1 to 6), and each gate resistance command value 8i3 (i=1 to 6) are output as values ​​based on each setting function. For example, for each cycle of the carrier frequency, that is, for each basic pulse of the PWM control, each gate signal 8i1 (i=1 to 6), each gate voltage command value 8i2 (i=1 to 6), and each gate resistance command value 8i3 (i=1 to 6) are output from the drive controller 11, and the gate voltage signal 8i4 (i=1 to 6) based on these values ​​is applied from the gate drive unit 8i (i=1 to 6) to the gate of each semiconductor switch element 4i (i=1 to 6) to drive each semiconductor switch element 4i (i=1 to 6).

[0054] like Fig. 9A The gate voltage setting function Vgs, or Fig. 10A When the value is changed stepwise during one AC cycle, as in the setting function Rgs of the gate resistance, Fig.11 The time point of the peak or trough of the PWM carrier wave shown in FIG. 1 (the time point indicated by ●) is set as the timing of the change. That is, the cycle of the stepwise change of the value is set as one cycle of the PWM carrier wave ( Fig.11 The changing timing can be set to a time point that makes it a peak or trough of the carrier wave.

[0055] In addition, Fig.11 The case where the timing of the change is synchronized with the peak or trough of the PWM carrier is shown in FIG. 1 , but the timing of the change can also be determined as an arbitrary phase of the PWM carrier. The change cycle is determined by the performance of the controller side, but the change cycle of the carrier frequency, gate voltage, and gate resistance is set as a cycle longer than one cycle of the PWM carrier, and the timing of the change can be set to a time point that is the same phase as the carrier.

[0056] Regarding the step-wise change cycle of gate voltage, gate resistance, and carrier frequency, when changing the command value in terms of gate voltage, Figure 1 The gate voltage value of the gate driving unit shown in the figure changes. However, a smoothing capacitor must be provided in the portion where the gate voltage is applied. Due to the capacitor capacitance of the smoothing capacitor, the change in the gate voltage is delayed relative to the step-by-step change in the command value. In particular, when the capacitor capacitance is increased, the change in the gate voltage may become longer than the period of change in the carrier cycle. On the other hand, the change in the carrier frequency and the change in the gate resistance become changes without a time constant. Therefore, it is also possible to change the gate voltage in a step-by-step manner with an AC cycle, that is, a slow cycle, and on the other hand, change the carrier frequency and the gate resistance with a carrier cycle, that is, a fast cycle.

[0057] Figures 8A to 10B The carrier frequency, gate resistance and gate voltage setting functions shown are updated as shown in FIG. Fig.12 There are 8 types as shown in the table. Combination 1 is an operation mode in which no update is performed. When the setting function is set in step ST4, combinations 2 to 8 correspond. When the setting function is changed at the update timing and then maintained until the next update timing, it is classified as yes.

[0058] For example, in the case of combination 2, only the setting function of the carrier frequency is updated. That is, in step ST5, only the setting function of the carrier frequency is changed without changing the setting function of the gate voltage and the setting function of the gate resistance, and the loss is calculated in step ST6. This process is repeated N times to determine the setting function of the carrier frequency that minimizes the loss.

[0059] The carrier frequency is set from the perspective of the control quality of the inverter's sinusoidal current, but the gate voltage and gate resistance are set from the perspective of the loss of a single switch. Fig.12 By selecting a combination of parameters to be updated from the combinations of parameters to be updated, it is possible to explore driving conditions with smaller losses compared to the case where the updated setting parameters are only the carrier frequency alone, or only the gate resistance and the gate voltage.

[0060] Implementation method 2.

[0061] In the first embodiment, (1) the lower limit of the gate resistance is set according to the current value and (3) the withstand voltage of the semiconductor switch element within one AC cycle. For example, when a battery is used as a power source on the DC side, it is assumed that the DC voltage changes over a much longer period than the AC cycle. It is preferable to set the lower limit of the gate resistance according to the DC voltage that changes in this way, taking into account the surge voltage on the motor side, noise, and false turn-on of the semiconductor switch element.

[0062] When considering the surge voltage on the motor side, it is not just the withstand voltage of the semiconductor switch element itself that is considered. Since the surge voltage superimposed on the output voltage of the inverter via the output cable is applied to the motor input terminal, the surge voltage needs to meet the upper limit of the withstand voltage determined by the insulation strength of the motor. In addition, when the gate resistance is reduced to increase the switching speed, it may cause increased noise and false connection (the state where the semiconductor switch element is turned on without following the gate signal's disconnection signal) and other factors, which may deteriorate the reliability. Therefore, the switching speed needs to be suppressed to a certain speed or less in advance. The switching speed determined by the surge voltage at the input terminal of these semiconductor switch elements and the motor, and the switching speed determined by the suppression of noise and false connection of the semiconductor switch element, in addition to the sinusoidal current of the inverter, also depends on the DC voltage.

[0063] Therefore, in the present second embodiment, when determining the setting function of the gate resistance Rg described in the first embodiment, the DC voltage and the output current are used as input information, and in addition to the upper limit of the switching speed determined based on the allowable value of the surge voltage determined by the withstand voltage of the semiconductor switching element and the allowable value of the surge voltage determined by the withstand voltage of the input end of the motor, the upper limit of the switching speed predetermined to suppress noise and erroneous connection of the semiconductor switching element is also considered to determine the lower limit value Rgl of the gate resistance.

[0064] The setting function of the gate resistance Rg is updated in the driving condition updating section 1123. Fig.13 As shown, the DC voltage detection signal 5112 and the current detection signal 6112 are input to the driving condition updating section 1123 .

[0065] Fig.14 as well as Fig.15 It is shown in Figure 6The flowchart showing the determination of the gate resistance variation range is a flowchart of the process step ST4 in the drive condition update unit 1123 in the process flowchart of the drive condition setting unit 112 described in the above. Here, in addition to the upper limit of the switching speed determined by the allowable value of the surge voltage determined by the withstand voltage of the semiconductor switching element and the allowable value of the surge voltage determined by the withstand voltage of the input end of the motor, the lower limit of the gate resistance variation range is determined in consideration of the upper limit of the switching speed determined in advance to prevent noise and erroneous connection. ST1, ST2, ST5, ST6, ST7 and ST8 other than ST4 are the same as Figure 6 Therefore, in Figure 5 That is, at the update timing, the execution includes Fig.14 as well as Fig.15 The processing of step ST4 shown in FIG. Figure 6 In the processing shown, each setting function of the carrier frequency, the gate voltage, and the gate resistance within one cycle Trot of the AC is determined and updated.

[0066] Step ST4 is a step of determining the variation range of the carrier frequency, the variation range of the gate voltage, and the variation range of the gate resistance in the same manner as in the first embodiment. Fig.14 The step ST41 of determining the variation range of the carrier frequency and the gate voltage shown is the same as that of the first embodiment. In the second embodiment, in the step ST42 of determining the variation range of the gate resistance, a condition is further added to the condition described in the first embodiment. These variation ranges are determined as a function of at least one AC cycle of the upper limit value and the lower limit value as a range that should be determined in a manner so that the setting function of each parameter converges within its variation range. As described in the first embodiment, each setting function and each variation range are not limited to one AC cycle, but can also be set as a function of a period longer than one AC cycle. The following is an example in which each setting function and each variation range are set as a function of the period of one AC cycle.

[0067] like Fig.14 As shown, in step ST42 of determining the upper limit value Rgu and the lower limit value Rgl of the gate resistance Rg, the upper limit value Rgu is mainly determined by the element withstand voltage of the semiconductor switch element (step ST421). Fig.15 Show Fig.14Detailed processing flow of step ST43 for determining the lower limit value Rgl of the gate resistance shown in the figure. First, the current DC voltage and the output current of one AC cycle are read in (step ST431). The output current of one AC cycle is stored as a function with a phase as a parameter, for example. Next, the allowable value of the surge voltage taking into account the DC voltage, the withstand voltage of the semiconductor switching element, and the output current is expressed as a function of one AC cycle (step ST432). In addition, the allowable value of the surge voltage taking into account the DC voltage, the withstand voltage of the input end of the motor, and the output current is expressed as a function of one AC cycle (step ST433).

[0068] From the functions of the allowable values ​​of these surge voltages, a value with a lower allowable value of the surge voltage is selected for each phase of one AC cycle, and the function of the allowable value of the surge voltage during one AC cycle is determined. The switching speed of the semiconductor switching element corresponding to the allowable value of the surge voltage is the upper limit of the switching speed, and the switching speed is determined as a function of one AC cycle (step ST434). Here, the switching speed di / dt1 allowed according to the allowable value of the surge voltage is calculated based on the following formula. The absolute value of the surge voltage (the value obtained by superimposing the surge voltage on the DC voltage) is set to Vsurge, the DC voltage is set to Vdc, and the parasitic inductance is set to L. Regarding the parasitic inductance L, the value measured in advance during installation is adopted as a constant.

[0069] di / dt1=(Vsurge-Vdc) / L Formula (1)

[0070] On the other hand, the upper limit di / dt2 of the switching speed is determined based on the limit of the noise and the erroneous connection of the semiconductor switch element (step ST435). The upper limit of the switching speed is determined based on the limit of the noise and the erroneous connection of the semiconductor switch element corresponding to the peak value of the DC voltage and current at that time point, for example.

[0071] Then, the gate resistance corresponding to the function di / dt1 of the switching speed determined in step ST434 and the upper limit di / dt2 of the switching speed determined in step ST435 is calculated, and the values ​​of the two are compared for each phase of one AC cycle. The larger value is selected to determine the lower limit value Rgl of the gate resistance as a function of one AC cycle (step ST436).

[0072] Here, in step ST434, the function of the upper limit of the switching speed for each function may be determined based on the function of the allowable value of each surge voltage, and in step ST436, the function of the upper limit of the two switching speeds and the switching speed determined in step ST435 may be compared for each phase to determine the lower limit of the gate resistance. By setting the minimum (slowest) switching speed as the upper limit of the switching speed for each phase, the function of the switching speed is obtained, and the function of the gate resistance corresponding to the function of the switching speed is obtained, so that the lower limit of the gate resistance can be determined as a function of one AC cycle. Alternatively, the function of the gate resistance corresponding to the upper limit of each switching speed may be first obtained, and the maximum gate resistance value may be used as the lower limit of the gate resistance for each phase to determine the function of the lower limit of the gate resistance for one AC cycle.

[0073] In any case, the gate resistance corresponding to the upper limit of the slowest switching speed is determined as the lower limit value for each phase of the AC based on the upper limit of the switching speed of the semiconductor switching element determined by the allowable value of the surge voltage of the semiconductor switching element, the upper limit of the switching speed of the semiconductor switching element determined by the allowable value of the surge voltage of the motor, and the upper limit of the switching speed of the semiconductor switching element determined by the noise generated by the power conversion device and the limitation of the erroneous connection of the semiconductor switching element. The lower limit value of the variation range of the gate resistance can be determined as a function of one AC cycle.

[0074] Fig.16 The upper limit value Rgu and the lower limit value Rgl (Rgl1 and Rgl2) of the gate resistance are schematically shown. The relationship between the lower limit value Rgl and the switching speed di / dt is shown. The upper limit value Rgu of the gate resistance Rg is a value determined mainly based on the element withstand voltage in step ST421. Rgl1 is the gate resistance value corresponding to di / dt1 calculated in step ST434. Fig.16 As shown, the switching speed di / dt1 determined by the allowable value of the surge voltage varies from the value when the DC voltage is maximum and the output current is at the peak value to the value when the DC voltage is minimum and the output current is 0A. Rgl2 is the gate resistance value corresponding to the switching speed di / dt2 determined by the limit of noise and erroneous connection of the switch determined in step ST435. In addition, the change in DC voltage is not enough to produce a significant difference during one AC cycle, so Rgl2 and Rgl1 corresponding to the output current that changes in one AC cycle are compared for each phase, and the larger value in the phase is determined as Rgl in the phase. By determining Rgl in one AC cycle, it is possible to determine the function of Rgl in one AC cycle. Fig.17 An example of a function of the upper limit value Rgu and the lower limit value Rgl of the gate resistance in one AC cycle is shown. Fig.17 The example shows an example in which Rgl2 is greater than Rgl1 in a phase with small output current, and Rgl1 is greater than Rgl2 in a phase with large output current, which becomes a function of setting Rgl2 to the value of Rgl in a phase with small output current, and setting Rgl1 to the value of Rgl in a phase with large output current.

[0075] The upper limit value Rgu of the gate resistance determined in step ST421 and the lower limit value Rgl of the gate resistance determined in step ST436 are set as the variation range of the gate resistance Rg (step ST422). The setting function of the gate resistance is set so that the value is within the variation range ( Figure 6 Step ST5).

[0076] According to the second embodiment, insulation breakdown, noise, and erroneous connection of the semiconductor switching element of the motor can be suppressed, and low loss of the inverter can be achieved. In addition, by considering the DC voltage, when the DC voltage is lower than the maximum value (worst condition), the lower limit value Rgl can be further expanded, and further low loss can be achieved. That is, when the DC voltage is not considered, the lower limit value Rgl of the gate resistance is fixed under the condition that the DC voltage is maximum, but by considering the DC voltage, when the DC voltage is low, Rgl can be made smaller than Rgl when the DC voltage is maximum. As a result, the switching loss can be reduced compared to the switching loss under the condition that the DC voltage is maximum, and further low loss of the power conversion device can be achieved.

[0077] Implementation method 3.

[0078] Fig.16 1 is a flowchart showing the processing in the drive condition setting unit 112 of the power conversion device according to the second embodiment. Fig.13 In the process of processing Figure 6 The judgment process of step ST3 is added between step ST2 and step ST4 of the process flow. That is, when the loss obtained as the loss of the current semiconductor switch element is less than the predetermined value ("No" in step ST3), the driving condition is not updated, and the driving is continued with the current setting function. When the loss obtained is greater than the predetermined value ("Yes" in step ST3), steps ST4 to ST7 are executed.

[0079] In this way, when the current loss is small, no unnecessary processing is performed, so the load on the computing device that performs the processing can be reduced.

[0080] Figure 2 The driving controller 11 shown is specifically as follows Fig.17As shown, it is provided with a CPU (Central Processing Unit) or other operation processing device 11p, a storage device 11m for exchanging data with the operation processing device 11p, an input / output interface 11f for inputting and outputting signals between the operation processing device 11p and the outside, etc. As the operation processing device 11p, it is also possible to have an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and various signal processing circuits, etc. In addition, as the operation processing device 11p, it is also possible to have a plurality of devices of the same type or devices of different types, and to perform each process in a shared manner. As the storage device 11m, it is provided with a RAM (Random Access Memory) configured to read and write data to the operation processing device 11p, a ROM (Read Only Memory) configured to read data from the operation processing device 11p, etc. The input / output interface 11f is composed of, for example, an A / D converter (connector) for inputting sensor signals output from the voltage sensor 51, the current sensor 61, the temperature sensor 7i (i=1 to 6), etc., to the operation processing device 11p. Figure 2 The gate drive units 8i (i=1 to 6) may be configured to include an interface for outputting gate signals 8i1 (i=1 to 6) to the gate drive units 8i (i=1 to 6). In addition, the gate drive units 8i (i=1 to 6) may be provided in the drive controller 11.

[0081] Various illustrative embodiments and examples are described in this application, but the various features, methods and functions described in one or more embodiments are not limited to the application of specific embodiments, but can be applied to the embodiments alone or in various combinations. Therefore, countless unillustrated variations can be envisioned within the scope of the technology disclosed in the specification of this application. For example, it includes the case where at least one constituent element is deformed, the case where at least one constituent element is added or the case where at least one constituent element is omitted, and the case where at least one constituent element is extracted and combined with constituent elements of other embodiments.

[0082] Explanation of symbols

[0083] 10: power conversion device; 11: drive controller; 20: DC power supply; 4i (i=1~6): semiconductor switch element; 8i (i=1~6): gate drive unit; 8i2 (i=1~6): gate voltage command value; 8i3 (i=1~6): gate resistance command value; 51: voltage sensor; 511: DC voltage detection value; 61: current sensor; 611: current detection value; 7i (i=1~6): temperature sensor; 7i1 (i=1~6): temperature detection value; 112: drive condition setting unit; 911: carrier frequency command value; 9411: conduction loss characteristics of semiconductor switch element; 9421: switching loss characteristics of semiconductor switch element; 951: gate signal pattern; 1122: loss calculation unit; 1123: drive condition update unit.

Claims

1. A power conversion device, comprising a drive controller for controlling a semiconductor switching element by PWM control, for performing conversion between direct current and alternating current, wherein: The drive controller uses a PWM carrier to set the pulse width of the PWM control, and calculates the current loss of the semiconductor switch element in a predetermined loss calculation period according to the current driving conditions at a predetermined update timing with respect to the carrier frequency as the frequency of the PWM carrier, the gate voltage of the semiconductor switch element, and the gate resistance of the semiconductor switch element as the driving conditions of the semiconductor switch element. The process of changing the driving condition and calculating the loss in the loss calculation period by calculation is repeated a predetermined number of times, the driving condition that minimizes the loss is determined, and the semiconductor switch element is controlled under the determined driving condition.

2. A power conversion device, comprising a drive controller for controlling a semiconductor switching element by PWM control, for performing conversion between direct current and alternating current, wherein: The drive controller uses a PWM carrier to set the pulse width of the PWM control, and calculates the loss of the semiconductor switch element in a predetermined loss calculation period according to the current driving conditions at a predetermined update timing with respect to the carrier frequency of the PWM carrier as the frequency of the PWM carrier, the gate voltage of the semiconductor switch element, and the gate resistance of the semiconductor switch element as the driving conditions of the semiconductor switch element. When the loss is greater than a predetermined value, The process of changing the driving condition and calculating the loss in the loss calculation period by calculation is repeated a predetermined number of times, the driving condition that minimizes the loss is determined, and the semiconductor switch element is controlled under the determined driving condition.

3. The power conversion device according to claim 1 or 2, wherein: Regarding the driving conditions, a variation range of the carrier frequency, a variation range of the gate voltage, and a variation range of the gate resistance are set, and the carrier frequency, the gate voltage, and the gate resistance are respectively set as functions of at least one cycle of the alternating current in such a manner as to be within the set respective variation ranges.

4. The power conversion device according to any one of claims 1 to 3, wherein: The loss is obtained by applying the temperature of the semiconductor switching element, the DC voltage on the DC side of the power conversion device, the AC current on the AC side of the power conversion device and the driving conditions to the conduction loss characteristics and the switching loss characteristics. The conduction loss characteristic is the loss caused by the voltage drop due to the current flowing through the semiconductor switching element, which is provided by the gate voltage, the junction temperature of the semiconductor switching element and the current flowing through the semiconductor switching element as parameters. The switching loss characteristic is the loss during switching of the semiconductor switching element, which is provided by the gate voltage, the gate resistance, the junction temperature of the semiconductor switching element, the DC voltage applied to the semiconductor switching element and the current flowing through the semiconductor switching element as parameters.

5. The power conversion device according to any one of claims 1 to 4, wherein: The loss calculation period is a period of at least one cycle of the alternating current.

6. The power conversion device according to any one of claims 1 to 5, wherein: The update timing is set for each period that is an integral multiple of one cycle of the alternating current.

7. The power conversion device according to any one of claims 1 to 6, wherein: The parameter of the driving condition for changing the driving condition is at least one of a gate voltage of the semiconductor switch element and a gate resistance of the semiconductor switch element, and the carrier frequency.

8. The power conversion device according to claim 3, wherein: A motor is connected to one side of the AC, and based on an upper limit of the switching speed of the semiconductor switching element determined by an allowable value of a surge voltage of the semiconductor switching element, an upper limit of the switching speed of the semiconductor switching element determined by an allowable value of a surge voltage of the motor, and an upper limit of the switching speed of the semiconductor switching element determined by noise generated by the power conversion device and limitation of erroneous connection of the semiconductor switching element, a gate resistance corresponding to the upper limit of the slowest switching speed is determined as a lower limit value for each phase of the AC, and the lower limit value of the variation range of the gate resistance is determined as a function of at least one cycle of the AC.

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