Method and device for video processing and medium

Abstract

Embodiments of the present disclosure provide a solution for video processing. A method for video processing is presented. The method comprises: for a conversion between a video unit of a video and a bitstream of the video, determining a block vector of the video unit based on a base block vector candidate and a parameter related to a block vector difference; and performing a conversion based on the block vector.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to video processing techniques, and more particularly, to block vector encoding and decoding. Background Art

[0002] Nowadays, digital video capabilities are being applied to all aspects of people's lives. Various types of video compression technologies, such as MPEG-2, MPEG-4, ITU-TH.263, ITU-TH.264 / MPEG-4 Part 10 Advanced Video Codec (AVC), ITU-TH.265 High Efficiency Video Codec (HEVC) standard, and Versatile Video Codec (VVC) standard have been proposed for video encoding / decoding. However, it is generally expected to further improve the encoding and decoding efficiency of video encoding and decoding technologies. Summary of the invention

[0003] The embodiments of the present disclosure provide a solution for video processing.

[0004] In a first aspect, a method for video processing is proposed. The method includes: for conversion between a video unit of a video and a bitstream of the video, determining a block vector of the video unit based on a base block vector candidate and a parameter related to a block vector difference; and performing conversion based on the block vector. In this way, the coding efficiency of block vector coding and decoding can be improved.

[0005] In a second aspect, a device for video processing is provided. The device includes a processor and a non-volatile memory having instructions thereon. The instructions, when executed by the processor, cause the processor to perform the method according to the first aspect of the present disclosure.

[0006] In a third aspect, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores instructions, which enable a processor to execute the method according to the first aspect of the present disclosure.

[0007] In a fourth aspect, another non-transitory computer-readable recording medium is provided. The non-transitory computer-readable recording medium stores a bitstream of a video, the bitstream being generated by a method performed by an apparatus for video processing. The method includes: determining a block vector of a video unit of the video based on a base block vector candidate and a parameter related to a block vector difference; and generating a bitstream based on the block vector.

[0008] In a fifth aspect, a method for storing a bitstream of a video is provided, the method comprising: determining a block vector of a video unit of the video based on a base block vector candidate and a parameter related to a block vector difference; generating a bitstream based on the block vector; and storing the bitstream in a non-transitory computer-readable recording medium.

[0009] This summary is provided to introduce some concepts in a simplified form, which are further described in the following detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become more apparent through the following detailed description with reference to the accompanying drawings. In the exemplary embodiments of the present disclosure, the same reference numerals generally refer to the same components.

[0011] Figure 1 A block diagram showing an example video encoding and decoding system according to some embodiments of the present disclosure is shown;

[0012] Figure 2 A block diagram illustrating a first example video encoder according to some embodiments of the present disclosure is shown;

[0013] Figure 3 A block diagram of an example video decoder according to some embodiments of the present disclosure is shown;

[0014] Figure 4 shows the intra-frame template matching search area used;

[0015] Figure 5 The MMVD search point is shown;

[0016] Figure 6 An example of deriving BVDx and BVDy from BVDI is shown, indicated as a single integer;

[0017] Figure 7a An example of deriving BVDy from BVDI when BVPx=0 is shown;

[0018] Figure 7b An example of deriving BVDx from BVDI when BVPy=0 is shown;

[0019] Figure 8 A flowchart of a method for video processing according to an embodiment of the present disclosure is shown; and

[0020] Fig. 9 A block diagram of a computing device is shown in which various embodiments of the present disclosure may be implemented.

[0021] Throughout the drawings, same or similar reference numbers generally refer to same or similar elements. DETAILED DESCRIPTION

[0022] The principles of the present disclosure are now described in conjunction with some embodiments. It should be understood that these embodiments are described only for the purpose of illustrating and helping those skilled in the art to understand and implement the present disclosure, and do not imply any limitation on the scope of the present disclosure. In addition to the methods described below, the disclosure described herein can also be implemented in various ways.

[0023] In the following description and claims, unless defined otherwise, all scientific and technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0024] References in this disclosure to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment must include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an example embodiment, whether or not explicitly described, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in relation to other embodiments.

[0025] It should be understood that although the terms "first" and "second" etc. can be used to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the listed terms.

[0026] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "including", "comprising", and / or "having" when used herein indicate the presence of the features, elements, and / or components, etc., but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Example Environment

[0027] Figure 11 is a block diagram illustrating an example video codec system 100 that may utilize the techniques of the present disclosure. As shown, the video codec system 100 may include a source device 110 and a destination device 120. The source device 110 may also be referred to as a video encoding device, and the destination device 120 may also be referred to as a video decoding device. In operation, the source device 110 may be configured to generate encoded video data, and the destination device 120 may be configured to decode the encoded video data generated by the source device 110. The source device 110 may include a video source 112, a video encoder 114, and an input / output (I / O) interface 116.

[0028] Video source 112 may include a source such as a video capture device. Examples of a video capture device include, but are not limited to, an interface that receives video data from a video content provider, a computer graphics system for generating video data, and / or combinations thereof.

[0029] The video data may include one or more pictures. The video encoder 114 encodes the video data from the video source 112 to generate a bitstream. The bitstream may include a bit sequence that forms a coded representation of the video data. The bitstream may include a coded picture and associated data. The coded picture is a coded representation of the picture. The associated data may include a sequence parameter set, a picture parameter set, and other grammatical structures. The I / O interface 116 may include a modulator / demodulator and / or a transmitter. The coded video data may be directly transmitted to the destination device 120 via the network 130A via the I / O interface 116. The coded video data may also be stored on a storage medium / server 130B for access by the destination device 120.

[0030] The destination device 120 may include an I / O interface 126, a video decoder 124, and a display device 122. The I / O interface 126 may include a receiver and / or a modem. The I / O interface 126 may obtain encoded video data from the source device 110 or the storage medium / server 130B. The video decoder 124 may decode the encoded video data. The display device 122 may display the decoded video data to the user. The display device 122 may be integrated with the destination device 120, or may be outside the destination device 120, which is configured to be connected to an external display device interface.

[0031] The video encoder 114 and the video decoder 124 may operate according to a video compression standard, such as the High Efficiency Video Codec (HEVC) standard, the Versatile Video Codec (VVC) standard, and other existing and / or further standards.

[0032] Figure 2is a block diagram showing an example of a video encoder 200 according to some embodiments of the present disclosure, which may be Figure 1 An example of a video encoder 114 in the system 100 is shown.

[0033] Video encoder 200 may be configured to implement any or all of the techniques of this disclosure. Figure 2 In the example of , video encoder 200 includes multiple functional components. The techniques described in this disclosure can be shared between the various components of video encoder 200. In some examples, a processor can be configured to perform any or all of the techniques described in this disclosure.

[0034] In some embodiments, the video encoder 200 may include a partitioning unit 201, a prediction unit 202, a residual generation unit 207, a transformation unit 208, a quantization unit 209, an inverse quantization unit 210, an inverse transformation unit 211, a reconstruction unit 212, a buffer 213 and an entropy coding unit 214, and the prediction unit 202 may include a mode selection unit 203, a motion estimation unit 204, a motion compensation unit 205 and an intra-frame prediction unit 206.

[0035] In other examples, the video encoder 200 may include more, fewer, or different functional components. In one example, the prediction unit 202 may include an intra-block copy (IBC) unit. The IBC unit may perform prediction in an IBC mode, where at least one reference picture is a picture where the current video block is located.

[0036] Furthermore, although some components (such as the motion estimation unit 204 and the motion compensation unit 205) may be integrated, for the purpose of explanation, these components are described in detail below. Figure 2 are shown separately in the example.

[0037] The partitioning unit 201 may partition a picture into one or more video blocks. The video encoder 200 and the video decoder 300 may support various video block sizes.

[0038] The mode selection unit 203 may select one of a plurality of codec modes (intra-frame coding or inter-frame coding), for example, based on the error result, and provide the generated intra-frame codec block or inter-frame codec block to the residual generation unit 207 to generate residual block data, and to the reconstruction unit 212 to reconstruct the codec block for use as a reference picture. In some examples, the mode selection unit 203 may select a combination of intra-frame and inter-frame prediction (CIIP) modes, where the prediction is based on an inter-frame prediction signal and an intra-frame prediction signal. In the case of inter-frame prediction, the mode selection unit 203 may also select a resolution for the motion vector (e.g., sub-pixel precision or integer pixel precision) for the block.

[0039] To perform inter-frame prediction on the current video block, the motion estimation unit 204 may generate motion information for the current video block by comparing the current video block with one or more reference frames from the buffer 213. The motion compensation unit 205 may determine a predicted video block for the current video block based on the motion information and decoded samples of pictures from the buffer 213 other than the picture associated with the current video block.

[0040] The motion estimation unit 204 and the motion compensation unit 205 may perform different operations on the current video block, for example, depending on whether the current video block is in an I slice, a P slice, or a B slice. As used herein, an "I slice" may refer to a portion of a picture consisting of macroblocks, all of which are based on macroblocks within the same picture. Furthermore, as used herein, in some aspects, a "P slice" and a "B slice" may refer to a portion of a picture consisting of macroblocks that are independent of macroblocks in the same picture.

[0041] In some examples, the motion estimation unit 204 may perform unidirectional prediction on the current video block, and the motion estimation unit 204 may search the reference pictures of list 0 or list 1 to find the reference video block for the current video block. The motion estimation unit 204 may then generate a reference index and a motion vector, the reference index indicating the reference picture in list 0 or list 1 containing the reference video block, and the motion vector indicating the spatial displacement between the current video block and the reference video block. The motion estimation unit 204 may output the reference index, the prediction direction indicator, and the motion vector as the motion information of the current video block. The motion compensation unit 205 may generate a predicted video block for the current video block based on the reference video block indicated by the motion information of the current video block.

[0042] Alternatively, in other examples, the motion estimation unit 204 may perform bidirectional prediction on the current video block. The motion estimation unit 204 may search the reference pictures in list 0 for a reference video block for the current video block, and may also search the reference pictures in list 1 for another reference video block for the current video block. The motion estimation unit 204 may then generate a plurality of reference indexes and a plurality of motion vectors, the plurality of reference indexes indicating a plurality of reference pictures in list 0 and list 1 containing a plurality of reference video blocks, and the plurality of motion vectors indicating a plurality of spatial displacements between the plurality of reference video blocks and the current video block. The motion estimation unit 204 may output the plurality of reference indexes and the plurality of motion vectors of the current video block as motion information of the current video block. The motion compensation unit 205 may generate a predicted video block for the current video block based on the plurality of reference video blocks indicated by the motion information of the current video block.

[0043] In some examples, motion estimation unit 204 may output a complete set of motion information for use in a decoding process by a decoder. Alternatively, in some embodiments, motion estimation unit 204 may signal motion information of a current video block with reference to motion information of another video block. For example, motion estimation unit 204 may determine that motion information of a current video block is sufficiently similar to motion information of a neighboring video block.

[0044] In one example, motion estimation unit 204 may indicate to video decoder 300 a value in a syntax structure associated with the current video block that indicates that the current video block has the same motion information as another video block.

[0045] In another example, the motion estimation unit 204 may identify another video block and a motion vector difference (MVD) in a syntax structure associated with the current video block. The motion vector difference indicates the difference between the motion vector of the current video block and the motion vector of the indicated video block. The video decoder 300 may use the motion vector of the indicated video block and the motion vector difference to determine the motion vector of the current video block.

[0046] As discussed above, the video encoder 200 may signal motion vectors in a predictive manner.Two examples of prediction signaling techniques that may be implemented by the video encoder 200 include Advanced Motion Vector Prediction (AMVP) and merge mode signaling.

[0047] The intra prediction unit 206 may perform intra prediction on the current video block. When the intra prediction unit 206 performs intra prediction on the current video block, the intra prediction unit 206 may generate prediction data for the current video block based on decoded samples of other video blocks in the same picture. The prediction data for the current video block may include a prediction video block and various syntax elements.

[0048] The residual generation unit 207 may generate residual data for the current video block by subtracting (e.g., indicated by a minus sign) the prediction video block(s) of the current video block from the current video block. The residual data of the current video block may include residual video blocks corresponding to different sample portions of samples in the current video block.

[0049] In other examples, such as in skip mode, there may be no residual data for the current video block, and the residual generation unit 207 may not perform a subtraction operation.

[0050] Transform processing unit 208 may generate one or more transform coefficient video blocks for a current video block by applying one or more transforms to the residual video block associated with the current video block.

[0051] After transform processing unit 208 generates a transform coefficient video block associated with the current video block, quantization unit 209 may quantize the transform coefficient video block associated with the current video block based on one or more quantization parameter (QP) values ​​associated with the current video block.

[0052] The inverse quantization unit 210 and the inverse transform unit 211 may apply inverse quantization and inverse transform to the transform coefficient video block, respectively, to reconstruct a residual video block from the transform coefficient video block. The reconstruction unit 212 may add the reconstructed residual video block to corresponding samples from one or more predicted video blocks generated by the prediction unit 202 to generate a reconstructed video block associated with the current video block for storage in the buffer 213.

[0053] After reconstruction unit 212 reconstructs the video block, a loop filtering operation may be performed to reduce video blocking artifacts in the video block.

[0054] The entropy coding unit 214 may receive data from other functional components of the video encoder 200. When the entropy coding unit 214 receives data, the entropy coding unit 214 may perform one or more entropy coding operations to generate entropy-coded data and output a bitstream including the entropy-coded data.

[0055] Figure 3 is a block diagram showing an example of a video decoder 300 according to some embodiments of the present disclosure, which may be Figure 1 An example of a video decoder 124 in the system 100 is shown.

[0056] Video decoder 300 may be configured to perform any or all of the techniques of this disclosure. Figure 3 In the example of , video decoder 300 includes multiple functional components. The techniques described in this disclosure can be shared between the various components of video decoder 300. In some examples, a processor can be configured to perform any or all of the techniques described in this disclosure.

[0057] exist Figure 3 In the example of , the video decoder 300 includes an entropy decoding unit 301, a motion compensation unit 302, an intra prediction unit 303, an inverse quantization unit 304, an inverse transform unit 305, and a reconstruction unit 306 and a buffer 307. In some examples, the video decoder 300 can perform a decoding process that is generally opposite to the encoding process described with respect to the video encoder 200.

[0058] The entropy decoding unit 301 can retrieve the encoded bitstream. The encoded bitstream may include entropy-encoded video data (e.g., blocks of encoded video data). The entropy decoding unit 301 can decode the entropy-encoded video data, and the motion compensation unit 302 can determine motion information from the entropy-encoded video data, the motion information including motion vectors, motion vector precision, reference picture list indexes, and other motion information. The motion compensation unit 302 can determine the information, for example, by performing AMVP and merge mode. AMVP is used, including deriving several most likely candidates based on data and reference pictures of adjacent PBs. The motion information typically includes horizontal and vertical motion vector displacement values, one or two reference picture indexes, and in the case of prediction areas in B strips, also includes an identification of which reference picture list is associated with each index. As used herein, in some aspects, "merge mode" may refer to deriving motion information from blocks that are adjacent in the spatial or temporal domain.

[0059] The motion compensation unit 302 may generate motion compensated blocks, possibly performing interpolation based on interpolation filters.Identifiers for the interpolation filters used with sub-pixel precision may be included in the syntax elements.

[0060] The motion compensation unit 302 may calculate interpolated values ​​for sub-integer pixels of a reference block using interpolation filters used by the video encoder 200 during encoding of the video block. The motion compensation unit 302 may determine the interpolation filters used by the video encoder 200 based on received syntax information, and the motion compensation unit 302 may use the interpolation filters to generate a prediction block.

[0061] The motion compensation unit 302 may use at least part of the syntax information to determine the size of blocks used to encode (multiple) frames and / or (multiple) slices of the encoded video sequence, partition information describing how each macroblock of a picture of the encoded video sequence is partitioned, a mode indicating how each partition is encoded, one or more reference frames (and reference frame lists) for each inter-coded block, and other information for decoding the encoded video sequence. As used herein, in some aspects, a "slice" may refer to a data structure that can be decoded independently of other slices of the same picture in terms of entropy coding and decoding, signal prediction, and residual signal reconstruction. A slice may be an entire picture, or it may be a region of a picture.

[0062] The intra prediction unit 303 may use, for example, an intra prediction mode received in the bitstream to form a prediction block from spatially neighboring blocks. The inverse quantization unit 304 inversely quantizes (i.e., dequantizes) the quantized video block coefficients provided in the bitstream and decoded by the entropy decoding unit 301. The inverse transform unit 305 applies an inverse transform.

[0063] The reconstruction unit 306 may obtain a decoded block, for example, by adding the residual block to the corresponding prediction block generated by the motion compensation unit 302 or the intra prediction unit 303. If necessary, a deblocking filter may also be applied to filter the decoded block to remove blocking artifacts. The decoded video block is then stored in a buffer 307, which provides reference blocks for subsequent motion compensation / intra prediction, and the buffer 307 also generates a decoded video for presentation on a display device.

[0064] Some example embodiments of the present disclosure will be described in detail below. It should be noted that the section titles used in this document are for ease of understanding, and the embodiments disclosed in the section are not limited to that section. In addition, although some embodiments are described with reference to a multifunctional video codec or other specific video codecs, the disclosed technology is also applicable to other video coding and decoding technologies. In addition, although some embodiments describe the video coding and decoding steps in detail, it should be understood that the corresponding decoding steps of the de-coding will be implemented by the decoder. In addition, the term video processing includes video coding or compression, video decoding or decompression, and video transcoding, in which video pixels are represented from one compression format to another compression format or at different compression bit rates. 1. Brief Overview The present disclosure relates to video coding techniques. Specifically, it relates to intra-frame block replication in video coding. The video coding techniques can be applied to standards that are being developed or planned, for example, next-generation video coding standards that exceed the general video coding standard (ITU-T Recommendation ITU-T H.266: General Video Codec, https: / / www.itu.int / rec / T-REC-H.266). The video coding techniques can also be used for future video coding standards or video codecs. 2. Introduction Video codec standards have evolved mainly through the development of the well-known ITU-T and ISO / IEC standards. ITU-T developed H.261 and H.263, ISO / IEC developed MPEG-1 and MPEG-4 Visual, and the two organizations jointly developed H.262 / MPEG-2 Video and H.264 / MPEG-4 Advanced Video Codec (AVC), H.265 / HEVC and the latest H.266 / Versatile Video Codec (VVC) standards. Since H.261, video codec standards are based on a hybrid video codec structure, where temporal prediction plus transform codec is used. In order to explore future video codec technologies beyond VVC, the Joint Video Exploration Team (JVET) started developing the Enhanced Compression Model in April 2021. Since then, JVET has adopted many new methods and put them into reference software. The latest software can be found at https: / / vcgit.hhi.fraunhofer.de / ecm / ECM / - / tags / ECM-4.0. 2.1 Virtual Pipeline Data Unit A Virtual Pipeline Data Unit (VPDU) is defined as a non-overlapping MxM-luma (L) / NxN-chroma (C) unit in a picture. In a hardware decoder, consecutive VPDUs are processed simultaneously by multiple pipeline stages; different stages process different VPDUs simultaneously. The VPDU size is roughly proportional to the buffer size in most pipeline stages, so it is very important to keep the VPDU size small. In the HEVC hardware decoder, the VPDU size is set to the maximum transform block (TB) size. In VVC, the VPDU size increases to 64x64-luma / 32x32-chroma for the 4:2:0 format. 2.2 Intra-frame Block Copying in VVC To support intra-block copy (IBC) in VVC, the concept of virtual buffer is used for reference buffer management. As in the JVET-T2001-v2 document, given the CTU size, i.e. CtbSizeY, the buffer width in luma samples is defined as: IbcBufWidthY=256*128 / CtbSizeY. The corresponding chroma IBC buffer is defined as: IbcBufWidthC=IbcBufWidthY / SubWidthC, Where SubWidthC depends on the chroma format defined in the following table. Table 1. SubWidthC and SubHeightC values ​​derived from sps_chroma_format_idc The height of the buffer in luma samples is CtbSizeY. In VVC, the VPDU concept is applied to achieve parallel decoding between different VPDUs within a CTU to increase decoding throughput. The VPDU size can be derived from the CTU size, as shown in the following table. Table 2. VPDU size derived from CTU size in VVC VVC only supports CTU sizes of 32x32, 64x64, and 128x128. At the start of decoding a CTU row in a slice, the luma IBC buffer is reset to -1. Before decoding a new VPDU, the luma buffer corresponding to the VPDU is also reset to -1. After the data of the decoded VPDU is completed before loop filtering, the corresponding buffer samples are updated with the VPDU data just reconstructed. After reconstructing the CU, the reconstructed samples before loop filtering are stored in the IBC buffer as follows (as described in the text of JVET-T2001-v2): For i=0..nCurrSw-1, j=0..nCurrSh-1, the following assignment is made: xVb=(xCurr+i)%((cIdx==0)?IbcBufWidthY:IbcBufWidthC) (1197) yVb=(yCurr+j)%((cIdx==0)?CtbSizeY:(CtbSizeY / subHeightC)) (1198) IbcVirBuf[cIdx][xVb][yVb]=recSamples[xCurr+i][yCurr+j] (1199) If the CU uses IBC mode, its prediction is formed as follows: When cIdx is equal to 0, for x=xCb..xCb+cbWidth-1 and y=yCb..yCb+cbHeight-1, the following applies: xVb=(x+(bv[0]>>4))&(IbcBufWidthY-1) (1096) yVb=(y+(bv[1]>>4))&(CtbSizeY-1) (1097) predSamples[x-xCb][y-yCb]=IbcVirBuf[0][xVb][yVb] (1098). When cIdx is not equal to 0, for x=xCb / SubWidthC..xCb / SubWidthC+cbWidth / SubWidthC-1 and y=yCb / SubHeightC..yCb / SubHeightC+cbHeight / SubHeightC-1, the following apply: xVb=(x+(bv[0]>>(3+SubWidthC)))&(IbcBufWidthC-1) (1099) yVb=(y+(bv[1]>>(3+SubHeightC)))&((CtbSizeY / subHeightC)-1) (1100) predSamples[x-(xCb / SubWidthC)][y-(yCb / SubHeightC)]=IbcVirBuf[cIdx][xVb][yVb] (1101). 2.3 Enhanced Compression Model After completing the first version of VVC, JVET began to develop a test model to explore further improvements to the coding efficiency of VVC. The test model is named the enhanced compression model. Many new coding tools (e.g., intra-frame temporal matching, dependent quantization with 8 states) are integrated into the VVC test model to improve coding efficiency. For a description of the newly added tools, please refer to "A. Browne, J. Chen, Y. Ye, S. Kim, "Algorithm description for Versatile Video Coding and Test Model 15 (VTM 15)," JVET-X2002". It should be noted that in ECM, the CTU size can be extended to 256x256. However, the IBC buffer with the extended CTU size and corresponding processing is undefined. 2.4 Intra-frame Template Matching Intra Template Matching Prediction (Intra TMP) is a special intra prediction mode that copies the best prediction block from the reconstructed part of the current frame, whose L-shaped template matches the current template. For a predefined search range, the encoder searches for the template that is most similar to the current template in the reconstructed part of the current frame and uses the corresponding block as the prediction block. The encoder then signals the use of this mode and performs the same prediction operation on the decoder side. The prediction signal is obtained by combining the L-shaped causal neighborhood of the current block with Figure 4 Another block of matches in the predefined search area is generated, including: R1: current CTU, R2: Upper left CTU, R3: Upper CTU, R4: Left CTU. SAD is used as the cost function. In each region, the decoder searches for the template with the minimum SAD relative to the current one and uses its corresponding block as the prediction block. The size of all regions (SearchRange_w, SearchRange_h) is set proportional to the block size (BlkW, BlkH) so that each pixel has a fixed number of SADs. That is: SearchRange_w=a*BlkW SearchRange_h=a*BlkH Where 'a' is a constant that controls the gain / complexity tradeoff. In practice, 'a' is equal to 5. The intra template matching tool is enabled for CUs of size less than or equal to 64 in width and height. This maximum CU size for intra template matching is configurable. Intra template matching prediction mode is signaled at CU level through a dedicated flag. 2.5 Merge Mode with MVD (MMVD) In addition to the merge mode, a merge mode with motion vector difference (MMVD) is introduced in VVC when the implicitly derived motion information is directly used for prediction sample generation of the current CU. The MMVD flag is signaled after sending the regular merge flag to specify whether the MMVD mode is used for the CU. In MMVD, after a merge candidate is selected, it is further refined by the MVD information transmitted by the signal. Further information includes a merge candidate flag, an index for specifying the magnitude of motion, and an index for indicating the direction of motion. In MMVD mode, one of the first two candidates in the merge list is selected to be used as the MV basis. The mmvd candidate flag is transmitted by the signal to specify which one to use between the first and second merge candidates. The distance index specifies the motion magnitude information and indicates a predefined offset from the starting point. Figure 5 As shown, the offset is added to the horizontal component or the vertical component of the starting MV. The relationship between the distance index and the predefined offset is specified in Table 3. Table 3. Relationship between distance index and predefined offset The direction index indicates the direction of the MVD relative to the starting point. The direction index can indicate four directions as shown in Table 4. It should be noted that the meaning of the MVD sign can change according to the information of the starting MV. When the starting MV is a non-predicted MV or a bidirectional predicted MV with two lists pointing to the same side of the current picture (i.e., the POCs of both references are greater than the POC of the current picture, or both are less than the POC of the current picture), the sign in Table 4 specifies the sign of the MV offset added to the starting MV. When the starting MV is a bidirectional predicted MV with two MVs pointing to different sides of the current picture (i.e., the POC of one reference is greater than the POC of the current picture, and the POC of the other reference is less than the POC of the current picture) and the POC difference in list 0 is greater than the POC difference in list 1, the sign in Table 4 specifies the sign of the MV offset added to the list 0 MV component of the starting MV, and the sign of the list 1 MV has an opposite value. Otherwise, if the POC difference in List 1 is greater than List 0, then the sign in Table 4 specifies the sign of the MV offset added to the List 1 MV component of the starting MV, and the sign of the List 0 MV has the opposite value. The MVD is scaled according to the POC difference in each direction. If the POC difference in both lists is the same, no scaling is required. Otherwise, if the POC difference in list 0 is greater than the POC difference in list 1, then the MVD of list 1 is scaled by defining the POC difference of L0 as td and the POC difference of L1 as tb. If the POC difference of L1 is greater than L0, then the MVD of list 0 is scaled in the same way. If the starting MV is unidirectionally predicted, then the MVD is added to the available MVs. Table 4. Sign of MV offset specified by direction index Directions to IDX 00 01 10 11 x-axis + - N / A N / A y-axis N / A N / A + - The syntax elements for direction index and distance index are mmvd_direction_idx and mmvd_distance_idx, respectively. mmvd_direction_idx is binarized using fixed length binarization and mmvd_distance_idx is binarized using truncated Rice binarization with cMax being 7 and cRiceParam being 0. The first bin of the binarized mmvd_distance_idx is encoded and decoded using CABAC with a specific context. 3. Potential Problems There are many problems when applying MMVD on block vectors, for example, the characteristics of block vectors are very different from those of motion vectors, which leads to inefficient representation of block vectors. This paper proposes several design points to improve the codec efficiency of block vector codecs. 4. Detailed solution In order to improve the encoding and decoding efficiency of block vectors, the method outlined below is disclosed. The embodiments should be considered as examples to explain the general concept and should not be interpreted in a narrow manner. In addition, these embodiments can be applied individually or in combination in any way. 1) The block vector (BVx, BVy) can be expressed as a function of the base candidate (BVPx, BVPy) and the index BVDI, i.e., (BVx, BVy) = f(BVPx, BVPy, BVDI). a. In one example, the base candidate (BVPx, BVPy) may be from a merge candidate, a spatial block vector candidate, a historical block vector candidate, a paired block vector candidate, or a constant block vector candidate. b. In one example, BVx=BVPx+fx(BVDI) and / or BVy=BVPy+fy(BVDI), where fx() and fy() represent functions with BVDI as input. c. In one example, BVx=BVPx+fx(BVPx, BVPy, BVDI) and / or BVy=BVPy+fy(BVPx, BVPy, BVDI), where fx() and fy() represent functions with BVPx, BVPy, BVDI as input. 2) The block vector (BVx, BVy) can be expressed as a function of the base candidate (BVPx, BVPy), the step index stepIdx and the direction index dirIdx, that is, (BVx, BVy) = f(BVP, BVPy, stepIdx, dirIdx). a. In one example, BVx=BVPx+fx(stepIdx,dirIdx) and / or BVy=BVPy+fy(stepIdx,dirIdx), where fx() and fy() represent functions with stepIdx and dirIdx as input. b. In one example, BVx=BVPx+fx(BVPx, BVPy, stepIdx, dirIdx) and / or BVy=BVPy+fy(BVPx, BVPy, stepIdx, dirIdx), where fx() and fy() represent functions with BVPx, BVPy, stepIdx, dirIdx as input. 3) The block vector (BVx, BVy) may be represented as a base candidate (BVPx, BVPy) added with a difference vector (BVDx, BVDy) which may be derived from the index BVDI. a. In one example, BVDx can be a function of BVDI. b. In one example, BVDy may be a function of BVDI. c. In one example, when BVPx is equal to 0, BVDx can be derived as 0. d. In one example, when BVPy is equal to 0, BVDy can be derived as 0. e. In one example, the function that derives BVDy may depend on whether BVPx is equal to zero. f. In one example, the function that derives BVDx may depend on whether BVPy is equal to zero. g. In one example, the function that derives BVDy may depend on whether BVPy is equal to zero. h. In one example, the function that derives BVDx may depend on whether BVPx is equal to zero. 4) The block vector (BVx, BVy) can be represented as a base candidate (BVPx, BVPy) added with a difference vector (BVDx, BVDy), which can be derived from the step index stepIdx and the direction index dirIdx. a. In one example, BVDx can be a function of stepIdx and dirIdx. b. In one example, BVDy may be a function of stepIdx and dirIdx. c. In one example, when BVPx is equal to 0, BVDx can be derived as 0. d. In one example, when BVPy is equal to 0, BVDy can be derived as 0. e. In one example, the function that derives BVDy may depend on whether BVPx is equal to zero. f. In one example, the function that derives BVDx may depend on whether BVPy is equal to zero. g. In one example, the function that derives BVDy may depend on whether BVPy is equal to zero. h. In one example, the function that derives BVDx may depend on whether BVPx is equal to zero. 5) BVDI or part of BVDI can be binarized using EGk binarization. a. In one example, BVDI>>1 can be binarized using EGk binarization. b. In one example, BVDI>>2 can be binarized using EGk binarization. c. In one example, BVDI>>k (eg, k is a positive integer) can be binarized using EGk binarization. 6) stepIdx or part of stepIdx can be binarized using EGk binarization. a. In one example, stepIdx>>1 can be binarized using EGk binarization. b. In one example, stepIdx>>2 can be binarized using EGk binarization. c. In one example, stepIdx>>k (eg, k is a positive integer) may be binarized using EGk binarization. 7) The last k bits (eg, k is a positive integer) of the BVDI may be binarized using fixed-length binarization. a. In one example, the last bit of BVDI may be binarized using fixed length binarization. b. In one example, the last two bits of BVDI may be binarized using fixed-length binarization. 8) The last k bits (eg, k is a positive integer) of stepIdx may be binarized using fixed-length binarization. a. In one example, the last bit of stepldx may be binarized using fixed-length binarization. b. In one example, the last two bits of stepldx may be binarized using fixed-length binarization. 9) BVDI can have a maximum and / or minimum value. 10) In one example, the step size difference between two adjacent step sizes may have a limit. a. In one example, the step size difference between two adjacent step sizes may be fixed. i. In one example, the step size difference between two adjacent step sizes may be k (eg, k=1). ii. In one example, the step size difference between two adjacent step sizes may be k (eg, k=2). b. In one example, the step size difference between two adjacent step sizes may be adaptive. c. In one example, the step size difference between two adjacent step sizes may not be greater than k. i. In one example, k can be 4. ii. In one example, k may be 8. iii. In one example, k may be 16. d. In one example, the step size difference between two adjacent step sizes can be adaptively set according to the step size value. i. In one example, if the larger step size is ≤ S1, the step size difference between two adjacent step sizes can be set to k1; if the larger step size is ≤ S2 and > S1, the step size difference between two adjacent step sizes can be set to k2; if the larger step size is > S2, the step size difference between two adjacent step sizes can be set to k3. For example, k1=1, k2=2, k3=4, S1=64, S2=128 11) Abs(BVDx)-1 and / or Abs(BVDy)-1 may be binarized using an EGk (k>1) binarization process. a. In one example, Abs(BVDx)-1 can be binarized using the EG2 / EG3 / EG4 / EG5 binarization process. i. In one example, the binarized code may be bypass coded. b. In one example, Abs(BVDy)-1 can be binarized using the EG2 / EG3 / EG4 / EG5 binarization process. i. In one example, the binarized code may be bypass coded. c. In one example, whether BVDx is equal to 0 may be context-coded. i. In one example, the context may depend on BVPx and / or BVPy. d. In one example, whether BVDy is equal to 0 may be context-coded. i. In one example, the context may depend on BVPx and / or BVPy. 5. Examples 5.1 Example #1 The block vector (BVx, BVy) is derived by the following equation: BVx=BVPx+BVDx BVy=BVPy+BVDy in It can be seen in Figure 6 . 5.2 Example #2 The block vector (BVx, BVy) is obtained by the following equation: BVx=BVPx+BVDx, BVy=BVPy+BVDy. When BVPx is equal to 0, BVDx can be set to 0 and BVDy is derived as When BVPy is equal to 0, BVDy can be set to 0, and BVDx is derived as Figure 7a An example of deriving BVDy from BVDI when BVPx=0 is shown, and Figure 7b An example of deriving BVDx from BVDI when BVPy=0 is shown. When BVPx and BVPy are both equal to 0 or both are not equal to 0, BVDx and BVDy can be derived by following the method described in Example #1. 5.3 Example #3 Exemplary encoding and decoding of (BVDx, BVDy) for reflecting item 11. abs_bvd_greater0_flag[x] is context coded. mvd_sign_flag and abs_bvd_minus1[x] are bypass coded.

[0065] As used herein, the term "video unit" or "video block" may be a sequence, picture, slice, tile, brick, sub-picture, codec tree unit (CTU) / codec tree block (CTB), CTU / CTB row, one or more codec units (CU) / codec blocks (CB), one or more CTU / CTB, one or more virtual pipeline data units (VPDU), sub-region within a picture / slice / tile / brick. The term "image compression" may refer to any variation of a signal processing method that compresses or processes the current input. Input images / videos include, but are not limited to, screen content and natural content.

[0066] Figure 8 A flow chart of a method 800 for video processing according to an embodiment of the present disclosure is shown. The method 800 is implemented during conversion between a video unit of a video and a bitstream of the video.

[0067] At block 810, for conversion between a video unit of a video and a bitstream of the video, a block vector of the video unit is determined based on a base block vector candidate and a parameter associated with a block vector difference. In other words, the block vector may be obtained by encoding / decoding the base block vector candidate and the parameter. In some embodiments, the base block vector candidate may include one of the following: a merge candidate, a spatial block vector candidate, a historical block vector candidate, a paired block vector candidate, or a constant block vector candidate.

[0068] At block 820, conversion is performed based on the block vector. In some embodiments, the conversion may include encoding the video unit into a bitstream. Alternatively or additionally, the conversion may include decoding the video unit from the bitstream. In this way, the codec efficiency of the block vector codec may be improved.

[0069] In some embodiments, the parameters related to the block vector difference include a base vector difference index (BVDI). In this case, the block vector is represented based on the base block vector candidate and the BVDI. For example, the block vector is represented as: (BVx, BVy) = f(BVPx, BVPy, BVDI), where BVx is the first element of the block vector and BVy is the second element of the block vector, the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and f() represents a function of the base block vector candidate and BVDI. In other words, the block vector (BVx, BVy) can be represented as a function of the base candidate (BVPx, BVPy) and the index BVDI, that is, (BVx, BVy) = f(BVPx, BVPy, BVDI).

[0070] In some embodiments, BVx=BVPx+fx(BVDI) and / or BVy=BVPy+fy(BVDI), and wherein fx() and fy() represent functions with BVDI as input. In some other embodiments, BVx=BVPx+fx(BVPx, BVPy, BVDI) and / or BVy=BVPy+fy(BVPx, BVPy, BVDI), and wherein fx() and fy() represent functions with BVPx, BVPy, BVDI as input.

[0071] In some embodiments, the parameters related to the block vector difference include a difference vector derived from the BVDI. In this case, the block vector is represented as a base block vector candidate added to the difference vector. For example, the block vector is represented as (BVx, BVy), BVx is the first element of the block vector, and BVy is the second element of the block vector, the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and the difference vector is represented as (BVDx, BVDy), BVDx is the first element of the difference vector, and BVDy is the second element of the difference vector. As an example, the block vector (BVx, BVy) can be represented as a function of the base candidate (BVPx, BVPy), the step index stepIdx and the direction index dirIdx, that is, (BVx, BVy) = f(BVPx, BVPy, stepIdx, dirIdx).

[0072] In some embodiments, BVDx is a function of BVDI. In some other embodiments, BVDy is a function of BVDI.

[0073] In some embodiments, if BVPx is equal to 0, then BVDx is derived as 0. In some other embodiments, if BVPy is equal to 0, then BVDy is derived as 0.

[0074] In some embodiments, the function from which BVDy is derived depends on whether BVPx is equal to 0. In some other embodiments, the function from which BVDx is derived depends on whether BVPy is equal to 0.

[0075] In some embodiments, the function from which BVDy is derived depends on whether BVPy is equal to 0. In some other embodiments, the function from which BVDx is derived depends on whether BVPx is equal to 0.

[0076] In some embodiments, the BVDI may include a maximum value. Alternatively or additionally, the BVDI may include a minimum value.

[0077] In some embodiments, the parameters related to the block vector difference include a step index and a direction index. In this case, the block vector is represented based on the base block vector candidate, the step index and the direction index.

[0078] In some embodiments, (BVx, BVy) = f(BVPx, BVPy, stepIdx, dirIdx), and ((BVx, BVy) represents a block vector, (BVPx, BVPy) represents a base block vector candidate, f() represents a function of the base block vector candidate, a step index and a direction index, stepIdx represents the step index, and dirIdx represents the direction index. For example, the block vector (BVx, BVy) can be expressed as a function of the base candidate (BVPx, BVPy), the step index stepIdx and the direction index dirIdx, that is, (BVx, BVy) = f(BVPx, BVPy, stepIdx, dirIdx).

[0079] In some embodiments, BVx=BVPx+fx(stepIdx,dirIdx) and / or BVy=BVPy+fy(stepIdx,dirIdx), and wherein fx() and fy() represent functions with stepIdx and dirIdx as inputs. In some other embodiments, BVx=BVPx+fx(BVPx,BVPy,stepIdx,dirIdx) and / or BVy=BVPy+fy(BVPx,BVPy,stepIdx,dirIdx), and wherein fx() and fy() represent functions with BVPx, BVPy, stepIdx, and dirIdx as inputs.

[0080] In some embodiments, the parameters related to the block vector difference include a difference vector derived from a step index and a direction index. In this case, the block vector can be represented as a base block vector candidate added to the difference vector. For example, the block vector is represented as (BVx, BVy), BVx is the first element of the block vector, and BVy is the second element of the block vector, the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and the difference vector is represented as (BVDx, BVDy), BVDx is the first element of the difference vector, and BVDy is the second element of the difference vector. For example, the block vector (BVx, BVy) can be represented as a base candidate (BVPx, BVPy) added to the difference vector (BVDx, BVDy), and the difference vector can be derived from the step index stepIdx and the direction index dirIdx.

[0081] In some embodiments, BVDx is a function of a step index and a direction index. In some other embodiments, BVDy is a function of a step index and a direction index.

[0082] In some embodiments, if BVPx is equal to 0, then BVDx is derived as 0. In some other embodiments, if BVPy is equal to 0, then BVDy is derived as 0.

[0083] In some embodiments, the function from which BVDy is derived depends on whether BVPx is equal to 0. In some other embodiments, the function from which BVDx is derived depends on whether BVPy is equal to 0.

[0084] In some embodiments, the function from which BVDy is derived depends on whether BVPy is equal to 0. In some other embodiments, the function from which BVDx is derived depends on whether BVPx is equal to 0.

[0085] In some embodiments, the step difference of the block vector between two adjacent step sizes has a value that follows a constraint. For example, in some embodiments, the step difference between two adjacent step sizes is fixed. In some embodiments, the step difference between two adjacent step sizes is equal to k, and where k is an integer. In some embodiments, k is equal to 1 or 2.

[0086] Alternatively, the step length difference between two adjacent step lengths is adaptive. In some embodiments, the step length difference between two adjacent step lengths is not greater than a predetermined number. In some embodiments, the predetermined number is one of the following: 4, 8 or 16.

[0087] In some embodiments, the step difference between two adjacent step sizes is adaptive according to the step value. For example, if the larger step size of two adjacent step sizes is not greater than S1, the step difference between the two adjacent step sizes is set to k1, and / or if the larger step size is not greater than S2 and greater than S1, the step difference between the two adjacent step sizes is set to k2, and / or if the larger step size is greater than S2, the step difference between the two adjacent step sizes is set to k3, and wherein k1, k2, k3, S1, and S2 are integers. In some embodiments, k1=1, k2=2, k3=4, S1=64, S2=128.

[0088] In some embodiments, BVDI or a portion of BVDI is binarized using EGk binarization. In some embodiments, BVDI with one bit right shift is binarized using EGk binarization. In one example, BVDI>>1 can be binarized using EGk binarization. In some other embodiments, BVDI with two bits right shift is binarized using EGk binarization. In one example, BVDI>>2 can be binarized using EGk binarization. In some embodiments, BVDI with k bits right shift is binarized using EGk binarization, where k is a positive integer. In one example, BVDI>>k (e.g., k is a positive integer) can be binarized using EGk binarization.

[0089] In some embodiments, the step index or a portion of the step index can be binarized using a specific binarization. In some embodiments, the step index with a one-bit right shift is binarized using a specific binarization. In one example, stepIdx>>1 can be binarized using EGk binarization. In some embodiments, the step index with a two-bit right shift is binarized using a specific binarization. In one example, stepIdx>>2 can be binarized using EGk binarization. In some embodiments, the step index with a k-bit right shift is binarized using a specific binarization, where k is a positive integer. In one example, stepIdx>>k (e.g., k is a positive integer) can be binarized using EGk binarization.

[0090] In some embodiments, the last k bits of BVDI are binarized using fixed length binarization, where k is a positive integer. In some embodiments, the last bit of BVDI is binarized using fixed length binarization. Alternatively or additionally, the last two bits of BVDI are binarized using fixed length binarization.

[0091] In some embodiments, the last k bits of the step index are binarized using fixed length binarization, where k is a positive integer. In some embodiments, the last bit of the step index is binarized using fixed length binarization. Alternatively or additionally, the last two bits of the step index are binarized using fixed length binarization.

[0092] In some embodiments, the absolute value of BVDx minus a predefined number is binarized using a specific binarization process. Alternatively or additionally, the absolute value of BVDy minus a predefined number is binarized using a specific binarization process. For example, Abs(BVDx)-1 and / or Abs(BVDy)-1 can be binarized using an EGk (k>1) binarization process.

[0093] In some embodiments, the specific binarization process includes one of the following: EG2 binarization process, EG3 binarization process, EG4 binarization process or EG5 binarization process. In one example, Abs(BVDx)-1 can be binarized using EG2 / EG3 / EG4 / EG5 binarization process. In one example, Abs(BVDy)-1 can be binarized using EG2 / EG3 / EG4 / EG5 binarization process. In some embodiments, the binarized code is bypass encoded and decoded.

[0094] In some embodiments, whether BVDx is equal to 0 is context-coded. In one embodiment, the context depends on at least one of: BVPx or BVPy.

[0095] In some embodiments, whether BVDy is equal to 0 is context-coded. In an example embodiment, the context depends on at least one of: BVPx or BVPy.

[0096] According to another embodiment of the present disclosure, a non-transitory computer-readable recording medium is provided. The non-transitory computer-readable recording medium stores a bitstream of a video generated by a method performed by a video processing device. The method includes: determining a block vector of a video unit of the video based on a base block vector candidate and a parameter related to a block vector difference; and generating a bitstream based on the block vector.

[0097] According to some other embodiments of the present disclosure, a method for storing a bitstream of a video is provided. The method includes: determining a block vector of a video unit of the video based on a base block vector candidate and a parameter related to a block vector difference; generating a bitstream based on the block vector; and storing the bitstream in a non-transitory computer-readable recording medium.

[0098] The embodiments of the present disclosure may be described by the following clauses, features of which may be combined in any reasonable way.

[0099] Clause 1. A video processing method, comprising: for conversion between a video unit of a video and a bitstream of the video, determining a block vector of the video unit based on base block vector candidates and parameters related to block vector differences; and performing the conversion based on the block vector.

[0100] Clause 2. The method of clause 1, wherein the parameter related to the block vector difference comprises a basis vector difference index (BVDI), and wherein the block vector is represented based on the basis block vector candidates and the BVDI.

[0101] Clause 3. A method according to clause 2, wherein the block vector is represented as: (BVx, BVy) = f(BVPx, BVPy, BVDI), where BVx is the first element of the block vector and BVy is the second element of the block vector, the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and f() represents a function of the base block vector candidate and the BVDI.

[0102] Clause 4. A method according to any one of clauses 1-3, wherein the base block vector candidate comprises one of the following: a merge candidate, a spatial block vector candidate, a historical block vector candidate, a paired block vector candidate, or a constant block vector candidate.

[0103] Clause 5. The method of clause 3, wherein BVx=BVPx+fx(BVDI), and / or BVy=BVPy+fy(BVDI), and wherein fx() and fy() represent functions with BVDI as input.

[0104] Clause 6. A method according to clause 3, wherein BVx = BVPx + fx(BVPx, BVPy, BVDI), and / or BVy = BVPy + fy(BVPx, BVPy, BVDI), and wherein fx() and fy() represent functions with BVPx, BVPy, BVDI as input.

[0105] Clause 7. A method according to clause 1, wherein the parameters related to the block vector difference include a difference vector derived from a BVDI, wherein the block vector is represented as the base block vector candidate added to the difference vector, and wherein the block vector is represented as (BVx, BVy), BVx is the first element of the block vector, and BVy is the second element of the block vector, wherein the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and wherein the difference vector is represented as (BVDx, BVDy), BVDx is the first element of the difference vector, and BVDy is the second element of the difference vector.

[0106] Clause 8. The method of clause 7, wherein BVDx is a function of the BVDI.

[0107] Clause 9. The method of clause 7, wherein BVDy is a function of the BVDI.

[0108] Clause 10. The method of clause 7, wherein if BVPx is equal to 0, then BVDx is derived as 0.

[0109] Clause 11. The method of clause 7, wherein if BVPy is equal to 0, then BVDy is derived as 0.

[0110] Clause 12. The method of clause 7, wherein the function for deriving BVDy depends on whether BVPx is equal to zero.

[0111] Clause 13. The method of clause 7, wherein the function for deriving BVDx depends on whether BVPy is equal to zero.

[0112] Clause 14. The method of clause 7, wherein the function for deriving BVDy depends on whether BVPy is equal to zero.

[0113] Clause 15. The method of clause 7, wherein the function for deriving BVDx depends on whether BVPx is equal to zero.

[0114] Clause 16. The method of any one of clauses 1 to 15, wherein the BVDI comprises at least one of: a maximum value or a minimum value.

[0115] Clause 17. The method of clause 1, wherein the parameters related to the block vector difference include a step index and a direction index; and wherein the block vector is represented based on the basis block vector candidate, the step index and the direction index.

[0116] Clause 18. A method according to clause 17, wherein (BVx, BVy) = f(BVPx, BVPy, stepIdx, dirIdx), and wherein (BVx, BVy) represents the block vector, (BVPx, BVPy) represents the base block vector candidate, f() represents the function of the base block vector candidate, the step index and the direction index, stepIdx represents the step index, and dirIdx represents the direction index.

[0117] Clause 19. The method of clause 17, wherein BVx=BVPx+fx(stepIdx,dirIdx), and / or BVy=BVPy+fy(stepIdx,dirIdx), and wherein fx() and fy() represent functions with stepIdx, dirIdx as input.

[0118] Clause 20. A method according to clause 17, wherein BVx = BVPx + fx(BVPx, BVPy, stepIdx, dirIdx), and / or BVy = BVPy + fy(BVPx, BVPy, stepIdx, dirIdx), and wherein fx() and fy() represent functions with BVPx, BVPy, stepIdx, dirIdx as input.

[0119] Clause 21. A method according to clause 1, wherein the parameters related to the block vector difference include a difference vector derived from a step index and a direction index, wherein the block vector is represented as the base block vector candidate to which the difference vector has been added, and wherein the block vector is represented as (BVx, BVy), BVx is the first element of the block vector, and BVy is the second element of the block vector, wherein the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and wherein the difference vector is represented as (BVDx, BVDy), BVDx is the first element of the difference vector, and BVDy is the second element of the difference vector.

[0120] Clause 22. The method of clause 21, wherein BVDx is a function of the step index and the direction index.

[0121] Clause 23. The method of clause 21, wherein BVDy is a function of the step index and the direction index.

[0122] Clause 24. The method of clause 21, wherein if BVPx is equal to 0, then BVDx is derived as 0.

[0123] Clause 25. The method of clause 21, wherein if BVPy is equal to 0, then BVDy is derived as 0.

[0124] Clause 26. The method of clause 21, wherein the function for deriving BVDy depends on whether BVPx is equal to zero.

[0125] Clause 27. The method of clause 21, wherein the function for deriving BVDx depends on whether BVPy is equal to zero.

[0126] Clause 28. The method of clause 21, wherein the function for deriving BVDy depends on whether BVPy is equal to zero.

[0127] Clause 29. The method of clause 21, wherein the function for deriving BVDx depends on whether BVPx is equal to zero.

[0128] Clause 30. A method according to any of clauses 1-29, wherein a step size difference of the block vector between two adjacent step sizes has a value that complies with a constraint.

[0129] Clause 31. The method of clause 30, wherein the step size difference between the two adjacent step sizes is fixed.

[0130] Clause 32. The method of clause 31, wherein the step size difference between the two adjacent step sizes is equal to k, and wherein k is an integer.

[0131] Clause 33. The method according to clause 32, wherein k is equal to 1 or 2.

[0132] Clause 34. The method of clause 30, wherein the step size difference between the two adjacent step sizes is adaptive.

[0133] Clause 35. The method of clause 30, wherein the step size difference between the two adjacent step sizes is no greater than a predetermined number.

[0134] Clause 36. The method of clause 35, wherein the predetermined number is one of: 4, 8, or 16.

[0135] Clause 37. The method of clause 30, wherein the step size difference between the two adjacent step sizes is adaptive according to a step size value.

[0136] Clause 38. A method according to Clause 37, wherein if the larger step size of the two adjacent step sizes is not greater than S1, the step size difference between the two adjacent step sizes is set to k1, and / or if the larger step size is not greater than S2 and is greater than S1, the step size difference between the two adjacent step sizes is set to k2, and / or if the larger step size is greater than S2, the step size difference between the two adjacent step sizes is set to k3, and wherein k1, k2, k3, S1 and S2 are integers.

[0137] Clause 39. The method of clause 38, wherein k1=1, k2=2, k3=4, S1=64, S2=128.

[0138] Clause 40. The method of any one of clauses 1 to 39, wherein the BVDI or a portion of the BVDI is binarized using EGk binarization.

[0139] Clause 41. The method of clause 40, wherein the BVDI with a one-bit right shift is binarized using EGk binarization.

[0140] Clause 42. The method of clause 40, wherein the BVDI with a two-bit right shift is binarized using EGk binarization.

[0141] Clause 43. The method of clause 40, wherein the BVDI with a k-bit right shift is binarized using EGk binarization, where k is a positive integer.

[0142] Clause 44. A method according to any one of clauses 1 to 39, wherein the step index or a portion of the step index is binarized using a specific binarization.

[0143] Clause 45. The method of clause 44, wherein the step index with a one-bit right shift is binarized using the particular binarization.

[0144] Clause 46. The method of clause 44, wherein the stride index with a two-bit right shift is binarized using the particular binarization.

[0145] Clause 47. The method of clause 44, wherein the step index with a k-bit right shift is binarized using a specific binarization, where k is a positive integer.

[0146] Clause 48. The method of any one of clauses 1 to 39, wherein the last k bits of the BVDI are binarized using fixed-length binarization, where k is a positive integer.

[0147] Clause 49. The method of clause 48, wherein the last bit of the BVDI is binarized using the fixed-length binarization, or wherein the last two bits of the BVDI are binarized using the fixed-length binarization.

[0148] Clause 50. The method of any one of clauses 1 to 39, wherein the last k bits of the step index are binarized using fixed length binarization, where k is a positive integer.

[0149] Clause 51. The method of clause 50, wherein the last bit of the step index is binarized using the fixed-length binarization, or wherein the last two bits of the step index are binarized using the fixed-length binarization.

[0150] Clause 52. A method according to any one of clauses 1 to 39, wherein BVDx minus the absolute value of a predefined number is binarized using a specific binarization process, and / or wherein BVDy minus the absolute value of the predefined number is binarized using the specific binarization process.

[0151] Clause 53. The method according to Clause 52, wherein the specific binarization process includes one of the following: an EG2 binarization process, an EG3 binarization process, an EG4 binarization process, or an EG5 binarization process.

[0152] Clause 54. The method of clause 53, wherein the binarized code is bypass encoded.

[0153] Clause 55. The method of clause 52, wherein whether BVDx is equal to 0 is context-coded.

[0154] Clause 56. The method of clause 55, wherein the context depends on at least one of: BVPx or BVPy.

[0155] Clause 57. The method of clause 52, wherein whether BVDy is equal to 0 is context-coded.

[0156] Clause 58. The method of clause 57, wherein the context depends on at least one of: BVPx or BVPy.

[0157] Clause 59. The method of any one of clauses 1 to 58, wherein the converting comprises encoding the video unit into the bitstream.

[0158] Clause 60. The method of any one of clauses 1 to 58, wherein the converting comprises decoding the video unit from the bitstream.

[0159] Clause 61. An apparatus for video processing, comprising a processor and a non-transitory memory having instructions thereon, wherein the instructions, when executed by the processor, cause the processor to perform the method of any one of clauses 1 to 60.

[0160] Clause 62. A non-transitory computer-readable storage medium storing instructions that cause a processor to perform the method of any one of clauses 1 to 60.

[0161] Item 63. A non-transitory computer-readable recording medium storing a bitstream of a video, the bitstream being generated by a method performed by a video processing device, wherein the method comprises: determining a block vector of a video unit of the video based on base block vector candidates and parameters related to block vector differences; and generating the bitstream based on the block vectors.

[0162] Clause 64. A method for storing a bitstream of a video, comprising: determining a block vector of a video unit of the video based on base block vector candidates and parameters related to block vector differences; generating the bitstream based on the block vectors; and storing the bitstream in a non-transitory computer-readable recording medium. Example Device

[0163] Fig. 9 A block diagram of a computing device 900 in which various embodiments of the present disclosure may be implemented is shown. The computing device 900 may be implemented as a source device 110 (or video encoder 114 or 200) or a destination device 120 (or video decoder 124 or 300), or may be included in a source device 110 (or video encoder 114 or 200) or a destination device 120 (or video decoder 124 or 300).

[0164] It should be understood that Fig. 9 The computing device 900 shown in FIG. 9 is for illustrative purposes only and is not intended to in any way imply any limitation on the functionality and scope of the embodiments of the present disclosure.

[0165] like Fig. 9 As shown, computing device 900 includes a general computing device 900. Computing device 900 may include at least one or more processors or processing units 910, memory 920, storage unit 930, one or more communication units 940, one or more input devices 950, and one or more output devices 960.

[0166] In some embodiments, the computing device 900 can be implemented as any user terminal or server terminal with computing capabilities. The server terminal can be a server provided by a service provider, a large computing device, etc. The user terminal can be, for example, any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a station, a unit, a device, a multimedia computer, a multimedia tablet computer, an Internet node, a communicator, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an electronic book device, a gaming device, or any combination thereof, and includes the accessories and peripherals of these devices, or any combination thereof. It is conceivable that the computing device 900 can support any type of interface to the user (such as a "wearable" circuit device, etc.).

[0167] The processing unit 910 may be a physical processor or a virtual processor and may implement various processes based on a program stored in the memory 920. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the computing device 900. The processing unit 910 may also be referred to as a central processing unit (CPU), a microprocessor, a controller, or a microcontroller.

[0168] The computing device 900 typically includes various computer storage media. Such media can be any media accessible by the computing device 900, including but not limited to volatile media and non-volatile media, or removable media and non-removable media. The memory 920 can be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (such as a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM) or flash memory) or any combination thereof. The storage unit 930 can be any removable or non-removable medium, and can include machine-readable media, such as a memory, a flash drive, a disk or other media that can be used to store information and / or data and can be accessed in the computing device 900.

[0169] The computing device 900 may also include additional removable / non-removable storage media, volatile / non-volatile storage media. Fig. 9 Although not shown in the figure, a magnetic disk drive for reading from and / or writing to a removable nonvolatile magnetic disk and an optical disk drive for reading from and / or writing to a removable nonvolatile optical disk may be provided. In this case, each drive may be connected to the bus (not shown) via one or more data medium interfaces.

[0170] The communication unit 940 communicates with another computing device via a communication medium. In addition, the functions of the components in the computing device 900 can be implemented by a single computing cluster or multiple computing machines that can communicate via a communication connection. Therefore, the computing device 900 can operate in a networked environment using logical connections to one or more other servers, networked personal computers (PCs), or other general network nodes.

[0171] The input device 950 may be one or more of various input devices, such as a mouse, keyboard, trackball, voice input device, etc. The output device 960 may be one or more of various output devices, such as a display, a speaker, a printer, etc. With the aid of the communication unit 940, the computing device 900 may also communicate with one or more external devices (not shown), such as storage devices and display devices, and the computing device 900 may also communicate with one or more devices that enable a user to interact with the computing device 900, or any device that enables the computing device 900 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.), if necessary. Such communication may be performed via an input / output (I / O) interface (not shown).

[0172] In some embodiments, some or all components of the computing device 900 may also be arranged in a cloud computing architecture rather than being integrated in a single device. In a cloud computing architecture, components may be provided remotely and work together to implement the functions described in the present disclosure. In some embodiments, cloud computing provides computing, software, data access and storage services, which will not require the end user to know the physical location or configuration of the system or hardware that provides these services. In various embodiments, cloud computing provides services via a wide area network (e.g., the Internet) using a suitable protocol. For example, a cloud computing provider provides applications via a wide area network, which can be accessed through a web browser or any other computing component. The software or components of the cloud computing architecture and the corresponding data may be stored on a remote server. The computing resources in a cloud computing environment may be merged or distributed at the location of a remote data center. Cloud computing infrastructures may provide services through a shared data center, although they appear as a single access point for users. Therefore, cloud computing architectures may be used to provide components and functions described herein from a service provider at a remote location. Alternatively, they may be provided by a conventional server, or installed directly or otherwise on a client device.

[0173] In an embodiment of the present disclosure, the computing device 900 may be used to implement video encoding / decoding. The memory 920 may include one or more video encoding / decoding modules 925 having one or more program instructions. These modules can be accessed and executed by the processing unit 910 to perform the functions of the various embodiments described herein.

[0174] In an example embodiment performing video encoding, input device 950 may receive video data as input to be encoded 970. The video data may be processed, for example, by video codec module 925 to generate an encoded bitstream. The encoded bitstream may be provided as output 980 via output device 960.

[0175] In an example embodiment performing video encoding, input device 950 may receive video data as input to be encoded 970. The video data may be processed by, for example, video codec module 925 to generate an encoded bitstream. The encoded bitstream may be provided as output 980 via output device 960.

[0176] Although the present disclosure has been specifically shown and described with reference to the preferred embodiments of the present disclosure, it will be understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present application as defined by the appended claims. These changes are intended to be encompassed by the scope of the present application. Therefore, the foregoing description of the embodiments of the present application is not intended to be limiting.

Claims

1. A video processing method, comprising: For conversion between a video unit of a video and a bitstream of the video, determining a block vector of the video unit based on base block vector candidates and parameters related to block vector differences; as well as The conversion is performed based on the block vector.

2. The method of claim 1 , wherein the parameters related to the block vector difference comprise a basis vector difference index (BVDI), and Wherein the block vector is represented based on the base block vector candidate and the BVDI.

3. The method according to claim 2, wherein the block vector is represented as: (BVx,BVy)=f(BVPx,BVPy,BVDI), Wherein BVx is the first element of the block vector and BVy is the second element of the block vector, the base block vector candidate is expressed as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and f() represents a function of the base block vector candidate and the BVDI.

4. The method according to any one of claims 1 to 3, wherein the base block vector candidate comprises one of the following: Merge candidates, Spatial block vector candidates, Historical block vector candidates, Paired block vector candidates, or Constant block vector candidates.

5. The method according to claim 3, wherein BVx = BVPx + fx (BVDI), and / or BVy=BVPy+fy(BVDI), and Where fx() and fy() represent functions with BVDI as input.

6. The method according to claim 3, wherein BVx = BVPx + fx (BVPx, BVPy, BVDI), and / or BVy=BVPy+fy(BVPx,BVPy,BVDI), and Where fx() and fy() represent functions with BVPx, BVPy, and BVDI as input.

7. The method of claim 1 , wherein the parameter related to the block vector difference comprises a difference vector derived from a BVDI, wherein the block vector is represented as the basis block vector candidate added to the difference vector, and wherein the block vector is represented as (BVx, BVy), BVx is the first element of the block vector, and BVy is the second element of the block vector, wherein the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and Wherein the difference vector is represented as (BVDx, BVDy), BVDx is the first element of the difference vector, and BVDy is the second element of the difference vector. The method of claim 7 , wherein BVDx is a function of the BVDI.

9. The method of claim 7, wherein BVDy is a function of the BVDI.

10. The method of claim 7, wherein if BVPx is equal to 0, then BVDx is derived as 0. The method of claim 7 , wherein if BVPy is equal to 0, then BVDy is derived as 0.

12. The method of claim 7, wherein the function for deriving BVDy depends on whether BVPx is equal to 0. The method of claim 7 , wherein the function for deriving BVDx depends on whether BVPy is equal to zero. The method of claim 7 , wherein the function for deriving BVDy depends on whether BVPy is equal to zero. The method of claim 7 , wherein the function for deriving BVDx depends on whether BVPx is equal to zero.

16. The method according to any one of claims 1 to 15, wherein the BVDI comprises at least one of the following: a maximum value or a minimum value.

17. The method of claim 1, wherein the parameters associated with the block vector difference include a step index and a direction index; and The block vector is represented based on the base block vector candidate, the step index and the direction index.

18. The method of claim 17, wherein (BVx, BVy) = f(BVPx, BVPy, stepIdx, dirIdx), and Wherein (BVx, BVy) represents the block vector, (BVPx, BVPy) represents the base block vector candidate, f() represents the function of the base block vector candidate, the step index and the direction index, stepIdx represents the step index, and dirIdx represents the direction index.

19. The method of claim 17, wherein BVx = BVPx + fx (stepIdx, dirIdx), and / or BVy=BVPy+fy(stepIdx,dirIdx), and Where fx() and fy() represent functions with stepIdx and dirIdx as input.

20. The method of claim 17, wherein BVx = BVPx + fx (BVPx, BVPy, stepIdx, dirIdx), and / or BVy=BVPy+fy(BVPx,BVPy,stepIdx,dirIdx), and Where fx() and fy() represent functions with BVPx, BVPy, stepIdx, and dirIdx as input.

21. The method of claim 1, wherein the parameters related to the block vector difference include a difference vector derived from a step size index and a direction index, wherein the block vector is represented as the base block vector candidate to which the difference vector has been added, and wherein the block vector is represented as (BVx, BVy), BVx is the first element of the block vector, and BVy is the second element of the block vector, wherein the base block vector candidate is represented as (BVPx, BVPy), BVPx is the first element of the base block vector candidate, and BVPy is the second element of the base block vector candidate, and Wherein the difference vector is represented as (BVDx, BVDy), BVDx is the first element of the difference vector, and BVDy is the second element of the difference vector.

22. The method of claim 21, wherein BVDx is a function of the step index and the direction index.

23. The method of claim 21, wherein BVDy is a function of the step index and the direction index.

24. The method of claim 21, wherein if BVPx is equal to 0, then BVDx is derived as 0.

25. The method of claim 21, wherein if BVPy is equal to 0, then BVDy is derived as 0.

26. The method of claim 21, wherein the function for deriving BVDy depends on whether BVPx is equal to zero.

27. The method of claim 21, wherein the function for deriving BVDx depends on whether BVPy is equal to zero.

28. The method of claim 21, wherein the function for deriving BVDy depends on whether BVPy is equal to zero.

29. The method of claim 21, wherein the function for deriving BVDx depends on whether BVPx is equal to zero.

30. The method according to any one of claims 1-29, wherein the step size difference of the block vector between two adjacent step sizes has a value that complies with a constraint.

31. The method of claim 30, wherein the step size difference between the two adjacent step sizes is fixed.

32. The method of claim 31, wherein the step size difference between the two adjacent step sizes is equal to k, and wherein k is an integer.

33. The method of claim 32, wherein k is equal to 1 or 2.

34. The method of claim 30, wherein the step size difference between the two adjacent step sizes is adaptive.

35. The method of claim 30, wherein the step size difference between the two adjacent step sizes is no greater than a predetermined number.

36. The method of claim 35, wherein the predetermined number is one of: 4, 8 or 16.

37. The method of claim 30, wherein the step size difference between the two adjacent step sizes is adaptive according to a step size value.

38. The method of claim 37, wherein if the larger of the two adjacent step sizes is not greater than S1, the step size difference between the two adjacent step sizes is set to k1, and / or If the larger step size is not greater than S2 and greater than S1, the step size difference between two adjacent step sizes is set to k2, and / or If the larger step size is greater than S2, the step size difference between two adjacent step sizes is set to k3, And wherein k1, k2, k3, S1 and S2 are integers.

39. The method of claim 38, wherein k1=1, k2=2, k3=4, S1=64, S2=128.

40. The method of any one of claims 1 to 39, wherein the BVDI or a portion of the BVDI is binarized using EGk binarization.

41. The method of claim 40, wherein the BVDI with a one-bit right shift is binarized using EGk binarization.

42. The method of claim 40, wherein the BVDI with a two-bit right shift is binarized using EGk binarization.

43. The method of claim 40, wherein the BVDI with a k-bit right shift is binarized using EGk binarization, where k is a positive integer.

44. A method according to any one of claims 1 to 39, wherein the step index or a part of the step index is binarized using a specific binarization.

45. The method of claim 44, wherein the step index with a one-bit right shift is binarized using the particular binarization.

46. ​​The method of claim 44, wherein the stride index with a two-bit right shift is binarized using the particular binarization.

47. The method of claim 44, wherein the stride index with a k-bit right shift is binarized using a specific binarization, where k is a positive integer.

48. The method of any one of claims 1 to 39, wherein the last k bits of the BVDI are binarized using fixed-length binarization, where k is a positive integer.

49. The method of claim 48, wherein the last bit of the BVDI is binarized using the fixed-length binarization, or The last two bits of the BVDI are binarized using the fixed-length binarization.

50. The method of any one of claims 1 to 39, wherein the last k bits of the step index are binarized using fixed-length binarization, where k is a positive integer.

51. The method of claim 50, wherein the last bit of the step index is binarized using the fixed length binarization, or The last two bits of the step index are binarized using the fixed-length binarization.

52. The method according to any one of claims 1 to 39, wherein BVDx minus a predefined number of absolute values ​​is binarized using a specific binarization process, and / or The absolute value of BVDy minus the predefined number is binarized using the specific binarization process.

53. The method according to claim 52, wherein the specific binarization process comprises one of the following: EG2 binarization process, EG3 binarization process, EG4 binarization process, or EG5 binarization process.

54. The method of claim 53, wherein the binarized code is bypass coded.

55. The method of claim 52, wherein whether BVDx is equal to 0 is context-coded.

56. The method of claim 55, wherein the context depends on at least one of: BVPx or BVPy.

57. The method of claim 52, wherein whether BVDy is equal to 0 is context-coded.

58. The method of claim 57, wherein the context depends on at least one of: BVPx or BVPy.

59. The method of any one of claims 1 to 58, wherein the converting comprises encoding the video unit into the bitstream.

60. The method of any one of claims 1 to 58, wherein the converting comprises decoding the video unit from the bitstream.

61. An apparatus for video processing, comprising a processor and a non-volatile memory having instructions thereon, wherein the instructions, when executed by the processor, cause the processor to perform the method of any one of claims 1 to 60.

62. A non-transitory computer readable storage medium storing instructions, the instructions causing a processor to execute the method according to any one of claims 1 to 60.

63. A non-transitory computer-readable recording medium storing a bit stream of a video, the bit stream being generated by a method performed by a video processing device, wherein the method comprises: determining a block vector of a video unit of the video based on the base block vector candidate and a parameter related to the block vector difference; as well as The bitstream is generated based on the block vectors.

64. A method for storing a bitstream of a video, comprising: determining a block vector of a video unit of the video based on the base block vector candidate and a parameter related to the block vector difference; generating the bitstream based on the block vector; as well as The bit stream is stored in a non-transitory computer-readable recording medium.

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