Bonding assemblies including conductive via structures extending through word lines in step regions and methods of making same

Abstract

A bond assembly includes a first memory die and a logic die. The first memory die includes a first alternating stack of first insulating layers and first conductive layers, a first memory opening filling structure, a first stepped dielectric material portion, and a first cylindrical conductive via structure, the first cylindrical conductive via structure includes a respective conductive shaft portion extending vertically through a respective subset of the first conductive layers, a respective conductive base portion, and a respective conductive pillar top portion contacting a horizontal surface of a respective one of the first conductive layers. The logic die includes a logic side bond pad bonded to the first cylindrical conductive via structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] For all purposes, this application claims the benefit of the entire contents of U.S. non-provisional application No. 17 / 822,182, filed on August 25, 2022, entitled "BONDED ASSEMBLY CONTAINING CONDUCTIVE VIA STRUCTURES EXTENDING THROUGH WORD LINES IN A STAIRCASE REGION AND METHODS FOR MAKING THE SAME," and the contents are hereby incorporated by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to bonded assemblies of memory and logic dies including conductive via structures extending through word lines in a stepped region and methods of forming the same. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to an embodiment of the present disclosure, a bonding component includes: a first memory die, the first memory die including a first alternating stack of a first insulating layer and a first conductive layer, a first memory opening filling structure, a first stepped dielectric material portion and a first columnar conductive via structure, the first memory opening filling structures are located in a first memory opening extending vertically through the first alternating stack and include corresponding vertical stacks of first memory elements, the first stepped dielectric material portion contacts a horizontal stepped surface of the first alternating stack, the first columnar conductive via structures include corresponding conductive axis portions extending vertically through corresponding subsets of the first conductive layers, corresponding conductive base portions connected to first ends of the corresponding conductive axis portions, and corresponding conductive column top portions connected to second ends of the corresponding conductive axis portions and contacting a horizontal stepped surface of a corresponding one of the first conductive layers; and a logic die, the logic die including a driver circuit, a logic side metal interconnect structure embedded in a logic side dielectric material layer, and a logic side bonding pad bonded to the first columnar conductive via structure.

[0006] According to another embodiment of the present disclosure, a method for forming a bonding component is provided, the method comprising: providing a first memory die, the first memory die comprising a first alternating stack of a first insulating layer and a first conductive layer, a first memory opening filling structure, a first stepped dielectric material portion and a first columnar conductive via structure, the first memory opening filling structures being located within a first memory opening extending vertically through the first alternating stack and comprising a corresponding vertical stack of first memory elements, the first stepped dielectric material portion contacting a horizontal stepped surface of the first alternating stack, the first columnar conductive via structures comprising corresponding conductive axis portions extending vertically through corresponding subsets of the first conductive layers, corresponding conductive base portions connected to first ends of the corresponding conductive axis portions, and corresponding conductive column top portions connected to second ends of the corresponding conductive axis portions and contacting a horizontal stepped surface of a corresponding one of the first conductive layers; providing a logic die, the logic die comprising a driver circuit, a logic side metal interconnect structure embedded in a logic side dielectric material layer, and a logic side bonding pad; and bonding the logic side bonding pad to the conductive base portion of the first columnar conductive via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a dielectric buffer layer and a mid-process source level material layer on a first carrier substrate according to an embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A FIG. 1 is a magnified view of the source level material layers during the process.

[0009] Figure 2is a vertical cross-sectional view of an exemplary structure after forming a first layer of alternate stacking of first insulating layers and first spacer material layers according to an embodiment of the present disclosure.

[0010] Figure 3 is a vertical cross-sectional view of an exemplary structure after patterning a first layer stepped region on a first layer alternating stack according to an embodiment of the present disclosure.

[0011] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a first backward stepped dielectric material portion and an interlayer dielectric layer according to an embodiment of the present disclosure.

[0012] Figure 5A is a vertical cross-sectional view of an exemplary structure after forming a first layer memory opening according to an embodiment of the present disclosure.

[0013] Figure 5B yes Figure 5A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Figure 5A A plane of a vertical section.

[0014] FIG. 6A to FIG. 6B Sequential vertical cross-sectional views of a first layer memory opening during expansion of an upper region of the first layer memory opening according to an embodiment of the present disclosure are shown.

[0015] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming a sacrificial memory opening filling portion according to an embodiment of the present disclosure.

[0016] Fig. 8A is a vertical cross-sectional view of an exemplary structure after forming an alternating stack of a second insulating layer and a second spacer material layer, a second backward stepped dielectric material portion, and a second insulating capping layer according to an embodiment of the present disclosure.

[0017] Figure 8B yes Fig. 8A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig. 8A A plane of a vertical section.

[0018] Fig.9A is a vertical cross-sectional view of an exemplary structure after forming a second-level memory opening according to an embodiment of the present disclosure.

[0019] Fig. 9B yes Fig.9A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig.9A A plane of a vertical section.

[0020] Fig. 10Ais a vertical cross-sectional view of an exemplary structure after forming an inter-layer memory opening according to an embodiment of the present disclosure.

[0021] Fig. 10B yes Fig. 10A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig. 10A A plane of a vertical section.

[0022] FIG. 11A to FIG. 11D are sequential vertical cross-sectional views of inter-layer memory openings during formation of a memory opening filling structure according to an embodiment of the present disclosure.

[0023] Fig. 12A is a vertical cross-sectional view of an exemplary structure after forming a memory stack structure according to an embodiment of the present disclosure.

[0024] Fig. 12B yes Fig. 12A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig. 12A A plane of a vertical section.

[0025] Fig.13A is a vertical cross-sectional view of an exemplary structure after forming a through-stack insulating material portion according to an embodiment of the present disclosure.

[0026] Fig. 13B yes Fig.13A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig.13A A plane of a vertical section.

[0027] Fig.14A is a vertical cross-sectional view of an exemplary structure after forming a step region via cavity, a peripheral region via cavity, and an array region via cavity according to an embodiment of the present disclosure.

[0028] Fig. 14B yes Fig.14A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig.14A A plane of a vertical section.

[0029] Fig.15A , Fig. 15B and Fig. 15C Respectively in Fig.14A and Fig. 14B An enlarged vertical cross-sectional view of a step area through-hole cavity, a peripheral area through-hole cavity, and an array area through-hole cavity in a processing step of FIG.

[0030] Fig.16A , Fig. 16B and Fig. 16CMagnified vertical cross-sectional views of a step area via cavity, a peripheral area via cavity, and an array area via cavity, respectively, after an isotropic etching process to convert the step area via cavity into a ribbed via cavity according to an embodiment of the present disclosure.

[0031] Fig.17A , Fig. 17B and Fig. 17C Magnified vertical cross-sectional views of a step region via cavity, a peripheral region via cavity, and an array region via cavity, respectively, after depositing a conformal dielectric via liner according to an embodiment of the present disclosure.

[0032] Fig.18A , Fig.18B and Fig.18C 2 are enlarged vertical cross-sectional views of a step region via cavity, a peripheral region via cavity, and an array region via cavity, respectively, after forming various sacrificial via fill material portions therein according to an embodiment of the present disclosure.

[0033] Fig.19 is Fig.18A , Fig.18B and Fig.18C Vertical cross-sectional view of an exemplary structure during a processing step of .

[0034] Fig. 20A is a vertical cross-sectional view of an exemplary structure after forming backside trenches according to an embodiment of the present disclosure.

[0035] Fig. 20B yes Fig. 20A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig. 20A A plane of a vertical section.

[0036] FIG. 21A to FIG. 21E According to an embodiment of the present disclosure, the intermediate buried semiconductor layer is replaced by Figure 1B Sequential vertical cross-sectional views of regions of an exemplary structure during the process of forming a source level material layer while various material portions within the source level material layer are formed.

[0037] Fig. 22 is Fig.21E Vertical cross-sectional view of an exemplary structure during a processing step of .

[0038] Fig.23 is a vertical cross-sectional view of an exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0039] Fig.24 is a vertical cross-sectional view of an exemplary structure after forming a conductive layer in a backside recess according to an embodiment of the present disclosure.

[0040] Fig.25Ais a vertical cross-sectional view of an exemplary structure after forming a dielectric wall structure in the backside trench according to an embodiment of the present disclosure.

[0041] Fig.25B yes Fig.25A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig.25A A plane of a vertical section.

[0042] Fig.25C , Fig.25D and Fig.25E Respectively in Fig.25A and Fig.25B An enlarged vertical cross-sectional view of a step area through-hole cavity, a peripheral area through-hole cavity, and an array area through-hole cavity in a processing step of FIG.

[0043] Fig.26 is an enlarged vertical cross-sectional view of a step region via cavity after removing a portion of a sacrificial via fill material according to an embodiment of the present disclosure.

[0044] Fig.27A , Fig.27B and Fig.27C Magnified vertical cross-sectional views of a step area via cavity, a peripheral area via cavity, and an array area via cavity, respectively, after an anisotropic etching process that physically exposes the annular surface of the conductive layer and the surface of the underlying lower-level metal interconnect structure according to an embodiment of the present disclosure.

[0045] Fig.28A is a vertical cross-sectional view of an exemplary structure after forming various contact via structures in various via cavities according to an embodiment of the present disclosure.

[0046] Fig.28B yes Fig.28A A top view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Fig.28A A plane of a vertical section.

[0047] Fig.28C , Fig.28D and Fig.28E Respectively in Fig.28A and Fig.28B An enlarged vertical cross-sectional view of a step area through-hole cavity, a peripheral area through-hole cavity, and an array area through-hole cavity in a processing step of FIG.

[0048] Fig.28F is an enlarged view of a region of a pillar-shaped conductive via structure formed in a stepped region via cavity.

[0049] Fig.29A is a vertical cross-sectional view of an exemplary structure after forming a drain contact via structure according to an embodiment of the present disclosure.

[0050] Fig.29B is along Fig.28A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Fig.28A A plane of a vertical section.

[0051] Fig.30 is a vertical cross-sectional view of an exemplary structure after forming a higher level metal line structure according to an embodiment of the present disclosure.

[0052] Fig.31 is a vertical cross-sectional view of an exemplary structure after forming a metal interconnect structure, an interconnect level dielectric material layer, and a memory side bond pad to provide a first memory die according to an embodiment of the present disclosure.

[0053] Fig.32 is a vertical cross-sectional view of an exemplary structure after attaching a second carrier substrate according to an embodiment of the present disclosure.

[0054] Fig.33A is a vertical cross-sectional view of an exemplary structure after the first carrier substrate is removed according to an embodiment of the present disclosure.

[0055] Fig.33B , Fig.33C and Fig.33D Respectively in Fig.33A An enlarged vertical cross-sectional view of a columnar conductive via structure, a peripheral area contact via structure, and an array area contact via structure in a processing step of FIG.

[0056] Fig.34A is a vertical cross-sectional view of an exemplary structure after bonding a logic die to a memory die according to an embodiment of the present disclosure.

[0057] Fig.34B is Fig.34A An enlarged vertical cross-sectional view of the area surrounding the pillar-shaped conductive via structure during a processing step of FIG.

[0058] Fig.35 is a vertical cross-sectional view of an exemplary structure after attaching an additional memory die according to an embodiment of the present disclosure.

[0059] Fig.36 is a vertical cross-sectional view of an exemplary structure after thinning the back side of the logic-side substrate and forming a back side bonding structure according to an embodiment of the present disclosure.

[0060] Fig.37 is a vertical cross-sectional view of a first alternative configuration of an exemplary structure after attaching an additional memory die according to an embodiment of the present disclosure.

[0061] Fig.38 is a vertical cross-sectional view of a first alternative configuration of an exemplary structure after thinning the back side of the logic-side substrate and forming a backside bonding structure according to an embodiment of the present disclosure.

[0062] Fig.39 is a vertical cross-sectional view of a second alternative configuration of the exemplary structure after thinning the back side of the logic-side substrate and forming a backside bonding structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] The performance of a memory package can be enhanced by bonding at least one memory die to a logic die, the logic die including peripheral circuitry for operating a three-dimensional memory array within the at least one memory die. As described above, embodiments of the present disclosure relate to a bonded assembly of memory and logic dies including conductive via structures extending through word lines in a stepped region of a memory die, and methods of forming the same, various aspects of which are described in detail herein.

[0064] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0065] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0066] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0067] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0068] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 5 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 5S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0069] Various three-dimensional memory devices of the present disclosure include three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. The three-dimensional NAND string can be located in a single three-dimensional NAND string array. The driver circuit can be formed on the same substrate as the NAND string, or formed on a substrate different from the NAND string, and then the driver circuit is bonded to the NAND string. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0070] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0071] refer to Figure 1A and Figure 1B , showing an exemplary structure according to an embodiment of the present disclosure. Figure 1B yes Figure 1AAn enlarged view of the source level material layer 10' in the process shown. The exemplary structure includes a first carrier substrate 908 including a substrate material layer 909, a dielectric buffer layer 768 formed on the front surface of the first carrier substrate 908, and an optional planar conductive material layer 6 and a source level material layer 10' in the process. The substrate material layer 909 may include a semiconductor material, an insulating material and / or a conductive material. In one embodiment, the carrier substrate 908 includes a commercially available silicon wafer, and the substrate material layer 909 may include an upper portion of a silicon wafer or an epitaxial silicon layer grown on a silicon wafer. The dielectric buffer layer 768 may include a single dielectric material layer or multiple dielectric material layers. In one embodiment, the dielectric buffer layer 768 may include a silicon oxide layer.

[0072] The optional planar conductive material layer 6 (if present) provides a high conductivity conduction path for the current flowing into or out of the source level material layer 10' during the process. The optional planar conductive material layer 6 includes a conductive material such as a metal or a heavily doped semiconductor material. The optional planar conductive material layer 6 may, for example, include a tungsten layer with a thickness in the range of 3nm to 100nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on the top of the planar conductive material layer 6 as a diffusion barrier. The planar conductive material layer 6 may be used as a special source line in a finished device. The optional planar conductive material layer 6 may include a metal compound material, such as a conductive metal nitride (e.g., tin) and / or a metal (e.g., W). The thickness of the optional planar conductive material layer 6 may be in the range of 5nm to 100nm, but smaller and larger thicknesses may also be used.

[0073] The source level material layer 10' in the process may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a buried source layer when formed, which is used as a common source region of a vertical field effect transistor of a three-dimensional memory device. In one embodiment, the source level material layer 10' in the process may include a lower source layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, an upper sacrificial liner 105, an upper source layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118 from bottom to top.

[0074] The lower source layer 112 and the upper source layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source layer 112 and the upper source layer 116 may be opposite to the conductivity type of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source layer 112 and the upper source layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source layer 112 and the upper source layer 116 may be in the range of 10nm to 300nm (such as 20nm to 150nm), but smaller and larger thicknesses may also be used.

[0075] The source level sacrificial layer 104 comprises a sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm (such as 60nm to 200nm), but smaller and larger thicknesses can also be used.

[0076] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although lesser and greater thicknesses can also be used.

[0077] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon by an annealing process. The thickness of the optional source level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0078] The optional planar conductive material layer 6 and the process source level material layer 10' can be patterned to provide openings in areas where through-stack contact via structures and through-dielectric contact via structures are subsequently formed. The patterned portion of the stack of the planar conductive material layer 6 and the process source level material layer 10' is present in each memory array region 100, and a three-dimensional memory stack structure will be formed in each memory array region. In one embodiment, the openings in the optional planar conductive material layer 6 and the process source level material layer 10' can be formed in the area of ​​the step region 200, and the contact via structure of the contact word line conductive layer will be formed in the area of ​​the step region. In one embodiment, additional openings in the optional planar conductive material layer 6 and the process source level material layer 10' can be formed in the area of ​​the memory array region 100, and a three-dimensional memory array including a memory stack structure will be formed in the area of ​​the memory array region. Additional dielectric material can be deposited around the patterned planar conductive material layer 6 and the process source level material layer 10', and can be incorporated into the dielectric buffer layer 768. An optional peripheral region 400 that is subsequently filled with a portion of the field dielectric material may be provided adjacent to the stepped region 200 .

[0079] See also Figure 2 , subsequently forming an alternating stack of first material layers and second material layers. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first layer alternating stack. A level of the first layer alternating stack is referred to herein as a first layer level, and a level of the alternating stack to be subsequently formed immediately above the first layer level is referred to herein as a second layer level, and so on.

[0080] The first layer of alternating stacking may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are clearly contemplated herein.

[0081] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 may be formed above the source level material layer during the process. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0082] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first elements may have the same thickness, or may have different thicknesses. The second elements may have the same thickness, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0083] The first layer alternating stack (132, 142) may include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0084] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0085] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0086] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0087] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair may be in the range of 2 to 1024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first layer alternating stack (132, 142) may have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0088] A first insulating capping layer 170 is then formed over the first alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 includes the same dielectric material as the first insulating layer 132. The thickness of the insulating capping layer 170 can be in the range of 20 nm to 300 nm, although lesser and greater thicknesses can also be used.

[0089] refer to Figure 3, the first insulating capping layer 170 and the first layer alternating stack (132, 142) can be patterned to form a first stepped surface in the stepped region 200. The stepped region 200 may include a corresponding first stepped region and a second stepped region, in which the first stepped surface is formed, and in which an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface can be formed, for example, by forming a mask layer having an opening therein, etching a cavity within the level of the first insulating capping layer 170 and iteratively expanding the etching region, and by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching region so that the cavity is vertically recessed.

[0090] refer to Figure 4 , a dielectric material may be deposited to fill the first stepped cavity to form a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is located. The first layer alternating stack (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0091] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 165, 170). The interlayer dielectric layer 180 includes a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may include a doped silicate glass having a greater etching rate than the material of the first insulating layer 132 (which may include undoped silicate glass). For example, the interlayer dielectric layer 180 may include phospholipase glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

[0092] refer to Figure 5A and Figure 5B , a first layer memory opening 149 may be formed. Figure 5BThe location of the step S in the first layer of alternating stack (132, 142) is shown in dashed lines. The first layer of memory openings 149 extend through the first layer of alternating stack (132, 142) to at least the top surface of the source level material layer 10' in the process. The first layer of memory openings 149 can be formed at locations in the memory array area 100 where a vertically stacked memory stack structure including memory elements will be subsequently formed. For example, a photolithographic material stack (not shown) including at least a photoresist layer can be formed above the first insulating cap layer 170 (and optional interlayer dielectric layer 180, if present), and the photolithographic material stack can be photolithographically patterned to form an opening in the photolithographic material stack. The pattern in the photolithographic material stack can be transferred through the first insulating cap layer 170 (and optional interlayer dielectric layer 180) and through the entire first layer of alternating stack (132, 142) by at least one anisotropic etch using the patterned photolithographic material stack as an etch mask. Portions of the first insulating capping layer 170 (and optional interlayer dielectric layer 180) and the first layer alternating stack (132, 142) located below the opening in the patterned photolithographic material stack are etched to form the first layer memory opening 149. In other words, the pattern in the patterned photolithographic material stack is transferred through the first insulating capping layer 170 and the first layer alternating stack (132, 142) to form the first layer memory opening 149.

[0093] In one embodiment, the chemistry of the anisotropic etching process used to etch through the material of the first layer alternating stack (132, 142) can be alternating to optimize the etching of the first material and the second material in the first layer alternating stack (132, 142). The anisotropic etching can be, for example, a series of reactive ion etching or a single etching (e.g., CF4 / O2 / Ar etching). The sidewalls of the first layer memory opening 149 can be substantially vertical, or can be tapered. Subsequently, the patterned photolithographic material stack can be subsequently removed, for example, by ashing.

[0094] Optionally, the portion of the first level memory opening 149 at the level of the interlayer dielectric layer 180 may be expanded laterally by isotropic etching. Fig. 6A and Figure 6B A processing sequence for laterally extending portions of the first level memory opening 149 at the level of the inter-level dielectric layer 180 is shown. Fig. 6A The first layer memory openings 149 are shown immediately after anisotropic etching to form the first layer memory openings 149. The anisotropic etching may be terminated after each of the first layer memory openings 149 extends to the lower source layer 112. The interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate than the first insulating layer 132 (which may include undoped silicate glass). Figure 6B , an isotropic etch (such as a wet etch using HF) may be employed to expand the lateral dimensions of the first-level memory opening at the level of the interlayer dielectric layer 180. The portion of the first-level memory opening 149 positioned at the level of the interlayer dielectric layer 180 may optionally be widened to provide a larger landing pad for a second-level memory opening that will subsequently be formed through the second-level alternating stack (subsequently formed prior to forming the second-level memory opening).

[0095] refer to Figure 7 , a sacrificial memory opening filling portion 148 may be formed in the first layer memory opening 149. For example, a sacrificial filling material layer is deposited in the first layer memory opening 149. The sacrificial filling material layer includes a sacrificial material that can be selectively removed subsequently based on the materials of the first insulator layer 132 and the first sacrificial material layer 142. In one embodiment, the sacrificial filling material layer may include a semiconductor material such as silicon (e.g., a-Si or polycrystalline silicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop layer (such as a silicon oxide layer having a thickness in the range of 1 nm to 3 nm) may be employed prior to depositing the sacrificial filling material layer. The sacrificial filling material layer may be formed by a non-conformal deposition or a conformal deposition method. In another embodiment, the sacrificial filling material layer may include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing.

[0096] Portions of the deposited sacrificial material may be removed from above the first insulating capping layer 170 (and the optional interlayer dielectric layer 180, if present). For example, the sacrificial fill material layer may be recessed to the top surface of the first insulating capping layer 170 (and the optional interlayer dielectric layer 180) using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the first insulating layer 170 (and the optional layer 180, if present) may be used as an etch stop layer or a planarization stop layer. Each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial memory opening filling portion 148. The top surface of the sacrificial memory opening filling portion 148 may be coplanar with the top surface of the interlayer dielectric layer 180 (or if the interlayer dielectric layer 180 is not present, the first insulating capping layer 170). The sacrificial memory opening filling portion 148 may or may not include a cavity.

[0097] refer to Fig. 8A and Figure 8B, a second layer structure may be formed above the first layer structure (132, 142, 170, 148). The second layer structure may include additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may be subsequently formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0098] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0099] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0100] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0101] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair may be in the range of 2 to 1024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) may have a uniform thickness that is substantially constant within each corresponding second sacrificial material layer 242.

[0102] The second stepped surface in the second stepped region can be formed in the stepped region 200 using the same set of processing steps as the processing steps used to form the first stepped surface in the first stepped region, wherein the pattern of at least one mask layer is appropriately adjusted. A second backward stepped dielectric material portion 265 can be formed over the second stepped surface in the stepped region 200.

[0103] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242). The second insulating capping layer 270 includes a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may include silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) may include silicon nitride.

[0104] Generally speaking, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source level material layer 10' during the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the stepped region on at least one alternating stack (132, 142, 232, 242).

[0105] Optionally, a drain selection level isolation structure 72 may be formed through a subset of the layers in the upper portion of the second layer alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain selection level shallow trench isolation structure 72 corresponds to a level at which a drain selection level conductive layer is subsequently formed. The drain selection level isolation structure 72 includes a dielectric material such as silicon oxide. The drain selection level isolation structure 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0106] refer to Fig.9A and Fig. 9B, a second layer memory opening 249 extending through the second layer structure (232, 242, 270, 265) is formed in an area covering the sacrificial memory opening filling portion 148. For example, a photoresist layer may be applied to the second layer structure (232, 242, 270, 265) and may be photolithographically patterned to form a pattern that is the same as the pattern of the sacrificial memory opening filling portion 148 (i.e., the pattern of the first layer memory opening 149). Therefore, the second layer memory opening 249 may be patterned using a photolithographic mask used to pattern the first layer memory opening 149. Anisotropic etching may be performed to transfer the pattern of the photolithographically patterned photoresist layer through the second layer structure (232, 242, 270, 265). In one embodiment, the chemistry of the anisotropic etching process used to etch through the material of the second layer alternating stack (232, 242) may be alternating to optimize the etching of the alternating material layers in the second layer alternating stack (232, 242). The anisotropic etching may be, for example, a series of reactive ion etchings. For example, the patterned photoresist material stack may be removed by ashing after the anisotropic etching process. The top surface of the lower sacrificial memory opening filling portion 148 may be physically exposed at the bottom of each second-level memory opening 249.

[0107] refer to Fig. 10A and Fig. 10B , an etching process can be performed to selectively remove the sacrificial material of the sacrificial memory opening filling portion 148 relative to the material of the second layer alternating stack (232, 242) and the first layer alternating stack (132, 142) (e.g., C4F8 / O2 / Ar etching). When removing the sacrificial memory opening filling portion 148, each pair of vertically adjacent second layer memory openings 249 and first layer memory openings 149 forms a continuous cavity extending through the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242). The continuous cavity is referred to herein as a memory opening 49 (or an interlayer memory opening). During the process, the surface of the source level material layer 10' can be physically exposed at the bottom of each memory opening 49. The location of the step S in the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) is shown in dotted lines.

[0108] FIG. 11A to FIG. 11D Sequential cross-sectional views of the memory openings 49 are provided during the formation of the memory opening fill structure 58 or the support post structure 20. The same structural changes occur in each memory opening 49.

[0109] refer to Fig.11A , showing Fig. 10A and Fig. 10B Memory opening 49 in an exemplary device structure of FIG. Memory opening 49 extends through the first layer structure and the second layer structure.

[0110] refer to Fig. 11B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride).

[0111] Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, their alloys, and their stacks. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source atomized chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in the range of 1nm to 20nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include a plurality of dielectric metal oxide layers having different material compositions.

[0112] Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 may be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Alternatively, the blocking dielectric layer 52 may be omitted, and a backside blocking dielectric layer may be formed after a backside recess is formed on the surface of the memory film to be subsequently formed.

[0113] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

[0114] In another embodiment, the sacrificial material layer (142, 242) may be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. Although the present disclosure is described using an embodiment in which the charge storage layer 54 is a single continuous layer, embodiments in which the charge storage layer 54 is replaced by a plurality of vertically spaced memory material portions (which may be charge trapping material portions or electrically isolated conductive material portions) are expressly contemplated herein.

[0115] The charge storage layer 54 may be formed as a single charge storage layer of uniform composition, or may include a stack of multiple charge storage layers. Multiple charge storage layers (if used) may include multiple spaced-apart floating gate material layers containing conductive materials (e.g., metals such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or semiconductor materials (e.g., polycrystalline or amorphous semiconductor materials including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or in addition, the charge storage layer 54 may include an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 may include conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of charge storage layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be employed.

[0116] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be employed. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0117] The semiconductor channel material layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0118] refer to Fig. 11C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or deposited by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0119] refer to Fig.11D , a doped semiconductor material may be deposited in the cavity covering the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping conductivity type of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has a doping of a second conductivity type. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 covering the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0120] Each remaining portion of the doped semiconductor material having the doping of the second conductivity type constitutes a drain region 63. The drain region 63 may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain region 63 may be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0121] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0122] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. In the process, the source level material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265), the interlayer dielectric layer 180, and the memory opening filling structure 58 together constitute a memory level component.

[0123] See also Fig. 12A and Fig. 12B , shows an exemplary structure after forming memory opening filling structure 58 .

[0124] refer to Fig.13A and Fig. 13B A first contact level dielectric layer 280 may be formed on the memory level components. The first contact level dielectric layer 280 is formed at the contact level, through which various contact via structures are subsequently formed to the drain region 63, and various conductive layers are formed to replace the sacrificial material layer (142, 242) in subsequent processing steps.

[0125] For example, a through stack via cavity may be formed with the memory array region 100 by applying and patterning a photoresist layer to form an opening therein, and by anisotropically etching a portion of the first contact level dielectric layer 280, the alternating stack (132, 146, 232, 246), and the dielectric buffer layer 768 located below the opening in the photoresist layer. In one embodiment, each of the through stack via cavities may be formed within a corresponding three-dimensional memory array such that each through stack via cavity is laterally surrounded by a memory opening fill structure 58. In one embodiment, one or more of the through stack via cavities may be formed through the drain select level isolation structure 72. However, other locations may also be selected. In one embodiment, a first through stack via cavity may be formed in the region of an opening in the source level material layer 10' and the optional planar conductive material layer 6 during the process.

[0126] The dielectric material is deposited in the through-stack via cavity. The dielectric material may include a silicon oxide-based material, such as undoped silicate glass, doped silicate glass, or a flowable oxide material. The dielectric material may be deposited by a conformal deposition method, such as chemical vapor deposition or spin coating. A void may be formed in the unfilled portion of each through-stack via cavity. The excess portion of the deposited dielectric material may be removed from above the horizontal plane including the top surface of the first contact level dielectric layer 280, for example, by chemical mechanical planarization or recess etching. Each remaining dielectric material portion that fills a corresponding through-stack via cavity in the through-stack via cavity constitutes a through-stack insulating material portion 576. The through-stack insulating material portion 576 contacts the sidewalls of the alternating stack (132, 146, 232, 246).

[0127] refer to Fig.14A , Fig. 14B , Fig.15A , Fig. 15B and Fig. 15C, a photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form various openings in areas where via cavities are subsequently formed. Openings may be formed over the through-stack insulating material portion 576 in the memory array region 100, over the horizontal surface of the stepped surface in the stepped region 200, and in the peripheral region 400. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through various material portions in the memory level assembly. Various contact via cavities (183 and optionally 483 and / or 583) may be formed through the memory level assembly. Specifically, the various contact via cavities (183, 483, 583) may extend vertically to the top surface of the first carrier substrate 908.

[0128] The various contact via cavities (183, 483, 583) formed through the memory level components include a step region via cavity 183 extending through a corresponding one of the horizontal surfaces of the stepped surface in the step region 200, a peripheral region via cavity 483 extending through the rearward stepped dielectric material portion (265, 165) in the peripheral region 400, and an array region via cavity 583 formed through a corresponding one of the through-stack insulating material portions 576 in the memory array region 100. In one embodiment, each of the various contact via cavities (183, 483, 583) can be a cylindrical via cavity. As used herein, a "cylindrical via cavity" refers to a via cavity having only one or more straight sidewalls such that each straight sidewall is vertical or substantially vertical. As used herein, a surface is "substantially vertical" if the taper angle of the surface relative to the vertical direction is less than 5 degrees. Each stepped region via cavity 183 is a cylindrical via cavity that extends through the second backward stepped dielectric material portion 265 and a subset of the layers within the second alternating stack (232, 242) and the first alternating stack (132, 142) and over the first carrier substrate 908. A top surface of a corresponding one of the first carrier substrates 908 may be physically exposed at the bottom of each of the various contact via cavities (183, 483, 583).

[0129] refer to Fig.16A , Fig. 16B and Fig. 16C, an isotropic etching process may be performed to laterally recess the insulating layer (132, 232) relative to the spacer material layer (such as the first sacrificial material layer and the second sacrificial material layer (142, 242)). Each step region via cavity 183 may be transformed from a cylindrical via cavity to a ribbed via cavity 183'. As used herein, a "ribbed via cavity" refers to a via cavity that includes at least one annular lateral protrusion volume. Each annular lateral protrusion volume of a ribbed via cavity is referred to herein as a "ribbed region".

[0130] In one embodiment, the rear stepped dielectric material portion (165, 265) may include the same dielectric material as the insulating layer (132, 232) or a similar dielectric material. For example, the first insulating layer and the second insulating layer (132, 232) may include undoped silicate glass, and the rear stepped dielectric material portion (165, 265) may include undoped silicate glass or doped silicate glass. In this case, by selectively etching the material of the rear stepped dielectric material portion (165, 265) and the insulating layer (132, 232) of the spacer material layer (i.e., the first sacrificial material layer and the second sacrificial material layer (142, 242)), a ribbed through-hole cavity 183' may be formed from the cylindrical stepped region through-hole cavity 183.

[0131] In one embodiment, the dielectric materials of the first contact level dielectric layer 270, the first insulating cap layer and the second insulating cap layer (170, 270), the first backward stepped dielectric material portion and the second backward stepped dielectric material portion (165, 265), and the insulating layer (132, 232) may include silicon oxide materials (such as undoped silicate glass and various doped silicate glasses), and the first sacrificial material layer and the second sacrificial material layer (142, 242) may include sacrificial materials of non-silicate glass materials (such as silicon nitride or semiconductor materials). In this case, the isotropic etching process can etch the dielectric material of the first contact level dielectric layer 270, the first insulating cap layer and the second insulating cap layer (170, 270), the first backward stepped dielectric material portion and the second backward stepped dielectric material portion (165, 265), and the insulating layer (132, 232) and can selectively etch to the material of the first sacrificial material layer and the second sacrificial material layer (142, 242) to form a ribbed through-hole cavity 183'.

[0132] In one embodiment, the spacer material layers of the alternating stack (132, 142, 232, 242) may include sacrificial material layers (142, 242) composed of silicon nitride, and the insulating layers (132, 232) and the rear stepped dielectric material portions (265, 165) may include silicon oxide materials. In this case, the rear stepped dielectric material portions (165, 265) and each insulating layer (132, 232) physically exposed to the stepped region through-hole cavity 183 may be isotropically recessed by a wet etching process using hydrofluoric acid. Each ribbed through-hole cavity 183' may include a ribbed cavity region extending through the alternating stack (132, 142, 232, 242), an overlying cavity laterally surrounded by a second rear-stepped dielectric material portion 265 and optionally by a first rear-stepped dielectric material portion 165 (in the case where the ribbed through-hole cavity 183' extends only through a first layer of alternating stack (132, 142) and not through a second layer of alternating stack (232, 242)), a lower cavity located below the alternating stack (132, 142, 232, 242), and an annular recess AR or ribbed region formed at the level of the insulating layer (132, 232) in a subset of the layers within the alternating stack (132, 142, 232, 242) through which the ribbed through-hole cavity 183' vertically extends.

[0133] Each of the peripheral region via cavity 483 and the array region via cavity 583 may be laterally isotropically expanded to form an expanded peripheral region via cavity 483' and an expanded array region via cavity 583'. In one embodiment, the dielectric material of the first contact level dielectric layer 280, the first and second insulating capping layers (170, 270), the first and second backward stepped dielectric material portions (165, 265), and the insulating layer (132, 232) may include the same dielectric material (such as undoped silicate glass), and the peripheral region via cavity 483' and the expanded array region via cavity 583' may be cylindrical cavities. Alternatively, the dielectric materials of the first contact level dielectric layer 280, the first insulating cap layer and the second insulating cap layer (170, 270), the first backward stepped dielectric material portion and the second backward stepped dielectric material portion (165, 265), and the insulating layer (132, 232) may have different etching rates during the isotropic etching process, and the peripheral area through-hole cavity 483' and the extended array area through-hole cavity 583' may include lateral steps having lateral dimensions less than a recess distance of the lateral recess of the sacrificial material layer (142, 242).

[0134] refer to Fig.17A , Fig. 17B and Fig. 17C, a conformal dielectric via liner 846L may be deposited at the periphery of the ribbed via cavity 183', the extended peripheral area via cavity 483', and the extended array area via cavity 583' by a conformal deposition process. The conformal dielectric via liner 846L includes a dielectric material different from the material of the sacrificial material layer (142, 242). For example, the conformal dielectric via liner 846L may include silicon oxide or a dielectric metal oxide (such as aluminum oxide). In one embodiment, the conformal dielectric via liner 846L may include undoped silicate glass formed by thermal decomposition of tetraethyl orthosilicate (TEOS). The thickness of the conformal dielectric via liner 846L may be greater than half of the maximum thickness of the sacrificial material layer (142, 242). The portion 84F of the conformal dielectric via liner 846L deposited at the periphery of the ribbed via cavity 183' fills the annular recess AR (i.e., the ribbed area). The neck portion 84N of the conformal dielectric via liner 846L can be formed around at least one annular portion of each set of conformal dielectric via liner 846L, and the at least one annular portion fills the annular recess of each ribbed via cavity 183'. An annular seam 84S can exist within each portion of the conformal dielectric via liner 846L that fills the annular recess AR. The conformal dielectric via liner 846L can be formed directly on each physically exposed top surface of the first carrier substrate 908. After depositing the conformal dielectric via liner 846L, an unfilled void 183" can exist within each ribbed via cavity 183'. After depositing the conformal dielectric via liner 846L, an unfilled void 483" can exist within each extended peripheral area via cavity 483'. After depositing the conformal dielectric via liner 846L, an unfilled void 583" may exist within each extended array area via cavity 583'.

[0135] refer to Fig.18A , Fig.18B , Fig.18C and Fig.19, a sacrificial via fill material may be deposited in each unfilled void (183", 483", 583") in the step area via cavity, the peripheral area via cavity, and the array area via cavity by a conformal deposition process. By depositing the sacrificial via fill material and planarizing the sacrificial via fill material from above the top surface of the first contact level dielectric layer 280, various sacrificial via fill material portions (16, 484, 584) may be formed in the unfilled voids (183", 483", 583"). The sacrificial via fill material is a material that may be selectively removed relative to the material of the conformal dielectric via liner 846L. For example, the sacrificial via fill material may include a semiconductor material such as amorphous silicon or a dielectric material such as organic silicate glass. The sacrificial via fill material may be deposited by a non-conformal deposition process or a conformal deposition process. Void 16' may exist in the lower portion of each step area via cavity. Planarization of the sacrificial via fill material may be performed by a chemical mechanical planarization (CMP) process or by a recess etch process.The horizontal portion of the conformal dielectric via liner 846L may be removed from above the top surface of the first contact level dielectric layer 280 by the planarization process.

[0136] Each remaining portion of the sacrificial material filling the voids constitutes a sacrificial via filling material portion (16, 484, 584). The sacrificial via filling material portion (16, 484, 584) includes a step area sacrificial via filling material portion 16 formed in the step area via cavity, a peripheral area sacrificial via filling material portion 484 formed in the peripheral area via cavity, and an array area sacrificial via filling material portion 584 formed in the array area via cavity. Each remaining portion of the conformal dielectric via liner 486L in each via cavity constitutes a conformal insulating liner (84, 486, 586). The conformal insulating liner (84, 486, 586) includes a step area conformal dielectric via liner 84, a peripheral area conformal insulating liner 486, and an array area conformal insulating liner 586. Each stepped region conformal dielectric via liner 84 may include: a neck portion 84N extending vertically through a corresponding subset of the layers in the alternating stack (132, 142, 232, 242); an upper cylindrical portion 84U extending through the first contact level dielectric layer 280 and the second back stepped dielectric material portion 265 and optionally through the first back stepped dielectric material portion 165; a lower cylindrical portion 84L extending through the bottommost first insulating layer 132 and the dielectric buffer layer 768; and a bottom portion contacting the top surface of the substrate material layer 909. Each contiguous group of stepped region conformal dielectric via liner 84 and stepped region sacrificial via fill material portion 16 constitutes a stepped region sacrificial via structure 36.

[0137] refer to Fig. 20A , Fig. 20B and Fig.21A , and then a backside trench 79 is formed through the first contact level dielectric layer 280 and the memory level component. For example, a photoresist layer can be applied on the first contact level dielectric layer 280 and photolithographically patterned to form an elongated opening extending along a first horizontal direction (e.g., a word line direction) hd1. An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the main part of the memory level component to the in-process source level material layer 10'. For example, the backside trench 79 can extend through the optional source select level conductive layer 118, the source level insulating layer 117, the upper source layer 116, and the upper sacrificial liner 105 and extend into the source level sacrificial layer 104. The optional source select level conductive layer 118 and the source level sacrificial layer 104 can be used as an etch stop layer for the anisotropic etching process to form the backside trench 79. The photoresist layer can then be removed, for example, by ashing.

[0138] The backside trenches 79 extend along a first horizontal direction hd1 and are thus elongated along the first horizontal direction hd1. The backside trenches 79 may be laterally spaced apart from each other along a second horizontal direction hd2 that may be perpendicular to the first horizontal direction hd1. The backside trenches 79 may extend through the memory array region 100 (which may extend above the memory plane) and the step region 200. The backside trenches 79 may laterally divide the memory hierarchy assembly into memory blocks.

[0139] The backside trench spacer 74 can be formed on the sidewalls of the backside trench 79 by conformal deposition of a dielectric spacer material and anisotropic etching of the dielectric spacer material. The dielectric spacer material is a material that can selectively remove the material of the first insulating layer and the second insulating layer (132, 232). For example, the dielectric spacer material may include silicon nitride. The lateral thickness of the backside trench spacer 74 can be in the range of 4nm to 60nm (such as 8nm to 30nm), but smaller and larger thicknesses can also be used.

[0140] refer to Fig.21B , an etchant may be introduced into the backside trench in an isotropic etching process that selectively etches the material of the source level sacrificial layer 104 relative to the material of the backside trench spacers 74, the upper sacrificial liner 105, and the lower sacrificial liner 103. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, the backside trench spacers 74 comprise silicon nitride, and the upper and lower sacrificial liners (105, 103) comprise silicon oxide, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") may be used to selectively remove the source level sacrificial layer 104 relative to the backside trench spacers 74 and the upper and lower sacrificial liners (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0141] refer to Fig. 21C , a series of isotropic etchants (such as wet etchants) may be applied to the physically exposed portion of the memory film 50 in the source cavity 109 through the backside trench 79 and the source cavity 109 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower sacrificial liners (105, 103) may be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 may be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower sacrificial liners (105, 103). The top surface of the lower source layer 112 and the bottom surface of the upper source layer 116 may be physically exposed to the source cavity 109.

[0142] refer to Fig.21D , a doped semiconductor material having a doping of a second conductivity type may be deposited by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and a dopant precursor gas may flow simultaneously into a processing chamber including the exemplary structure. For example, if the second conductivity type is n-type, a semiconductor precursor gas (such as silane, disilane, or dichlorosilane), an etchant gas (such as hydrogen chloride), and a dopant precursor gas (such as phosphine, arsine, or antimonide) may flow. The deposited doped semiconductor material forms a source contact layer 114, which may contact the sidewalls of the vertical semiconductor channel 60. The duration of the selective semiconductor deposition process may be selected so that the source cavity is filled with the source contact layer 114, and the source contact layer 114 contacts the exposed portion of the semiconductor channel 60 and the bottom portion of the inner sidewall of the backside trench spacer 74. In one embodiment, the doped semiconductor material may include doped polysilicon.

[0143] The layer stack including the lower source layer 112, the source contact layer 114 and the upper source layer 116 constitutes a buried source layer (112, 114, 116) which serves as a common source region connecting each of the vertical semiconductor channels 60 and having a doping of the second conductivity type. The average dopant concentration of the buried source layer (112, 114, 116) can be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations can also be used. The layer group including the buried source layer (112, 114, 116), the source level insulating layer 117 and the optional source selection level conductive layer 118 constitutes the source level layer 10, which replaces the source level layer 10' during the process.

[0144] refer to Fig.21E and Fig. 22 , an isotropic etching process may be performed to remove the backside trench spacers 74. In an illustrative example, if the backside trench spacers 74 include silicon nitride, a wet etch using hot phosphoric acid may be employed to selectively remove the backside trench spacers relative to the material of the source contact layer 114, the insulating layer (132, 232), the first and second insulating capping layers (170, 270), and the first contact level dielectric layer 280.

[0145] refer to Fig.23 For example, an isotropic etching process can be used to introduce an etchant into the back side trench 79 that selectively etches the material of the first sacrificial material layer and the second sacrificial material layer (142, 242) relative to the material of the first and second insulating layers (132, 232), the first and second insulating cap layers (170, 270), the material of the conformal insulating liner (84, 486, 586), the material of the outermost layer of the memory film 50, and the material of the sacrificial through-hole filling material portion (16, 484, 584). For example, the first sacrificial material layer and the second sacrificial material layer (142, 242) may include silicon nitride, the materials of the first and second insulating layers (132, 232), the first and second insulating capping layers (170, 270), the conformal insulating liner (84, 486, 586), and the material of the outermost layer of the memory film 50 may include silicon oxide material, and the material of the sacrificial via filling material portion (16, 484, 584) may include doped polysilicon, doped silicon-containing alloy material, or doped silicate glass or organic silicate glass, which has a greater etching rate than the silicon oxide material of the first and second insulating layers (132, 232), the first and second insulating capping layers (170, 270), and the conformal insulating liner (84, 486, 586). The first backside recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. The second backside recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed.

[0146] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the first sacrificial material layer and the second sacrificial material layer (142, 242) include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching tank including phosphoric acid, which etches silicon nitride in a manner selective to silicon oxide, silicon, and various other materials used in the art. In the case where the sacrificial material layer (142, 242) includes a semiconductor material, a wet etching process (which may use a wet etchant such as a KOH solution) or a dry etching process (which may include vapor phase HCl) may be used.

[0147] Each of the first backside recess and the second backside recess (143, 243) can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first backside recess and the second backside recess (143, 243) can be greater than the height of the corresponding backside recess (143, 243). A plurality of first backside recesses 143 can be formed in a volume from which the material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses 243 can be formed in a volume from which the material of the second sacrificial material layer 242 is removed. Each of the first backside recess and the second backside recess (143, 243) can extend substantially parallel to the top surface of the substrate 908. The backside recess (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the insulating layer (132 or 232) covering it. In one embodiment, each of the first backside recessed portion and the second backside recessed portion (243, 243) may have a uniform height throughout.

[0148] refer to Fig.24 , a backside blocking dielectric layer (not shown) may optionally be deposited in the backside recess and the backside trench 79 and above the first contact level dielectric layer 280. The backside blocking dielectric layer may be deposited on a physically exposed portion of the outer surface of the memory stack structure 55, the physically exposed portion being part of the memory opening filling structure 58. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. If employed, the backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 60 nm, but smaller and larger thicknesses may also be employed.

[0149] At least one conductive material may be deposited in the plurality of backside recesses (243, 243), on the sidewalls of the backside trenches 79, and over the first contact level dielectric layer 280. The at least one conductive material may include at least one metallic material, ie, a conductive material including at least one metallic element.

[0150] A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 243, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0151] The metal material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The metal material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy, such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that can be deposited in the back side recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metal material may include a metal, such as tungsten and / or a metal nitride. In one embodiment, the metal material for filling the back side recess may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the metal material may be deposited by chemical vapor deposition or atomic layer deposition.

[0152] The residual conductive material may be removed from the interior of the backside trench 79. Specifically, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246) may be a conductive line structure.

[0153] A subset of the second conductive layer 246 located at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) located below the drain select gate electrode can be used as a combination of a control gate and a word line located at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55.

[0154] Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layer (146, 246). A subset of the conductive layer (146, 246) may include a word line for the memory element. The memory level assembly is positioned above the substrate material layer 909. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 that vertically extends through at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a corresponding insulating layer (132 or 232) and a corresponding conductive layer (146 or 246). At least one alternating stack (132, 146, 232, 246) includes stepped regions including steps in which each underlying conductive layer (146, 246) extends further along a first horizontal direction hd1 than any overlying conductive layer (146, 246) in the memory level assembly.

[0155] refer to FIG. 25A to FIG. 25E , the insulating material may be deposited in the backside trench 79 by a conformal deposition process. Excess portions of the insulating material deposited on the top surface of the first contact level dielectric layer 280 may be removed by a planarization process, such as recess etching or a chemical mechanical planarization (CMP) process. Each remaining portion of the insulating material in the backside trench 79 constitutes a dielectric wall structure 76. The dielectric wall structure 76 includes an insulating material, such as silicon oxide, silicon nitride, and / or a dielectric metal oxide. Each dielectric wall structure 76 may extend vertically through a first alternating stack (132, 146) of first insulating layers 132 and first conductive layers 146 and a second alternating stack (232, 246) of second insulating layers 232 and second conductive layers 246, and extend laterally along a first horizontal direction hd1 and be laterally spaced apart from each other along a second horizontal direction hd2. FIG. 25C to FIG. 25E The backside blocking dielectric layer 44 is explicitly shown in FIG.

[0156] refer to Fig.26The sacrificial material of the sacrificial via fill material portion (16,484,584) can be selectively removed relative to the material of the conformal insulating liner (84,486,586) and the first contact level dielectric layer 280. For example, if the sacrificial via fill material portion (16,484,584) includes a doped semiconductor material, such as doped amorphous silicon or polycrystalline silicon, a wet etch using a KOH or TMY solution can be used to remove the sacrificial via fill material portion (16,484,584). If the sacrificial via fill material portion (16,484,584) includes an organic silicate glass or a doped silicate glass (such as borosilicate glass), the sacrificial via fill material portion (16,484,584) can be removed by a wet etch process using dilute hydrofluoric acid. Each stepped via cavity may include a stepped region conformal dielectric via liner 84 and a columnar void 85, the columnar void including a shaft-shaped void region extending through a subset of the alternating stacked (132, 246, 232, 246) layers, a pillar-top-shaped void region overlying the shaft-shaped void region, and a base-shaped void region covering the shaft-shaped void region.

[0157] As used herein, a "columnar" element refers to an element having the general shape of a Doric column, i.e., an element having a shaft portion extending with straight or tapered sidewalls, a capital portion having a larger lateral dimension than the shaft portion and covering the shaft portion, and a base portion having a larger lateral dimension than the shaft portion and located below the shaft portion. Each stepped region conformal dielectric via liner 84 may include: a neck portion 84N, which surrounds the axis portion and extends vertically through a corresponding subset of the layers in the alternating stack (132, 142, 232, 242); an upper cylindrical portion 84U, which surrounds the column top portion and extends through the first contact level dielectric layer 280 and the second backward stepped dielectric material portion 265 and optionally through the first backward stepped dielectric material portion 165; a lower cylindrical portion 84L, which surrounds the base portion and extends through the bottommost first insulating layer 132 and the dielectric buffer layer 768; and a bottom portion, which contacts the top surface of the substrate material layer 909.

[0158] refer to Fig.27A , Fig.27B and Fig.27C, an anisotropic etching process may be performed to remove horizontal portions of the step region conformal dielectric via liner 84 that are not masked by the overlying structure. The anisotropic etching process may include a terminal etching step of etching the physically exposed portion of the backside blocking dielectric layer 44. Thus, the annular top surface of the corresponding topmost conductive layer (146 or 246) in a set of conductive layers (146, 246) and the cylindrical surface of the topmost conductive layer (146 or 246) through which each corresponding columnar void 85 extends may be physically exposed within each step region via cavity. Further, an opening may be formed at the bottommost portion of each step region conformal dielectric via liner 84.

[0159] Each step region conformal dielectric via liner 84 can be divided into a ribbed insulating liner 842 and a cylindrical insulating liner 844. Each ribbed insulating liner 842 includes: a neck portion 84N that continuously extends from the topmost conductive layer (146 and / or 246) within the subset of conductive layers (146 and / or 246) to the bottommost conductive layer (146 and / or 246) within the subset of conductive layers (146 and / or 246); laterally protruding annular ribbed areas 842F that have an annular shape; a cylindrical portion 842C that has a cylindrical shape and is located below the alternating stack (132, 146, 232, 246); and an annular area 842A that is adjacent to the bottom portion of the cylindrical portion 842C and has an annular shape. The outer sidewall of the laterally protruding annular ribbed area 842F can be cylindrical. Each cylindrical insulating liner (eg, spacer) 844 may be embedded within the second stepped back dielectric material portion 265 and may be embedded within the first stepped back dielectric material portion 165. The top surface of the substrate material layer 909 may be physically exposed by an anisotropic etching process under each columnar void 85.

[0160] The anisotropic etching removes horizontal portions of the peripheral region conformal insulating liner 486 and the array region conformal insulating liner 586. The peripheral region cylindrical void 485 may be formed in each peripheral region via cavity, and the array region cylindrical void 585 may be formed in each array region via cavity. The top surface of the substrate material layer 909 may be physically exposed by the anisotropic etching process below the peripheral region cylindrical void 485 and the array region cylindrical void 585.

[0161] refer to FIG. 28A to FIG. 28F, at least one conductive material may be deposited in columnar voids 85, peripheral region cylindrical voids 485, and array region cylindrical voids 585. The at least one conductive material may include a metal liner material that is conformally deposited to form metal liner 86A within each void and a metal fill material that is conformally deposited to form metal fill portion 86B. In one embodiment, metal liner 86A may include a conductive metal nitride (such as tin), and metal fill portion 86B may include a metal (such as tungsten, cobalt, molybdenum, or copper).

[0162] Each combination of the metal liner 86A and the metal filling portion 86B filling the columnar void 85 constitutes a columnar conductive via structure 86C. Each columnar conductive via structure 86C may include a conductive shaft portion 86S extending through the set of conductive layers (146, 246), a conductive pillar top portion 86P covering the conductive shaft portion 86S and contacting the topmost conductive layer (146 or 246) whose top surface is exposed in each columnar void 85, a conductive base portion 86B located below the bottommost conductive layer 146 within the set of conductive layers (146, 246), and a downward protruding portion 86R protruding downward from the conductive base portion 86B. Due to the conformal nature of the deposition process for depositing the conductive material of the columnar conductive via structure 86C, a package void 86V may be present within each conductive base portion 86B. The conductive pillar top portion 86P and the conductive base portion 86B have a larger lateral extent than the conductive shaft portion 86S within each columnar conductive via structure 86C. In one embodiment, each columnar conductive via structure 86C includes a corresponding conductive shaft portion 86S having a first width w1; a corresponding conductive base portion 86B having a second width w2 greater than the first width w1; and a corresponding conductive pillar top portion 86P having a third width w3 greater than the first width w1. The third width w3 can be the same as, greater than, or less than the second width w2, depending on the material composition of the rear stepped dielectric material portion (165, 265) and the dielectric buffer layer 768.

[0163] Each columnar conductive via structure 86C is formed directly on the top surface of the topmost conductive layer (146 or 246) in a set of conductive layers (146, 246) through which the corresponding columnar conductive via structure 86C extends. Except for the topmost conductive layer (146 or 246), each conductive layer (146, 246) in the subset of conductive layers (146, 246) is electrically isolated from the columnar conductive via structure 86C by the ribbed insulating liner 842. Each columnar conductive via structure 86C is formed on the inner sidewalls of the ribbed insulating liner 842 and the cylindrical insulating liner 844. At least one of the columnar conductive via structures 86C can be formed directly on the top surface of the substrate material layer 909.

[0164] Each combination of the metal liner 86A and the metal filling portion 86B filling the peripheral region cylindrical void 485 constitutes a peripheral region contact via structure 488. Each combination of the metal liner 86A and the metal filling portion 86B filling the array region cylindrical void 585 constitutes an array region contact via structure 588. Each of the peripheral region contact via structure 488 and the array region contact via structure 588 may contact the substrate material layer 909. Each conductive layer (146, 246) may include a conductive metal liner 146A and a conductive filling material portion 146B.

[0165] Each combination of the columnar conductive via structure 86C, the ribbed insulating liner 842, and the cylindrical insulating liner 844 located within the step region via cavity constitutes a lateral insulating via structure 86. Each lateral insulating via structure 86 includes a corresponding columnar conductive via structure 86 as a conductive via structure, and includes a corresponding ribbed insulating liner 842 and a corresponding cylindrical insulating liner 844 as lateral insulating structures. The gap between the ribbed insulating liner 842 and the cylindrical insulating liner 844 provides an annular conductive path where the columnar conductive via structure 86C and the conductive layer (146 or 246) make surface-to-surface contact.

[0166] refer to Fig.29A and Fig.29B , the drain contact via structure 88 may be formed directly on the top surface of the drain region 63 through the first contact level dielectric layer 280 .

[0167] refer to Fig.30 , at least one additional dielectric layer may be formed above the first contact level dielectric layer 280, and additional metal interconnect structures (referred to herein as higher-level metal interconnect structures 92) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line-level dielectric layer 284 formed above the first contact level dielectric layer 280. The higher-level metal interconnect structures 92 may include: bit lines 92B, which contact a corresponding one of the drain contact via structures 88; word line connection line structures 92W, which contact a corresponding one of the pillar-shaped conductive via structures 86C; peripheral area line structures 92P, which contact a corresponding one of the peripheral area contact via structures 488; and array area line structures 92A, which contact a corresponding one of the array area contact via structures 588.

[0168] refer to Fig.31, shows an exemplary structure after forming additional metal interconnect structures, additional interconnect level dielectric material layers, and memory side bonding pads 98 to provide a first memory die 1000. The collection of all metal interconnect structures is referred to herein as a memory side metal interconnect structure 92 or a first memory side metal interconnect structure. The memory side metal interconnect structure 92 may include a metal line structure and a metal via structure. The interconnect level dielectric material layer is referred to herein as a memory side dielectric material layer 90 or a first memory side dielectric material layer. The memory side bonding pad 98 may include a conductive bonding pad, such as a copper or copper alloy bonding pad, which may be subsequently used for metal-to-metal bonding with a matching metal bonding pad disposed in another semiconductor die (not shown). The memory side bonding pad 98 in the first memory die 1000 is also referred to as a first memory side bonding pad 98 and is electrically connected to the first memory side metal interconnect structure 92.

[0169] In one embodiment, the first memory die 1000 includes a first alternating stack (132, 146, 232, 246) of first insulating layers 132, 232 and first conductive layers 146, 246, a first memory opening filling structure 58, a first stepped dielectric material portion (165, 265), and a first pillar-shaped conductive via structure 86C, the first memory opening filling structures being located within a first memory opening 49 extending vertically through the first alternating stack (132, 146, 232, 246) and including a first memory element. The stack, the first stepped dielectric material portion contacts the stepped surface of the first alternating stack (132, 146, 232, 246), these first columnar conductive through-hole structures include corresponding conductive axis portions 86S extending vertically through corresponding subsets of the first conductive layers 146, 246, corresponding conductive base portions 86B connected to the first ends of the corresponding conductive axis portions 86S, and corresponding conductive column top portions 86P connected to the second ends of the corresponding conductive axis portions 86S and contacting the annular horizontal surface of a corresponding one of the first conductive layers 146, 246.

[0170] refer to Fig.32, the second carrier substrate 600 can be attached to the horizontal surface of the first memory die 1000, which includes the physically exposed horizontal surface of the first memory side bonding pad 98. For example, a sacrificial adhesive layer (not shown) can be employed to attach the second carrier substrate 600 to the first memory die 1000. Alternatively, oxide-to-oxide bonding can be used to attach an oxide (e.g., silicon oxide) layer on the surface of the second carrier substrate 600 to the oxide (e.g., silicon oxide) layer 90 forming the horizontal surface of the first memory die 1000. The substrate of the second carrier substrate 600 includes a carrier substrate material, which can be selected from any material that can be used for the first carrier substrate 908 as described above.

[0171] refer to FIG. 33A to FIG. 33D , the first carrier substrate 908 may be removed from the assembly of the first memory die 1000 and the second carrier substrate 600. For example, the first carrier substrate 908 may be removed by grinding, polishing, an isotropic etching process, and / or an anisotropic etching process. Alternatively or in addition, a sacrificial spacer layer (not shown) and / or a sacrificial adhesive layer (not shown) may be employed between the first carrier substrate 908 and the assembly of the first memory die 1000 and the second carrier substrate 600 to facilitate the removal and subsequent reuse of the first carrier substrate 908. When the first carrier substrate 908 is removed, the bottom surface (i.e., the backside surface) of the dielectric buffer layer 760 and the end surfaces of the lateral insulating via structure 86, the peripheral region contact via structure 488, and the array region contact via structure 588 may be physically exposed. Specifically, the flat horizontal surface of the conductive base portion 86B of the columnar conductive via structure 86C, the annular cylindrical portion 842C of the ribbed insulating liner 842, and the horizontal end surfaces of the peripheral region contact via structure 488 and the array region contact via structure 588 can be physically exposed when removing the first carrier substrate 908. In the case where the flat horizontal surface of the conductive base portion 86B of the columnar conductive via structure 86C is covered by the insulating material after removing the carrier substrate 908, the insulating material can be removed by selective etching to expose the flat horizontal surface of the conductive base portion 86B of the columnar conductive via structure 86C.

[0172] In the case where the first columnar conductive via structure 86C, the peripheral region contact via structure 488 and the array region contact via structure 588 include copper, a touch-up polishing process can be used so that the physically exposed surface of the logic side bonding pad 788 to the first columnar conductive via structure 86C, the peripheral region contact via structure 488 and the array region contact via structure 588 includes a copper surface that can subsequently be used for copper-to-copper bonding.

[0173] refer to Fig.34A and Fig.34B, a logic die 700 is provided. The logic die 700 includes a driver circuit 720, which may include a complementary metal oxide semiconductor (CMOS) transistor located on a logic substrate, and the logic substrate includes a logic side semiconductor material layer 712. The logic substrate may include a silicon wafer or a silicon-on-insulator wafer, and the logic side semiconductor material layer 712 may include a doped well in the top portion of the logic substrate and / or an epitaxial semiconductor layer located on the logic substrate. The driver circuit 720 may be configured to drive an electrical node within the first memory die 1000. In one embodiment, an optional logic side through-substrate connection structure 730 may be formed in an upper portion of the logic substrate. Each logic side through-substrate connection structure 730 may include a logic side laterally isolated through-substrate via structure 734 and a logic side substrate insulating spacer 732 surrounding the logic side laterally isolated through-substrate via structure 734. A logic die dielectric material layer 760 may be formed above the driver circuit 720 and may be embedded in the logic side dielectric material layer 760. The logic die bonding pads 788 may be embedded in the topmost level of the logic side dielectric material layer 780. The logic side bonding pads 788 are electrically connected to corresponding nodes (e.g., source, drain, or gate) of the driver circuit 720. The pattern of the logic side bonding pads 788 may be a mirror image of the patterns of the first pillar-shaped conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 of the first memory die 1000.

[0174] The logic die 700 may be bonded to the first memory die 1000. The logic die 700 may be attached to the substrate side of the first memory die 1000 by bonding the logic side bonding pad 788 to the first pillar-shaped conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 of the first memory die 1000. Metal-to-metal bonding (such as copper-to-copper bonding) or hybrid bonding (such as metal-to-metal and dielectric-to-dielectric bonding) may be employed to bond the logic side bonding pad 788 to the first pillar-shaped conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 of the first memory die 1000. In one embodiment, each of the logic side bonding pad 788, the first pillar-shaped conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 may include copper, and copper-to-copper bonding may be employed.

[0175] In one embodiment, a first subset of the logic side bonding pads 788 may be bonded to the conductive base portion 86B of the first pillar-shaped conductive via structure 86C via metal-to-metal bonding. A second subset of the logic side bonding pads 788 may be bonded to the planar end surface of the peripheral region contact via structure 488 via metal-to-metal bonding. A third subset of the logic side bonding pads 788 may be bonded to the planar end surface of the array region contact via structure 588 via metal-to-metal bonding. In the case of hybrid bonding, a dielectric-to-dielectric bond (such as an oxide-to-oxide bond) may be formed between the logic side dielectric material layer 760 and the dielectric buffer layer 768 in the first memory die 1000. The first memory die 1000 may be directly attached to the logic die 700.

[0176] refer to Fig.35 , the second carrier substrate 600 may be detached from the bonded assembly including the logic die 700 and the first memory die 1000. A suitable cleaning process may be performed to clean the physically exposed horizontal surfaces of the first memory die 1000.

[0177] A second memory die 1002 may be provided. In one embodiment, the second memory die 1002 includes a second alternating stack (32, 46) of second insulating layers 32 and second conductive layers 46, a second memory opening filling structure 158, and a second stepped dielectric material portion (165, 265) located within a second memory opening extending vertically through the second alternating stack (32, 46) and including a respective vertical stack of second memory elements, the second stepped dielectric material portion contacting a stepped surface of the second alternating stack (32, 46).

[0178] The second memory die 1002 may be formed in the same manner as the first memory die 1000, and includes a pillar-shaped conductive via structure 86C (hereinafter referred to as a second pillar-shaped conductive via structure 86C), a peripheral region contact via structure 488, and an array region contact via structure 588. In one embodiment, the second memory die 1002 includes a second pillar-shaped conductive via structure 86C, the second pillar-shaped conductive via structure including a corresponding conductive shaft portion 86S extending vertically through a corresponding subset of the second conductive layers 46, a corresponding conductive base portion 86B connected to a first end of the corresponding conductive shaft portion 86S, and a corresponding conductive pillar top portion 86P connected to a second end of the corresponding conductive shaft portion 86S and contacting an annular horizontal surface of a corresponding one of the second conductive layers 46. According to an aspect of the disclosure, the pattern of the second pillar conductive via structure 86C, the peripheral area contact via structure 488 and the array area contact via structure 588 in the second memory die 1002 may be the same as the pattern of the first memory side bonding pad 98 of the first memory die 1000 .

[0179] The second memory die 1002 may be bonded to the first memory die 1000. For example, a metal-to-metal bond may be induced between the first memory-side bond pad 98 of the first memory die 1000 and the set of the second pillar-shaped conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 in the second memory die 1002. For example, a copper-to-copper bond may be employed between the first memory-side bond pad 98 of the first memory die 1000 and the set of the second pillar-shaped conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 in the second memory die 1002.

[0180] In one embodiment, a first subset of the memory side bonding pads 98 of the first memory die 1000 can be bonded to the conductive base portion 86B of the second pillar-shaped conductive via structure 86C of the second memory die 1002 via metal-to-metal bonding. A second subset of the memory side bonding pads 98 of the first memory die 1000 can be bonded to the planar end surface of the peripheral region contact via structure 488 of the second memory die 1002 via metal-to-metal bonding. A third subset of the memory side bonding pads 98 of the first memory die 1000 can be bonded to the planar end surface of the array region contact via structure 588 of the second memory die 1002 via metal-to-metal bonding. In the case of hybrid bonding, a dielectric-to-dielectric bond (such as an oxide-to-oxide bond) can be formed between the memory side dielectric material layer 90 of the first memory die 1000 and the dielectric buffer layer 768 in the second memory die 1002. The second memory die 1002 can be directly attached to the first memory die 1000.

[0181] In one embodiment, the second pillar-shaped conductive via structure 86C is electrically connected to a corresponding one of the first pillar-shaped conductive via structures 86C. In one embodiment, the first memory die 1000 includes a first memory-side metal interconnect structure 92 embedded in the first memory-side dielectric material layer 90 and a first memory-side bonding pad 98 electrically connected to the first memory-side metal interconnect structure 92; and the conductive base portion 86B of the second pillar-shaped conductive via structure 86C is bonded to the first memory-side bonding pad 98. The peripheral region contact via structures 488 and / or the array region contact via structures 588 in the first and second memory dies (1000, 1002) can be used to electrically connect the semiconductor devices in the driver circuit 720 in the logic die 700 to an external voltage source.

[0182] exist Fig.36In the illustrated alternative embodiment, the back side of the logic side semiconductor material layer 712 may be optionally thinned, for example, by grinding, polishing, an isotropic etching process (such as a wet etching process) and / or an anisotropic etching process (such as a reactive ion etching process). The thinning of the logic side semiconductor material layer 712 may continue until the surface of the logic side laterally isolated through-substrate via structures 734 (if present) is physically exposed. Each laterally isolated through-substrate via structure 934 may be laterally surrounded by a corresponding substrate insulating spacer 932. Each continuous combination of a substrate insulating spacer 932 and a laterally isolated through-substrate via structure 934 constitutes a logic side through-substrate connection structure 930.

[0183] The back side insulating layer 790 may be deposited on the back side surface of the logic side semiconductor material layer 712 thinned by the thinning process. The back side insulating layer 790 includes an insulating material such as silicon oxide and may have a thickness in the range of 500 nm to 5 microns. The back side bonding structure 798 may be formed in the back side insulating layer 790 so that each back side bonding structure 798 contacts the horizontal surface of a corresponding one of the laterally isolated through-substrate via structures 934. Therefore, each back side bonding structure 798 is located on the back side of the logic side semiconductor material layer 712 (which is the semiconductor substrate of the logic die 700) and is electrically connected to a corresponding one of the laterally isolated through-substrate via structures 934. The back side bonding structure 798 may be used to electrically connect the semiconductor device in the driver circuit 720 in the logic die 700 to an external voltage source.

[0184] According to various embodiments of the present disclosure and together with reference to Figures 1A to 36, a bonded assembly includes: a first memory die 1000, the first memory die including a first alternating stack (132, 146, 232, 246) of a first insulating layer (132, 232) and a first conductive layer (146, 246), a first memory opening filling structure 58, a first stepped dielectric material portion (165, 265), and a first pillar-shaped conductive via structure 86C, the first memory opening filling structures being located within first memory openings 49 extending vertically through the first alternating stack and including respective vertical stacks of first memory elements (e.g., portions of a memory film 50, such as portions of a layer 54 of the memory film 50), the first stepped dielectric material portions contacting stepped horizontal surfaces of the first alternating stack, and the first pillar-shaped conductive via structures 86C. A first memory die 1000 includes a corresponding conductive shaft portion 86S extending vertically through a corresponding subset of the first conductive layer (146, 246), a corresponding conductive base portion 86B connected to a first end of the corresponding conductive shaft portion 86S, and a corresponding conductive pillar top portion 86P connected to a second end of the corresponding conductive shaft portion 86S and contacting a horizontal stepped surface of a corresponding one of the first conductive layers (146, 246); and a logic die 700, the logic die including a driver circuit 720 configured to drive electrical nodes (e.g., word lines and bit lines) within the first memory die 1000, a logic side metal interconnect structure 780 embedded in a logic side dielectric material layer 760, and a logic side bonding pad 788 bonded to the conductive base portion 86B of the first pillar conductive via structure 86C.

[0185] In one embodiment, the logic side bonding pad 788 is bonded to the conductive base portion 86B of the first pillar-shaped conductive via structure 86C; the corresponding conductive shaft portion 86S has a first width w1; the corresponding conductive base portion 86B has a second width w2 greater than the first width w1; and the corresponding conductive pillar top portion 86P has a third width w3 greater than the first width w1. In one embodiment, the conductive base portion 86B of the first pillar-shaped conductive via structure 86C is closer to the logic die 700 relative to the distance of any of the first conductive layers (146, 246) within the first alternating stack (132, 146, 232, 246) to the logic die 700. In one embodiment, the logic side bonding pad 788 is bonded to the conductive base portion 86B of the first pillar-shaped conductive via structure 86C via metal-to-metal bonding. In one embodiment, the conductive pillar top portion 86P of the first pillar-shaped conductive via structure 86C is laterally surrounded by the first stepped dielectric material portion (165, 265).

[0186] In one embodiment, each conductive shaft portion 86S of the first cylindrical conductive via structure 86C is laterally surrounded by a corresponding ribbed insulating liner 842, which includes a lateral protrusion located at the level of a subset of the first insulating layer 32. In one embodiment, the corresponding ribbed insulating liner 842 laterally surrounds the conductive base portion 86B of a corresponding one of the first cylindrical conductive via structures 86C. In one embodiment, each conductive pillar top portion 86P of the first cylindrical conductive via structure 86C is laterally surrounded by a corresponding cylindrical insulating liner 844, which includes the same insulating material as the ribbed insulating liner 842.

[0187] In one embodiment, the bonding assembly includes a second memory die 1002 bonded to the first memory die 1000 and including a second alternating stack (32, 46) of second insulating layers 32 and second conductive layers 46, a second memory opening filling structure 158, a second stepped dielectric material portion (165, 265), and a second columnar conductive via structure 86C, wherein the second memory opening filling structures are located within a second memory opening 49 extending vertically through the second alternating stack (32, 46) and include corresponding vertical stacks of second memory elements, the second stepped dielectric material portion contacting a horizontal stepped surface of the second alternating stack (32, 46), and the second columnar conductive via structures include corresponding conductive shaft portions 86S extending vertically through corresponding subsets of the second conductive layers 46, corresponding conductive base portions 86B connected to first ends of the corresponding conductive shaft portions 86S, and corresponding conductive column top portions 86P connected to second ends of the corresponding conductive shaft portions 86S and contacting a horizontal stepped surface of a corresponding one of the second conductive layers 46. In one embodiment, the second pillar-shaped conductive via structures 86C are electrically connected to a corresponding one of the first pillar-shaped conductive via structures 86C.

[0188] In one embodiment, the first memory die 1000 includes a first memory side metal interconnect structure 92 embedded in a first memory side dielectric material layer 90 and a first memory side bonding pad 98 electrically connected to the first memory side metal interconnect structure 92; and a conductive base portion 86B of a second columnar conductive via structure 86C is bonded to the first memory side bonding pad 98.

[0189] In one embodiment, the first memory die 1000 includes a semiconductor material layer 10 located on a first alternating stack; the first memory opening filling structure 58 also includes a corresponding vertical semiconductor channel 60 having an end electrically connected to the semiconductor material layer 10; and the semiconductor material layer 10 has a vertical extent smaller than the conductive base portion of the first columnar conductive via structure 86C.

[0190] refer to Fig.37 , showing a first alternative configuration of the exemplary structure. By removing the second carrier substrate 600 from the bonded assembly including the logic die 700 and the first memory die 1000 and by bonding the second memory die 1002 to the first memory die 1000 so that the first memory side bonding pad 98 in the first memory die 1000 is bonded to the second memory side bonding pad 98 of the second memory die 1002, the Fig.34A and Fig.34B The first exemplary structure shown in derives a first alternative configuration of the exemplary structure. In other words, in this alternative embodiment, the top of the first memory die 1000 is bonded to the top of the second memory die 1002. According to one aspect of the present disclosure, the pattern of the second memory side bonding pads 98 of the second memory die 1002 can be a mirror image of the pattern of the first memory side bonding pads 98 of the first memory die 1000.

[0191] For example, a metal-to-metal bond may be induced between the first memory side bond pad 98 of the first memory die 1000 and the second memory side bond pad 98 of the second memory die 1002. For example, a copper-to-copper bond may be employed between the first memory side bond pad 98 of the first memory die 1000 and the second memory side bond pad 98 of the second memory die 1002. In the case where a hybrid bond is employed, a dielectric-to-dielectric bond (such as an oxide-to-oxide bond) may be formed between the memory side dielectric material layer 90 of the first memory die 1000 and the memory side dielectric material layer 90 in the second memory die 1002. The second memory die 1002 may be directly attached to the first memory die 1000.

[0192] In a first alternative configuration of the exemplary structure, the first memory die 1000 includes a first memory side metal interconnect structure 92 embedded in a first memory side dielectric material layer 90 and a first memory side bonding pad 98 electrically connected to the first memory side metal interconnect structure 92; the second memory die 1002 includes a second memory side metal interconnect structure 92 embedded in a second memory side dielectric material layer 90 and a second memory side bonding pad 98 electrically connected to the second memory side metal interconnect structure 92; and the second memory side bonding pad 98 is bonded to the first memory side bonding pad 98.

[0193] In one embodiment, end surfaces of the second pillar conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 may be physically exposed after the second memory die 1002 is bonded to the first memory die 1000. Optionally, an additional memory die (not shown) may be bonded to the second memory die 1002 such that a bonding structure in the additional memory die is bonded to a corresponding one of the second pillar conductive via structure 86C, the peripheral region contact via structure 488, and the array region contact via structure 588 of the second memory die 1002.

[0194] refer to Fig.38 , you can optionally perform a reference Fig.36 The processing steps are described to thin the back side of the logic side semiconductor material layer 712. The back side insulating layer 790 can be deposited on the back side surface of the logic side semiconductor material layer 712 thinned by the thinning process. The back side bonding structures 798 can be formed in the back side insulating layer 790 so that each back side bonding structure 798 contacts the horizontal surface of a corresponding one of the laterally isolated through substrate via structures 934.

[0195] refer to Fig.39 By attaching the third memory die 1003 to the second memory die 1002, Fig.36 The exemplary structure shown or Fig.38 The first alternative configuration of the exemplary structure shown leads to the second alternative configuration of the exemplary structure. In general, the third memory die 1003 can be formed in the same manner as the first memory die and / or the second memory die (1000 and / or 1002). The metal bonding structure of the third memory die 1003 on the side facing the second memory die 1002 can be arranged as a mirror image of the metal bonding structure of the second memory die 1002. In general, the third memory die 1003 can be attached to the second memory die 1002 before or after thinning the logic die 700.

[0196] In one embodiment, the metal bonding structure of the second memory die 1002 facing the third memory die 1003 may include the second memory side bonding pad 98, and the metal bonding structure of the third memory die 1003 facing the second memory die 1002 may include the third memory side bonding pad 98.

[0197] In another embodiment, the metal bonding structure of the second memory die 1002 facing the third memory die 1003 may include a second memory side bonding pad 98, and the metal bonding structure of the third memory die 1003 facing the second memory die 1002 may include a third columnar conductive via structure 86C, a peripheral area contact via structure 488, and an array area contact via structure 588 located in the third memory die 1003.

[0198] In one embodiment, the metal bonding structure of the second memory die 1002 facing the third memory die 1003 may include a second columnar conductive via structure 86C, a peripheral area contact via structure 488 and an array area contact via structure 588 located in the second memory die 1002, and the metal bonding structure of the third memory die 1003 facing the second memory die 1002 may include a third memory side bonding pad 98.

[0199] In another embodiment, the metal bonding structure of the second memory die 1002 facing the third memory die 1003 may include a second columnar conductive via structure 86C, a peripheral area contact via structure 488, and an array area contact via structure 588 located in the second memory die 1002, and the metal bonding structure of the third memory die 1003 facing the second memory die 1002 may include a third columnar conductive via structure 86C, a peripheral area contact via structure 488, and an array area contact via structure 588 located in the third memory die 1003.

[0200] Various embodiments of the present disclosure may be used to provide zia-type columnar conductive via structures 86C that may be used as bonding structures. These bonding structures provide a more compact memory die 1000 and allow a higher thermal budget to be used to form the logic die 700 before bonding the logic die to the memory die 1000.

[0201] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joining assembly, comprising: a first memory die comprising a first alternating stack of first insulating layers and first conductive layers, a first memory opening filling structure located within a first memory opening extending vertically through the first alternating stack and comprising a respective vertical stack of first memory elements, the first stepped dielectric material portion contacting a horizontal stepped surface of the first alternating stack, and a first pillar-shaped conductive via structure comprising a respective conductive shaft portion extending vertically through a respective subset of the first conductive layers, a respective conductive base portion connected to a first end of the respective conductive shaft portion, and a respective conductive pillar top portion connected to a second end of the respective conductive shaft portion and contacting the horizontal stepped surface of a respective one of the first conductive layers; and A logic die includes a driver circuit for the memory die, a logic side metal interconnect structure embedded in the logic side dielectric material layer, and a logic side bonding pad bonded to the first pillar-shaped conductive via structure.

2. The joint assembly of claim 1, wherein: the logic-side bonding pad being bonded to the conductive base portion of the first pillar-shaped conductive via structure; The corresponding conductive shaft portion has a first width; the respective conductive base portion having a second width greater than the first width; and The respective conductive pillar top portions have a third width greater than the first width.

3. The joint assembly according to claim 1, wherein: The conductive base portion of the first pillar-shaped conductive via structure is closer to the logic die than any one of the first conductive layers within the first alternating stack is to the logic die.

4. The joint assembly of claim 1, wherein: The logic-side bond pad is bonded to the conductive base portion of the first pillar-shaped conductive via structure via a metal-to-metal bond.

5. The joint assembly of claim 1, wherein: The conductive pillar top portion of the first pillar-shaped conductive via structure is laterally surrounded by the first stepped dielectric material portion.

6. The joint assembly of claim 1, wherein: Each conductive shaft portion of the first cylindrical conductive via structure is laterally surrounded by a respective ribbed insulating liner comprising lateral protruding portions at the level of a subset of the first insulating layer.

7. The joint assembly of claim 6, wherein: The respective ribbed insulating liner laterally surrounds a conductive base portion of a respective one of the first cylindrical conductive via structures.

8. The joint assembly of claim 6, wherein: Each conductive pillar top portion of the first pillar-shaped conductive via structure is laterally surrounded by a corresponding cylindrical insulating liner comprising the same insulating material as the ribbed insulating liner.

9. The bonding assembly of claim 1 , further comprising a second memory die bonded to the first memory die and comprising a second alternating stack of second insulating layers and second conductive layers, a second memory opening filling structure, a second stepped dielectric material portion, and a second columnar conductive via structure, the second memory opening filling structure being located within a second memory opening extending vertically through the second alternating stack and comprising a corresponding vertical stack of second memory elements, the second stepped dielectric material portion contacting a horizontal stepped surface of the second alternating stack, the second columnar conductive via structure comprising a corresponding conductive axis portion extending vertically through a corresponding subset of the second conductive layers, a corresponding conductive base portion connected to a first end of the corresponding conductive axis portion, and a corresponding conductive column top portion connected to a second end of the corresponding conductive axis portion and contacting the horizontal stepped surface of a corresponding one of the second conductive layers.

10. The joint assembly of claim 9, wherein: The second columnar conductive via structure is electrically connected to a corresponding one of the first columnar conductive via structures.

11. The joint assembly of claim 10, wherein: The first memory die includes a first memory side metal interconnect structure embedded within a first memory side dielectric material layer and a first memory side bond pad electrically connected to the first memory side metal interconnect structure; The second memory die includes a second memory side metal interconnect structure embedded within a second memory side dielectric material layer and a second memory side bond pad electrically connected to the second memory side metal interconnect structure; and The second memory side bonding pad is bonded to the first memory side bonding pad.

12. The joint assembly of claim 10, wherein: The first memory die includes a first memory side metal interconnect structure embedded within a first memory side dielectric material layer and a first memory side bond pad electrically connected to the first memory side metal interconnect structure; and The conductive base portion of the second pillar-shaped conductive via structure is bonded to the first memory-side bond pad.

13. The joint assembly of claim 1, wherein: the first memory die comprising a layer of semiconductor material on the first alternating stack; The first memory opening filling structure further includes a corresponding vertical semiconductor channel having an end electrically connected to the semiconductor material layer; and The layer of semiconductor material has a smaller vertical extent than the conductive base portion of the first pillar-shaped conductive via structure.

14. A method for forming a joint assembly, the method comprising: providing a first memory die, wherein the first memory die comprises a first alternating stack comprising a first insulating layer and a first conductive layer, a first memory opening filling structure, a first stepped dielectric material portion, and a first pillar-shaped conductive via structure, the first memory opening filling structure being located within a first memory opening extending vertically through the first alternating stack and comprising a respective vertical stack of first memory elements, the first stepped dielectric material portion contacting a horizontal stepped surface of the first alternating stack, the first pillar-shaped conductive via structure comprising a respective conductive shaft portion extending vertically through a respective subset of the first conductive layers, a respective conductive base portion connected to a first end of the respective conductive shaft portion, and a respective conductive pillar top portion connected to a second end of the respective conductive shaft portion and contacting the horizontal stepped surface of a respective one of the first conductive layers; providing a logic die, the logic die comprising a driver circuit, a logic side metal interconnect structure embedded in a logic side dielectric material layer, and a logic side bonding pad; as well as The logic-side bond pad is bonded to the conductive base portion of the first pillar-shaped conductive via structure.

15. The method according to claim 14, wherein: the logic-side bond pad being bonded to the conductive base portion of the first pillar-shaped conductive via structure via a metal-to-metal bond; and The first memory opening filling structure also includes a corresponding vertical semiconductor channel.

16. The method according to claim 14, further comprising: providing a second memory die, wherein the second memory die includes a second alternating stack of second insulating layers and second conductive layers, a second memory opening filling structure, a second stepped dielectric material portion, the second memory opening filling structure being located within a second memory opening extending vertically through the second alternating stack and including a corresponding vertical stack of second memory elements, the second stepped dielectric material portion contacting a horizontally stepped surface of the second alternating stack; as well as The second memory die is bonded to the first memory die.

17. The method according to claim 16, wherein: The second memory die includes a second columnar conductive via structure, which includes a corresponding conductive axis portion extending vertically through a corresponding subset of the second conductive layers, a corresponding conductive base portion connected to a first end of the corresponding conductive axis portion, and a corresponding conductive column top portion connected to a second end of the corresponding conductive axis portion and contacting the horizontal stepped surface of a corresponding one of the second conductive layers.

18. The method according to claim 17, wherein: The second columnar conductive via structure is electrically connected to a corresponding one of the first columnar conductive via structures.

19. The method of claim 17, wherein: The first memory die includes a first memory side metal interconnect structure embedded within a first memory side dielectric material layer and a first memory side bond pad electrically connected to the first memory side metal interconnect structure; and The conductive base portion of the second pillar-shaped conductive via structure is bonded to the first memory-side bond pad.

20. The method of claim 16, wherein: The first memory die includes a first memory side metal interconnect structure embedded within a first memory side dielectric material layer and a first memory side bond pad electrically connected to the first memory side metal interconnect structure; The second memory die includes a second memory side metal interconnect structure embedded within a second memory side dielectric material layer and a second memory side bond pad electrically connected to the second memory side metal interconnect structure; and The second memory side bonding pad is bonded to the first memory side bonding pad.

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