Semiconductor structure for detecting metal bonding strength and test method

Abstract

The application provides a semiconductor structure and a testing method for detecting metal bonding strength, the semiconductor structure comprising: a first substrate; a first dielectric layer on the first substrate and two first metal bonding layers on the first dielectric layer; a second substrate; a second metal bonding layer on a first surface of the second substrate, the first substrate and the second substrate being bonded by the first metal bonding layer and the second metal bonding layer; a first testing terminal and a second testing terminal; a first metal interconnection structure and a second metal interconnection structure in the first dielectric layer, the first testing terminal and the second testing terminal being electrically connected to the two first metal bonding layers through the first metal interconnection structure and the second metal interconnection structure respectively; and a conductive layer, the conductive layer being electrically connected to the testing terminals through the first metal interconnection structure or the second metal interconnection structure. The application can realize fast, accurate and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer and the second metal bonding layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and testing method for detecting the strength of metal bonding. Background Technology

[0002] Micro-Electro-Mechanical Systems (MEMS) are typical systems that integrate sensors, micro-actuators, and micro-circuits, and are widely used in many fields such as automotive, aerospace, biomedicine, and military.

[0003] Metal bonding is a critical step in the manufacturing process of MEMS devices, used to permanently encapsulate the silicon substrate with a capping layer to form a sealed cavity structure. The degree of metal bonding directly affects the mechanical strength, hermeticity, and lifespan of MEMS devices. Therefore, establishing an efficient and accurate testing method is essential to ensuring the quality and performance of MEMS devices. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, the present invention provides a semiconductor structure for detecting metal bond strength, the semiconductor structure comprising:

[0006] First base;

[0007] A first dielectric layer located on the first substrate and two spaced-apart first metal bonding layers located on the first dielectric layer;

[0008] Second basement;

[0009] A second metal bonding layer is disposed on the first surface of the second substrate and corresponding to the first metal bonding layer, wherein the first substrate and the second substrate are bonded through the first metal bonding layer and the second metal bonding layer;

[0010] First test terminal and second test terminal;

[0011] A first metal interconnect structure and a second metal interconnect structure are located in the first dielectric layer. The first test terminal is electrically connected to one of the first metal bonding layers through the first metal interconnect structure, and the second test terminal is electrically connected to the other first metal bonding layer through the second metal interconnect structure.

[0012] A conductive layer corresponding to the second substrate and disposed on the first dielectric layer; the conductive layer is electrically connected to the first test terminal or the second test terminal through the first metal interconnect structure or the second metal interconnect structure.

[0013] In some embodiments of this application, a third substrate and a second dielectric layer are also included, wherein the second surface of the second substrate and the third substrate are bonded together through the second dielectric layer.

[0014] In some embodiments of this application, a first chamber is formed between the first substrate and the second substrate, and a second chamber is formed between the third substrate and the second substrate. An opening is provided in the second substrate, and the first chamber and the second chamber are connected through the opening.

[0015] In some embodiments of this application, the first metal bonding layer comprises aluminum and the second metal bonding layer comprises germanium.

[0016] In some embodiments of this application, the semiconductor structure is disposed in at least one exposure area of ​​the wafer, and a MEMS device is also disposed in the exposure area.

[0017] In another aspect, the present invention provides a method for testing the metal bond strength, the method comprising:

[0018] Provide a semiconductor structure as described in any one of the above descriptions for detecting the strength of metal bonds;

[0019] The semiconductor structure is subjected to capacitance testing based on the first test terminal and the second test terminal in the semiconductor structure to obtain capacitance test data;

[0020] The bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined based on the capacitance test data.

[0021] In some embodiments of this application, determining the bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure based on the capacitance test data includes:

[0022] The actual bonding thickness between the first metal bonding layer and the second metal bonding layer is calculated based on the capacitance test data.

[0023] The mutual solubility thickness between the first metal bonding layer and the second metal bonding layer is calculated based on the actual bonding thickness.

[0024] The bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined based on the mutual solubility thickness.

[0025] In some embodiments of this application, the actual bonding thickness is calculated based on the following formula:

[0026]

[0027] Wherein, C is the capacitance test data, k is the dielectric constant of the semiconductor structure, ε0 is the dielectric constant of vacuum, A is the overlapping area between the mass block in the second substrate and the conductive layer in the first substrate in the semiconductor structure, and d0 is the actual bonding thickness.

[0028] In some embodiments of this application, the mutual solubility thickness is positively correlated with the original thickness of the second metal bonding layer.

[0029] In some embodiments of this application, the mutual solubility thickness and the degree of bonding are positively correlated.

[0030] The present invention relates to a semiconductor structure and testing method for detecting metal bonding strength. The second substrate of the semiconductor structure and the conductive layer disposed on the first dielectric layer can constitute a capacitor structure. The capacitance of the semiconductor structure can be tested through the first test terminal and the second test terminal. Then, the bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure can be determined based on the capacitance test data. The test is highly efficient, the test data is accurate, and it does not damage the semiconductor structure. It quantifies the bonding degree of the first metal bonding layer and the second metal bonding layer, and can achieve fast, accurate, and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer and the second metal bonding layer. Attached Figure Description

[0031] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0032] In the attached image:

[0033] Figure 1 A cross-sectional schematic diagram of a semiconductor structure with strong metal bonding according to a specific embodiment of the present invention is shown.

[0034] Figure 2 A flowchart of a method for testing the metal bond strength according to a specific embodiment of the present invention is shown.

[0035] Figure 3 shows a test result diagram of a wafer according to a specific embodiment of the present invention. Detailed Implementation

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0037] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0042] Traditional metal bonding testing methods have many shortcomings, such as low testing efficiency, inaccurate test data, and highly destructive testing processes.

[0043] Therefore, in view of the aforementioned technical problems, the present invention proposes a semiconductor structure with strong metal bonding, the semiconductor structure comprising: a first substrate; a first dielectric layer located on the first substrate and two spaced-apart first metal bonding layers located on the first dielectric layer; a second substrate; a second metal bonding layer located on a first surface of the second substrate and corresponding to the first metal bonding layers, the first substrate and the second substrate being bonded together through the first metal bonding layers and the second metal bonding layers; a first test terminal and a second test terminal; a first metal interconnect structure and a second metal interconnect structure located in the first dielectric layer, the first test terminal being electrically connected to one of the first metal bonding layers through the first metal interconnect structure, and the second test terminal being electrically connected to the other first metal bonding layer through the second metal interconnect structure; a conductive layer corresponding to the second substrate and disposed on the first dielectric layer; the conductive layer being electrically connected to the first test terminal or the second test terminal through the first metal interconnect structure or the second metal interconnect structure.

[0044] According to the semiconductor structure with strong metal bonding according to this application, the second substrate of the semiconductor structure and the conductive layer disposed on the first dielectric layer can form a capacitor structure. The capacitor structure can be tested by the first test terminal and the second test terminal. Then, the bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure can be determined based on the capacitor test data. The test is efficient, the test data is accurate, and it will not damage the semiconductor structure. It can achieve fast, accurate, and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer and the second metal bonding layer.

[0045] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0046] Example 1

[0047] The following is for reference. Figure 1 This application describes a semiconductor structure with strong metal bonding according to an embodiment of the present application. The semiconductor structure with strong metal bonding includes: a first substrate 111; a first dielectric layer 112 located on the first substrate 111 and two spaced-apart first metal bonding layers 113 located on the first dielectric layer 112; a second substrate 121; a second metal bonding layer 122 located on a first surface of the second substrate 121 and corresponding to the first metal bonding layers 113, wherein the first substrate 111 and the second substrate 121 are bonded through the first metal bonding layers 113 and the second metal bonding layer 122; a first test terminal 114 and a second test terminal 115 located on the first dielectric layer 111; The first metal interconnect structure 116 and the second metal interconnect structure 117 in 12 are used to connect the first test terminal 114 to one of the first metal bonding layers 113 through the first metal interconnect structure 116, and the second test terminal 115 to the other first metal bonding layer 113 through the second metal interconnect structure 117. The conductive layer 118, which corresponds to the second substrate 121 and is disposed on the first dielectric layer 112, is electrically connected to the first test terminal 114 or the second test terminal 115 through the first metal interconnect structure 116 or the second metal interconnect structure 117.

[0048] Specifically, in this embodiment, the second substrate 121 of the semiconductor structure and the conductive layer 118 disposed on the first dielectric layer 112 can constitute a capacitor structure. The semiconductor structure is subjected to capacitance testing through the first test terminal 114 and the second test terminal 115. Based on the capacitance test data, the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure can be determined. The test is efficient, the test data is accurate, and it does not damage the semiconductor structure. It quantifies the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122, and enables fast, accurate, and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122.

[0049] In some embodiments, the first substrate 111 may be any suitable semiconductor substrate, such as a bulk silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked on insulator (SSOI), silicon on insulator stacked on insulator (S-SiGeOI), silicon on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0050] In some embodiments, the second substrate 121 may have a first surface and a second surface opposite to each other, the first surface being the lower surface of the second substrate 121 and the second surface being the upper surface of the second substrate 121.

[0051] The second substrate 121 may include a device layer and a mass block disposed on the device layer. The conductive layer 118 on the first dielectric layer 112 is disposed corresponding to the mass block in the device layer, thereby forming a capacitor structure through the spaced conductive layer 118 and the mass block. Of course, in addition to the mass block, the mass block on the device layer may be replaced with other types of conductive structures to form a capacitor structure with the conductive layer 118 on the first dielectric layer 112, and there is no limitation on this.

[0052] In some embodiments, the first metal bonding layer 113 may include aluminum (Al) and the second metal bonding layer 122 may include germanium (Ge). Of course, the first metal bonding layer 113 and the second metal bonding layer 122 may also include any other suitable metal, and there is no limitation thereto.

[0053] In some embodiments, the first test terminal 114 and the second test terminal 115 may be located on the first dielectric layer 112 outside the first metal bonding layer 113, or they may be disposed on the second substrate 121, as long as it can be ensured that the capacitance test can be performed on the capacitor structure formed by the second substrate 121 and the conductive layer 118 through the first test terminal 114 and the second test terminal 115.

[0054] In some embodiments, the materials of the first test terminal 114, the second test terminal 115, the first metal interconnect structure 116, and the second metal interconnect structure 117 can be any suitable metal material, including but not limited to at least one metal selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al.

[0055] In some embodiments, contact holes are provided in the first dielectric layer 112 at positions corresponding to the first metal bonding layer 113 and the test end. Metal plugs are formed by filling the contact holes with metal material. The first test end 114 and one of the first metal bonding layers 113 are electrically connected to the first metal interconnect structure 116 through their corresponding metal plugs. The second test end 115 and the other first metal bonding layer 113 are electrically connected to the second metal interconnect structure 117 through their corresponding metal plugs. The metal material filled in the contact holes can be any suitable metal material, including but not limited to at least one metal selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al.

[0056] In some embodiments, the material of the first dielectric layer 112 may be silicon dioxide or any other suitable dielectric material, and there is no limitation thereto.

[0057] In some embodiments, a third substrate 131 and a second dielectric layer 141 are also included, wherein the second surface of the device layer 121 and the third substrate 131 are bonded together through the second dielectric layer 141.

[0058] The third substrate can be any suitable semiconductor substrate, and the material of the second dielectric layer 141 can be referred to the description of the first dielectric layer 112 above. There are no limitations on the material of the second dielectric layer 141.

[0059] In some embodiments, such as Figure 1 As shown, a first chamber 123 is formed between a first base 111 and a second base 121, and a second chamber 132 is formed between a third base 131 and a second base 121. An opening 124 is provided in the second base 121, and the first chamber 123 and the second chamber 132 are connected through the opening 124.

[0060] The first chamber 123 and the second chamber 132 can simulate the chamber structure in a MEMS device. In a MEMS device, one chamber can be used for the sensor part, such as accommodating structures sensitive to physical quantities like pressure and acceleration. The other chamber can be used as an actuator part, providing space for actuators such as micromotors and micropumps.

[0061] In some embodiments, a semiconductor structure is disposed in at least one exposure area of ​​the wafer, and a MEMS device is also disposed in the exposure area.

[0062] Specifically, the wafer surface can be divided into a grid of rectangular regions of equal size according to the exposure areas. Each region within a grid is called a cell, and each cell contains an exposure area, the area of ​​which is slightly smaller than that of the cell. Each exposure is called a "shot," and multiple device designs (dies) can be located within a single exposure area. Normally, the device designs located in each exposure area of ​​the wafer are MEMS devices. In this embodiment, to test the degree of metal bonding in the MEMS device, a semiconductor structure is located in at least one exposure area of ​​the wafer. For example, a semiconductor structure can be located in one exposure area of ​​the wafer, or in multiple exposure areas of the wafer, or in each exposure area of ​​the wafer. By setting up a semiconductor structure, actual MEMS devices can be simulated using the semiconductor structure. Capacitance tests are performed on the semiconductor structure through the first test terminal 114 and the second test terminal 115. Based on the capacitance test data, the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure can be determined. The test is highly efficient, the test data is accurate, and it does not damage the semiconductor structure. The bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 is quantified, enabling fast, accurate, and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122, so as to reflect the quality and performance of MEMS devices on the same wafer.

[0063] It should be noted that when a semiconductor structure is set in each exposure area of ​​the wafer, the degree of metal bonding and uniformity of different exposure areas of the entire wafer can be detected.

[0064] like Figures 3A-3C As shown in the figure, the green circle area represents the wafer, and each grid contains an exposure area. The red line represents the overflow area where the first metal bonding layer 113 and the second metal bonding layer 122 are bonded. It can be seen that... Figure 3B , Figure 3A and Figure 3C The overflow area in the middle decreases sequentially, that is... Figure 3B , Figure 3A and Figure 3C The bonding degree and uniformity of the first metal bonding layer 113 and the second metal bonding layer 122 are improved.

[0065] Example 2

[0066] According to another aspect of this application, a method for testing the strength of metal bonding is provided.

[0067] For example, such as Figure 2 As shown, the method for testing the metal bond strength of the present invention includes the following steps:

[0068] Step S21: Provide the semiconductor structure for detecting metal bonding strength as described in Embodiment 1;

[0069] Step S22: Perform capacitance testing on the semiconductor structure based on the first test terminal 114 and the second test terminal 115 in the semiconductor structure to obtain capacitance test data.

[0070] Step S23: Determine the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure based on the capacitance test data.

[0071] According to the metal bonding strength testing method of this application, a capacitance test is performed on a semiconductor structure used to detect the metal bonding strength through a first test terminal 114 and a second test terminal 115. Then, the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure is determined based on the capacitance test data. The test is highly efficient, the test data is accurate, and it does not damage the semiconductor structure. It quantifies the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122, and enables fast, accurate, and non-destructive real-time monitoring of the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122.

[0072] In some embodiments, in step S22, the first test terminal 114 and the second test terminal 115 in the semiconductor structure can be connected to an electrical testing instrument to obtain capacitance test data of the semiconductor structure. The capacitance test data includes the capacitance value C of the semiconductor structure.

[0073] In some embodiments, in step S23, determining the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure based on capacitance test data may include: calculating the actual bonding thickness of the first metal bonding layer 113 and the second metal bonding layer 122 based on the capacitance test data; calculating the mutual solubility thickness of the first metal bonding layer 113 and the second metal bonding layer 122 based on the actual bonding thickness; and determining the bonding degree of the first metal bonding layer 113 and the second metal bonding layer 122 in the semiconductor structure based on the mutual solubility thickness.

[0074] After obtaining the capacitance test data, the actual bonding thickness between the first metal bonding layer 113 and the second metal bonding layer 122 can be calculated using any suitable method. For example, the actual bonding thickness can be calculated based on the following capacitance formula:

[0075]

[0076] Where C is the capacitance test data of the semiconductor structure, k is the dielectric constant of the semiconductor structure, ε0 is the dielectric constant of vacuum, A is the overlapping area between the mass block in the second substrate 121 and the conductive layer 118 in the first substrate 111 in the semiconductor structure, and d0 is the actual bonding thickness between the first metal bonding layer 113 and the second metal bonding layer 122.

[0077] Substituting the measured capacitance test data C into the above formula, and given the dielectric constant k of the semiconductor structure, the dielectric constant ε0 of vacuum, and the overlapping area A between the mass block in the second substrate 121 and the conductive layer 118 in the first substrate 111, the actual bonding thickness d0 between the first metal bonding layer 113 and the second metal bonding layer 122 can be calculated.

[0078] From a qualitative perspective, the mutual solubility thickness is positively correlated with the original thickness of the second metal bonding layer 122. That is, the greater the original thickness of the second metal bonding layer 122, the greater the mutual solubility thickness between the first metal bonding layer 113 and the second metal bonding layer 122.

[0079] From a qualitative perspective, after calculating the actual bonding thickness d0 between the first metal bonding layer 113 and the second metal bonding layer 122, the mutual solubility thickness between them can be calculated using any suitable method. For example, the mutual solubility thickness can be calculated based on the following formula:

[0080] d0=d 第二金属键合层 -d 互溶 +d 台阶

[0081] Where d0 is the actual bonding thickness between the first metal bonding layer 113 and the second metal bonding layer 122, d 第二金属键合层 The original thickness of the second metal bonding layer 122 (for example, when the second metal bonding layer 122 is Ge metal, it can be the original thickness of Ge), d 互溶 d represents the mutual solubility thickness between the first metal bonding layer 113 and the second metal bonding layer 122. 台阶 This represents the thickness of the standard step (STD step) in a semiconductor structure.

[0082] Substituting the calculated actual bonding thickness d0 of the first metal bonding layer 113 and the second metal bonding layer 122 into the above formula, and given the original thickness d of the second metal bonding layer 122... 第二金属键合层 The thickness d of the STD step 台阶 That is, the mutual solubility thickness d between the first metal bonding layer 113 and the second metal bonding layer 122 can be calculated. 互溶 .

[0083] The mutual solubility thickness of the first metal bonding layer 113 and the second metal bonding layer 122 is positively correlated with the degree of bonding between the first metal bonding layer 113 and the second metal bonding layer 122. That is, the greater the mutual solubility thickness of the first metal bonding layer 113 and the better the degree of bonding between the first metal bonding layer 113 and the second metal bonding layer 122, the better the mechanical strength, hermeticity and lifespan of the MEMS device on the same wafer.

[0084] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor structure for detecting the strength of metal bonds, characterized in that, The semiconductor structure includes: First base; A first dielectric layer located on the first substrate and two spaced-apart first metal bonding layers located on the first dielectric layer; Second basement; A second metal bonding layer is disposed on the first surface of the second substrate and corresponding to the first metal bonding layer, wherein the first substrate and the second substrate are bonded through the first metal bonding layer and the second metal bonding layer; First test terminal and second test terminal; A first metal interconnect structure and a second metal interconnect structure are located in the first dielectric layer. The first test terminal is electrically connected to one of the first metal bonding layers through the first metal interconnect structure, and the second test terminal is electrically connected to the other first metal bonding layer through the second metal interconnect structure. A conductive layer corresponding to the second substrate and disposed on the first dielectric layer; the conductive layer is electrically connected to the first test terminal or the second test terminal through the first metal interconnect structure or the second metal interconnect structure.

2. The semiconductor structure as described in claim 1, characterized in that, It also includes a third substrate and a second dielectric layer, wherein the second surface of the second substrate and the third substrate are bonded together through the second dielectric layer.

3. The semiconductor structure as described in claim 2, characterized in that, A first chamber is formed between the first substrate and the second substrate, and a second chamber is formed between the third substrate and the second substrate. An opening is provided in the second substrate, and the first chamber and the second chamber are connected through the opening.

4. The semiconductor structure as described in claim 1, characterized in that, The first metal bonding layer comprises aluminum, and the second metal bonding layer comprises germanium.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure is disposed in at least one exposure area of ​​the wafer, and a MEMS device is also disposed in the exposure area.

6. A method for testing the strength of metallic bonds, characterized in that, The testing method includes: A semiconductor structure for detecting metal bonding strength as described in any one of claims 1 to 5 is provided; The semiconductor structure is subjected to capacitance testing based on the first test terminal and the second test terminal in the semiconductor structure to obtain capacitance test data; The bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined based on the capacitance test data.

7. The test method as described in claim 6, characterized in that, Determining the bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure based on the capacitance test data includes: The actual bonding thickness between the first metal bonding layer and the second metal bonding layer is calculated based on the capacitance test data. The mutual solubility thickness between the first metal bonding layer and the second metal bonding layer is calculated based on the actual bonding thickness. The bonding degree of the first metal bonding layer and the second metal bonding layer in the semiconductor structure is determined based on the mutual solubility thickness.

8. The test method as described in claim 7, characterized in that, The actual bond thickness is calculated based on the following formula: Wherein, C is the capacitance test data, k is the dielectric constant of the semiconductor structure, ε0 is the dielectric constant of vacuum, A is the overlapping area between the mass block in the second substrate and the conductive layer in the first substrate in the semiconductor structure, and d0 is the actual bonding thickness.

9. The test method as described in claim 8, characterized in that, The mutual solubility thickness is positively correlated with the original thickness of the second metal bonding layer.

10. The test method as described in claim 7, characterized in that, The mutual solubility thickness and the degree of bonding are positively correlated.

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