Method for correcting capacitance measurement value under large electric leakage

Abstract

The invention provides a method for correcting a capacitance measurement value under large electric leakage, and provides a parallel binary model for measuring the capacitance value of a gate oxide layer of a gate oxide MOS (Metal Oxide Semiconductor) device, and the parallel binary model is a parallel circuit model formed by connecting a parallel capacitor Cp and an equivalent resistor Rp in parallel; selecting the parallel binary model through an LCP tester, and measuring the gate oxide MOS device by adopting a frequency f1 to obtain a parallel capacitance Cp1 and a parallel conductance Gp1; calculating a dissipation factor D1 when D1lt; when the value is 0.1, the measured shunt capacitance Cp1 is the capacitance value of the gate oxide layer in the gate oxide MOS device; when D1gt; when the capacitance value is 0.1, a parallel binary model is selected through an LCP tester, the gate oxide MOS device is measured by adopting the frequency f2, parallel capacitance Cp2 and parallel conductance Gp2 are obtained, and the actual capacitance value C of the gate oxide layer of the gate oxide MOS device is obtained.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for correcting a capacitance measurement value under large leakage. Background Art

[0002] LCR (Inductance Capacitance Resistance) tester is a measuring instrument for measuring the electrical parameters of semiconductor inductance, resistance, and capacitance devices. In wafer-level WAT testing, the most common use of LCR tester is to measure capacitance parameters, especially the capacitance value of Gate Oxide. When measuring at the wafer level, the high potential end is usually connected to Bulk and the low potential end is connected to Gate to ensure the accuracy and stability of the measurement. The simplified measurement circuit diagram is as follows: Figure 1 shown.

[0003] LCR meters have high measurement accuracy and a wide range of applications. However, in advanced processes such as below 28nm, the thickness of Gate Oxide is getting thinner and thinner, and the leakage current is getting larger and larger, especially in the accumulation area and inversion area of ​​MOS devices. When the voltage rises to close to the operating voltage VDD (or -VDD), the leakage current at the Gate end increases sharply due to direct tunneling current, and the capacitance measurement value often decreases.

[0004] This low capacitance measurement value is not the real value. It is related to the binary measurement model adopted by the capacitance measuring instrument. The capacitance measuring instrument usually simplifies the capacitance measurement into a parallel model ( Figure 2a ) and the series model ( Figure 2b ). The selection of these two capacitance models is built into the measuring instrument for users to choose. The capacitance measurement value at the wafer level is small and is more suitable for the parallel model. Therefore, the traditional wafer-level capacitance measurement uses Figure 2a The parallel binary model shown consists of a parallel circuit formed by a parallel capacitor Cp and an equivalent resistor Rp.

[0005] The actual Gate Oxide cross-section diagram and equivalent circuit diagram are shown in Figure 3 In addition to the parallel connection of Cp and Rp, there is also a series resistor Rs, which is mainly composed of contact resistance and substrate resistance. In traditional processes, Rp is very large, Rs is very small, and Rs is much smaller than Rp, so it is ignored and simplified to Figure 2a However, in advanced technology, due to the thin thickness of Gate Oxide, when the voltage attached to the Gate terminal increases, the leakage current increases sharply due to the direct tunneling current. At this time, the equivalent resistance Rp of the Gate Oxide capacitor decreases sharply, and Rs is no longer much smaller than Rp, and Rs becomes non-negligible.

[0006] The following formula can illustrate the relationship between the value Cm measured by the binary model and the true value Cp, as well as Rp and Rs:

[0007]

[0008] Where ω=2*π*f, f is the test frequency. The Rp of the traditional process is very large, and the Rs / Rp and (Rs / Rp)^2 in the denominator are very small. After calculation, (ω*Cp*Rs)^2 is also small enough to be ignored. Therefore, the measured value Cm is very close to Cp. However, the Rp of the advanced process becomes smaller, and Rs / Rp and (Rs / Rp)^2 become non-ignorable. Therefore, the measured value Cm is less than Cp.

[0009] By adopting higher test frequencies, such as test frequencies above 10M, and using higher-end measuring instruments, such as Keysight E4990, reasonable capacitance values ​​of thin Gate Oxide under advanced processes can also be obtained. However, new problems will also arise: 1. These instruments are not commonly used WAT (Wafer Acceptable Test) measuring equipment, and the degree of automation is not high, so they are not suitable for batch measurement; 2. Higher frequency measurements are usually more sensitive to device structures and parasitic circuits of measuring instruments; inappropriate Layout (circuit design) and hardware environment also make it difficult to obtain reasonable results, and are not suitable for wafer batch production and testing environments. Summary of the invention

[0010] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for correcting the capacitance measurement value under large leakage, which is used to solve the problem in the prior art that the traditional binary model of the LCR meter fails due to large leakage current and the capacitance value is lower than the true value.

[0011] To achieve the above-mentioned object and other related objects, the present invention provides a method for correcting the capacitance measurement value under large leakage, which at least comprises:

[0012] Step 1: providing a parallel binary model for measuring the gate oxide layer capacitance value of a gate oxide MOS device, wherein the parallel binary model is a parallel circuit model formed by connecting a parallel capacitor Cp and an equivalent resistor Rp in parallel;

[0013] Step 2: Select the parallel binary model through the LCP tester, use the frequency f1 to measure the gate oxide MOS device, and obtain the parallel capacitance Cp1 and the parallel conductance Gp1; calculate the dissipation factor D1=Gp1 / (ω*Cp1), where ω=2*π*f1; when D1<0.1, the measured parallel capacitance Cp1 is the capacitance value of the gate oxide layer in the gate oxide MOS device; when D1>0.1, proceed to step 3;

[0014] Step 3: Using the LCP tester, select the parallel binary model, use the frequency f2 to measure the gate oxide MOS device, and obtain the parallel capacitance Cp2 and the parallel conductance Gp2;

[0015] Step 4: Give formula 1: Formula 2: Wherein rs is the resistance value of the series resistor; Cp1, Gp1, Cp2, Gp2 are substituted into Formula 1 and Formula 2 to obtain the actual capacitance value C of the gate oxide layer of the gate oxide MOS device.

[0016] Preferably, in step 2, the gate oxide MOS device is measured using the frequency f1, and the obtained parallel capacitance Cp1 is a capacitance value that changes continuously with different voltages.

[0017] Preferably, in step 2, when the dissipation factor D1>0.1, the parallel capacitor Cp1 is a capacitance value that cannot be accurately measured under large leakage.

[0018] Preferably, in step 2, when the dissipation factor D1>0.1, the parallel capacitance Cp1 tends to increase and then decrease as the voltage increases.

[0019] Preferably, in step 2, when the dissipation factor D1>0.1, when the voltage is greater than 1V, the parallel capacitance Cp1 decreases sharply.

[0020] Preferably, the frequency f2 in step three is a frequency point at which the LCR tester has undergone frequency calibration.

[0021] Preferably, the method for selecting the frequency f2 in step three is: give three frequency values ​​f different from the frequency f1 respectively, and calculate the corresponding three dissipation factors D2=Gp2 / (ω*Cp2), where ω=2*π*f; take the smallest corresponding frequency value in D2 as the frequency f2.

[0022] Preferably, the rs in step 4 is a composition of the contact resistance and the substrate resistance in the gate oxide MOS device.

[0023] As described above, the method for correcting the capacitance measurement value under large leakage of the present invention has the following beneficial effects: the present invention uses the capacitance ternary model calculation formula, adopts a conventional LCR meter to measure two frequencies, and obtains a gate oxide layer capacitance value that is closer to the actual value after calculation. The capacitance value measured under large leakage is corrected. The corrected capacitance value is more consistent with the physical characteristics of the device and is a more reasonable value. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1Shown is a simplified schematic diagram of gate oxide layer capacitance measurement in a gate oxide MOS device in the prior art;

[0025] Figure 2a Shown is a schematic diagram of a binary parallel measurement model of capacitors in the prior art;

[0026] Figure 2b Shown is a schematic diagram of a binary series connection measurement model of capacitors in the prior art;

[0027] Figure 3 Shown is a schematic diagram of a ternary measurement model of capacitance in the prior art;

[0028] Figure 4 It is a schematic diagram of a curve showing the change of capacitance value with voltage measured by the parallel binary model in the LCR measuring instrument of the present invention;

[0029] Figure 5 The graph showing the change of capacitance value with voltage value obtained after calculation in step 4 of the present invention is as follows;

[0030] Figure 6 A comparison chart is shown between the conventional LCR capacitance measurement value, the capacitance measurement value of the present invention, and the capacitance measurement value of Keysight E4990. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0033] The present invention provides a method for correcting a capacitance measurement value under large leakage, which at least comprises:

[0034] Step 1: Provide a parallel binary model for measuring the gate oxide layer capacitance value of a gate oxide MOS device. The parallel binary model is a parallel circuit model formed by connecting a parallel capacitor Cp and an equivalent resistor Rp in parallel; that is, Figure 2a The parallel circuit model in .

[0035] Step 2: Select the parallel binary model through the LCP tester, use the frequency f1 to measure the gate oxide MOS device, and obtain the parallel capacitance Cp1 and the parallel conductance Gp1; calculate the dissipation factor D1=Gp1 / (ω*Cp1), where ω=2*π*f1; when D1<0.1, the measured parallel capacitance Cp1 is the capacitance value of the gate oxide layer in the gate oxide MOS device; when D1>0.1, proceed to step 3;

[0036] The selection of the capacitance model of the parallel binary model is built into the measuring instrument for the user to select. In step 2, the gate oxide layer capacitance in the gate oxide MOS device is measured using frequency f1 to obtain the parallel capacitance Cp1 and the parallel conductance Gp1.

[0037] Furthermore, in the step 2 of this embodiment, the gate oxide MOS device is measured using the frequency f1, and the obtained parallel capacitance Cp1 is a capacitance value that changes continuously with different voltages.

[0038] The present invention further states that in step 2 of this embodiment, when the dissipation factor D1>0.1, the parallel capacitor Cp1 has a capacitance value that cannot be accurately measured under large leakage. The present invention further states that in step 2 of this embodiment, when the dissipation factor D1>0.1, the parallel capacitor Cp1 has a tendency to rise and then fall as the voltage increases. Figure 4 As shown, Figure 4 It is a schematic diagram of a curve showing the change of capacitance with voltage measured by the parallel binary model in the LCR meter of the present invention.

[0039] The present invention further provides that in step 2 of this embodiment, when the dissipation factor D1>0.1, when the voltage is greater than 1V, the parallel capacitance Cp1 decreases sharply. Figure 4 As shown, it can be seen that when the voltage is close to and greater than 1 volt, the capacitance value decreases dramatically. This step 2 requires observing whether the capacitance measurement value is normal. If the capacitance "drops" under high voltage, there is an "uncertain" large leakage capacitance. Calculate the dissipation factor D1 = Gp1 / (ω*Cp1), ω = 2*π*f, where π = 3.1415926. The larger D is, the more serious the device leakage is; when D>0.1, the device meets the characteristics of large leakage capacitance.

[0040] Step 3: Using the LCP tester, select the parallel binary model, use the frequency f2 to measure the gate oxide MOS device, and obtain the parallel capacitance Cp2 and the parallel conductance Gp2;

[0041] In the present invention, the frequency f2 in step 3 of this embodiment is a frequency point of the LCR tester after frequency calibration. The frequency f2 in this step is different from the frequency f1 in step 2.

[0042] The present invention further provides that the method for selecting the frequency f2 in step 3 of this embodiment is: three frequency values ​​f different from the frequency f1 are given respectively, and three corresponding dissipation factors D2=Gp2 / (ω*Cp2), where ω=2*π*f are calculated respectively; and the smallest corresponding frequency value in D2 is taken as the frequency f2. Therefore, the selection of the frequency f2 in this step is based on the calculated value of the dissipation factor D2, and the frequency point where D2 is smaller is selected as much as possible.

[0043] Step 4: Give formula 1: Formula 2: Wherein rs is the resistance value of the series resistor; Cp1, Gp1, Cp2, Gp2 are substituted into Formula 1 and Formula 2 to obtain the actual capacitance value C of the gate oxide layer of the gate oxide MOS device.

[0044] According to the present invention, the rs in step 4 of this embodiment is a composition of the contact resistance and the substrate resistance in the gate oxide MOS device.

[0045] The present invention introduces a more accurate three-element capacitance model through a conventional LCR meter, and can calculate the accurate capacitance value through capacitance measurement at two frequencies. According to the impedance measurement principle, if the Figure 2a The impedance measured by the LCR instrument is: Y(b) = Gp + jωCp; while using the binary capacitor model Figure 3 The actual measured impedance of the ternary capacitor model is: Wherein, C and G are the true values ​​of capacitance and conductance, and rs is the composition of contact resistance and substrate resistance in the gate oxide MOS device. The relationship between the measured values ​​Cp and Gp and the true values ​​C and G can be obtained as follows: In the above relationship, in addition to C and G, which are the values ​​that the present invention hopes to calculate, the series resistance Rs is unknown, so there are three unknown parameters in total. In the process of measuring capacitance using LCR, using a frequency, such as f1, the values ​​of Cp1 and Gp1 can be measured at the same time, and two equations are obtained, which is not enough to obtain the values ​​of C, G, and Rs. If a reference frequency point f2 is added, the values ​​of Cp2 and Gp2 can be measured, and four equations are obtained, and then the values ​​of C and P are obtained by calculation.

[0046] like Figure 5 As shown, Figure 5 The graph shows the change of capacitance value with voltage value obtained after calculation in step 4 of the present invention.

[0047] A solution to the problem of Gate Oxide capacitance “dropping” under advanced technology is to use higher measurement frequency and more accurate measurement instruments. Figure 4 The data point with the most severe "drop" (voltage is 1.5V) was compared and verified, such as Figure 6 As shown, Figure 6 A comparison chart is shown between the conventional LCR capacitance measurement value, the capacitance measurement value of the present invention, and the capacitance measurement value of Keysight E4990. Figure 6 The data in proves that the capacitance value calculated by the present invention is closer to the measurement result of Keysight E4990 than the initial test value. Therefore, the present invention can obtain a measurement method suitable for advanced process large leakage capacitance by using a commonly used LCR meter.

[0048] In summary, the present invention uses a capacitance ternary model calculation formula and a conventional LCR meter to measure two frequencies, and obtains a gate oxide layer capacitance value that is closer to the actual value after calculation. The capacitance value measured under large leakage is corrected. The corrected capacitance value is more consistent with the physical characteristics of the device and is a more reasonable value. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for correcting capacitance measurement under large leakage, characterized in that: At least: Step 1: providing a parallel binary model for measuring the gate oxide layer capacitance value of a gate oxide MOS device, wherein the parallel binary model is a parallel circuit model formed by connecting a parallel capacitor Cp and an equivalent resistor Rp in parallel; Step 2: Select the parallel binary model through the LCP tester, use the frequency f1 to measure the gate oxide MOS device, and obtain the parallel capacitance Cp1 and the parallel conductance Gp1; calculate the dissipation factor D1=Gp1 / (ω*Cp1), where ω=2*π*f1; when D1<0.1, the measured parallel capacitance Cp1 is the capacitance value of the gate oxide layer in the gate oxide MOS device; when D1>0.1, proceed to step 3; Step 3: Using the LCP tester, select the parallel binary model, use the frequency f2 to measure the gate oxide MOS device, and obtain the parallel capacitance Cp2 and the parallel conductance Gp2; Step 4: Give formula 1: Formula 2: Wherein rs is the resistance value of the series resistor; Cp1, Gp1, Cp2, Gp2 are substituted into Formula 1 and Formula 2 to obtain the actual capacitance value C of the gate oxide layer of the gate oxide MOS device.

2. The method for correcting the capacitance measurement value under large leakage according to claim 1, characterized in that: In step 2, the gate oxide MOS device is measured using the frequency f1, and the obtained parallel capacitance Cp1 is a capacitance value that changes continuously with different voltages.

3. The method for correcting the capacitance measurement value under large leakage according to claim 2, characterized in that: In step 2, when the dissipation factor D1>0.1, the parallel capacitor Cp1 has a capacitance value that cannot be accurately measured under large leakage.

4. The method for correcting the capacitance measurement value under large leakage according to claim 3, characterized in that: In step 2, when the dissipation factor D1>0.1, the parallel capacitance Cp1 tends to increase and then decrease as the voltage increases.

5. The method for correcting the capacitance measurement value under large leakage according to claim 4, characterized in that: In step 2, when the dissipation factor D1>0.1, when the voltage is greater than 1V, the parallel capacitance Cp1 decreases sharply.

6. The method for correcting the capacitance measurement value under large leakage according to claim 1, characterized in that: The frequency f2 in step 3 is the frequency point at which the LCR tester has undergone frequency calibration.

7. The method for correcting capacitance measurement under large leakage conditions according to claim 1, characterized in that: The method for selecting the frequency f2 in step three is: give three frequency values ​​f different from the frequency f1 respectively, and calculate the corresponding three dissipation factors D2=Gp2 / (ω*Cp2), where ω=2*π*f; take the smallest corresponding frequency value in D2 as the frequency f2.

8. The method for correcting capacitance measurement under large leakage conditions according to claim 1, characterized in that: The rs in step 4 is the composition of the contact resistance and substrate resistance in the gate oxide MOS device.

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