Register self-checking method, system, electronic device and storage medium under ARM architecture

Abstract

The invention discloses a register self-checking method, system, electronic device and storage medium under ARM architecture. In the method, a connection register lr is used as a register to be checked, and a general register R0-R12 is used as an auxiliary register. A data stack is firstly opened, and the original data in each register is temporarily stored in the data stack, and the starting address of the data stack and the program working mode before modification are also stored in the data stack. Then, the auxiliary register is initialized, and finally, the register to be tested is assigned a value through the auxiliary register, and a March algorithm is used to detect whether a certain bit of data in the register will have an impact on other data when it suddenly changes, so as to realize register self-checking. The self-checking method can detect whether a fault occurs inside the register under the ARM architecture, so as to give an early warning to the system with the fault, so as to prevent unpredictable problems from occurring in the system due to the fault of the register inside the chip.

Description

Technical Field

[0001] The present invention relates to the field of register testing technology, and more specifically, to a register self-test system, electronic equipment and storage medium under an ARM architecture. Background Art

[0002] The main technologies for detecting internal registers of chips in the existing technology are: the patent application entitled "A Self-test Chip and Self-test Method" discloses a test scheme for performing real-time verification operations on data stored in registers, and the patent application entitled "DRAM Fault Detection Method and Device Based on March Algorithm" discloses a test scheme for testing DRAM by reading and writing data in DRAM using the March algorithm.

[0003] However, existing test schemes cannot realize self-check of internal faults of a single register, and can only test whether the register is normal by reading and writing the register once. Existing test methods cannot test whether writing a bit inside the register from 0 to 1 will affect a nearby bit of data.

[0004] In summary, at this stage, there is an urgent need to develop a register self-test method, system, electronic device and storage medium under the ARM architecture to solve the above-mentioned problems. Summary of the invention

[0005] An object of the present invention is to provide a new technical solution for a register self-check method, system, electronic device and storage medium under an ARM architecture.

[0006] According to a first aspect of the present invention, a register self-checking method under an ARM architecture is provided.

[0007] The methods include:

[0008] A register self-checking method under ARM architecture, characterized in that the method comprises:

[0009] Step S1: storing the data in the general registers R0-R7 and the connection register lr into the first data stack;

[0010] Step S2: storing the starting address of the first data stack into the general register R7, and storing the program working mode before modification into the general register R4;

[0011] Step S3: when it is detected that the program working mode is modified, a second data stack is opened in the memory, and the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 are stored in the second data stack, and then the starting address of the second data stack is stored in the general register R7;

[0012] Step S4: Initialize the general registers R0-R12 respectively;

[0013] Step S5: first write the data in the initialized general register Rn into the connection register lr and then write the data in the connection register lr into the general register R0, where n=1-12, to realize the self-detection of the register and obtain the self-detection result.

[0014] Optionally, the step S1 specifically includes:

[0015] Put the data in the general register R7 and the connection register lr into the first data stack;

[0016] The data in the general registers R0-R6 are placed into 7 consecutive data stack storage spaces after the starting address of the first data stack.

[0017] Optionally, the program operating mode is modified by modifying data in a program status register;

[0018] The program working mode is any one of a user mode, a fast interrupt mode, an interrupt mode, a management mode, a stop mode, a system mode and an undefined mode.

[0019] Optionally, step S4 specifically includes: setting the values ​​in general registers R0, R2, R4, R6, R8, R10 and R12 to 0xFFFFFFFF, and setting the values ​​in general registers R1, R3, R5, R7, R9 and R11 to 0x00000000, respectively.

[0020] Optionally, the step S5 specifically includes:

[0021] Write the data in the general register R1 into the connection register lr. At this time, the data stored in the general register R1 and the connection register lr are both 0x00000000;

[0022] Write the data in the general register R2 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0023] Write the data in the general register R1 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0024] Write the data in the general register R3 into the data in the connection register lr, then write the data in the general register R4 into the data in the connection register lr. At this time, the data in the connection register is 0xFFFFFFFF. Finally, write the data in the connection register lr into the general register R0.

[0025] Write the data in general register R5 into connection register lr. At this time, the data in connection register lr is 0x00000000. Then write the data in connection register lr into general register R0.

[0026] Write the data in the general register R6 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0027] Write the data in the general register R7 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0028] Write the data in the general register R8 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0029] Write the data in the general register R9 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0030] Write the data in the general register R10 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0031] Write the data in the general register R11 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0032] The data in the general register R12 is written into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then the data in the connection register lr is written into the general register R0.

[0033] Optionally, after step S5, the following steps are further included:

[0034] Step S6: read the data stored in the corresponding general registers R8-R12 from the second data stack to the general registers R8-R12, read the starting address of the first data stack stored from the second data stack to the general register R7, and read the program working mode before modification from the second data stack to the general register R4, and then read the program working mode before modification from the general register R4 to the program status register.

[0035] Optionally, after step S6, the following steps are further included:

[0036] Step 7: If the self-test result is successful, the data stored in the corresponding general registers R0-R6 are read from the first data stack into the general registers R0-R6, and the data stored in the corresponding general registers R7 and the connection register lr are read from the first data stack and written into the general register R7 and the connection register lr respectively.

[0037] According to a second aspect of the present invention, a register self-checking system under an ARM architecture is provided, the system comprising:

[0038] A first processing module is configured to store data in the general registers R0-R7 and the connection register lr into a first data stack;

[0039] The second processing module is configured to store the starting address of the first data stack into the general register R7, and store the program working mode before modification into the general register R4;

[0040] The third processing module is configured to, when detecting that the program working mode is modified, open a second data stack in the memory, store the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 in the second data stack, and then store the starting address of the second data stack in the general register R7;

[0041] A fourth processing module is configured to initialize the general registers R0-R12 respectively;

[0042] The fifth processing module is configured to write the data in the initialized general register Rn into the connection register lr first and then write the data in the connection register lr into the general register R0, where n=1-12, to realize the self-detection of the register and obtain the self-detection result.

[0043] Optionally, the first processing module is specifically configured to: put the data in the general register R7 and the connection register lr into the first data stack; put the data in the general registers R0-R6 into 7 consecutive data stack storage spaces after the starting address of the first data stack.

[0044] Optionally, the program operating mode is modified by modifying data in a program status register;

[0045] The program working mode is any one of a user mode, a fast interrupt mode, an interrupt mode, a management mode, a stop mode, a system mode and an undefined mode.

[0046] Optionally, the fourth processing module is specifically configured to: set the values ​​in the general registers R0, R2, R4, R6, R8, R10 and R12 to 0xFFFFFFFF, and set the values ​​in the general registers R1, R3, R5, R7, R9 and R11 to 0x00000000, respectively.

[0047] Optionally, the fourth processing module is specifically configured to:

[0048] Write the data in the general register R1 into the connection register lr. At this time, the data stored in the general register R1 and the connection register lr are both 0x00000000;

[0049] Write the data in the general register R2 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0050] Write the data in the general register R1 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0051] Write the data in the general register R3 into the data in the connection register lr, then write the data in the general register R4 into the data in the connection register lr. At this time, the data in the connection register is 0xFFFFFFFF. Finally, write the data in the connection register lr into the general register R0.

[0052] Write the data in general register R5 into connection register lr. At this time, the data in connection register lr is 0x00000000. Then write the data in connection register lr into general register R0.

[0053] Write the data in the general register R6 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0054] Write the data in the general register R7 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0055] Write the data in the general register R8 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0056] Write the data in the general register R9 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0057] Write the data in the general register R10 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0058] Write the data in the general register R11 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0059] The data in the general register R12 is written into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then the data in the connection register lr is written into the general register R0.

[0060] Optionally, the system also includes: a sixth processing module, configured to read out the data stored in the corresponding general registers R8-R12 from the second data stack into the general registers R8-R12, read out the starting address of the first data stack stored from the second data stack into the general register R7, and read out the program working mode before modification from the second data stack into the general register R4, and then read out the program working mode before modification from the general register R4 into the program status register.

[0061] Optionally, the system also includes: a seventh processing module, which is configured to read the data stored in the corresponding general registers R0-R6 from the first data stack into the general registers R0-R6 if the self-test result is successful, and read the data stored in the corresponding general registers R7 and connection register lr from the first data stack to write them into the general register R7 and connection register lr respectively.

[0062] According to a third aspect of the present invention, an electronic device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a register self-test method under an ARM architecture as described in the first aspect of the present invention are implemented.

[0063] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the register self-test method under the ARM architecture as described in the first aspect of the present invention are implemented.

[0064] According to an embodiment disclosed in the present invention, a register self-checking method and system under an ARM architecture of the present invention has the following beneficial effects:

[0065] In the register self-checking method under the ARM architecture of the present invention, the connection register lr is used as the register to be checked, the general registers R0-R12 are used as auxiliary registers, a data stack is first opened, the original data in each register is temporarily stored in the data stack, and the starting address of the data stack and the program working mode before modification are also stored in the data stack, and then the auxiliary register is initialized, and finally the register to be tested is assigned a value through the auxiliary register and the March algorithm is used to detect whether a certain bit of data in the register will have an impact on other data, so as to realize register self-checking; the present invention provides a self-checking method for internal faults of a single register, which can detect whether a fault occurs inside the register under the ARM architecture, thereby giving an early warning to the system with the fault, and preventing unpredictable problems in the system due to the internal register fault of the chip.

[0066] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0068] Figure 1 A schematic diagram of a flow chart of a register self-checking method under an ARM architecture provided according to an embodiment;

[0069] Figure 2 A schematic diagram of the structure of a register self-check system under an ARM architecture provided according to an embodiment;

[0070] Figure 3 A schematic diagram of an electronic device. DETAILED DESCRIPTION

[0071] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0072] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0073] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0074] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0075] Embodiment 1:

[0076] See also Figure 1 As shown, an embodiment of the present invention provides a register self-checking method under an ARM architecture, the method comprising:

[0077] Step S1: Store the data in the general registers R0-R7 and the link register lr into the first data stack.

[0078] It should be noted that, in this embodiment, before performing register self-test, an original data stack is first opened in the memory. The size of the data stack can be 320 bytes, and of course it can also be other sizes, which are determined according to the actual amount of stored data and are not listed here one by one.

[0079] Optionally, step S1 in the register self-checking method under the ARM architecture of this embodiment specifically includes:

[0080] Put the data in the general register R7 and the connection register lr into the first data stack;

[0081] The data in the general registers R0-R6 are placed into 7 consecutive data stack storage spaces after the starting address of the first data stack.

[0082] It should be noted that, at this time, in this embodiment, the data in the first data stack is sorted as: R7-1r-R0-R1-R2-R3-R4-R5-R6.

[0083] Step S2: Store the starting address of the first data stack into the general register R7, and store the program working mode before modification into the general register R4.

[0084] It should be noted that in this embodiment, the data of general registers R7 and R4 have been placed in the first data stack in step S1. At this time, general register R7 is used to store the starting address of the first data stack, and general register R4 is used to store the program working mode before modification. For example, the program working mode is the management mode at this time, and the program status register is used to record and store the current program working mode.

[0085] Step S3: when it is detected that the program working mode is modified, a second data stack is opened in the memory, and the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 are stored in the second data stack, and then the starting address of the second data stack is stored in the general register R7;

[0086] In this embodiment, the size of the second data stack can be 320 bytes, and of course it can be other sizes, which are determined according to the actual amount of stored data, and are not listed here one by one.

[0087] Optionally, in the register self-check method under the ARM architecture of this embodiment, the program working mode is modified by modifying the data in the program status register;

[0088] The program working mode is any one of the user mode, fast interrupt mode, interrupt mode, management mode, abort mode, system mode and undefined mode.

[0089] It should be noted that the program working mode is set by writing data to the program status register, but when the written data is compared and found to be inconsistent with the previous original data, it is determined that the program working mode is modified.

[0090] Since different working modes of the program correspond to different data stack addresses, when the working mode of the program changes, the data stack address will change. At this time, the first data stack starting address (data stack address) in the original program working mode placed in R7 is placed in the second data stack (new data stack), and the second data stack starting address is placed in the R7 register.

[0091] In the processor mode of the ARM architecture, there are generally 17 registers, namely general registers R0-R15 and register CPSR. Among them, the general register R14 is called the link register (lr, i.e. Link Register), which is mainly used to store the subroutine return address or interrupt return address. In addition to system mode and user mode, there is also register SPSR in other modes (registers CPSR and SPSR are both program status registers, among which register SPSR is used to save the value in CPSR before the interrupt, so as to restore the processor program status after the interrupt returns). Among these registers, except for the stack pointer register R13 and the program counter R15 (PC) and registers CPSR and SPSR, the remaining registers can use the March algorithm for self-test.

[0092] Since the data stored in the general registers R8-R15 in different working modes are inconsistent, it is necessary to store the data in the general registers used in R8-R15 into the data stack after the working mode is switched. Therefore, after the program working mode is modified, the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 are stored in the second data stack.

[0093] Step S4: Initialize the general registers R0-R12 respectively;

[0094] Before starting the self-test, the general registers R0-R12 need to be initialized, that is, the values ​​in the general registers need to be set.

[0095] Optionally, step S4 in the register self-test method under the ARM architecture of this embodiment is specifically: setting the values ​​in the general registers R0, R2, R4, R6, R8, R10 and R12 to 0xFFFFFFFF, and setting the values ​​in the general registers R1, R3, R5, R7, R9 and R11 to 0x00000000, respectively.

[0096] Step S5: first write the data in the initialized general register Rn into the connection register lr and then write the data in the connection register lr into the general register R0, where n=1-12, to realize the self-detection of the register and obtain the self-detection result.

[0097] It should be noted that by first writing the general registers R0-R12 into the connection register lr and then writing the data in the connection register lr into the general register R0, it is verified that no matter whether the data in the connection register lr changes from 0 to 1 or from 1 to 0, it will not affect the reading or writing of data from the general registers R0-R12 to the connection register lr.

[0098] Optionally, step S5 in the register self-checking method under the ARM architecture of this embodiment specifically includes:

[0099] Write the data in the general register R1 into the connection register lr. At this time, the data stored in the general register R1 and the connection register lr are both 0x00000000;

[0100] Write the data in the general register R2 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0101] Write the data in the general register R1 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0102] Write the data in the general register R3 into the data in the connection register lr, then write the data in the general register R4 into the data in the connection register lr. At this time, the data in the connection register is 0xFFFFFFFF. Finally, write the data in the connection register lr into the general register R0.

[0103] Write the data in general register R5 into connection register lr. At this time, the data in connection register lr is 0x00000000. Then write the data in connection register lr into general register R0.

[0104] Write the data in the general register R6 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0105] Write the data in the general register R7 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0106] Write the data in the general register R8 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0107] Write the data in the general register R9 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0108] Write the data in the general register R10 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0109] Write the data in the general register R11 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0110] The data in the general register R12 is written into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then the data in the connection register lr is written into the general register R0.

[0111] Optionally, the register self-checking method under the ARM architecture of this embodiment further includes after step S5:

[0112] Step S6: read the data stored in the corresponding general registers R8-R12 from the second data stack to the general registers R8-R12, read the starting address of the first data stack stored from the second data stack to the general register R7, and read the program working mode before modification from the second data stack to the general register R4, and then read the program working mode before modification from the general register R4 to the program status register.

[0113] Optionally, the register self-checking method under the ARM architecture of this embodiment further includes after step S6:

[0114] Step 7: If the self-test result is successful, the data stored in the corresponding general registers R0-R6 are read from the first data stack into the general registers R0-R6, and the data stored in the corresponding general registers R7 and the connection register lr are read from the first data stack and written into the general register R7 and the connection register lr respectively.

[0115] The register self-checking method under the ARM architecture of the present invention is described in detail below with a specific embodiment:

[0116] Step 1: Open a data stack of 320 bytes, namely the first data stack.

[0117] Step 2: Put the data in the general register R7 and the connection register lr into the first data stack for temporary storage;

[0118] Step 3: The general register R7 has been stored in the first data stack in step 2. At this time, the data in the general registers R0-R6 are first placed in the 7 consecutive data stack storage spaces starting from the starting address of the first data stack, and then the general register R7 is used as the storage location of the starting address of the first data stack.

[0119] Step 4: Before starting the test, in order to keep the program running in the same state before and after the self-test, the data in the registers involved in the self-test under the ARM architecture needs to be stored in the data stack. Since the data stored in registers R8-R15 in different working modes are inconsistent, the data in the general registers used in R8-R15 needs to be stored in the data stack after the working mode of the chip is switched;

[0120] Step 5: In order to be able to read the program working mode before modification later, it is necessary to read the current program working mode into the general register R4 before switching the program working mode, and then store the data in the general register R4 into the second data stack.

[0121] Step 6: Since there are seven system operation modes under the ARM architecture, namely user mode, fast interrupt mode, interrupt mode, management mode, abort mode, system mode and undefined mode, it is necessary to perform self-test on the corresponding registers in these modes respectively. The following uses the system mode as an example for explanation; write the system mode into the program status register and change the current program working mode to the system mode.

[0122] Step 7: Different working modes correspond to different data stack addresses. When the working mode of the program changes, the data stack address will change. At this time, the first data stack address placed in the general register R7 is placed in the second data stack (ie, the new data stack), and the second data stack address is placed in the general register R7.

[0123] Step 8: As of step 7, the program working mode modification operation is completed. In the processor mode of the ARM architecture, there are generally 17 registers, namely general registers R0-R15 and register CPSR, among which general register R14 is called link register (lr, i.e. Link Register) and is mainly used to store subroutine return address or interrupt return address. In addition to system mode and user mode, there is also register SPSR in other modes (registers CPSR and SPSR are both program status registers, among which register SPSR is used to save the value in CPSR before interruption, so as to restore the processor program status after the interruption returns). Among these registers, except for stack pointer register R13 and program counter R15 (PC) and registers CPSR and SPSR, the rest of the registers can use March algorithm for self-test. The following takes link register lr as an example to illustrate.

[0124] Step 9: Store the data of R8-R12 into the second data stack;

[0125] Step 10: In the previous step, the data in the general registers R0-R12 have been stored in the data stack. The data in the registers R0-R12 can be read and written later. Before starting the March algorithm, the general registers R0-R12 are initialized. The initialization process is as follows:

[0126] Set the value in general register R0 to 0xFFFFFFFF, the value in general register R1 to 0x00000000, the value in general register R2 to 0xFFFFFFFF, and so on, until general register R12 is set to 0xFFFFFFFF;

[0127] Step 11: After the general registers are initialized, the March algorithm self-test begins. The first step of the March algorithm is to write the data in the general register R1 into the connection register lr. At this time, the data stored in the general register R1 and the connection register lr are both 0x00000000. The purpose of this step is to assign an initial value to the connection register lr and to test whether the process of writing data from the general register R1 to the connection register lr is normal.

[0128] Step 12: At this time, the data in the connection register lr is 0x00000000, and the data 0xFFFFFFFF in the general register R2 is written into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF, and the data 0xFFFFFFFF in the connection register lr is written into the general register R0. By comparing the data in the general registers R0 and R2, it is determined whether there is a problem with the register after reading data from the connection register lr to the general register R0 and writing data from the general registers R1 and R2 to the connection register lr and the data in the connection register lr changes from 0 to 1;

[0129] Step 13: At this time, the data in the connection register lr is 0xFFFFFFFF, the data 0x00000000 in the general register R1 is written into the connection register lr, and then the data 0x00000000 in the connection register lr is written into the general register R0. By comparing the data in the general registers R0 and R1, it is determined whether there is a problem in reading data from the connection register lr to the general register R0 and writing data from the general register R1 to the connection register lr, and whether the data in the connection register lr changes from 1 to 0.

[0130] Step 14: At this time, the data in the connection register 1r is 0x00000000, the data 0x00000000 in the general register R3 is written into the connection register 1r, and the data 0xFFFFFFFF in R4 is written into the connection register 1r, and finally the data 0x00000000 in the connection register 1r is written into the general register R0. By comparing the data in the general registers R4 and R0, it is determined whether there is a problem in writing data from the general registers R3 and R4 to the connection register 1r and changing the data in the connection register 1r from 0 to 1;

[0131] Step 15: At this time, the data in the connection register lr is 0xFFFFFFFF, the data 0x00000000 in the general register R5 is written into the connection register lr, and then the data 0x00000000 in the connection register lr is written into the general register R0. By comparing the data in the general registers R5 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R5, and changing the data in the connection register lr from 1 to 0;

[0132] Step 16: At this time, the data in the connection register lr is 0x00000000, and the data 0xFFFFFFFF in the general register R6 is written into the connection register lr, and then the data 0xFFFFFFFF in the connection register lr is written into the general register R0. By comparing the data in the general registers R6 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R6, and changing the data in the connection register lr from 0 to 1;

[0133] Step 17: At this time, the data in the connection register lr is 0xFFFFFFFF, the data 0x00000000 in the general register R7 is written into the connection register lr, and then the data 0x00000000 in the connection register lr is written into the general register R0. By comparing the data in the general registers R7 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R7, and changing the data in the connection register lr from 1 to 0;

[0134] Step 18: At this time, the data in the connection register lr is 0x00000000, and the data 0xFFFFFFFF in the general register R8 is written into the connection register lr, and then the data 0xFFFFFFFF in the connection register lr is written into the general register R0. By comparing the data in the general registers R8 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R8, and changing the data in the connection register lr from 0 to 1;

[0135] Step 19: At this time, the data in the connection register lr is 0xFFFFFFFF, the data 0x00000000 in the general register R9 is written into the connection register lr, and then the data 0x00000000 in the connection register lr is written into the general register R0. By comparing the data in the general registers R9 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R9, and changing the data in the connection register lr from 1 to 0;

[0136] Step 20: At this time, the data in the connection register lr is 0x00000000, the data 0xFFFFFFFF in the general register R10 is written into the connection register lr, and then the data 0xFFFFFFFF in the connection register lr is written into the general register R0. By comparing the data in the general registers R10 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R10, and changing the data in the connection register lr from 0 to 1;

[0137] Step 21: At this time, the data in the connection register lr is 0xFFFFFFFF, the data 0x00000000 in the general register R11 is written into the connection register lr, and then the data 0x00000000 in the connection register lr is written into the general register R0. By comparing the data in the general registers R11 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R11, and changing the data in the connection register lr from 1 to 0;

[0138] Step 22: At this time, the data in the connection register lr is 0x00000000, and the data 0xFFFFFFFF in the general register R12 is written into the connection register lr, and then the data 0xFFFFFFFF in the connection register lr is written into the general register R0. By comparing the data in the general registers R12 and R0, it is determined whether there is a problem in reading data from the connection register lr to R0, reading data from the connection register lr to the general register R12, and changing the data in the connection register lr from 0 to 1;

[0139] Step 23: It is verified through steps 10 to 22 that no matter the data in the connection register lr changes from 0 to 1 or from 1 to 0, it will not affect the general registers R0-R12 reading or writing data to the connection register lr;

[0140] Step 24: In step 9, general registers R8-R12 are stored in the data stack. After the self-check is completed, the data in general registers R8-R12 are read from the second data stack to restore the original data of R8-R12. In step 9, the program working mode before modification has been stored in the second data stack. At this time, the data needs to be read out to the general register R4. In step 9, the stack address of the first data stack is stored in the second data stack. At this time, the data needs to be read out to the general register R7;

[0141] Step 25: In step 24, the program working mode data before modification has been read into the general register R4. Now, the program working mode needs to be rewritten into the program status register to switch back to the working mode before modification;

[0142] Step 26: At this point, the working mode and the data stack start address have been restored to the state before the mode switching. In step 5, it was explained that there are seven modes, and all seven modes need to be self-checked. Switch to other modes here and repeat from step 10 to step 25. I will not go into details here.

[0143] Step 27: If the self-test is successful, the address data stored in the general register R2 is set to 0xff, and then the process goes to step 29;

[0144] Step 28: If the self-test fails, the address data stored in the general register R2 is set to 0xfe;

[0145] It should be noted that the address data stored in the general register R2 is passed in the form of parameters when the test starts.

[0146] Step 29: After the self-check is completed, the data in the general registers R0-R6 needs to be restored, and the data is read from the first data stack and put into R0-R6;

[0147] Step 30: Read the data of the connection register lr and the data of the general register R7 from the first data stack;

[0148] Step 31: deregister the first data stack and end the self-check;

[0149] Step 32: The self-test of the entire connection register LR is completed.

[0150] In summary, in the register self-check method under the ARM architecture of the embodiment of the present invention, the connection register lr is used as the register to be checked, and the general registers R0-R12 are used as auxiliary registers. A data stack is first opened, and the original data in each register is temporarily stored in the data stack, and the starting address of the data stack and the program working mode before modification are also stored in the data stack. Then, the auxiliary register is initialized, and finally the register to be tested is assigned a value through the auxiliary register and the March algorithm is used to detect whether a certain bit of data in the register will have an impact on other data when it mutates, so as to realize register self-check. The embodiment of the present invention provides a self-check method for internal faults of a single register, which can detect whether a fault occurs inside the register under the ARM architecture, thereby giving an early warning to the system with the fault, and preventing unpredictable problems in the system due to internal register faults of the chip.

[0151] Embodiment 2:

[0152] The embodiment of the present invention provides a register self-checking system under the ARM architecture, based on the register self-checking method under the ARM architecture described in the first embodiment, see Figure 2 As shown, the system 100 includes:

[0153] The first processing module 10 is configured to store the data in the general registers R0-R7 and the connection register lr into the first data stack;

[0154] The second processing module 20 is configured to store the starting address of the first data stack into the general register R7, and store the program working mode before modification into the general register R4;

[0155] The third processing module 30 is configured to, when detecting that the program working mode has been modified, open a second data stack in the memory, store the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 in the second data stack, and then store the starting address of the second data stack in the general register R7;

[0156] The fourth processing module 40 is configured to initialize the general registers R0-R12 respectively;

[0157] The fifth processing module 50 is configured to write the data in the initialized general register Rn into the connection register lr first and then write the data in the connection register lr into the general register R0, where n=1-12, to implement self-detection of the register and obtain a self-detection result.

[0158] Optionally, the first processing module in the register self-check system under the ARM architecture of this embodiment is specifically configured to: put the data in the general register R7 and the connection register lr into the first data stack; put the data in the general registers R0-R6 into 7 consecutive data stack storage spaces after the starting address of the first data stack.

[0159] Optionally, in the register self-checking system under the ARM architecture of this embodiment, the program working mode is modified by modifying the data in the program status register;

[0160] The program working mode is any one of the user mode, fast interrupt mode, interrupt mode, management mode, abort mode, system mode and undefined mode.

[0161] Optionally, the fourth processing module in the register self-check system under the ARM architecture of this embodiment is specifically configured to: set the values ​​in the general registers R0, R2, R4, R6, R8, R10 and R12 to 0xFFFFFFFF, and set the values ​​in the general registers R1, R3, R5, R7, R9 and R11 to 0x00000000, respectively.

[0162] Optionally, the fourth processing module in the register self-checking system under the ARM architecture of this embodiment is specifically configured as follows:

[0163] Write the data in the general register R1 into the connection register lr. At this time, the data stored in the general register R1 and the connection register lr are both 0x00000000;

[0164] Write the data in the general register R2 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0165] Write the data in the general register R1 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0166] Write the data in the general register R3 into the data in the connection register lr, then write the data in the general register R4 into the data in the connection register lr. At this time, the data in the connection register is 0xFFFFFFFF. Finally, write the data in the connection register lr into the general register R0.

[0167] Write the data in general register R5 into connection register lr. At this time, the data in connection register lr is 0x00000000. Then write the data in connection register lr into general register R0.

[0168] Write the data in the general register R6 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0169] Write the data in the general register R7 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0170] Write the data in the general register R8 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0171] Write the data in the general register R9 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0172] Write the data in the general register R10 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0.

[0173] Write the data in the general register R11 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0.

[0174] The data in the general register R12 is written into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then the data in the connection register lr is written into the general register R0.

[0175] Optionally, the register self-check system under the ARM architecture of this embodiment also includes: a sixth processing module, which is configured to read out the data stored in the corresponding general registers R8-R12 from the second data stack to the general registers R8-R12, read out the starting address of the first data stack stored from the second data stack to the general register R7, and read out the program working mode before modification from the second data stack to the general register R4, and then read out the program working mode before modification from the general register R4 to the program status register.

[0176] Optionally, the register self-check system under the ARM architecture of this embodiment also includes: a seventh processing module, which is configured to read the data stored in the corresponding general registers R0-R6 from the first data stack into the general registers R0-R6 if the self-check result is successful, and read the data stored in the corresponding general register R7 and the connection register lr from the first data stack to write them into the general register R7 and the connection register lr respectively.

[0177] Embodiment three:

[0178] The present invention discloses an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a register self-checking method under an ARM architecture in any one of the first embodiments disclosed in the present invention are implemented.

[0179] Figure 3 is a structural diagram of an electronic device according to an embodiment of the present invention, such as Figure 3 As shown, the electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected via a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, near field communication (NFC) or other technologies. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a button, a trackball or a touch pad set on the housing of the electronic device, or an external keyboard, touch pad or mouse, etc.

[0180] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a structural diagram of the part related to the technical solution of the present disclosure, and does not constitute a limitation on the electronic device to which the technical solution of the present application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0181] Embodiment 4:

[0182] The embodiment of the present invention discloses a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the register self-checking method under an ARM architecture in any one of the first embodiments of the present invention are implemented.

[0183] Please note that the technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above embodiments only express several implementation methods of the present application, and their descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present application, several variations and improvements can be made, which all belong to the scope of protection of the present application. Therefore, the scope of protection of the patent in this application shall be based on the attached claims.

[0184] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0185] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A register self-checking method under ARM architecture, characterized in that: The method comprises: Step S1: storing the data in the general registers R0-R7 and the connection register lr into the first data stack; Step S2: storing the starting address of the first data stack into the general register R7, and storing the program working mode before modification into the general register R4; Step S3: when it is detected that the program working mode is modified, a second data stack is opened in the memory, and the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 are stored in the second data stack, and then the starting address of the second data stack is stored in the general register R7; Step S4: Initialize the general registers R0-R12 respectively; Step S5: writing the data in the initialized general register Rn into the connection register lr first and then writing the data in the connection register lr into the general register R0, where n=1-12, to realize the self-detection of the register and obtain the self-detection result; The step S1 specifically includes: Put the data in the general register R7 and the connection register lr into the first data stack; Put the data in general registers R0-R6 into 7 consecutive data stack storage spaces after the starting address of the first data stack; After step S5, the following steps are also included: Step S6: read the data stored in the corresponding general registers R8-R12 from the second data stack to the general registers R8-R12, read the starting address of the first data stack stored from the second data stack to the general register R7, and read the program working mode before modification from the second data stack to the general register R4, and then read the program working mode before modification from the general register R4 to the program status register.

2. The register self-checking method under the ARM architecture according to claim 1, characterized in that: Modify the program working mode by modifying the data in the program status register; The program working mode is any one of a user mode, a fast interrupt mode, an interrupt mode, a management mode, a stop mode, a system mode and an undefined mode.

3. The register self-checking method under the ARM architecture according to claim 1, characterized in that: The step S4 specifically includes: setting the values ​​in the general registers R0, R2, R4, R6, R8, R10 and R12 to 0xFFFFFFFF respectively, and setting the values ​​in the general registers R1, R3, R5, R7, R9 and R11 to 0x00000000 respectively.

4. The register self-checking method under the ARM architecture according to claim 3, characterized in that: The step S5 specifically includes: Write the data in the general register R1 into the connection register lr. At this time, the data stored in the general register R1 and the connection register lr are both 0x00000000; Write the data in the general register R2 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0. Write the data in the general register R1 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0. Write the data in the general register R3 into the data in the connection register lr, then write the data in the general register R4 into the data in the connection register lr. At this time, the data in the connection register is 0xFFFFFFFF. Finally, write the data in the connection register lr into the general register R0. Write the data in general register R5 into connection register lr. At this time, the data in connection register lr is 0x00000000. Then write the data in connection register lr into general register R0. Write the data in the general register R6 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0. Write the data in the general register R7 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0. Write the data in the general register R8 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0. Write the data in the general register R9 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0. Write the data in the general register R10 into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then write the data in the connection register lr into the general register R0. Write the data in the general register R11 into the connection register lr. At this time, the data in the connection register lr is 0x00000000. Then write the data in the connection register lr into the general register R0. The data in the general register R12 is written into the connection register lr. At this time, the data in the connection register lr is 0xFFFFFFFF. Then the data in the connection register lr is written into the general register R0.

5. The register self-checking method under the ARM architecture according to claim 1, characterized in that: After step S6, the following steps are also included: Step 7: If the self-test result is successful, the data stored in the corresponding general registers R0-R6 are read from the first data stack into the general registers R0-R6, and the data stored in the corresponding general registers R7 and the connection register lr are read from the first data stack and written into the general register R7 and the connection register lr respectively.

6. A register self-checking system under ARM architecture, the system adopts the method according to any one of claims 1 to 5, characterized in that: The system comprises: A first processing module is configured to store data in the general registers R0-R7 and the connection register lr into a first data stack; Put the data in the general register R7 and the connection register lr into the first data stack; Put the data in general registers R0-R6 into 7 consecutive data stack storage spaces after the starting address of the first data stack; The second processing module is configured to store the starting address of the first data stack into the general register R7, and store the program working mode before modification into the general register R4; The third processing module is configured to, when detecting that the program working mode is modified, open a second data stack in the memory, store the program working mode before modification stored in the general register R4, the starting address of the first data stack stored in the general register R7, and the data in the general registers R8-R12 in the second data stack, and then store the starting address of the second data stack in the general register R7; A fourth processing module is configured to initialize the general registers R0-R12 respectively; The fifth processing module is configured to write the data in the initialized general register Rn into the connection register lr first and then write the data in the connection register lr into the general register R0, where n=1-12, to realize the self-detection of the register and obtain the self-detection result; The sixth processing module is configured to read out the data stored in the corresponding general registers R8-R12 from the second data stack into the general registers R8-R12, read out the starting address of the first data stack stored from the second data stack into the general register R7, and read out the program working mode before modification from the second data stack into the general register R4, and then read out the program working mode before modification from the general register R4 into the program status register.

7. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps in the register self-test method under the ARM architecture described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps in the register self-check method under the ARM architecture according to any one of claims 1 to 5 are implemented.

Images