Hardware-in-the-loop test interface management method and system and computer equipment

Abstract

The invention provides a hardware-in-the-loop test interface management method and system and computer equipment, and the method comprises the steps: obtaining first interface information which comprises interface information provided by hardware equipment on a hardware-in-the-loop rack; analyzing a test requirement input by a user, searching in the first interface information based on an analysis result, and recording the searched interface information as second interface information; and performing interface allocation on the second interface information according to an interface allocation strategy determined in advance or in real time, and performing interface connection on the to-be-tested equipment according to an interface allocation result. According to the method and the device, the interface resources of the hardware on the ring rack can be automatically identified, distributed and connected, manual intervention is reduced, the test efficiency of the to-be-tested equipment in the test process is improved, and risks caused by manual misoperation are reduced. Through automatic interface allocation and connection, required interface resources can be quickly prepared for the to-be-tested equipment, and the test preparation time is shortened.

Description

Technical Field

[0001] The present application relates to the field of simulation test technology, and in particular to a hardware-in-the-loop test interface management method and system, and a computer device. Background Art

[0002] Hardware in the loop (HIL) simulation is a development and testing technology for real-time embedded systems. It simulates and adds mathematical representations of relevant dynamic systems through real-time simulation hardware, and then connects to the simulation system platform through the I / O (Input / Output, referred to as I / O) interface. Among them, for the management of I / O interface resources, related technologies have been able to achieve a certain degree of automation. However, although related technologies have made certain progress, there is currently no solution that can fully automate, efficiently and accurately allocate and connect HIL device I / O interface resources.

[0003] In traditional HIL test environments, the allocation and connection of I / O interfaces usually need to be done manually, which is not only inefficient but also prone to errors. Especially in complex test scenarios involving a large number of I / O interfaces and test equipment, manual management becomes more difficult. Moreover, manual management of I / O interface resources often leads to insufficient resource utilization. Sometimes some I / O interfaces may be idle for a long time, while others are overly worn due to frequent use. At the same time, in the process of manually allocating and connecting I / O interfaces, the existence of human factors may cause inconsistencies in the test environment, thereby affecting the accuracy and reliability of the test results. Therefore, with the continuous increase and change of test requirements, traditional manual management methods are difficult to cope with complex test scenarios and expansion requirements. And in traditional test environments, once problems or abnormalities occur in I / O interface resources, it is often difficult to discover and handle them in a timely manner. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a hardware-in-the-loop test interface management method and system, and a computer device, which are used to solve the problems of I / O interface allocation and connection when performing HIL testing in the prior art.

[0005] To achieve the above objectives and other related objectives, the present application provides a hardware-in-the-loop test interface management method, comprising the following steps:

[0006] Acquire first interface information, wherein the first interface information includes interface information provided by a hardware device on a hardware-in-the-loop rack;

[0007] Parsing the test requirement, searching for interface information in the first interface information based on the parsed result of the test requirement, and recording the found interface information as second interface information;

[0008] According to the interface allocation strategy determined in advance or in real time, interface allocation is performed on the second interface information, and interface connection is performed on the device to be tested according to the interface allocation result.

[0009] In one embodiment of the present application, the process of performing interface connection on the device to be tested according to the interface allocation result includes:

[0010] Generate an interface connection instruction according to the interface allocation result;

[0011] Based on the interface connection instruction, the interface is connected or disconnected by connecting the shorting bar on the matrix board to perform interface connection on the device under test; and

[0012] The interface connection results are displayed through the wiring harness connection fault test box located on the hardware-in-the-loop test bench;

[0013] Wherein, the device under test is connected to the connection matrix board, and the connection matrix board is connected to the wiring harness connection fault test box.

[0014] In one embodiment of the present application, before parsing the test requirements, the method further includes:

[0015] Based on at least one fault test of the device under test, the test requirement is generated by a text description expression; or,

[0016] Based on at least one fault test of the device under test, generating the test requirement through a configuration file; or,

[0017] Based on at least one fault test of the device under test, the test requirement is interactively generated through a graphical user interface.

[0018] In one embodiment of the present application, the process of parsing the test requirements includes:

[0019] Preprocessing the test requirements, the preprocessing comprising at least one of the following: removing characters, formatting text, parsing configuration file structure, parsing graphical user interface interaction;

[0020] Extract key information from the preprocessed test requirements according to preset parsing rules or templates, the key information including: interface type, number of interfaces, and connection relationship between interfaces;

[0021] The key information is checked and verified, and the key information after the inspection and verification is output as structured data to obtain the analysis result of the test requirement.

[0022] In one embodiment of the present application, the process of determining the interface allocation strategy includes: determining the interface allocation strategy based on interface availability, polling quantity, minimum number of connections, weight distribution, interface historical usage records, and load balancing degree.

[0023] In one embodiment of the present application, after performing interface connection on the device to be tested according to the interface allocation result, the method further includes:

[0024] Record interface connection data, and dynamically adjust the interface allocation strategy based on the interface connection data; wherein the interface connection data includes: interface connection success rate, interface connection response time.

[0025] In one embodiment of the present application, after performing interface connection on the device to be tested according to the interface allocation result, the method further includes:

[0026] The interface allocation result is compared with the interface connection result, and when an interface conflict occurs, an alarm message is sent according to a preset alarm method; wherein, if the interface resource corresponding to the interface allocation result is inconsistent with the interface resource corresponding to the interface connection result, it indicates that an interface conflict occurs.

[0027] The present application also provides a hardware-in-the-loop test interface management system, the system comprising:

[0028] An interface resource manager, configured to obtain first interface information, wherein the first interface information includes interface information provided by a hardware device on a hardware-in-the-loop rack;

[0029] Parser, used to parse test requirements;

[0030] An allocation and connection module is used to search for interface information in the first interface information according to the analysis results based on the test requirements, and record the found interface information as second interface information; and, according to a pre- or real-time determined interface allocation strategy, to allocate an interface to the second interface information, and to make an interface connection to the device to be tested according to the interface allocation result.

[0031] In one embodiment of the present application, the system further includes:

[0032] A monitoring alarm module, used to compare the interface allocation result with the interface connection result, and send an alarm message according to a preset alarm method when an interface conflict occurs; wherein, if the interface resource corresponding to the interface allocation result is inconsistent with the interface resource corresponding to the interface connection result, it indicates that an interface conflict occurs;

[0033] A display module is used to display the interface connection result through the wiring harness connection fault test box located on the hardware-in-the-loop test bench.

[0034] The present application also provides a computer device, which is used to implement the steps of the hardware-in-the-loop test interface management method as described in any one of the above; or, the computer device includes a hardware-in-the-loop test interface management system as described in any one of the above.

[0035] As described above, the present application provides a hardware-in-the-loop test interface management method and system, and a computer device, which have the following beneficial effects:

[0036] The present application obtains the first interface information, then parses the test requirements input by the user, and searches for interface information in the first interface information based on the parsed results of the test requirements, and records the found interface information as the second interface information; then, according to the interface allocation strategy determined in advance or in real time, the second interface information is allocated, and the interface connection is performed on the device to be tested according to the interface allocation result. Among them, the first interface information includes the interface information provided by the hardware device on the hardware-in-the-loop test bench. It can be seen that the present application can automatically identify, allocate and connect the interface resources on the hardware-in-the-loop test bench, greatly reducing manual intervention, not only improving the test efficiency of the device to be tested in the test process, but also reducing the risks caused by human operation errors. At the same time, the present application can quickly prepare the required interface resources for the device to be tested by automating the interface allocation and connection, shortening the test preparation time. Moreover, the present application can also dynamically adjust the interface resources according to the test requirements, which not only realizes the efficient use of interface resources, but also avoids the waste and idleness of interface resources, and ensures the smooth progress of the test process. Moreover, the present application provides a graphical user interface and interactive mode, so that users can input test requirements and conveniently view and manage the usage of interface resources, making the present application well maintainable and convenient for later functional upgrades and optimizations. In addition, the present application adopts a modular design, which can easily add new interface types and support more communication protocols to adapt to the ever-changing test requirements and technological developments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A flowchart of a hardware-in-the-loop test interface management method provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of the hardware structure for allocating and connecting interfaces to a device under test provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of a wiring harness connection fault test box provided in an embodiment of the present application;

[0040] Figure 4A schematic diagram of a connection matrix board provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of the hardware structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0043] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner, and therefore the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] Figure 1 FIG. 1 is a flow chart of a method for managing a hardware-in-the-loop test interface according to an embodiment of the present application. Specifically, in an exemplary embodiment, Figure 1 As shown, this embodiment provides a hardware-in-the-loop test interface management method, the method comprising the following steps:

[0045] S110, obtaining first interface information, the first interface information including interface information provided by the hardware device on the hardware-in-the-loop rack. As an example, in this embodiment or other embodiments, the interface information provided by the hardware device on the hardware-in-the-loop rack includes but is not limited to: the type of I / O interface, the number of I / O interfaces, the status of the I / O interface, the physical location of the I / O interface, etc.

[0046] S120, parsing the test requirements, and searching for interface information in the first interface information based on the parsed results of the test requirements, and recording the found interface information as the second interface information. In this embodiment or other embodiments, the test requirements are input by the user. As an example, the user can generate the test requirements through text description expression according to at least one fault test of the device under test. Specifically, the user can express the test requirements through a simple text description, such as "3 digital I / O interfaces and 2 analog I / O interfaces are required for communication testing". As another example, the user can generate the test requirements through a configuration file according to at least one fault test of the device under test. Specifically, the user can use a special configuration file to define the test requirements, and these configuration files usually have a specific format and structure, which is convenient for the parser to parse. As another example, the user can interactively generate the test requirements through a graphical user interface according to at least one fault test of the device under test. Specifically, for more complex test requirements, a graphical user interface can also be provided, and the user can input the test requirements by interactive methods such as dragging and clicking in the graphical user interface. In this embodiment or other embodiments, the second interface information includes but is not limited to: I / O interface type, I / O interface number, and connection relationship between I / O interfaces. In addition, in this embodiment or other embodiments, when a user inputs a test requirement, the user's operation authority can be strictly controlled to ensure that only authorized users can allocate and connect interface resources.

[0047] S130, according to the interface allocation strategy determined in advance or in real time, the second interface information is allocated an interface, and the interface is connected to the device under test according to the interface allocation result. As an example, in this embodiment or other embodiments, the device under test can be selected or set according to actual conditions, for example, a battery management system (Battery Management System, referred to as BMS) can be selected as the device under test.

[0048] According to the above records, in an exemplary embodiment, the process of performing interface connection on the device under test according to the interface allocation result includes: generating an interface connection instruction according to the interface allocation result; and, based on the interface connection instruction, connecting or disconnecting the interface through the short-circuit bus on the connection matrix board to perform interface connection on the device under test; and displaying the interface connection result through a harness connection fault test box located on the hardware-in-the-loop test bench; wherein the device under test is connected to the connection matrix board, and the connection matrix board is connected to the harness connection fault test box. In this embodiment or other embodiments, different real-time changes in interface resource allocation can be displayed through the silk-screen display panel on the harness connection fault test box, which is conducive to quickly locating the interface connection channel during the test process and increasing the test efficiency. As an example, the hardware structure diagram of this embodiment when performing interface allocation and connection on the device under test can be as follows Figure 2As shown, the schematic diagram of the wiring harness connection fault test box can be as shown Figure 3 As shown, the schematic diagram of connecting the matrix board can be as follows Figure 4 As shown. Figure 2 In the figure, number 1 indicates the hardware-in-the-loop HIL test bench, number 2 indicates the wiring harness connection fault test box (Break-Out Box, referred to as BOB), number 3 indicates the connection harness, number 4 indicates the battery management system BMS as the device under test, and number 5 indicates the host computer. Figure 3 In the figure, the number 6 indicates the silk screen display panel on the wiring harness connection fault test box BOB, and the number 7 indicates the short-circuit bar on the wiring harness connection fault test box BOB. Figure 4 In the figure, the number mark 8 on the left side indicates the connection matrix board, the numbers 1-8 on the right side indicate the connection rows of the matrix board, and the numbers 1-8 on the top indicate the connection columns of the matrix board.

[0049] According to the above records, in an exemplary embodiment, the process of parsing the test requirements may include: preprocessing the test requirements, including but not limited to removing characters, formatting text, parsing the configuration file structure, parsing one or more of the graphical user interface interaction; extracting key information from the preprocessed test requirements according to preset parsing rules or templates, the key information including: interface type, number of interfaces and connection relationship between interfaces; checking and verifying the key information, and outputting the key information after the inspection and verification as structured data to obtain the parsing result of the test requirements. Specifically, this embodiment can parse the test requirements input by the user through a parser. When the parser first receives the test requirement input submitted by the user, whether it is text, configuration file or user graphical interface input, it needs to be preprocessed. Therefore, this embodiment can perform necessary preprocessing on the input test requirements according to different input formats, such as removing irrelevant characters, formatting text or parsing the configuration file structure. Then, according to preset rules and templates, extract key information from the preprocessed test requirements, these key information include identifying the I / O interface type (such as digital I / O, analog I / O, etc.), counting the number of I / O interfaces and analyzing the connection relationship between I / O interfaces. At the same time, the extracted key information will be organized into structured data formats, such as dictionaries, lists or objects. These data structures can clearly represent the type, number and connection relationship of each I / O interface with other I / O interfaces. In addition, in order to ensure the accuracy of the parsing results, the extracted key information can be error checked and verified by the parser, including checking whether the number of I / O interfaces is reasonable and whether the connection relationship is consistent. If erroneous or inconsistent interface data is found, the parser can prompt it, or the parser can automatically correct it in combination with the historical usage record of the interface.

[0050] According to the above records, in an exemplary embodiment, the process of determining the interface allocation strategy includes: determining the interface allocation strategy based on interface availability, polling number, minimum number of connections, weight distribution, interface historical usage records and load balancing degree. Specifically, in this embodiment or other embodiments, the status information of the interface resources, such as availability, current load, connection status, etc., can be collected in real time or regularly. At the same time, a database or memory storage is used to maintain the status information of the interface resources to ensure the real-time and accuracy of the interface resource status information. Then, according to the load of the interface resources, a reasonable load balancing strategy is designed. For example, load balancing can be achieved by using polling number, minimum number of connections, weight distribution, etc. At the same time, the processing capacity and current load of the interface resources can also be considered to allocate new connection requests to interface resources with lighter loads to achieve load balancing. At the same time, the historical usage records of the interface resources are collected and stored, including the start and end time of each connection, the connection duration, the interface resource utilization rate and other information. By analyzing the historical data, the peak time period, the commonly used interface resources and other patterns are identified for reference when allocating interface resources. Finally, the interface allocation strategy can be determined based on the current interface resource status, load balancing strategy and historical data prediction, taking into account factors such as interface availability, polling quantity, minimum number of connections, weight distribution, historical interface usage records and load balancing degree.

[0051] According to the above records, in an exemplary embodiment, after the interface connection is performed on the device to be tested according to the interface allocation result, the embodiment may also include: recording the interface connection data, and dynamically adjusting the interface allocation strategy based on the interface connection data; wherein the interface connection data includes: interface connection success rate, interface connection response time. Specifically, in the embodiment or other embodiments, during the use of interface resources, feedback data such as connection success rate, response time, etc. can be continuously collected, and then the interface allocation strategy can be dynamically adjusted according to the feedback data to adapt to the dynamically changing resource environment and user needs. In addition, after determining or dynamically adjusting the interface allocation strategy, the embodiment can use the connection pool technology to pre-establish and manage a certain number of interface connections to improve connection efficiency and stability. Therefore, the embodiment dynamically adjusts the interface resources according to the test requirements, which not only realizes the efficient use of interface resources, but also avoids the waste and idleness of interface resources, and ensures the smooth progress of the test process.

[0052] According to the above records, in an exemplary embodiment, after the interface connection is made to the device to be tested according to the interface allocation result, the embodiment may also include: comparing the interface allocation result with the interface connection result, and sending an alarm message according to a preset alarm method when an interface conflict occurs; wherein, if the interface resources corresponding to the interface allocation result are inconsistent with the interface resources corresponding to the interface connection result, it indicates that an interface conflict occurs. As an example, in the present embodiment or other embodiments, the preset alarm method may be set according to actual conditions, such as an alarm method such as a user graphical interface or email. The alarm message may be pre-set, and the present embodiment does not impose specific restrictions. The recipient of the alarm message may be a user who inputs the test requirements, so that the user can deal with problems such as interface conflicts in a timely manner.

[0053] According to the above records, in an exemplary embodiment, this embodiment can also collect all or part of the data during the entire test process of the device under test, and encrypt the data for storage and transmission to prevent data leakage or tampering. At the same time, the operating status of all hardware devices can also be regularly backed up and restored to ensure that normal operation can be quickly restored when a failure occurs.

[0054] In summary, the present application provides a method for managing a hardware-in-the-loop test interface, which obtains the first interface information, then parses the test requirements input by the user, and searches for interface information in the first interface information based on the parsing results of the test requirements, and records the found interface information as the second interface information; then, according to the interface allocation strategy determined in advance or in real time, the second interface information is allocated an interface, and the interface connection is performed on the device to be tested according to the interface allocation result. Wherein, the first interface information includes the interface information provided by the hardware device on the hardware-in-the-loop test bench. It can be seen that the present method can automatically identify, allocate and connect the interface resources on the hardware-in-the-loop test bench, greatly reducing manual intervention, not only improving the test efficiency of the device to be tested in the test process, but also reducing the risks caused by human operation errors. At the same time, the present method can quickly prepare the required interface resources for the device to be tested by automating the interface allocation and connection, shortening the test preparation time. Moreover, the present method can also dynamically adjust the interface resources according to the test requirements, which not only realizes the efficient use of interface resources, but also avoids the waste and idleness of interface resources, and ensures the smooth progress of the test process. Moreover, by providing a graphical user interface and interactive mode, the method allows users to input test requirements and conveniently view and manage the usage of interface resources, making the method well maintainable and convenient for later functional upgrades and optimizations. In addition, the method adopts a modular design, which can easily add new interface types and support more communication protocols to adapt to the ever-changing test requirements and technological developments.

[0055] In another exemplary embodiment of the present application, the embodiment further provides a hardware-in-the-loop test interface management system, comprising:

[0056] The interface resource manager is used to obtain first interface information, wherein the first interface information includes interface information provided by the hardware device on the hardware-in-the-loop rack. As an example, in this embodiment or other embodiments, the interface information provided by the hardware device on the hardware-in-the-loop rack includes but is not limited to: the type of I / O interface, the number of I / O interfaces, the status of the I / O interface, the physical location of the I / O interface, etc.

[0057] A parser is used to parse the test requirements. In this embodiment or other embodiments, the test requirements are input by the user. As an example, the user can generate the test requirements through text description expression according to at least one fault test of the device under test. Specifically, the user can express the test requirements through a simple text description, such as "3 digital I / O interfaces and 2 analog I / O interfaces are required for communication testing". As another example, the user can generate the test requirements through a configuration file according to at least one fault test of the device under test. Specifically, the user can use a special configuration file to define the test requirements, and these configuration files usually have a specific format and structure, which is convenient for the parser to parse. As another example, the user can interactively generate the test requirements through a graphical user interface according to at least one fault test of the device under test. Specifically, for more complex test requirements, a graphical user interface can also be provided, and the user can input the test requirements through interactive methods such as dragging, clicking, etc. in the graphical user interface. In addition, in this embodiment or other embodiments, when the user enters the test requirements, the user's operation authority can be strictly controlled to ensure that only authorized users can allocate and connect interface resources.

[0058] An allocation and connection module is used to search for interface information in the first interface information according to the analysis results based on the test requirements, and record the found interface information as the second interface information; and, according to the interface allocation strategy determined in advance or in real time, allocate interfaces to the second interface information, and make interface connections to the device under test according to the interface allocation results. In this embodiment or other embodiments, the process of making interface connections to the device under test according to the interface allocation results includes: generating an interface connection instruction according to the interface allocation results; and, based on the interface connection instructions, connecting or disconnecting the interface by connecting the short-circuit bus on the matrix board to make interface connections to the device under test. In this embodiment or other embodiments, the second interface information includes but is not limited to: I / O interface type, I / O interface number, and connection relationship between I / O interfaces. In addition, in this embodiment or other embodiments, the device under test can be selected or set according to actual conditions. For example, a battery management system BMS can be selected as the device under test. As an example, the hardware structure diagram of this embodiment when allocating and connecting interfaces to the device under test can be as follows Figure 2 As shown, the schematic diagram of the wiring harness connection fault test box can be as shown Figure 3 As shown, the schematic diagram of connecting the matrix board can be as follows Figure 4 As shown. Figure 2 In the figure, number 1 indicates the hardware-in-the-loop HIL test bench, number 2 indicates the wiring harness connection fault test box BOB, number 3 indicates the connection wiring harness, number 4 indicates the battery management system BMS as the device under test, and number 5 indicates the host computer. Figure 3 In the figure, the number 6 indicates the silk screen display panel on the wiring harness connection fault test box BOB, and the number 7 indicates the short-circuit bar on the wiring harness connection fault test box BOB. Figure 4 In the figure, the number mark 8 on the left side indicates the connection matrix board, the numbers 1-8 on the right side indicate the connection rows of the matrix board, and the numbers 1-8 on the top indicate the connection columns of the matrix board.

[0059] According to the above records, in an exemplary embodiment, the hardware-in-the-loop test interface management system may also include:

[0060] The monitoring alarm module is used to compare the interface allocation result with the interface connection result, and when an interface conflict occurs, an alarm message is sent according to a preset alarm method; wherein, if the interface resources corresponding to the interface allocation result are inconsistent with the interface resources corresponding to the interface connection result, it indicates that an interface conflict occurs. As an example, in this embodiment or other embodiments, the preset alarm method can be set according to actual conditions, such as a user graphical interface or email alarm method. Among them, the alarm information can be pre-set, and this embodiment does not make specific restrictions. The recipient of the alarm information can be the user who inputs the test requirements, so that the user can deal with interface conflicts and other problems in a timely manner.

[0061] The display module is used to display the interface connection result through the wiring harness connection fault test box located on the hardware-in-the-loop test bench. Specifically, the present embodiment can display different real-time changes of interface resource allocation through the silk-screen display panel on the wiring harness connection fault test box, which is conducive to quickly locating the interface connection channel during the test process and increasing the test efficiency.

[0062] According to the above records, in an exemplary embodiment, the process of parsing the test requirements by the parser may include: preprocessing the test requirements, including but not limited to removing characters, formatting text, parsing the configuration file structure, parsing one or more of the graphical user interface interactions; extracting key information from the preprocessed test requirements according to preset parsing rules or templates, the key information including: interface type, number of interfaces and connection relationship between interfaces; checking and verifying the key information, and outputting the key information after the inspection and verification as structured data to obtain the parsing result of the test requirements. Specifically, the present embodiment can parse the test requirements input by the user through the parser. When the parser first receives the test requirement input submitted by the user, whether it is text, configuration file or user graphical interface input, it needs to be preprocessed. Therefore, the present embodiment can perform necessary preprocessing on the input test requirements according to different input formats, such as removing irrelevant characters, formatting text or parsing the configuration file structure. Then, according to the preset rules and templates, extract key information from the preprocessed test requirements, which includes identifying the I / O interface type (such as digital I / O, analog I / O, etc.), counting the number of I / O interfaces and analyzing the connection relationship between I / O interfaces. At the same time, the extracted key information will be organized into structured data formats, such as dictionaries, lists or objects. These data structures can clearly represent the type, number and connection relationship of each I / O interface with other I / O interfaces. In addition, in order to ensure the accuracy of the parsing results, the extracted key information can be error checked and verified by the parser, including checking whether the number of I / O interfaces is reasonable and whether the connection relationship is consistent. If erroneous or inconsistent interface data is found, the parser can prompt it, or the parser can automatically correct it in combination with the historical usage record of the interface.

[0063] According to the above records, in an exemplary embodiment, the process of determining the interface allocation strategy includes: determining the interface allocation strategy based on interface availability, polling number, minimum number of connections, weight distribution, interface historical usage records and load balancing degree. Specifically, in this embodiment or other embodiments, the status information of the interface resources, such as availability, current load, connection status, etc., can be collected in real time or regularly. At the same time, a database or memory storage is used to maintain the status information of the interface resources to ensure the real-time and accuracy of the interface resource status information. Then, according to the load of the interface resources, a reasonable load balancing strategy is designed. For example, load balancing can be achieved by using polling number, minimum number of connections, weight distribution, etc. At the same time, the processing capacity and current load of the interface resources can also be considered to allocate new connection requests to interface resources with lighter loads to achieve load balancing. At the same time, the historical usage records of the interface resources are collected and stored, including the start and end time of each connection, the connection duration, the interface resource utilization rate and other information. By analyzing the historical data, the peak time period, the commonly used interface resources and other patterns are identified for reference when allocating interface resources. Finally, the interface allocation strategy can be determined based on the current interface resource status, load balancing strategy and historical data prediction, taking into account factors such as interface availability, polling quantity, minimum number of connections, weight distribution, historical interface usage records and load balancing degree.

[0064] According to the above records, in an exemplary embodiment, after the allocation connection module performs interface connection on the device to be tested according to the interface allocation result, it can also include: recording interface connection data, and dynamically adjusting the interface allocation strategy based on the interface connection data; wherein the interface connection data includes: interface connection success rate, interface connection response time. Specifically, in this embodiment or other embodiments, during the use of interface resources, feedback data such as connection success rate, response time, etc. can be continuously collected, and then the interface allocation strategy can be dynamically adjusted according to the feedback data to adapt to the dynamically changing resource environment and user needs. In addition, after determining or dynamically adjusting the interface allocation strategy, this embodiment can use the connection pool technology to pre-establish and manage a certain number of interface connections to improve connection efficiency and stability. Therefore, this embodiment dynamically adjusts the interface resources according to the test requirements, which not only realizes the efficient use of interface resources, but also avoids the waste and idleness of interface resources, and ensures the smooth progress of the test process.

[0065] According to the above records, in an exemplary embodiment, the hardware-in-the-loop test interface management system of this embodiment may also include: an encrypted storage module and a backup module. The encrypted storage module is used to collect all or part of the data of the entire test process of the device under test, and encrypt the data for storage and transmission to prevent data leakage or tampering; the backup module can regularly back up and restore the operating status of all hardware devices to ensure that normal operation can be quickly restored when a failure occurs.

[0066] In summary, the present application provides a hardware-in-the-loop test interface management system, which obtains the first interface information, then parses the test requirements input by the user, and searches for interface information in the first interface information based on the parsing results of the test requirements, and records the found interface information as the second interface information; then, according to the interface allocation strategy determined in advance or in real time, the second interface information is allocated, and the interface connection is performed on the device to be tested according to the interface allocation result. Among them, the first interface information includes the interface information provided by the hardware device on the hardware-in-the-loop bench. It can be seen that the system can automatically identify, allocate and connect the interface resources on the hardware-in-the-loop bench, greatly reducing manual intervention, not only improving the test efficiency of the device to be tested in the test process, but also reducing the risks caused by human operation errors. At the same time, the system can quickly prepare the required interface resources for the device to be tested by automating the interface allocation and connection, shortening the test preparation time. Moreover, the system can also dynamically adjust the interface resources according to the test requirements, which not only realizes the efficient use of interface resources, but also avoids the waste and idleness of interface resources, ensuring the smooth progress of the test process. Moreover, this system provides a graphical user interface and interactive mode, allowing users to input test requirements and conveniently view and manage the use of interface resources, making the system well maintainable and convenient for later functional upgrades and optimizations. In addition, this system adopts a modular design, which can easily add new interface types and support more communication protocols to adapt to the ever-changing test requirements and technological developments.

[0067] It should be noted that the hardware-in-the-loop test interface management system provided in the above embodiment and the hardware-in-the-loop test interface management method provided in the above embodiment belong to the same concept, wherein the specific manner in which the hardware-in-the-loop test interface management method performs operations has been described in detail in the above method embodiment, and will not be repeated here. In actual applications, the hardware-in-the-loop test interface management system provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the hardware-in-the-loop test interface management system into different functional modules, and then implement all or part of the functions of the corresponding functional modules through the hardware-in-the-loop test interface management method described in the above embodiment, and no specific restrictions are made here.

[0068] In another exemplary embodiment of the present application, the embodiment further provides a computer device, which includes an interface resource manager, a parser, a distribution connection module, a monitoring alarm module, a wiring harness connection fault test box BOB silk screen display module and a user graphical interface module. As an example, the computer device in this embodiment can be a host computer.

[0069] Specifically, the interface resource manager can collect and manage all available I / O interface resource information on the HIL bench. This interface resource information includes the type, quantity, status (whether idle), physical location, etc. of the I / O interface. The interface resource manager obtains and updates this information by communicating with the hardware devices on the bench in real time to ensure the accuracy and real-time performance of the interface resources.

[0070] Specifically, the parser can parse the test requirements submitted by the user and extract key information such as the I / O interface type, quantity, and connection relationship. This key information is crucial for subsequent I / O interface allocation and connection operations to ensure that the test process can proceed smoothly. The parser can execute the following test requirement process, parsing process, and test requirement output process.

[0071] Among them, the test requirement process includes: the parser supports multiple formats of requirement input to meet the usage habits and scenario requirements of different users. The following are several common input formats: Text description: Users can express test requirements through simple text descriptions, such as "3 digital I / O interfaces and 2 analog I / O interfaces are required for communication testing." Configuration file: Users can use special configuration files to define test requirements. These configuration files usually have specific formats and structures to facilitate parsing by the parser. User graphical interface input: For more complex test requirements, the parser can also provide a user graphical interface, allowing users to enter test requirements through interactive methods such as dragging and clicking.

[0072] The parsing process includes: Input reception, the parser first receives the test requirement input submitted by the user, whether it is text, configuration file or user graphical interface input. Preprocessing: Depending on the input format, the parser will perform necessary preprocessing on the input, such as removing irrelevant characters, formatting text or parsing the configuration file structure. Information extraction: The parser will extract key information from the preprocessed input according to preset rules and templates. This includes identifying the type of I / O interface (such as digital I / O, analog I / O, etc.), counting the number of I / O interfaces, and analyzing the connection relationship between I / O interfaces. Structured data generation: The extracted key information will be organized into a structured data format, such as a dictionary, list or object. These data structures can clearly represent the type, number and connection relationship of each I / O interface with other I / O interfaces. Error checking and verification: To ensure the accuracy of the parsing results, the parser will perform error checking and verification on the extracted key information. This includes checking whether the number of I / O interfaces is reasonable and whether the connection relationship is consistent. If incorrect or inconsistent data is found, the parser will prompt or automatically correct it.

[0073] The test requirement output process includes: the parser outputs the extracted key information in the form of structured data for subsequent I / O interface allocation and connection operations. These output data can be directly used for test environment configuration and test script generation, thereby simplifying the test process and improving test efficiency.

[0074] Specifically, the distribution connection module is mainly composed of the wiring harness connection fault test box BOB and the connection matrix board. The distribution connection module works closely with the parser and the interface resource manager to ensure the effective allocation and accurate connection of interface resources. Specifically, receiving the parsed requirements: the distribution connection module first receives the key information provided by the parser, including the required I / O interface type, quantity and connection relationship. Interface resource search and allocation: the distribution connection module searches for qualified I / O interface resources from the interface resource manager based on the received information. During the allocation process, the distribution connection module will comprehensively consider various factors, such as the availability of interface resources, load balancing and historical usage records, to optimize the interface resource allocation effect. If there are multiple qualified I / O interface resources, the distribution connection module will select based on certain strategies (such as polling, priority, etc.). Generate connection instructions: Once the I / O interface resource allocation is completed, the distribution connection module will automatically generate corresponding connection instructions. These instructions describe in detail how to connect the allocated I / O interface to the test equipment or system. Execute connection operations: the distribution connection module communicates with the connection matrix board on the test bench through a hardware interface or communication protocol. According to the generated connection instructions, the connection allocation module controls the connection matrix board to perform actual connection operations, such as connecting or disconnecting specific I / O interface connections. Interface resource allocation and automated connection strategy: (1) Interface resource monitoring and status management: Establish an interface resource monitoring system to collect interface resource status information in real time or regularly, such as availability, current load, connection status, etc. Use database or memory storage to maintain interface resource status information to ensure the real-time and accuracy of interface resource status information. (2) Load balancing strategy: Design a reasonable load balancing strategy based on the load of interface resources. For example, algorithms based on polling, minimum number of connections, weight allocation, etc. can be used to achieve load balancing. Considering the processing capacity and current load of interface resources, new connection requests are allocated to interface resources with lighter loads to achieve load balancing. (3) Historical usage record analysis: Collect and store historical usage records of interface resources, including the start and end time of each connection, connection duration, interface resource utilization, etc. Analyze historical data to identify patterns such as peak hours and commonly used interface resources for reference when allocating interface resources. (4) Automated allocation algorithm: Design an automated allocation algorithm that takes into account factors such as the availability of interface resources, load balancing, and historical usage records. The algorithm can select the most appropriate interface resource for a new connection request based on the current interface resource status, load balancing strategy, and historical data predictions. (5) Connection management and scheduling: Implement a connection management and scheduling mechanism to automatically establish and maintain connections based on the results of the allocation algorithm. Use connection pool technology to pre-establish and manage a certain number of connections to improve connection efficiency and stability. (6) Feedback and adjustment: During the use of interface resources, continuously collect feedback data, such as connection success rate, response time, etc.Adjust the allocation algorithm and load balancing strategy based on feedback data to adapt to the dynamically changing interface resource environment and user needs.

[0075] Specifically, the monitoring and alarm module can monitor the allocated I / O interface resources in real time, detect the status changes of interface resources, data transmission conditions, etc. Once an abnormal situation is found, such as interface resource conflict, data transmission error, etc., the monitoring and alarm module will immediately trigger the alarm mechanism and notify the user through the user graphical interface or email, so that the problem can be handled in time.

[0076] Specifically, the wire harness connection fault test box BOB silk screen display module can display specific channel information after the allocation connection module allocates I / O interface resources. The silk screen display panel on the wire harness connection fault test box BOB can change in real time with the different allocation of interface resources, which is conducive to quickly locating the channel during the test and increasing the test efficiency.

[0077] Specifically, the user graphical interface module can provide a user graphical interface to facilitate users to view and manage the usage of I / O interface resources. Users can view the real-time status, historical records, test reports and other information of interface resources through the user graphical interface. At the same time, users can also submit test requirements, configure system parameters, monitor alarm information, etc. through the user graphical interface. The user graphical interface design in this embodiment is concise and clear, easy to operate and understand.

[0078] In another exemplary embodiment of the present application, the embodiment further provides a computer device, which may include a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program so that the computer device executes Figure 1 The steps of the hardware-in-the-loop test management method. Figure 5 FIG. 1 is a schematic diagram showing a structure of a computer device 1000. Figure 5 As shown, the computer device 1000 includes: a processor 1010 , a memory 1020 , a power supply 1030 , a display unit 1040 , and an input unit 1060 .

[0079] The processor 1010 is the control center of the computer device 1000. It uses various interfaces and lines to connect various components, and executes various functions of the computer device 1000 by running or executing computer programs / instructions stored in the memory 1020, thereby monitoring the computer device 1000 as a whole. In the embodiment of the present application, when the processor 1010 calls the computer program stored in the memory 1020, the following is executed: Figure 1The steps of the hardware-in-the-loop test management method. Optionally, the processor 1010 may include one or more processing units; preferably, the processor 1010 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application, etc., and the modem processor mainly processes wireless communication. In some embodiments, the processor and memory may be implemented on a single chip, and in some embodiments, they may also be implemented separately on separate chips.

[0080] The memory 1020 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, various applications, etc.; the data storage area may store instruction data, etc. created according to the use of the computer device 1000. In addition, the memory 1020 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices, etc.

[0081] The computer device 1000 also includes a power source 1030 (such as a battery) for supplying power to various components. The power source can be logically connected to the processor 1010 through a power management system, so that the power management system can manage functions such as charging, discharging, and power consumption.

[0082] The display unit 1040 may be used to display information input by the user or information provided to the user and various menus of the computer device 1000, and in the embodiment of the present application, is mainly used to display the display interface of each application in the computer device 1000 and objects such as text and pictures displayed in the display interface. The display unit 1040 may include a display panel 1050. The display panel 1050 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0083] The input unit 1060 may be used to receive information such as numbers or characters input by the user. The input unit 1060 may include a touch panel 1070 and other input devices 1080. The touch panel 1070, also known as a touch screen, may collect touch operations of the user on or near it (such as operations of the user using a finger, a stylus, or any other suitable object or accessory on or near the touch panel 1070).

[0084] Specifically, the touch panel 1070 can detect the user's touch operation, detect the signal brought by the touch operation, convert these signals into touch point coordinates, send them to the processor 1010, and receive and execute the command sent by the processor 1010. In addition, the touch panel 1070 can be implemented in various types such as resistive, capacitive, infrared and surface acoustic wave. Other input devices 1080 can include but are not limited to one or more of a physical keyboard, function keys (such as volume control keys, power on / off keys, etc.), a trackball, a mouse, a joystick, etc.

[0085] Of course, the touch panel 1070 can cover the display panel 1050. When the touch panel 1070 detects a touch operation on or near it, it is transmitted to the processor 1010 to determine the type of touch event, and then the processor 1010 provides a corresponding visual output on the display panel 1050 according to the type of touch event. Figure 5 In the embodiment, the touch panel 1070 and the display panel 1050 are two independent components to implement the input and output functions of the computer device 1000, but in some embodiments, the touch panel 1070 and the display panel 1050 can be integrated to implement the input and output functions of the computer device 1000.

[0086] The computer device 1000 may further include one or more sensors, such as a pressure sensor, a gravity acceleration sensor, a proximity light sensor, etc. Of course, according to the needs of specific applications, the computer device 1000 may also include other components such as a camera.

[0087] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the above-mentioned device can perform the above-mentioned Figure 1 The steps of the hardware-in-the-loop test management method.

[0088] It can be understood by those skilled in the art that Figure 5 This is only an example of a computer device and does not constitute a limitation on the device. The device may include more or fewer components than shown in the figure, or combine certain components, or different components. For the convenience of description, the above parts are divided into modules (or units) according to their functions and described separately. Of course, when implementing this application, the functions of each module (or unit) can be implemented in the same or multiple software or hardware.

[0089] Those skilled in the art should understand that the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be applied to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0090] It should be understood that, although the terms first, second, etc. may be used to describe interface information, etc. in the embodiments of the present application, these terms are only used to distinguish interface information from each other. For example, without departing from the scope of the embodiments of the present application, the first interface information may also be referred to as the second interface information, and similarly, the second interface information may also be referred to as the first interface information.

[0091] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A method for managing a hardware-in-the-loop test interface, characterized in that: The method comprises the following steps: Acquire first interface information, wherein the first interface information includes interface information provided by a hardware device on a hardware-in-the-loop rack; Parsing the test requirement, searching for interface information in the first interface information based on the parsed result of the test requirement, and recording the found interface information as second interface information; According to the interface allocation strategy determined in advance or in real time, interface allocation is performed on the second interface information, and interface connection is performed on the device to be tested according to the interface allocation result.

2. The hardware-in-the-loop test interface management method according to claim 1, characterized in that: The process of connecting the interface of the device to be tested according to the interface allocation result includes: Generate an interface connection instruction according to the interface allocation result; Based on the interface connection instruction, the interface is connected or disconnected by connecting the shorting bar on the matrix board to perform interface connection on the device under test; and The interface connection results are displayed through the wiring harness connection fault test box located on the hardware-in-the-loop test bench; Wherein, the device under test is connected to the connection matrix board, and the connection matrix board is connected to the wiring harness connection fault test box.

3. The hardware-in-the-loop test interface management method according to claim 1, characterized in that: Before parsing the test requirements, the method further includes: Based on at least one fault test of the device under test, the test requirement is generated by a text description expression; or, Based on at least one fault test of the device under test, generating the test requirement through a configuration file; or, Based on at least one fault test of the device under test, the test requirement is interactively generated through a graphical user interface.

4. The hardware-in-the-loop test interface management method according to claim 1 or 3, characterized in that: The process of parsing test requirements includes: Preprocessing the test requirements, the preprocessing comprising at least one of the following: removing characters, formatting text, parsing configuration file structure, parsing graphical user interface interaction; Extract key information from the preprocessed test requirements according to preset parsing rules or templates, the key information including: interface type, number of interfaces, and connection relationship between interfaces; The key information is checked and verified, and the key information after the inspection and verification is output as structured data to obtain the analysis result of the test requirement.

5. The hardware-in-the-loop test interface management method according to claim 1 or 2, characterized in that: The process of determining the interface allocation strategy includes: determining the interface allocation strategy based on interface availability, polling quantity, minimum connection quantity, weight distribution, interface historical usage record and load balancing degree.

6. The hardware-in-the-loop test interface management method according to claim 5, characterized in that: After performing interface connection on the device to be tested according to the interface allocation result, the method further includes: Record interface connection data, and dynamically adjust the interface allocation strategy based on the interface connection data; wherein the interface connection data includes: interface connection success rate, interface connection response time.

7. The hardware-in-the-loop test interface management method according to claim 1, characterized in that: After the interface connection is performed on the device to be tested according to the interface allocation result, the method further includes: The interface allocation result is compared with the interface connection result, and when an interface conflict occurs, an alarm message is sent according to a preset alarm method; wherein, if the interface resource corresponding to the interface allocation result is inconsistent with the interface resource corresponding to the interface connection result, it indicates that an interface conflict occurs.

8. A hardware-in-the-loop test interface management system, characterized in that: The system comprises: An interface resource manager, configured to obtain first interface information, wherein the first interface information includes interface information provided by a hardware device on a hardware-in-the-loop rack; Parser, used to parse test requirements; an allocation connection module, configured to search for interface information in the first interface information according to a parsing result based on the test requirement, and record the found interface information as second interface information; And, according to the interface allocation strategy determined in advance or in real time, interface allocation is performed on the second interface information, and interface connection is performed on the device to be tested according to the interface allocation result.

9. The hardware-in-the-loop test interface management system according to claim 8, characterized in that: The system also includes: A monitoring alarm module, used to compare the interface allocation result with the interface connection result, and send an alarm message according to a preset alarm method when an interface conflict occurs; wherein, if the interface resource corresponding to the interface allocation result is inconsistent with the interface resource corresponding to the interface connection result, it indicates that an interface conflict occurs; A display module is used to display the interface connection result through the wiring harness connection fault test box located on the hardware-in-the-loop test bench.

10. A computer device, characterized in that: The computer device is used to implement the steps of the hardware-in-the-loop test interface management method as described in any one of claims 1 to 7; or, the computer device includes the hardware-in-the-loop test interface management system as described in claim 8 or 9.

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