A solid-state drive storage module

Abstract

A solid state disk storage module contains two or more storage particles, comprising: a storage controller integrating a first storage control die chip and a second storage control die chip; the first and second storage control die chips contain corresponding die interconnection controllers, and the die interconnection controllers of the first and second storage control die chips establish communication between the chips for data exchange between the chips, and then data read and write of the two or more storage particles; wherein the data exchange between the chips includes: the die interconnection controller of the first storage control die chip forwards data to the second storage control die chip; or the die interconnection controller of the second storage control die chip forwards data to the first storage control die chip. The embodiments of the present disclosure improve the performance of the storage controller by integrating the first storage control die chip and the second storage control die chip in the storage controller to establish a communication connection, and meet the application requirements of multiple read and write channels.

Description

Technical Field

[0001] This article relates to storage chip technology, particularly a solid-state drive (SSD) storage module. Background Technology

[0002] In the design of storage modules, including solid-state drives, to meet storage capacity requirements, multiple storage chips are often integrated into the same storage module. A single storage controller chip is used to control the large-capacity multi-read and write channels of the storage module. However, as the number of storage chips increases, the performance of the storage controller chip will be unable to meet the performance requirements of the multiple read and write channels, affecting the working performance of the storage module. How to improve the working performance of the storage module has become a technical problem that needs to be solved. Summary of the Invention

[0003] This application provides a solid-state drive storage module comprising two or more storage chips, including: a storage controller integrating a first storage control die chip and a second storage control die chip, wherein the storage chips and the storage controller are integrated on the same circuit board; the first storage control die chip and the second storage control die chip each include a corresponding die interconnect controller, and the die interconnect controllers of the first storage control die chip and the second storage control die chip establish inter-chip communication for data exchange between the chips, thereby enabling data read and write operations on the two or more storage chips;

[0004] The data exchange between the chips includes: the die interconnect controller of the first memory control die chip forwarding data to the second memory control die chip; or, the die interconnect controller of the second memory control die chip forwarding data to the first memory control die chip.

[0005] The embodiments disclosed herein improve the performance of the storage controller and meet the application requirements of multiple read / write channels by integrating a first storage controller die chip and a second storage controller die chip that establish a communication connection in the storage controller.

[0006] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0008] Figure 1 This is a structural block diagram of a solid-state drive storage module according to an embodiment of the present disclosure;

[0009] Figure 2 This is a schematic diagram of the physical connection of the storage controller according to an embodiment of this disclosure;

[0010] Figure 3 This is a schematic diagram of a bare die chip according to an embodiment of this disclosure;

[0011] Figure 4 This is a schematic diagram of a storage controller according to an embodiment of the present disclosure;

[0012] Figure 5 This is a schematic diagram of the communication process of the storage controller according to an embodiment of the present disclosure. Detailed Implementation

[0013] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0014] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0015] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0016] Figure 1 This is a structural block diagram of a solid-state drive storage module according to an embodiment of the present disclosure, as shown below. Figure 1 As shown, a solid-state drive (SSD) storage module (also known as an SSD module) contains two or more storage chips; a storage controller integrates a first storage control die chip and a second storage control die chip. The storage chips and the storage controller are integrated on the same circuit board. The first storage control die chip and the second storage control die chip each contain a corresponding die interconnect controller. The die interconnect controllers of the first storage control die chip and the second storage control die chip establish communication between the chips for data exchange, thereby enabling data read and write operations on the two or more storage chips.

[0017] This embodiment integrates a first storage control die chip and a second storage control die chip in a storage controller. A communication connection is established between the integrated first and second storage control die chips based on a die interconnect controller, thereby expanding the storage controller, improving its performance, and meeting the application requirements of multiple read / write channels.

[0018] In one exemplary instance, the die interconnect controller of the first memory control die chip and the die interconnect controller of the second memory control die chip are physically connected. Figure 2 This is a schematic diagram of the physical connection of the storage controller according to an embodiment of this disclosure, as shown below. Figure 2 As shown, the die interconnect controller of the first memory control die chip and the die interconnect controller of the second memory control die chip can be connected by a metal wire.

[0019] Figure 3 This is a schematic diagram of a bare die chip according to an embodiment of the present disclosure. It can be a first memory control bare die chip or a second memory control bare die chip, such as... Figure 3As shown, in addition to the die interconnect controller, both the first and second memory control die chips also include the following components: a host interface module, a data processing module, a cache module, and a FLASH management interface module; wherein,

[0020] The host interface is configured to: receive command messages from external modules accessing the storage controller, send the received command messages to the data processing module, and respond to external modules based on the data caching completion status of the caching module or the response status of the data processing module to the command messages;

[0021] The data processing module is configured to process data written by the host and / or data from the FLASH management interface module according to command messages, and send the processed data to the cache module.

[0022] The caching module is configured to cache received data and manage the queue pointers for the data cache.

[0023] The FLASH management interface module is configured to send read data from storage particles to the cache module or write data from the cache module to the storage particles.

[0024] In one exemplary embodiment, under the control of the die interconnect controller, data input from the host is processed by the data processing module and then sent to the cache module for caching; alternatively, data from the storage chip in the Flash management interface is processed by the data processing module and then sent to the cache module for caching. In this embodiment, the die interconnect controller of the first storage control die chip can forward data from its own cache module to the second storage control die chip, or the die interconnect controller of the second storage control die chip can forward data from its own cache module to the first storage control die chip.

[0025] See Figure 3 In the architecture shown, the die interconnect controller in this embodiment is located in the data flow path and performs data read or write processing in the first storage control die chip or the second storage control die chip.

[0026] The data flow branch point of either the first or second storage control die chip is located between the data processing module and the cache module.

[0027] In one exemplary instance, the data processing module of this disclosure embodiment is configured to: determine the data flow direction according to the command message; process the data written by the host and / or the data from the FLASH management interface module according to the determined data flow direction, and send the processed data to the cache module.

[0028] In one exemplary instance, the command message of this disclosure includes a Logical Cluster Address (LCA), which contains flow direction field information for identifying whether the data is handed over to a first storage control die chip or a second storage control die chip for processing. For example, LCA[0] == 1'b0 indicates that the data processing module's data stream is handed over to the first storage control die chip for processing, and LCA[0] == 1'b1 indicates that the data processing module's data stream is handed over to the second storage control die chip for processing.

[0029] In one exemplary instance, the data flow between the data processing module and the caching module in this disclosure embodiment is processed in the following manner:

[0030] Command messages, queue pointers, and DMA data;

[0031] The command message contains a Logical Cluster Address (LCA), which includes a flow direction field to identify whether the data is to be processed by the first or second storage control die chip. The queue pointer is issued by the cache module and is used as a parameter for command message processing. The queue pointer is synchronized to the first and second storage control dies. The flow direction field determines whether the first or second storage control die chip will perform data transmission and reception. DMA data is used to determine the data switching direction based on the flow direction field information.

[0032] Figure 4 This is a schematic diagram of a storage controller according to an embodiment of the present disclosure, as shown below. Figure 4 As shown, both the first and second storage control die chips include a die interconnect controller. The data streams of both the first and second storage control die chips are processed by the die interconnect controller before entering the cache module. The data streams in this embodiment include host write data and host read data. The host read data includes data reading and pre-reading.

[0033] In the embodiments of this disclosure, all command messages involved in host data writing have LCA, and all data streams can be decoupled based on LCA.

[0034] The embodiments of this disclosure involve reading command messages and queue pointers, wherein the command messages carry LCA and can be de-processed according to the LCA; the queue pointer carries a direction indicator after being transmitted through the die interconnect controller.

[0035] In this embodiment of the disclosure, the data stream processing between the first and second memory control die chips requires a die interconnect controller for command communication and state synchronization between them. This necessitates a communication mechanism including interrupts and buffering. This embodiment of the disclosure adds the following interrupts to the die interconnect controller:

[0036] Communication message reception interruption (Mailbox RX Intr, including message reception interruption other than management messages such as read and write messages), management message reception interruption (Mailbox ADM RX Intr), communication message transmission completion interruption (Mailbox TX_Done Intr), and management message transmission completion interruption (Mailbox ADM TX_Done Intr).

[0037] In one exemplary embodiment, the interrupt signal described above in this disclosure can be generated by a signal with varying levels, referring to related technologies. For example, Mailbox RX intr can be generated by an upward transition of the Flag signal, and Mailbox TX_Done Intr can be generated by a downward transition of the Flag signal. The die interconnect controller obtains Mailbox RX intr from the peer's flag register. The first storage control die chip notifies the second storage control die chip to receive data by setting its own flag register, and the second storage control die chip notifies the first storage control die chip that data transmission is complete by resetting the first storage control die chip's flag register. The actual data to be transmitted is written to the receiver's buffer by either the first or second storage control die chip through the die interconnect controller. In this disclosure, the first and second storage control die chips can be equipped with transmit / receive flags, transmit / receive parameters, a buffer base address, and a buffer size register for communication and data exchange.

[0038] Figure 5 This is a schematic diagram of the communication process of the storage controller according to an embodiment of this disclosure, as follows: Figure 5 As shown, the first memory control die chip first puts the data to be sent into the buffer, then sets the flag, and then receives an interrupt. The second memory control die chip retrieves the data to be sent from the buffer and sends it. Conversely, the second memory control die chip puts the data to be sent into the buffer, sets the flag, and then receives an interrupt. The first memory control die chip retrieves the data to be sent from the buffer and sends it.

[0039] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A solid state drive storage module comprising two or more storage grains, characterized in that, The application relates to a storage controller comprising: a storage controller integrating a first storage control die chip and a second storage control die chip, and storage grains integrated on the same circuit board as the storage controller; the first storage control die chip and the second storage control die chip each comprise a corresponding die interconnection controller, the die interconnection controller of the first storage control die chip and the die interconnection controller of the second storage control die chip establish communication between the chips for data exchange between the chips and data read and write of two or more storage grains; wherein the data exchange between the chips comprises: the die interconnection controller of the first storage control die chip forwards data to the second storage control die chip; or the die interconnection controller of the second storage control die chip forwards data to the first storage control die chip; and the die interconnection controller of the first storage control die chip and the die interconnection controller of the second storage control die chip are connected in a physical mode.

2. The solid state hard drive storage module of claim 1, wherein, The first storage control die chip and the second storage control die chip each further comprise the following components: a host interface module, a data processing module, a cache module and a FLASH management interface module; wherein, the host interface is arranged to receive a command message of an access to the storage controller by an external module, send the received command message to the data processing module, and reply to the external module according to data caching completion of the cache module or a reply of the data processing module to the command message; the data processing module is arranged to process data written by the host according to the command message and / or data from the FLASH management interface module, and send the processed data to the cache module; the cache module is arranged to cache the received data and manage a queue pointer of data caching; the FLASH management interface module is arranged to send read data from the storage grains to the cache module or write data in the cache module to the storage grains.

3. The solid state hard drive storage module of claim 2, wherein, The data processing module is arranged to: determine a data flow direction according to the command message, process data written by the host and / or data from the FLASH management interface module according to the determined data flow direction, and send the processed data to the cache module.

4. The solid state hard drive storage module of claim 3, wherein, The command message comprises a logical cluster address (LCA), and the LCA comprises flow direction field information for identifying that data is handed over to the first storage control die chip or the second storage control die chip for processing.

5. The solid state hard disk storage module of any of claims 2 to 4, wherein, Data flow between the data processing module and the cache module is processed in the following form: a command message, a queue pointer and DMA data. The command message contains a logical cluster address (LCA), and the LCA contains flow direction field information for identifying data to be handed over to the first storage control die chip or the second storage control die chip for processing. The queue pointer is issued by the cache module and is a parameter for processing the command message. The queue pointer is synchronized to the first storage control die chip and the second storage control die chip. According to the flow direction field information, data transmission is performed by the first storage control die chip or the second storage control die chip. The DMA data is used to switch the data direction according to the flow direction field information.

6. The solid state hard disk storage module of any of claims 1 to 4, wherein, The following interrupts are added to the die interconnection controller: A communication message received interrupt, a management message received interrupt, a communication message sent interrupt, and a management message sent interrupt.

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