Remote Direct Memory Access Verification Systems, Devices, and Clusters

Abstract

The present application provides a remote direct memory access verification system, device and cluster. The system includes: a first host including a remote direct memory access space; a first remote direct memory access device including one or more memory access entries, the memory access entry including an address space, access rights and entry status; the access rights indicate the type of access allowed, and the entry status indicates whether the remote direct memory access space is open for use; receiving a remote direct memory access request, the remote direct memory access request includes a first entry index, a first access type and a first access address; determining a first memory access entry corresponding to the first entry index according to the first entry index, and allowing access to the first access address when the entry status of the first memory access entry is open for use, the first access type belongs to the type specified by the access rights of the first memory access entry, and the first access address belongs to the address space of the first memory access entry.

Description

Technical Field

[0001] The present application relates to the field of data communication, and in particular to a remote direct memory access verification system, device and cluster. Background Art

[0002] Remote Direct Memory Access (RDMA) allows computers to directly access the memory of another computer from the memory of one computer without the intervention of the operating system kernel. RDMA can significantly reduce data transmission latency and host overhead, improve system performance and efficiency, and is often used in scenarios such as high-performance computing, data centers, and storage area networks that require high data transmission speed and response time.

[0003] However, since RDMA allows direct memory access, RDMA has certain risks that may allow unauthorized entities to access sensitive data. Summary of the invention

[0004] The present application provides a remote direct memory access verification system, device and cluster, which can improve the security of RDMA access.

[0005] In a first aspect, a remote direct memory access verification system is provided, comprising:

[0006] A first host includes a memory space, wherein the memory space includes a remote direct memory access space;

[0007] A first remote direct memory access device includes one or more memory access entries, wherein the memory access entry includes an address space, an access permission and an entry status, the address space is used to indicate the remote direct memory access space; the access permission is used to indicate the type of access to the remote direct memory access space allowed, and the entry status is used to indicate whether the remote direct memory access space is open for use; receiving a remote direct memory access request, wherein the remote direct memory access request includes a first entry index, a first access type and a first access address; determining a first memory access entry corresponding to the first entry index according to the first entry index, and allowing remote direct memory access to the first access address of the first host when the entry status of the first memory access entry is open for use, the first access type belongs to the type specified by the access permission of the first memory access entry, and the first access address belongs to the address space of the first memory access entry.

[0008] In the above scheme, the remote direct memory access request performs permission and address boundary verification, intercepts illegal access requests, improves the security of memory access, and offloads the virtual address to physical address conversion from the first host to the first remote direct memory access device, thereby improving the address conversion efficiency.

[0009] In some possible designs, the memory access entry further includes a virtual start address and a physical address access mode, the physical address access mode is direct physical address access, and the address space includes a memory start physical address and a memory end physical address;

[0010] The first remote direct memory access device is also used to obtain an access offset by subtracting the first access address from the virtual starting address, obtain an intra-page offset based on a low-order address in the virtual starting address, add the intra-page offset to the access offset to obtain a total offset, add the memory starting physical address to the total offset to obtain a physical access address, and determine that the first access address belongs to the address space of the first memory access entry when the physical access address is less than the memory ending physical address.

[0011] The above solution is suitable for scenarios with extremely high performance requirements, such as real-time operating systems and high-performance computing, because direct acquisition can avoid the overhead of intermediate conversion and calculation and achieve fast data access.

[0012] In some possible designs, the memory access entry further includes a virtual start address and a physical address access mode, the physical address access mode is an indirect physical address access, and the address space includes a physical address start index and a physical address end index.

[0013] The first remote direct memory access device is also used to obtain an access offset by subtracting the first access address from the virtual starting address, obtain an intra-page offset based on a low-order address in the virtual starting address, add the intra-page offset to the access offset to obtain a total offset, calculate a page table offset based on the total offset, add the page table offset to the physical address starting index to obtain an access index, and determine that the first access address belongs to the address space of the first memory access entry when the access index is less than the physical address ending index.

[0014] The above solutions usually have better compatibility and portability on different operating systems and hardware architectures.

[0015] In some possible designs, the access rights include local read permission and local write permission;

[0016] The first remote direct memory access device is also used to determine that the first access type belongs to the type specified by the access permission of the first memory access entry when the first access type is local read permission and the local read permission in the access permission is valid; and to determine that the first access type belongs to the type specified by the access permission of the first memory access entry when the first access type is local write permission and the local write permission in the access permission is valid.

[0017] In some possible designs, the access rights include remote read rights and remote write rights;

[0018] The first remote direct memory access device is also used to determine that the first access type belongs to the type specified by the access permission of the first memory access entry when the first access type is remote read permission and the remote read permission in the access permission is valid; and to determine that the first access type belongs to the type specified by the access permission of the first memory access entry when the first access type is remote write permission and the remote write permission in the access permission is valid.

[0019] In some possible designs, the remote direct memory access request is sent by a second remote direct memory access device, and the second remote direct memory access device and the second host belong to the same server.

[0020] In some possible designs, the remote direct memory access request further includes a first key,

[0021] The first remote direct memory access device is further configured to determine, according to the first entry index, a first memory access entry corresponding to the first entry index, when it is determined according to the first key that the second remote direct memory access device is allowed to access the first host.

[0022] In some possible designs, the remote direct memory access request is sent by a first remote direct memory access device, and the first remote direct memory access device and the first host belong to the same server.

[0023] In a second aspect, a computing device is provided, comprising a remote direct memory access verification system and a storage unit, wherein the remote direct memory access verification system and the storage unit are capable of communicating with each other, and the remote direct memory access verification system is a system as described in any one of the first aspects.

[0024] In a third aspect, a computing device cluster is provided, comprising a remote direct memory access verification system and a storage unit, wherein the remote direct memory access verification system and the storage unit can communicate with each other, and the remote direct memory access verification system is a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0026] Figure 1 It is a structural diagram of a remote direct memory access verification system provided by the present application;

[0027] Figure 2 It is a structural schematic diagram of a first host provided by the present application;

[0028] Figure 3 It is a mapping relationship between an index and a physical address provided by this application;

[0029] Figure 4 This is a verification diagram of a first access address provided by this application;

[0030] Figure 5 It is another verification schematic diagram of the first access address provided by the present application;

[0031] Figure 6 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0033] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a remote direct memory access verification system provided by this application. Figure 1 As shown, the remote direct memory access verification system provided by the present application includes: a first host 11 and a first remote direct memory access device 12 .

[0034] The first host 11 is a computing core and a control core, and can handle complex situations. The first host 11 can be a very large-scale integrated circuit. The main operating system and other software programs are installed in the first host 11, so that the first host 11 can access the memory and various PCIE devices. The first host 11 can quickly access the local memory through the on-chip bus. The first host 11 may include one or more processor cores. In one implementation, the first host 11 may be a multi-core chip, that is, a chip containing multiple processing cores. In another implementation, the first host 11 may include one or more processor cores. It can be a chip with one processing core. The first host includes a memory space, wherein the memory space includes a remote direct memory access space. The remote direct memory access space can be a continuous storage space or a discontinuous storage space.

[0035] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a first host provided by this application. Figure 2 As shown, the first host may include a memory address register 101, a memory data register 102, a program counter 103, an instruction register 104, an instruction decoder 105, a microcode read-only memory 106, an operation controller 107, a calculation unit 108, a general register group 109, an accumulator 110, a program status word register 111, a timing circuit 112 and a processor bus 120. The processor bus 120 may also be a data bus, a power bus, a control bus or a status signal bus, etc.

[0036] The first host is used to process instructions and data stored in the memory 113. In some embodiments, the instructions may include one or more instruction formats. The instruction format may indicate various fields (number of bits, position of bits, etc.) to specify the data processing operation to be performed and the operand on which the operation is to be performed. Some instruction formats may be further defined by instruction templates (or sub-formats).

[0037] In the first host, the memory address register 101 is used to store the address of the memory currently accessed by the first host, and the memory data register 102 is used to store the data and the read or write instructions read or written from the address by the first host, so as to make up for the difference in operating speed between the processor and the memory.

[0038] The timing circuit 112 provides a time reference for each component through a fixed clock. The time for the processor to execute an instruction is an instruction cycle. The program counter 103 is used to store the address of the next instruction. When the instructions are executed sequentially, the program counter 103 automatically adds the number of bytes of an instruction after each instruction is taken. When a transfer instruction is encountered, the program counter 103 specifies the address of the next instruction through the address code field in the transfer instruction. The instruction register 104 is used to save the instruction currently being executed. The instruction includes two fields, an operation code and an address code. The operation code part is decoded by the instruction decoder 105 to generate the control potential of the operation required by the instruction. The operation controller 107 can generate various operation control signals according to the control potential signal output by the instruction decoder and the timing signal generated by the timing circuit 112, and control the remaining components of the first host to complete the operation of taking and executing instructions.

[0039] A microinstruction is the smallest unit of instructions executed by a processor. An instruction can be a single microinstruction or composed of several microinstructions. An instruction composed of multiple microinstructions is called a complex instruction. Various mechanisms can be used to implement the decoding of complex instructions by the instruction decoder 105. Specific decoding mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the steps of the microinstructions corresponding to the complex instructions can be stored in the microcode read-only memory 106. During the decoding process, the instruction decoder 105 can query and obtain the operation code and address code of the microinstructions constituting the complex instructions from the microcode read-only memory 106, and decode the operation code part of the microinstructions in turn to generate the control potential required by the microinstructions.

[0040] The operation controller 107 has multiple buffers, and can send the decoded instructions to their respective reservation stations for storage according to the types of instructions. After analyzing the status of the hardware circuit of the computing unit and the specific situation of whether each instruction can be executed in advance, the instructions that can be executed in advance are scheduled to the corresponding computing unit 108 for execution. During this period, the instruction stream is reordered so that the instruction pipeline can proceed and be smoothly scheduled. Exemplarily, for instructions of integer calculation, the operation controller 107 can use the integer reservation station to save instructions and assign them to the integer computing unit for calculation; for instructions of floating-point calculation, the operation controller 107 can use the floating-point reservation station to save instructions and assign them to the floating-point computing unit for calculation.

[0041] The general register group 109 is used to store the data corresponding to the address code according to the address code of the instruction. The calculation unit 108 is used to receive the operation control signal of the operation controller 107 and perform calculations on the data stored in the general register group 109, including arithmetic operations (including basic operations such as addition, subtraction, multiplication and additional operations) and logical operations (including shifting, logical testing or comparison of two values). The temporary variables generated in the calculation are stored in the accumulator 110, and the information of the generated status is stored in the program status word register 111, such as the operation result carry / borrow flag (C), the operation result overflow flag (O), the operation result zero flag (Z), the operation result negative flag (N), the operation result sign flag (S), etc. The program status word register is also used to save information such as interrupts and the working status of the computing device, so that the first host can timely understand the machine operation status and program operation status.

[0042] The calculation unit 108 includes a variety of different circuit modules, which can be used to execute different instructions. For example, the integer calculation unit 1081 and the floating point calculation unit 1082 are used to perform arithmetic operations and logical operations on integers and floating point numbers, respectively.

[0043] It can be understood that the above-mentioned first host is only a specific embodiment. In actual application, it can also have more or fewer components, which will not be described in detail here.

[0044] Remote direct memory access devices are hardware devices that support RDMA technology. Common ones include network interface cards (NICs) that support RDMA, such as InfiniBand cards, Ethernet cards that support RoCE (RDMA over Converged Ethernet), etc. Network cards are used to provide hardware resources for network communications. Because they have a Media Access Control Address (MAC) address, they belong between Layer 1 and Layer 2 of the Open System Interconnection (OSI) model. It allows users to connect to each other via cables or wirelessly. Each network card has a unique 48-bit serial number called a MAC address, which is written in a read-only memory on the card.

[0045] A first remote direct memory access device includes one or more memory access entries, wherein the memory access entry includes an address space, an access permission, and an entry status. The address space is used to indicate the remote direct memory access space. The access permission is used to indicate the type of access to the remote direct memory access space. The entry status is used to indicate whether the remote direct memory access space is open for use. Optionally, the memory access entry also includes a virtual start address and a physical address access mode. The virtual start address is the starting position of the virtual memory space of the allocated remote direct memory access space. The physical address access mode may be direct physical address access or indirect physical address access. When the physical address access mode is direct physical address access, the address space includes a memory start physical address and a memory end physical address. The memory start physical address refers to the address of the starting position of the remote direct memory access space in the physical memory. The memory end physical address refers to the address of the ending position of the remote direct memory access space in the physical memory. When the physical address access mode is indirect physical address access, the address space includes a physical address start index and a physical address end index, and the physical address start index refers to the index value identifying the starting position in the remote direct memory access space. The physical address end index refers to the index value identifying the ending position in the remote direct memory access space. like Figure 3 As shown, the physical address start index corresponds to the first page physical start address, the first page physical start address points to the physical start address of the first page in the remote direct memory access space, and the physical address end index corresponds to the last page physical start address, and the last page physical start address points to the physical start address of the last page in the remote direct memory access space.

[0046] In a specific embodiment, the first host and the first remote direct memory access device belong to the same server. When the first remote direct memory access device needs the memory space of the first host, the driver in the first host sends a doorbell to notify the first remote direct memory access device to initiate a memory access request. The first remote direct memory access device receives the remote direct memory access request. The remote direct memory access request includes a first entry index, a first access type, and a first access address. The first remote direct memory access device determines a first memory access entry corresponding to the first entry index according to the first entry index. After the first memory access entry, the first remote direct memory access device performs the following verifications respectively:

[0047] The first remote direct memory access device determines that the entry status of the first memory access entry is open for use. If the entry status in the first memory access entry is invalid, it means that the first memory access entry has not been initialized, that is, there is no corresponding remote direct memory access space allocation; if the entry status in the first memory access entry is valid, it means that the first memory access entry has been allocated memory space, and the first remote direct memory access device can access the remote direct memory access space corresponding to the memory access entry.

[0048] The first remote direct memory access device compares the first access type with the type of permission in the first memory access entry. If the first access type is a local read permission, and the local read permission in the first memory access entry is valid, it is determined that the first access type belongs to the type specified by the access permission of the first memory access entry; if the first access type is a local write permission, and the local write permission in the first memory access entry is valid, it is determined that the first access type belongs to the type specified by the access permission of the first memory access entry.

[0049] The first remote direct memory access device may determine whether the first access address belongs to the remote direct memory access space in any one of the following two ways.

[0050] In the first method, if Figure 4 As shown, the first remote direct memory access device is also used to obtain the access offset by subtracting the first access address from the virtual start address, obtain the page offset based on the low-order address in the virtual start address, add the page offset to the access offset to obtain the total offset, add the memory start physical address to the total offset to obtain the physical access address, and when the physical access address is less than the memory end physical address, determine that the first access address belongs to the address space corresponding to the first memory access entry; when the physical access address is greater than or equal to the memory end physical address, determine that the first access address does not belong to the address space corresponding to the first memory access entry. The above scheme is suitable for scenarios with extremely high performance requirements, such as real-time operating systems, high-performance computing, etc., because direct acquisition can avoid the overhead of intermediate conversion and calculation, and achieve fast data access.

[0051] In the second method, if Figure 5As shown, the first remote direct memory access device obtains the access offset by subtracting the first access address from the virtual start address, obtains the in-page offset based on the low-order address in the virtual start address, adds the in-page offset to the access offset to obtain the total offset, calculates the page table offset based on the total offset, adds the physical address start index to the page table offset to obtain the access index, and when the access index is less than the physical address end index, determines that the first access address belongs to the address space corresponding to the first memory access entry. When the access index is greater than or equal to the physical address end index, determines that the first access address does not belong to the address space corresponding to the first memory access entry. The above scheme usually has better compatibility and portability on different operating systems and hardware architectures.

[0052] In summary, when the entry status of the first memory access entry is open for use, the first access type belongs to the type specified by the access permission of the first memory access entry, and the first access address belongs to the address space of the first memory access entry, remote direct memory access to the first access address of the first host is allowed. It can be understood that remote direct memory access to the first access address of the first host is allowed only when all of the above conditions are met. If any of the above conditions is not met, remote direct memory access to the first access address of the first host is not allowed.

[0053] In the above scheme, the remote direct memory access request performs permission and address boundary verification, intercepts illegal access requests, improves the security of memory access, and offloads the virtual address to physical address conversion from the first host to the first remote direct memory access device, thereby improving the address conversion efficiency.

[0054] In a specific embodiment, the first host and the first remote direct memory access device belong to the same server, and the second host and the second remote direct memory access device belong to the same server. When the second remote direct memory access device needs to access the memory space of the first host, the driver in the second host sends a doorbell to notify the second remote direct memory access device to initiate a memory access request. The first remote direct memory access device receives the remote direct memory access request. Among them, the remote direct memory access request includes a first entry index, a first access type and a first access address. The first remote direct memory access device is also used to determine whether the second remote direct memory access device is allowed to access the first host according to the first key in the remote direct memory access request. In the case of determining that the second remote direct memory access device is allowed to access the first host, the first remote direct memory access device determines the first memory access entry corresponding to the first entry index according to the first entry index. After determining the first memory access entry, the first remote direct memory access device performs the following verifications respectively:

[0055] The first remote direct memory access device determines that the entry status of the first memory access entry is open for use. If the entry status in the first memory access entry is invalid, it means that the first memory access entry has not been initialized, that is, there is no corresponding remote direct memory access space allocation; if the entry status in the first memory access entry is valid, it means that the first memory access entry has been allocated memory space, and the second remote direct memory access device can access the remote direct memory access space corresponding to the memory access entry.

[0056] The first remote direct memory access device compares the first access type with the type of permission in the first memory access entry. If the first access type is a remote read permission, and the remote read permission in the first memory access entry is valid, it is determined that the first access type belongs to the type specified by the access permission of the first memory access entry; if the first access type is a remote write permission, and the remote write permission in the first memory access entry is valid, it is determined that the first access type belongs to the type specified by the access permission of the first memory access entry.

[0057] The first remote direct memory access device may determine whether the first access address belongs to the remote direct memory access space in any one of the following two ways.

[0058] In the first mode, the first remote direct memory access device is also used to obtain the access offset by subtracting the first access address from the virtual start address, obtain the page offset based on the low-order address in the virtual start address, add the page offset to the access offset to obtain the total offset, add the memory start physical address to the total offset to obtain the physical access address, and when the physical access address is less than the memory end physical address, determine that the first access address belongs to the address space corresponding to the first memory access entry; when the physical access address is greater than or equal to the memory end physical address, determine that the first access address does not belong to the address space corresponding to the first memory access entry. The above scheme is suitable for scenarios with extremely high performance requirements, such as real-time operating systems, high-performance computing, etc., because direct acquisition can avoid the overhead of intermediate conversion and calculation, and achieve fast data access.

[0059] In the second method, the first remote direct memory access device obtains the access offset by subtracting the first access address from the virtual start address, obtains the in-page offset based on the low-order address in the virtual start address, adds the in-page offset to the access offset to obtain the total offset, calculates the page table offset based on the total offset, adds the physical address start index to the page table offset to obtain the access index, and when the access index is less than the physical address end index, determines that the first access address belongs to the address space corresponding to the first memory access entry. When the access index is greater than or equal to the physical address end index, determines that the first access address does not belong to the address space corresponding to the first memory access entry. The above scheme usually has better compatibility and portability on different operating systems and hardware architectures.

[0060] In summary, when the entry status of the first memory access entry is open for use, the first access type belongs to the type specified by the access permission of the first memory access entry, and the first access address belongs to the address space of the first memory access entry, remote direct memory access to the first access address of the first host is allowed. It can be understood that remote direct memory access to the first access address of the first host is allowed only when all of the above conditions are met. If any of the above conditions is not met, remote direct memory access to the first access address of the first host is not allowed.

[0061] In the above scheme, the remote direct memory access request performs permission and address boundary verification, intercepts illegal access requests, improves the security of memory access, and offloads the virtual address to physical address conversion from the first host to the first remote direct memory access device, thereby improving the address conversion efficiency.

[0062] See also Figure 6 , Figure 6 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410 , a communication interface 420 and a storage unit 430 .

[0063] The processing unit 410, the communication interface 420 and the storage unit 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, which is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processing unit 410 can also be used to implement some or all of the operation steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiment, such as the processing unit 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in the embodiment of the present application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-mentioned device embodiment, and the communication interface 420 can be specifically used for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be specifically used for the processing functions necessary to implement the functions of these devices and components, etc.

[0064] Figure 6 The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may provide processing capabilities in a coordinated manner in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 6 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 6 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0065] The processing unit 410 may have a variety of specific implementation forms. For example, the processing unit 410 may include a processor (central processing unit, CPU), a graphic processing unit (graphic processing unit, GPU), a neural-network processing unit (neural-network processing unit, NPU), a tensor processing unit (tensor processing unit, TPU) or a data processing unit (data processing unit, DPU) and other combinations thereof, which are not specifically limited in the embodiments of the present application. The processing unit 410 may also be a single-core processor or a multi-core processor. The processing unit 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a generic array logic (generic array logic, GAL) or any combination thereof. The processing unit 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (digital signal processor, DSP), etc. The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0066] The storage unit 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The storage unit 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The storage unit 430 may also be used to store program codes and data, so that the processing unit 410 can call the program codes stored in the storage unit 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 6 Show more or fewer components, or have different component configurations.

[0067] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0068] The present application also provides a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0069] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one network site, computer, server or data center to another network site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or it can be a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD, etc.), or a semiconductor medium (e.g., a solid-state hard disk), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A remote direct memory access verification system, characterized in that: include: A first host includes a memory space, wherein the memory space includes a remote direct memory access space; A first remote direct memory access device, comprising one or more memory access entries, wherein the memory access entry comprises an address space, an access permission and an entry status, wherein the address space is used to indicate the remote direct memory access space; the access permission is used to indicate the type of access to the remote direct memory access space allowed, and the entry status is used to indicate whether the remote direct memory access space is open for use; receiving a remote direct memory access request, wherein the remote direct memory access request comprises a first entry index, a first access type and a first access address; determining a first memory access entry corresponding to the first entry index according to the first entry index, and allowing remote direct memory access to the first access address of the first host when the entry status of the first memory access entry is open for use, the first access type belongs to the type specified by the access permission of the first memory access entry, and the first access address belongs to the address space of the first memory access entry; The memory access entry also includes a virtual start address and a physical address access mode, the physical address access mode is direct physical address access, and the address space includes a memory start physical address and a memory end physical address; The first remote direct memory access device is further used to obtain an access offset by subtracting the first access address from the virtual start address, obtain an intra-page offset based on a low-order address in the virtual start address, add the intra-page offset to the access offset to obtain a total offset, add the memory start physical address to the total offset to obtain a physical access address, and determine that the first access address belongs to the address space of the first memory access entry when the physical access address is less than the memory end physical address; or The memory access entry also includes a virtual start address and a physical address access mode, the physical address access mode is an indirect physical address access, and the address space includes a physical address start index and a physical address end index. The first remote direct memory access device is also used to obtain an access offset by subtracting the first access address from the virtual starting address, obtain an intra-page offset based on a low-order address in the virtual starting address, add the intra-page offset to the access offset to obtain a total offset, calculate a page table offset based on the total offset, add the page table offset to the physical address starting index to obtain an access index, and determine that the first access address belongs to the address space of the first memory access entry when the access index is less than the physical address ending index.

2. The system according to claim 1, characterized in that The access rights include local read permission and local write permission; The first remote direct memory access device is further configured to determine, when the first access type is a local read permission and the local read permission in the access permission is valid, that the first access type belongs to a type specified by the access permission of the first memory access entry; When the first access type is the local write permission and the local write permission in the access permission is valid, it is determined that the first access type belongs to the type specified by the access permission of the first memory access entry.

3. The system according to claim 1 or 2, characterized in that: The access rights include remote read permission and remote write permission; The first remote direct memory access device is further used to determine that the first access type belongs to the type specified by the access permission of the first memory access entry when the first access type is the remote read permission and the remote read permission in the access permission is valid; When the first access type is the remote write permission and the remote write permission in the access permission is valid, it is determined that the first access type belongs to the type specified by the access permission of the first memory access entry.

4. The system according to claim 3, characterized in that The remote direct memory access request is sent by a second remote direct memory access device, and the second remote direct memory access device and the second host belong to the same server.

5. The system according to claim 4, characterized in that The remote direct memory access request further includes a first key, The first remote direct memory access device is further configured to determine, according to the first entry index, a first memory access entry corresponding to the first entry index, when it is determined according to the first key that the second remote direct memory access device is allowed to access the first host.

6. The system according to claim 1, characterized in that The remote direct memory access request is sent by a first remote direct memory access device, and the first remote direct memory access device and the first host belong to the same server.

7. A computing device, characterized in that It comprises a remote direct memory access verification system and a storage unit, the remote direct memory access verification system and the storage unit can communicate with each other, and the remote direct memory access verification system is a system as described in any one of claims 1-6.

8. A computing device cluster, characterized in that: It comprises a remote direct memory access verification system and a storage unit, the remote direct memory access verification system and the storage unit can communicate with each other, and the remote direct memory access verification system is a system as described in any one of claims 1-6.

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