Memory neural circuit, neural circuit array and memory neural network

Abstract

The present invention discloses a memory neural circuit, a neural circuit array, and a memory neural network, which relate to the technical field of analog and digital circuits. The present invention includes seven transistors, a capacitor, six signal input terminals, and an output terminal Output. The seven transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. By integrating the long-term memory function and multi-modal signal processing capabilities, the neural circuit of the present invention can effectively process optical, pressure, and chemical signals, enabling it to adapt to a variety of application scenarios, breaking through the dependence on electrical signals in traditional solutions. By directly receiving and processing various types of input signals, the circuit achieves higher flexibility and adaptability. In addition, the circuit simulates the behavior and characteristics of neurons, has efficient signal processing and memory functions, and stores long-term memories by implementing mechanisms such as synaptic plasticity and long-term potentiation, making information processing more stable and reliable.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-digital circuits, and specifically to memory neural circuits, neural circuit arrays, and memory neural networks. Background Art

[0002] Neural synapses are important basic units for training the memory ability and processing data of the human brain. Therefore, developing new materials and new structures, and studying the plasticity of neural synapses based on new artificial materials and optoelectronic devices are of great significance for the research of neuromorphic devices and the realization of brain-like hardware design. Currently, common technical solutions for neural synapse devices include analog resistive synapse devices, phase change material synapse devices, electrochemical synapse devices, and organic synapse devices, etc.

[0003] Using circuits to simulate neuron behavior is also one of the directions for simulating the function of neural synapses. Currently, existing technical solutions include I&F Neuron Circuits (I&F), Leaky Integrate-and-Fire (LIF), NeuronCircuits, Spiking Neural Networks (SNNs), and Analog Synapse Circuits, etc. Among the existing neuron circuit solutions, the I&F and LIF models can basically simulate the firing mechanism of neurons, but they mainly rely on electrical signal processing and cannot effectively process optical, pressure, and chemical signals. Although SNNs can simulate the behavior of spiking neurons, they need to convert non-electrical signals into electrical signals. Therefore, limited by materials and processes, existing technologies usually can only achieve short-term information storage and lack support for long-term memory. For this reason, we propose memory neural circuits, neural circuit arrays, and memory neural networks. Summary of the Invention

[0004] The purpose of the present invention is to provide memory neural circuits, neural circuit arrays, and memory neural networks to solve the problems raised in the above background art.

[0005] According to the first aspect of the present invention, to achieve the above object, the present invention provides the following technical solution: A memory neural circuit, including seven transistors, a capacitor, six signal input terminals, and an output terminal Output. The seven transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The six signal input terminals are respectively a Vstimulus input terminal connected between the second transistor and the fourth transistor, an Sn input terminal connected to the second transistor, an Sn-1 input terminal connected to the fourth transistor, a VINT input terminal connected to the capacitor, an RD input terminal connected to the fifth transistor, and an ELVDD input terminal. And the output terminal Output is connected to the sixth transistor;

[0006] Among them, the second transistor, the third transistor, the seventh transistor, and the input terminals Sn, Vstimulus, and VINT form a reset unit of the circuit, which is used to clear or reset the signals of each node in the circuit;

[0007] The first transistor, the second transistor, the third transistor, the fourth transistor, the capacitor, and the input terminals Sn-1, Sn, and Vstimulus form a signal receiving and memory unit of the circuit, which is used to realize signal conversion and memory;

[0008] The first transistor, the fifth transistor, the sixth transistor, and the input terminals RD[N], ELVDD, and the output terminal Output form a signal reading and transmitting unit of the circuit, which is used to realize signal conversion and transmission.

[0009] Further, the second transistor, the third transistor, and the seventh transistor in the reset unit are all electrically connected through wires. The input control signal at the input terminal Sn can make the second transistor, the third transistor, and the seventh transistor conduct. At this time, the VINT input terminal receives a signal and writes it into each node inside the circuit, which is used to realize the potential reset of the transistor gate and the capacitor.

[0010] Further, the input terminal of the first transistor in the signal receiving and memory unit is connected to the output terminal of the second transistor. The second transistor and the third transistor are electrically connected through wires. The input terminal of the third transistor is connected to the capacitor. The output terminal of the fourth transistor is connected to the capacitor. The input control signal at the input terminal Sn-1 makes the fourth transistor conduct. At this time, the Vstimulus inputs an excitation signal, and the signal voltage is recorded at both ends of the capacitor, realizing the conversion of the current signal to the voltage signal, which is used to receive the signal. Subsequently, the third transistor and the fourth transistor are turned off to realize signal locking and memory.

[0011] Further, the output terminal of the first transistor in the signal reading and transmitting unit is connected to the input terminal of the sixth transistor. The sixth transistor is connected to the output terminal Output. The fifth transistor and the sixth transistor are electrically connected through wires. The input signal at the input terminal RD[N] makes the fifth transistor and the sixth transistor conduct. At this time, the capacitor controls the first transistor to convert the recorded voltage signal into a current signal, which is used to output and transmit the signal from the Output port.

[0012] Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor can be set as NPN transistors, PNP transistors, or CMOS transistors.

[0013] Further, a diode is connected in series at the Vstimulus input terminal, which is used to input pressure signals, chemical stimulation signals, or light stimulation signals;

[0014] Or it is connected in series with a sensor for sensing an external stimulus signal, converting the signal into an electrical stimulus signal and then inputting it into the circuit.

[0015] According to the second aspect of the present invention, the present invention provides a neural circuit array, including a plurality of the above-mentioned memory neural circuits, and the plurality of memory neural circuits are assigned to the logical rows and logical columns of the neural circuit array, and:

[0016] The Vstimulus input end of the memory neural circuits in each column is connected to the Output output end of the previous memory neural circuit for receiving an excitation signal from the corresponding previous-stage memory neural circuit during use;

[0017] The Sn-1 input ends of the previous memory neural circuit and the subsequent memory neural circuit in each row are connected to each other for transmitting action signals backward from the previous memory neural circuit during use.

[0018] According to the third aspect of the present invention, the present invention provides a memory neural network, including the above-mentioned neural circuit array.

[0019] The present invention has at least the following beneficial effects:

[0020] By integrating the long-term memory function and multi-modal signal processing ability, the neural circuit of the present invention can effectively process optical, pressure and chemical signals, making it adaptable to a variety of application scenarios, breaking through the dependence on electrical signals in traditional solutions. By directly receiving and processing various types of input signals, the circuit achieves higher flexibility and adaptability. In addition, the circuit simulates the behavior and characteristics of neurons, has efficient signal processing and memory functions, and stores long-term memory by implementing mechanisms such as synaptic plasticity and long-term potentiation, making information processing more stable and reliable.

[0021] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. Description of the Drawings

[0022] Figure 1 is the structural schematic diagram of the neural circuit in the present invention;

[0023] Figure 2 is the structural diagram of the neural circuit in the first embodiment of the present invention;

[0024] Figure 3 is the structural diagram of the neural circuit in the second embodiment of the present invention;

[0025] Figure 4 is the sub-structural diagram of a single memory neural circuit in the third embodiment of the present invention;

[0026] Figure 5It is a schematic diagram of the neural circuit array structure in the third embodiment of the present invention.

[0027] Reference numerals:

[0028] T1, the first transistor; T2, the second transistor; T3, the third transistor; T4, the fourth transistor; T5, the fifth transistor; T6, the sixth transistor; T7, the seventh transistor; C1, the capacitor. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0030] Please refer to Figure 1 - Figure 2 , the present invention provides technical solutions: a memory neural circuit, a neural circuit array, and a memory neural network, including seven transistors, a capacitor C1, six signal input terminals and an output terminal Output. The seven transistors are respectively the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The six signal input terminals are respectively the Vstimulus input terminal connected to the second transistor T2 and the fourth transistor T4, the Sn input terminal connected to the second transistor T2, the Sn-1 input terminal connected to the fourth transistor T4, the VINT input terminal connected to the capacitor C1, the RD input terminal connected to the fifth transistor T5, and the ELVDD input terminal. The output terminal Output is connected to the sixth transistor T6;

[0031] It should be noted that the Vstimulus port mainly inputs an excitation signal, which is used to input synaptic electrical stimulation (or various forms of signals such as optical stimulation) simulating nerves. The electrical signals include various types such as direct current, alternating current, and pulses;

[0032] Sn, Sn-1: mirror pulse input signals, which are timing control signals used to control signal writing and perform internal circuit reset;

[0033] Vint: a direct current input signal, which is used to reset and initialize the signals of the capacitor C1 and the transistors;

[0034] ELVDD: a direct current input signal, which is used to provide power for the circuit to work;

[0035] RD: The circuit signal output control signal, which can be a DC, AC or pulse signal, is used to control the electrical stimulation signal (cascadable) output to the next node after the neural circuit memory is converted;

[0036] Output: The output signal, which is the electrical stimulation signal output to the next node after the neural circuit memory is converted.

[0037] Regarding the technical solution of this embodiment, from the perspective of functional units, the circuit mainly includes three parts: a reset unit, a signal receiving and memory unit, and a signal reading and transmission unit, which respectively correspond to the functions of the presynaptic, synaptic cleft, and postsynaptic of the nerve;

[0038] Among them, the second transistor T2, the third transistor T3, the seventh transistor T7, and the input terminals Sn, Vstimulus, and VINT constitute the reset unit of the circuit, which is used to clear or reset the signals of each node in the circuit;

[0039] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the capacitor C1, and the input terminals Sn-1, Sn, and Vstimulus form the signal receiving and memory unit of the circuit, which is used to realize signal conversion and memory;

[0040] The first transistor T1, the fifth transistor T5, the sixth transistor T6, and the input terminals RD[N], ELVDD, and the output terminal Output form the signal reading and transmission unit of the circuit, which is used to realize signal conversion and transmission.

[0041] Regarding the technical solution of this embodiment, in the reset unit, the second transistor T2, the third transistor T3, and the seventh transistor T7 are all electrically connected through wires. The input control signal at the input terminal Sn can make the second transistor T2, the third transistor T3, and the seventh transistor T7 conduct. At this time, the VINT input terminal receives the signal and writes it into each node inside the circuit, so that the voltage signal across the capacitor C1 is reset or cleared. At this time, the capacitor C1 is connected to the first transistor T1, and the gate potential of the first transistor T1 can be reset.

[0042] Regarding the technical solution of this embodiment, the input end of the first transistor T1 in the signal receiving and memory unit is connected to the output end of the second transistor T2. The second transistor T2 and the third transistor T3 are electrically connected through a wire. The input end of the third transistor T3 is connected to the capacitor C1. The output end of the fourth transistor T4 is connected to the capacitor C1. The input end Sn-1 inputs a control signal to turn on the fourth transistor T4. At this time, the Vstimulus inputs an excitation signal, and the signal voltage is recorded at both ends of the capacitor C1, realizing the conversion from the current signal to the voltage signal for signal reception. Subsequently, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off, and the signal recorded at both ends of the capacitor C1 will be latched at the position of the first transistor T1, thereby realizing signal latching and memory.

[0043] Regarding the technical solution of this embodiment, the output end of the first transistor T1 in the signal reading and transmitting unit is connected to the input end of the sixth transistor T6. The sixth transistor T6 is connected to the output end Output. The fifth transistor T5 and the sixth transistor T6 are electrically connected through a wire. The input end RD[N] inputs a signal to turn on the fifth transistor T5 and the sixth transistor T6. At this time, the capacitor C1 controls the first transistor T1 to convert the recorded voltage signal into a current signal, and the current signal will be output through the sixth transistor T6 and its connected Output port, thereby realizing the output or transmission of the signal to the next stage.

[0044] Furthermore, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be set as NPN-type transistors, PNP-type transistors, or CMOS transistors.

[0045] Specifically, in actual use, the memory neural circuit first needs to input signals through the VINT input end to write to each node inside the circuit, realizing the potential reset of the transistor gate and the capacitor C1. Then, the Vstimulus inputs an excitation signal, and the signal voltage is recorded at both ends of the capacitor C1, realizing the conversion from the current signal to the voltage signal. Subsequently, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off to latch the signal and realize the memory function. Then, the fifth transistor T5 and the sixth transistor T6 are turned on, and the capacitor C1 controls the first transistor T1 to realize the conversion of the voltage signal into a current signal, which is read out from the Output-IPSC port or transmitted to the next neuron. Finally, the signal reading and transmitting unit and the reset and reset unit are turned off, and the Vstimulus input end continues to receive the excitation signal from the external or the previous neuron. Thus, a cycle is completed, and at the same time, this step can also enter the signal reset step.

[0046] Embodiment 2:

[0047] AsFigure 3 As shown in the figure, the fundamental difference between the second embodiment and the first embodiment is that a diode is connected in series to the Vstimulus input terminal, such that when an electrical signal is input to the Vstimulus input terminal to simulate the performance of an electrical synapse, a pressure signal, a chemical stimulus signal, or an optical stimulus signal can also be input;

[0048] A sensor can also be connected in series to the Vstimulus input terminal, which is used to sense an external stimulus signal and convert the signal into an electrical stimulus signal before inputting it into the circuit.

[0049] Embodiment Three:

[0050] As Figure 4 - Figure 5 shown in the figure, this embodiment provides a neural circuit array, which includes a plurality of the above-mentioned memory neural circuits. The plurality of memory neural circuits are assigned to the logical rows and logical columns of the neural circuit array, and:

[0051] The Vstimulus input terminals of the memory neural circuits in each column are connected to the Output output terminals of the previous memory neural circuit, which is used to receive an excitation signal from the corresponding previous-level memory neural circuit during use;

[0052] The Sn-1 input terminals of the previous memory neural circuit in each row are connected to the Sn-1 input terminals of the subsequent memory neural circuit, which is used to transmit action signals backward from the previous memory neural circuit during use.

[0053] It should be noted that Figure 4 is a display of the cascaded lead-out of a single neural circuit subunit. Each memory neural circuit can serve as a neuron synapse subunit, and multiple subunits are cascaded together to form a reticular neuron circuit array. As Figure 5 shown in the figure, the output signal of the previous-level circuit serves as the input excitation signal of the subsequent-level circuit. The scale of the specific array can be expanded in three-dimensional directions according to actual needs.

[0054] Embodiment Four:

[0055] This embodiment provides a memory neural network, which includes the above-mentioned neural circuit array.

[0056] In summary, the neural circuit of the present invention integrates the functions of long-term memory and multi-modal signal processing capabilities, can effectively process optical, pressure, and chemical signals, enabling it to adapt to a variety of application scenarios, breaking through the dependence on electrical signals in traditional solutions. By directly receiving and processing various types of input signals, the circuit achieves higher flexibility and adaptability. In addition, this circuit simulates the behavior and characteristics of neurons, has efficient signal processing and memory functions, and stores long-term memories by implementing mechanisms such as synaptic plasticity and long-term potentiation, making information processing more stable and reliable.

[0057] It should be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device.

[0058] For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. When an element is referred to as being "assembled on", "mounted on", "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are only for illustrative purposes and do not represent the only embodiments.

[0059] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

[0060] In the description of this specification, the description with reference to terms such as "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

Claims

1. A memory neural circuit, characterized in that: The circuit comprises seven transistors, a capacitor, six signal input terminals and an output terminal Output, wherein the seven transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the six signal input terminals are respectively a Vstimulus input terminal connected to the second transistor and the fourth transistor, a Sn input terminal connected to the second transistor, a Sn-1 input terminal connected to the fourth transistor, a VINT input terminal connected to the capacitor, an RD input terminal connected to the fifth transistor, and an ELVDD input terminal, and the output terminal Output is connected to the sixth transistor, wherein the ELVDD input terminal is used to input a DC signal to provide power for the circuit operation; The second transistor, the third transistor, the seventh transistor and the input terminals Sn, Vstimulus and VINT constitute a reset unit of the circuit, which is used to clear or reset the signals of each node in the circuit; The first transistor, the second transistor, the third transistor, the fourth transistor, the capacitor and the input terminals Sn-1, Sn, and Vstimulus constitute a signal receiving and memory unit of the circuit, which is used to realize signal conversion and memory; The first transistor, the fifth transistor, the sixth transistor, the input terminal RD, ELVDD, and the output terminal Output constitute a signal reading and transmitting unit of the circuit, which is used to realize signal conversion and transmission; The second transistor, the third transistor and the seventh transistor in the reset unit are all electrically connected to the gate through a wire, and the input terminal Sn inputs a control signal to turn on the second transistor, the third transistor and the seventh transistor. At this time, the VINT input terminal receives a signal and writes it into each node inside the circuit to achieve the potential reset of the transistor gate and the capacitor; The input end of the first transistor in the signal receiving and memory unit is connected to the output end of the second transistor, the gates of the second transistor and the third transistor are electrically connected through a wire, the input end of the third transistor is connected to the capacitor, the output end of the fourth transistor is connected to the capacitor, the input end Sn-1 inputs a control signal to turn on the fourth transistor, at this time Vstimulus inputs an excitation signal, the signal voltage is recorded at both ends of the capacitor, and the conversion from the current signal to the voltage signal is realized for signal reception, and then the second transistor, the third transistor and the fourth transistor are turned off for signal latch memory; The output end of the first transistor in the signal reading and transmission unit is connected to the input end of the sixth transistor, the sixth transistor is connected to the output end Output, the fifth transistor and the sixth transistor are electrically connected to the gate through a wire, and the input signal at the input end RD makes the fifth transistor and the sixth transistor turned on. At this time, the capacitor controls the first transistor to convert the recorded voltage signal into a current signal, which is used to realize the output and transmission of the signal from the Output port.

2. The memory neural circuit according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all configured as CMOS transistors.

3. The memory neural circuit according to claim 2, characterized in that: The Vstimulus input terminal is connected in series with a diode for inputting a pressure signal, a chemical stimulation signal or a light stimulation signal; Or a sensor is connected in series to sense external stimulation signals and convert the signals into electrical stimulation signals before inputting them into the circuit.

4. A neural circuit array, comprising a plurality of memory neural circuits according to any one of claims 1 to 3, characterized in that: A plurality of memory neural circuits are assigned to logical rows and logical columns of the neural circuit array, and: The Vstimulus input terminal of the memory neural circuit in each column is connected to the Output output terminal of the previous memory neural circuit, and is used to receive a stimulus signal from the corresponding previous memory neural circuit in use; The Sn-1 input terminal of the previous memory neural circuit in each row is connected to the Sn-1 input terminal of the next memory neural circuit, so as to transmit the action signal from the previous memory neural circuit to the next during use.

5. A memory neural network, characterized in that: Comprising a neural circuit array as claimed in claim 4.

Images