Semiconductor memory device capable of controlling row hammering and driving method thereof

Abstract

The invention relates to a semiconductor memory device capable of controlling row hammering and a driving method thereof. A semiconductor memory device may include a memory cell array and a row hammer control block. The memory cell array may include a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of memory cells arranged between the word lines and the bit lines. The row hammer control block may control a voltage of a victim word line adjacent to the selected word line among the word lines. The hammer control block may include a victim word line determination circuit and a victim voltage output circuit. The victim word line determination circuit may receive address information of the selected word line as address information of the attacker word line to determine at least one of the word lines adjacent to the attacker word line as a victim word line. The victim voltage output circuit may temporarily output a victim voltage different from a turn-off voltage during a drop section of the attacker word line, which may be applied to unselected word lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0091152, filed on Jul. 13, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor memory device and a method of driving the semiconductor memory device. More particularly, various embodiments of the present disclosure relate to a semiconductor memory device capable of controlling row hammering and a method of driving the semiconductor memory device. Background Art

[0004] Increasing the integration level (also referred to as integration density) of semiconductor memory devices results in a reduction in the pitch between word lines. The level of integration or density refers to how densely various components such as transistors, logic gates, and memory cells are integrated onto a semiconductor substrate. The higher the level of integration, the smaller the distance between conductive lines such as word lines becomes. Therefore, when adjacent word lines are selected, a phenomenon known as row hammer (or row hammering) can be observed, which can change the data characteristics of memory cells connected to adjacent word lines.

[0005] Row hammer presents safety and reliability issues, and therefore, new and improved techniques are needed to address row hammer for more advanced, more highly integrated semiconductor memory devices. Summary of the invention

[0006] Various embodiments of the present disclosure provide a semiconductor memory device having improved data reliability, and also provide a method of driving the semiconductor memory device.

[0007] According to an embodiment of the present disclosure, a semiconductor memory device is provided, which includes a memory cell array and a row hammer control block. The memory cell array may include a plurality of word lines, a plurality of bit lines intersecting the word lines, and a plurality of memory cells arranged at intersections between the word lines and the bit lines. The row hammer control block may control the voltage of a victim word line adjacent to a selected word line among the word lines. The row hammer control block may include a victim word line determination circuit and a victim voltage output circuit. The victim word line determination circuit may receive address information of a selected word line as address information of an aggressor word line to determine at least one word line adjacent to the aggressor word line among the word lines as a victim word line. The victim voltage output circuit may temporarily output a victim voltage different from a turn-off voltage during a falling section of the aggressor word line, and the turn-off voltage may be applied to unselected word lines.

[0008] According to an embodiment of the present disclosure, a method for driving a semiconductor memory device is provided, the method comprising applying a driving voltage to a selected word line among a plurality of word lines and applying a shutdown voltage to the remaining unselected word lines. The method further comprises applying a victim voltage different from the shutdown voltage to the word line closest to the selected word line during a falling section, where the voltage of the selected word line is changed from the driving voltage to the shutdown voltage.

[0009] According to an embodiment of the present disclosure, a method of driving a semiconductor memory device may include setting a victim word line according to address information of the aggressor word line, and applying a victim voltage different from an off voltage to the victim word line during a falling section of the aggressor word line.

[0010] According to an embodiment of the present disclosure, there is provided a semiconductor memory device including an active region, a first gate and a second gate, a drain, and a first source and a second source.

[0011] The first gate and the second gate may be arranged on the active region. The drain may be formed in the active region between the first gate and the second gate. The drain may be electrically connected to an unselected bit line. The first source may be formed in the active region outside the first gate. The first source may be electrically connected to the first storage capacitor. The second source may be formed in the active region outside the second gate. The second source may be electrically connected to the second storage capacitor. The first gate may be connected to a selected word line. The second gate may be connected to an unselected word line.

[0012] When the selected word line is disabled, the second gate receiving the off voltage may temporarily receive a victim voltage different from the off voltage.

[0013] According to an embodiment of the present disclosure, a victim voltage may be temporarily applied to a victim word line during a falling section of a selected word line (i.e., a falling section of an aggressor word line), and the victim voltage may be different from a turn-off voltage. Therefore, negative charges trapped in a portion of the selected word line that may serve as a transfer gate may not be moved to adjacent memory cells to prevent row hammering, thereby improving data reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be better understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a simplified block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0016] Figure 2is a plan schematic view illustrating a memory bank according to an embodiment of the present disclosure;

[0017] Figure 3 yes Figure 2 an enlarged plan schematic view of a portion "A" in FIG.

[0018] Figure 4 It is a graphic Figure 1 A simplified block diagram of the hammer control block in ;

[0019] Figure 5 is a timing diagram illustrating voltages applied to an aggressor word line, a victim word line, and unselected word lines according to an embodiment of the present disclosure;

[0020] Figure 6 is a flowchart of a method of controlling row hammering in a semiconductor memory device according to an embodiment of the present disclosure; and

[0021] Figure 7 is along Figure 3 A cross-sectional view taken along line VII-VII' in FIG. 1 is used to describe the operation for mitigating row hammering according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments and intermediate structures. Therefore, variations in the configurations and shapes of the illustrations, for example due to manufacturing techniques and / or tolerances, are expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes illustrated herein, but may include deviations in configurations and shapes that do not depart from the technical concept and scope of the present disclosure as defined in the appended claims.

[0023] Embodiments of the present invention are described herein with reference to cross-sections and / or plan views of idealized embodiments of the present invention. However, the embodiments of the present invention should not be construed as limiting the inventive concept. Although several embodiments of the present invention will be shown and described, those of ordinary skill in the art will recognize that changes may be made in these embodiments without departing from the principles and technical concepts of the present invention.

[0024] As used herein, a "memory device" refers to a microelectronic device that exhibits memory functionality, but is not necessarily limited to memory functionality. In other words, and by way of non-limiting example only, the term "memory device" includes not only conventional memory devices (e.g., conventional volatile memory; conventional non-volatile memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0025] As used herein, the term "configuration" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates operation of one or more of the structures and devices in a predetermined manner.

[0026] As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" refer to a principal plane of a structure, and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to a principal plane of a structure, and a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the figures, a "horizontal" or "transverse" direction may be perpendicular to an indicated "Z" axis, and may be parallel to an indicated "X" axis and / or parallel to an indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to an indicated "Z" axis, may be perpendicular to an indicated "X" axis, and may be perpendicular to an indicated "Y" axis.

[0027] As used herein, features (e.g., areas, structures, devices) described as being "adjacent" to each other mean and include features of the disclosed (one or more) identities that are positioned closest to each other (e.g., closest). Additional features (e.g., additional areas, additional structures, additional devices) that do not match the disclosed (one or more) identities of the "adjacent" features may be disposed between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other, such that no other features intervene between the "adjacent" features; or, the "adjacent" features may be positioned indirectly adjacent to each other, such that at least one feature having an identity different from the identity associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other mean and include features of the disclosed (one or more) identities that are positioned closest to each other (e.g., closest to each other). Furthermore, features described as being "horizontally adjacent" to each other mean and include features of the disclosed (one or more) identities that are positioned closest to each other (e.g., closest to each other).

[0028] As used herein, for ease of description, spatial relative terms such as "below", "below", "lower", "bottom", "above", "up", "top", "front", "back", "left", "right", etc. may be used to describe the relationship between an element or feature and another (one or more) element or (one or more) feature, as shown in the figure. Unless otherwise specified, spatial relative terms are intended to cover different orientations of materials other than the orientation depicted in the figure. For example, if the material in the figure is inverted, then the element described as being "below" or "below" or "below" or "on the bottom of" other elements or features will be oriented to be "above" or "on the top of" the other elements or features. Therefore, depending on the context in which the term "below" is used, the term can cover both the orientation above and below, which will be apparent to those of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein are interpreted accordingly.

[0029] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0030] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] As used herein, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Like reference numerals refer to like elements throughout.

[0032] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, property, or condition is met with some degree of variation, such as within an acceptable tolerance. By way of example, depending on the specific parameter, property, or condition that is substantially met, the parameter, property, or condition may be met by at least 90.0%, met by at least 95.0%, met by at least 99.0%, met by at least 99.9%, or even met by 100.0%.

[0033] The semiconductor memory device of various embodiments may include a plurality of memory cells. The memory cell may store at least one bit of information. The memory cell may be defined by word lines and bit lines that intersect each other. The word lines, bit lines, and memory cells may form a memory bank. The semiconductor memory device may include at least one memory bank. In addition, the semiconductor memory device may receive at least one command signal for indicating the operation of the semiconductor memory device. For example, the semiconductor memory device may refresh at least one word line of at least one memory bank based on a refresh command.

[0034] As is well known, information stored in a semiconductor memory device (particularly a dynamic random access memory (DRAM)) may decay as time passes. In order to preserve information in a memory cell, the memory cell may perform a refresh operation in a row unit (e.g., in a word line unit). During the refresh operation, a voltage for preserving data information may be regained in the word line.

[0035] The selected word line or the aggressor word line may cause a change in data information in memory cells connected to other physically adjacent word lines (hereinafter, referred to as victim word lines).

[0036] The semiconductor memory device of various embodiments can identify an aggressor word line and a victim word line. The semiconductor memory device can control the voltage level of the victim word line during a specific section. Therefore, the data of the memory cell connected to the victim word line can be prevented from being changed.

[0037] Figure 1 is a simplified block diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0038] refer to Figure 1 , the semiconductor memory device 100 may include a memory cell array 112 and a peripheral circuit Peri.

[0039] In an example embodiment, the memory cell array 112 and the peripheral circuit Peri may be arranged horizontally on one wafer. Alternatively, the memory cell array 112 and the peripheral circuit Peri may be arranged vertically on one wafer. For example, the memory cell array 112 may be arranged above the peripheral circuit Peri. Alternatively, the memory cell array 112 and the peripheral circuit Peri may be integrated in different wafers. The different wafers may then be combined with each other.

[0040] The memory cell array 112 may include a plurality of memory banks MB1-MBn. Each of the memory banks MB1-MBn may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections between the word lines WL and the bit lines BL. In some embodiments, the memory banks MB1-MBn may be integrated in one wafer or a plurality of wafers.

[0041] For example, each of the memory cells MC may include a switching transistor T and a storage capacitor CAP. When a word line and a bit line connected to the switching transistor T are selected, the switching transistor T may be enabled. Then, data may be stored in the storage capacitor CAP connected to the switching transistor T or data may be read from the storage capacitor CAP connected to the switching transistor T.

[0042] The peripheral circuit Peri may include an address decoding block 104 , a row control block 108 , a column control block 110 , a refresh control block 116 , and a row hammer control block 130 (also referred to as a row hammer control block).

[0043] The address decoding block 104 may receive an address ADD provided from an external device to generate a bank address BADD, a row address XADD, and a column address YADD.

[0044] The row control block 108 may receive a bank address BADD and a row address XADD to generate a row selection signal RS. For example, the row selection signal RS may include at least one signal. The row selection signal RS may include address information of a selected word line and row enable information for determining an enable time of the selected word line. A word line driver 121 that may be provided to each of the memory banks MB1 to MBn may select a selected memory bank, or at least one word line WL of a portion of a selected memory bank, in response to the row selection signal RS. The portion of the selected memory bank may be a sub-bank or a portion of a sub-bank.

[0045] The column control block 110 may receive the bank address BADD and the column address YADD, and may use these to select a bit line BL of a selected memory bank among the memory banks MB1 to MBn.

[0046] In example embodiments, the row control block 108 and the column control block 110 may correspond to each of the memory banks MB1 ˜MBn.

[0047] The memory cell array 112 may further include a sense amplifier 117 connected to the bit lines BL and / BL. The sense amplifier 117 may detect and amplify data read in the form of a voltage through the bit lines BL or / BL. The memory cell array 112 may further include a read / write driver 120 electrically connected to the sense amplifier 117. The read / write driver 120 may output the data amplified by the sense amplifier 117 as read data, or provide the sense amplifier 117 with write data provided from an external device.

[0048] The semiconductor memory device 100 may further include a refresh control block 116. The refresh control block 116 may generate a refresh address RXADD for refreshing at least one word line WL according to a refresh command. The refresh control block 116 may provide the refresh address RXADD to the row control block 108.

[0049] The refresh operation can prevent the loss of data due to charge leakage. For example, the refresh operation can be performed automatically. For example, the memory storage body can refresh the selected word line or the selected word line group including the word line in response to the automatic refresh operation. Then, the memory storage body can automatically refresh the next word line or the next word line group. The refresh control block 116 can cyclically refresh all word lines WL of the memory storage body MB1~MBn within a predetermined time selected to prevent data loss. For example, a typical refresh operation may include: 1) selecting a specific row of memory cells, 2) reading the data stored in each memory cell in the selected row, 3) after reading the data, refreshing the data, that is, rewriting the same data back to the memory cell, 4) repeating the above steps for the next row of memory cells until all memory cells have been refreshed. The refresh process is performed periodically to ensure that no data is lost.

[0050] The row hammer control block 130 may receive a bank address BADD and a row address XADD to determine a victim word line based on an aggressor word line. The row hammer control block 130 may output a victim voltage Vvic to the victim word line during a specific time. In some embodiments, the victim voltage Vvic may be output to the victim word line. Alternatively, the row hammer control block 130 may output an address or address information for indicating a victim word line to the memory cell array 112. The word line driver 121 of the memory cell array 112 may generate a victim voltage Vvic in response to an address for indicating a victim word line.

[0051] Hereinafter, the hammer control block 130 may be described in detail.

[0052] Figure 2 is a plan schematic view illustrating a memory bank according to some embodiments of the present disclosure.

[0053] refer to Figure 2 , the memory bank MB may include a plurality of word lines WLn-2 ˜WLn+2, a plurality of bit lines BL1 ˜BL4 and a plurality of active areas ACT.

[0054] The word lines WLn-2WLn+2 may extend in parallel with each other in a first direction D1. The bit lines BL1BL4 may extend in parallel with each other in a second direction D2, and the second direction D2 may be substantially perpendicular to the first direction D1.

[0055] Active areas ACT may be defined at intersections between word lines WLn-2 ˜ WLn+2 and bit lines BL1 ˜ BL4 .

[0056] Each of the active regions ACT may have a major axis b1 and a minor axis b2. The major axis b1 and the minor axis b2 of the active region ACT may be inclined with respect to the word lines WLn-2WLn+2 and the bit lines BL1BL4.

[0057] For example, one active area ACT may overlap two adjacent word lines. One active area ACT may electrically contact one bit line. Therefore, one active area ACT may include one bit line contact BLC and two storage node contacts SNC1 and SNC2. As a result, two memory cells MC1 and MC2 may be integrated in one active area ACT.

[0058] In some embodiments, in order to integrate more active areas ACT in a limited memory cell array, the active areas ACT may be arranged in a staggered shape.The active areas ACT may be defined on a semiconductor substrate or a structure on a semiconductor substrate by an isolation area ISO.

[0059] Figure 3 yes Figure 2 An enlarged plan schematic view of portion “A” is shown in FIG.

[0060] refer to Figure 3 , when the nth word line WLn and the first bit line BL1 are selected, a memory operation may be performed on the second memory cells MC2 in the first active region ACT10.

[0061] The selected nth word line WLn may receive a logic high level of a driving voltage during an enable section. The remaining unselected word lines may receive a logic low level of a turn-off voltage. The driving voltage and the turn-off voltage may be provided from a voltage generating circuit in the word line driver 121 or the peripheral circuit Peri.

[0062] The first portion G1 of the nth word line WLn overlapping the first active region ACT10 may be a main gate facilitating a memory operation of the second memory cell MC2 in the first memory region ACT10 .

[0063] The second portion G2 and the third portion G3 of the nth word line WLn, which overlap the second active area ACT20 and the third active area ACT30, respectively, may be transmission gates that do not contribute to the actual memory operation. That is, because the second active area ACT20 and the third active area ACT30 may be connected to the unselected bit lines BL2 and BL3, the second portion G2 and the third portion G3 may not turn on the switching transistor of the corresponding memory cell. The second portion G2 and the third portion G3 receive a high driving voltage, but correspond to the gate of the unselected memory cell, i.e., the transmission gate. Therefore, a parasitic electric field may be generated between the transmission gate and the storage capacitor adjacent to the transmission gate, and then the charge stored in the storage capacitor may leak.

[0064] In some embodiments, the main gate and the transfer gate can be defined as a portion of a selected word line. As mentioned above, the main gate can correspond to a portion of a word line that is on a selected memory cell or on an active area in which a corresponding memory cell can be integrated. The transfer gate can correspond to a portion of a word line that is on an unselected memory cell or on an active area in which a corresponding memory cell can be integrated.

[0065] In particular, since a logic high level of a driving voltage may be applied to the second portion G2 of the nth word line WLn, negative charges of a capacitor connected to the first storage node contact SNC1 in the second active region ACT20 may be captured in an interface between the capacitor and the second portion G2 due to Coulomb's law.

[0066] When the nth word line WLn is disabled so that an off voltage may be applied to the nth word line WLn, negative charges trapped in the second portion G2 may not easily return to the first storage node contact SNC1. The negative charges may float or move toward adjacent memory cells.

[0067] Therefore, data information in the first memory cell MC1 of the second active area ACT20 may decay. The floating negative charges may serve as a generation source of gate induced drain leakage (GIDL). As mentioned above, this may be row hammering.

[0068] Furthermore, in order to reduce an off current, when a pumping voltage Vpp or Vppw is used as a driving voltage and a negative voltage Vbb or Vbbw is used as an off voltage, a row hammer may be significantly increased.

[0069] In some embodiments, to prevent or mitigate the row hammering phenomenon, a selected word line may be set as an aggressor word line. At least one word line physically adjacent to the aggressor word line may be set as a victim word line. The voltage applied to the victim word line may then be controlled during a specific time to prevent or mitigate the row hammering.

[0070] Figure 4 It is a graphic Figure 1 Simplified block diagram of the hammer control block in .

[0071] refer to Figure 1 and Figure 4 , the row hammer control block 130 may include an aggressor word line determination circuit 132 , a victim word line determination circuit 134 , and a victim voltage output circuit 136 .

[0072] The attacker word line determination circuit 132 may receive the bank address BADD and the row address XADD to generate an attacker selection signal RS1 for selecting an attacker word line. In some embodiments, the attacker word line may be a selected word line of the memory cell array 112 .

[0073] The victim word line determination circuit 134 may receive the aggressor selection signal RS1 to determine at least one of the selected word line and the adjacent word line as a victim word line. The victim word line determination circuit 134 may generate a victim word line selection signal RS2 for selecting the victim word line.

[0074] The victim voltage output circuit 136 may receive the victim word line selection signal RS2 and enable information EN of the row selection signal to output the victim voltage Vvic to the victim word line during a falling edge section of the aggressor word line.

[0075] The victim voltage output circuit 136 may include a delay circuit 138 to output the victim voltage Vvic starting from the falling edge of the aggressor word line during a setup delay time of the delay circuit 138. After the delay time, the victim voltage output circuit 136 may be disabled and the victim word line may receive the off voltage.

[0076] In some embodiments, the victim voltage Vvic may have a voltage level different from that of the off voltage. For example, the victim voltage Vvic may include a negative voltage Vbb or Vbbw different from the off voltage, but is not limited thereto.

[0077] Alternatively, the row hammer control block 130 may not include the attacker word line determination circuit 132. In this case, the row hammer control block 130 may directly receive the word line selection signal RS output from the row control block 108 as the attacker selection signal RS1.

[0078] In some embodiments, the row hammer control block 130 may be separate from the row control block 108 and the refresh control block 116. Alternatively, the row hammer control block 130 may be part of the row control block 108 or part of the refresh control block 116.

[0079] Furthermore, the row hammer control block 130 may be provided to the peripheral circuit Peri. Alternatively, the row hammer control block 130 may be provided in the memory cell array 112.

[0080] Figure 5 is a timing diagram illustrating voltages applied to an aggressor word line, a victim word line, and an unselected word line according to an embodiment of the present disclosure, and Figure 6 is a flowchart of a method of controlling row hammering in a semiconductor memory device according to an embodiment of the present disclosure.

[0081] refer to Figure 5 and Figure 6 , when the nth word line WLn is selected, in operation S10, the row hammer control block 130 may determine the nth word line WLn as the aggressor word line AWL. The row hammer control block 130 may determine at least one neighboring word line of the neighboring word lines WLn±1 to WLn±a (a is a natural number) of the aggressor word line AWL as the victim word line VWL. The neighboring word lines WLn±1 to WLn±a may be options arbitrarily set by the designer based on the influence of the row hammer through the test.

[0082] In operation S20, a driving voltage Von may be applied to the selected nth word line WLn, ie, the attacker word line AWL. A turn-off voltage Voff may be applied to the unselected word lines WLn±1 to WLn±a. The driving voltage may include a logic high voltage, such as a pumping voltage Vpp or Vppw. The turn-off voltage Voff may include a logic low voltage, such as a ground voltage.

[0083] The process in operation S20 may be substantially the same as the process for driving a normal word line. Therefore, the process in operation S20 may be performed by the row control block 108 and the word line driver 121.

[0084] In operation S30, when the nth word line WLn as the aggressor word line AWL is disabled, the victim voltage Vvic may be applied to the victim word line VWL during the falling section FD of the aggressor word line AWL (see Figure 7 ).

[0085] The victim voltage Vvic may have a voltage level different from that of the off voltage Voff. In some embodiments, when the off voltage Voff includes a ground voltage (eg, approximately 0V), the victim voltage Vvic may include a negative voltage Vbb or Vbbw in a range of -0.1V to approximately -0.03V.

[0086] Furthermore, the falling section may be controlled by the delay value of the delay circuit 138 in the victim voltage output circuit 136. The delay value may be set arbitrarily by considering the level of row hammer in the memory device. The process in operation S30 may be performed by the row hammer control block 130.

[0087] In operation S40 , when the nth word line WLn is completely disabled, the off voltage Voff may be applied to the victim word line VWL.

[0088] refer to Figure 7 , operations for mitigating or preventing row hammering depending on the type of voltage application to a victim word line may be described.

[0089] Figure 7 is along Figure 3 A cross-sectional view taken along line VII-VII' in FIG. 1 is used to describe the operation for alleviating or preventing row hammering according to an embodiment of the present disclosure. Figure 7 An active region ACT20 including a transfer gate may be shown (eg, Figure 3 shown).

[0090] refer to Figure 3 and Figure 7 , the active region ACT20 may be defined on the semiconductor substrate or on a structure on the semiconductor substrate by the isolation region ISO.

[0091] The selected aggressor word line AWL and victim word line VWL may be disposed on the active region ACT20. The aggressor word line AWL may correspond to Figure 3 The second portion G2 of the nth word line WLn in FIG. The victim word line VWL may correspond to the n+1th word line WLn+1. Figure 7 The active area in Figure 3 When the third active area ACT30 is located in the vicinity, the victim word line VWL may correspond to the n-1th word line WLn-1.

[0092] The aggressor word line AWL and the victim word line VWL may have a buried gate structure, but are not limited thereto. A gate insulating layer GOX may be interposed between the aggressor word line AWL and the active region ACT20 and between the victim word line VWL and the active region ACT20.

[0093] N-type impurities n+ may be implanted into the active region ACT20 on both sides of the aggressor word line AWL and the victim word line VWL to form a drain D and a source S. The drain D may be located in the active region ACT20 between the aggressor word line AWL and the victim word line VWL. The source S may be located in the active region ACT20 outside the aggressor word line AWL and the victim word line VWL.

[0094] The drain D may be connected to the unselected bit line BL2 through the bit line contact BLC. The source S adjacent to the aggressor word line AWL may be connected to the first storage capacitor CAP1 through the first storage node contact SNC1. The source S adjacent to the victim word line VWL may be connected to the second storage capacitor CAP2 through the second storage node contact SNC2.

[0095] For example, when the driving voltage Von is applied to the nth word line WLn, negative charges of the first storage capacitor CAP1 may be trapped on the surface of the aggressor word line AWL by the influence of the electric field generated from the driving voltage Von.

[0096] When the aggressor word line AWL is disabled to have an off voltage Voff of a logic low level, negative charges trapped around the aggressor word line AWL may be protected from the influence of the electric field.

[0097] During the falling section FD of the attacker word line AWL (eg Figure 7 As shown in FIG. 1 , a victim voltage Vvic different from the off voltage Voff may be temporarily applied to the victim word line VWL. Therefore, the voltage level of the victim word line VWL may be temporarily lower than the voltage level of the aggressor word line AWL. As a result, negative charges may be distributed in the victim word line VWL through the victim voltage Vvic.

[0098] Therefore, a repulsive force may be generated between negative charges trapped in the victim word line VWL and negative charges concentrated on the aggressor word line AWL, so that negative charges decaying from the first storage capacitor CAP1 may return to the first storage capacitor and not move toward the victim word line VWL, thereby alleviating or preventing row hammering.

[0099] According to an embodiment, a victim voltage lower than the off voltage may be temporarily applied to the victim word line during the falling section of the aggressor word line. Thus, negative charge trapped in the portion of the selected word line that serves as the transfer gate may not be moved to adjacent memory cells to prevent or mitigate row hammering, thereby improving data reliability.

[0100] The above embodiments of the present disclosure are intended to illustrate rather than limit the present disclosure. Various alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any particular type of semiconductor device. In view of the present disclosure, other additions, deletions, or modifications are obvious and are intended to fall within the scope of the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor memory device, comprising: a memory cell array including a plurality of word lines and a plurality of bit lines crossing each other, and including a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines; as well as a row hammer control block configured to control a voltage of a victim word line adjacent to a selected word line among the plurality of word lines, The hammer control block includes: a victim word line determination circuit, which receives the address information of the selected word line as the address information of the aggressor word line, so as to determine at least one word line adjacent to the aggressor word line among the plurality of word lines as the victim word line; as well as A victim voltage output circuit is configured to temporarily output a victim voltage to the victim word line during a falling section of the aggressor word line, the victim voltage being different from an off voltage applied to unselected word lines.

2. The semiconductor memory device according to claim 1, wherein the row hammer control block further comprises an aggressor word line determination circuit which receives the address information of the selected word line to determine the selected word line as the aggressor word line. 3 . The semiconductor memory device according to claim 1 , wherein the off voltage comprises a ground voltage, and the victim voltage has a voltage level different from a voltage level of the off voltage. 4 . The semiconductor memory device according to claim 1 , wherein the victim voltage output circuit outputs the victim voltage during the falling section in response to a row enable signal for determining an enable section of the selected word line.

5. The semiconductor memory device according to claim 1, wherein the attacker word line includes an nth word line among the plurality of word lines, the victim word line includes at least one word line from an n±1th word line to an n±ath word line among the plurality of word lines, wherein a is a natural number, and the unselected word lines include the remaining word lines except the attacker word line and the victim word line.

6. A semiconductor memory device according to claim 1, wherein the memory cell array includes a plurality of memory banks, and the attacker word line and the victim word line are located in at least one memory bank among the plurality of memory banks, or in a portion of a selected memory bank among the plurality of memory banks.

7. A method for driving a semiconductor memory device, the method comprising: applying a driving voltage to a selected word line among a plurality of word lines; applying an off voltage to the remaining unselected word lines; as well as A victim voltage different from the turn-off voltage is applied to a word line adjacent to the selected word line among the unselected word lines during a falling section where a voltage of the selected word line is transitioned from the driving voltage to the turn-off voltage. 8 . The method of claim 7 , wherein the driving voltage comprises a voltage having a logic high level, the off voltage comprises a ground voltage, and the victim voltage has a voltage level lower than that of the off voltage.

9. The method according to claim 7, wherein the selected word line includes an nth word line among the plurality of word lines, and the word line adjacent to the selected word line includes at least one word line from an n±1th word line to an n±ath word line among the plurality of word lines, wherein a is a natural number. 10 . The method according to claim 7 , wherein a falling edge of the falling section from when the driving voltage is converted to the turn-off voltage is delayed.

11. A method for driving a semiconductor memory device, the method comprising: Setting a victim word line according to address information of the aggressor word line; as well as During a falling section of the aggressor word line, a victim voltage different from an off voltage is applied to the victim word line. 12 . The method according to claim 11 , wherein the address information of the attacker word line includes address information of a selected word line among word lines. 13 . The method of claim 12 , wherein the victim word line comprises at least one of word lines adjacent to the selected word line.

14. The method according to claim 12, further comprising: applying a driving voltage having a logic high level to the aggressor word line during an enable section of the aggressor word line; as well as The off voltage having a logic low level is applied to unselected word lines among the word lines.

15. A semiconductor memory device comprising: Active area; a first gate and a second gate, wherein the first gate and the second gate are arranged on the active area; a drain electrode disposed in the active region between the first gate electrode and the second gate electrode, the drain electrode being electrically connected to an unselected bit line; a first source electrode disposed in the active region outside the first gate electrode, the first source electrode being electrically connected to a first storage capacitor; as well as a second source electrode arranged in the active region outside the second gate electrode, the second source electrode being electrically connected to a second storage capacitor, wherein the first gate is connected to a selected word line, and the second gate is connected to an unselected word line, and Wherein, in the case where the second gate receives a turn-off voltage, when the selected word line is disabled, the second gate temporarily receives a victim voltage different from the turn-off voltage.

16. The semiconductor memory device according to claim 15, wherein when the selected word line is enabled, the first gate receives a driving voltage having a logic high level, and when the selected word line is disabled, the first gate is transitioned to the turn-off voltage having a logic low level. 17 . The semiconductor memory device according to claim 15 , wherein the victim voltage has a voltage level lower than a voltage level of the off voltage.

18. A method for driving a semiconductor memory device, the method comprising: selecting a word line among a plurality of word lines of a memory bank; applying a driving voltage to a selected word line; applying a turn-off voltage to remaining unselected word lines of the memory bank; as well as When the voltage of the selected word line drops from the driving voltage to the turn-off voltage, a victim voltage different from the turn-off voltage is applied to a word line disposed adjacent to the selected word line among the unselected word lines.

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