Non-volatile memory with auxiliary select gate line driver

Abstract

The invention relates to a nonvolatile memory with an auxiliary selection gate line driver. An array structure in the nonvolatile memory is composed of 2T2C memory cells. In addition, the memory cells in the array structure are further connected to the corresponding auxiliary select gate lines (auxiliary select gate lines). In addition, the auxiliary selection gate line driver can output a specific driving voltage to the auxiliary selection gate line, so that the programming efficiency, the erasing efficiency and the reading efficiency of the nonvolatile memory are improved.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory, and more particularly to a non-volatile memory with an auxiliary select gate line driver. Background Art

[0002] As is known to all, non-volatile memory can continue to store data after power is lost, so non-volatile memory has been widely used in electronic products. Furthermore, non-volatile memory includes a plurality of memory cells arranged in an array structure, and each memory cell includes a floating gate transistor.

[0003] Please refer to Figure 1A and Figure 1B , which is a schematic diagram of bias voltage for programming a memory cell of a conventional non-volatile memory. Figure 1C and Figure 1D , which is a schematic diagram of the bias voltage of a memory cell of a conventional non-volatile memory for performing a read operation. Figure 1E , which is a schematic diagram of bias voltage of a memory cell of a conventional non-volatile memory during an erase operation.

[0004] like Figure 1A As shown, the memory cell includes: a selection transistor M S , floating gate transistor M F , capacitor C1. That is, the memory cell is a memory cell with two transistors and one capacitor (2T1C memory cell). Furthermore, the memory cell is a multi-time programmable memory cell, referred to as an MTP memory cell.

[0005] Select transistor M S With floating gate transistor M F It is a p-type transistor formed in the N-type well region NW. The selection transistor M S The source terminal of the transistor M is connected to the source line (SL), and the transistor M is selected. S The gate terminal of the floating gate transistor M is connected to a word line (WL). F The source terminal is connected to the selection transistor M S The drain terminal of the floating gate transistor M FThe drain terminal of the capacitor C1 is connected to the bit line (BL). The capacitor C1 is composed of an n-type transistor and is formed in the P-type well region PW. The gate terminal of the n-type transistor forms the first terminal of the capacitor C1. The drain terminal and the source terminal of the n-type transistor are connected to each other to form the second terminal of the capacitor C1. The first terminal of the capacitor C1 is connected to the floating gate transistor M F The floating gate 10 of FIG. 1 is connected to an erase line (EL).

[0006] Basically, by providing a proper bias voltage to the memory cell, programming, reading and erasing operations can be performed on the memory cell.

[0007] like Figure 1A As shown, when programming the memory cell, an on voltage (V ON ) to the word line WL, the program voltage (V PP ) to the source line SL, ground voltage (0V) to the bit line BL, and erase line voltage (Erase line voltage, V EL ) to the erase line EL. Furthermore, a programming voltage V PP To the N-type well NW, provide the ground voltage (0V) to the P-type well PW. For example, the turn-on voltage V ON is 0V, programming voltage V PP is 7V, the erase line voltage V EL Between 0V and 3V.

[0008] like Figure 1A As shown, the selection transistor M S When the bit line BL is turned on, a program current (I PGM ). Therefore, in the floating gate transistor M F The channel region of the floating gate transistor M undergoes a channel hot electron injection effect (CHE injection effect for short), and electrons are injected into the floating gate transistor M. F The floating gate 10 of the memory cell is changed to a program state.

[0009] Compared to Figure 1A ,exist Figure 1B During the programming of the memory cell, an off voltage (V OFF ) to the word line WL so that the select transistor M SWhen the floating gate transistor M is turned off, no programming current is generated between the source line SL and the bit line BL. F No CHE injection effect occurs in the channel region, and electrons are not injected into the floating gate transistor M. F The floating gate 10 is configured such that the memory cell is not programmed but remains in an original state, such as an erase state.

[0010] like Figure 1C and Figure 1D As shown, when the memory cell is read, a turn-on voltage V is provided. ON To the word line WL, read voltage (read voltage, V READ ) to the source line SL, the ground voltage (0V) to the bit line BL, and the ground voltage (0V) to the erase line EL. Furthermore, a read voltage V READ To the N-type well NW, provide the ground voltage (0V) to the P-type well PW. For example, the read voltage V READ is 2V.

[0011] Basically, in the read operation, according to the floating gate transistor M F Whether there are electrons stored in the floating gate 10 will generate different read currents (read current, I READ ).like Figure 1C As shown, the floating gate transistor M F The floating gate 10 stores electrons. When the transistor M is selected S When turned on, a large read current I is generated between the source line SL and the bit line BL READ , can be determined as a programming state by a sensing circuit (not shown). Figure 1D As shown, the floating gate transistor M F The floating gate 10 does not store electrons. S When turned on, a read current I of almost zero is generated between the source line SL and the bit line BL READ , which can be determined as an erased state by a sensing circuit (not shown).

[0012] like Figure 1E As shown, when the memory cell is erased, a ground voltage (0V) is provided to the word line WL, a ground voltage (0V) is provided to the source line SL, and a ground voltage (0V) is provided to the bit line BL. EE ) to the erase line EL. Furthermore, a ground voltage (0V) is provided to the N-type well region NW, and a ground voltage (0V) is provided to the P-type well region PW. For example, the erase voltage V EE is 12V.

[0013] like Figure 1E As shown, since the erase line EL receives the erase voltage V EE , the capacitor C1 undergoes FN tunneling effect (Fowler-Nordheim tunneling effect, referred to as FN tunneling effect), and the electrons pass through the floating gate transistor M F The floating gate 10 is ejected to the erase line EL via the capacitor C1, so that the memory cell is changed to an erase state. Summary of the invention

[0014] The present invention relates to a non-volatile memory, comprising: an array structure, the array structure is connected to a first word line, a second word line, a source line, an erase line, a first auxiliary selection gate line, a second auxiliary selection gate line and a bit line; wherein the array structure comprises a first memory cell and a second memory cell; the first memory cell is connected to the first word line, the first auxiliary selection gate line, the erase line, the source line and the first bit line; the second memory cell is connected to the second word line, the second auxiliary selection gate line, the erase line, the source line and the first bit line a word line decoder generating a decoding signal; a word line driver receiving the decoding signal and connected to the first word line and the second word line, wherein the word line driver operates one of the first word line and the second word line according to the decoding signal; an auxiliary selection gate line driver receiving a mode signal and the decoding signal and connected to the first auxiliary selection gate line and the second auxiliary selection gate line; a bit line selector connected to the first bit line; and a sensing circuit, connected to the bit line selector; wherein, in a programming action, the first memory cell is determined to be a selected memory cell and the second memory cell is determined to be a non-selected memory cell; wherein, according to the mode signal, in a first phase of a first programming mode, the auxiliary selection gate line driver does not drive the first auxiliary selection gate line and the second auxiliary selection gate line; in a second phase of the first programming mode, the auxiliary selection gate line driver provides a first driving voltage to the first auxiliary selection gate line, and the auxiliary selection gate line driver does not drive the second auxiliary selection gate line; and the first driving voltage is a positive voltage; wherein, according to the mode signal, in a first phase of a second programming mode, the auxiliary selection gate line driver provides a second driving voltage to the first auxiliary selection gate line and the second auxiliary selection gate line; in a second phase of the second programming mode, the auxiliary selection gate line driver provides the first driving voltage to the first auxiliary selection gate line, and the auxiliary selection gate line driver does not drive the second auxiliary selection gate line; and the second driving voltage is a negative voltage.

[0015] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A and Figure 1B A schematic diagram of bias voltage for programming a memory cell of a known non-volatile memory;

[0017] Figure 1C and Figure 1D A schematic diagram of bias voltage for reading a memory cell of a known non-volatile memory;

[0018] Figure 1E A schematic diagram of bias voltage for erasing a memory cell of a known non-volatile memory;

[0019] Figure 2 An array structure of a non-volatile memory of the present invention;

[0020] Figure 3 The non-volatile memory of the present invention;

[0021] Figure 4 A circuit diagram of an auxiliary selection gate line driver of the present invention;

[0022] Figure 5A A bias table for the array structure in the first programming mode (PGM mode1);

[0023] Figure 5B A schematic diagram of related signals of the auxiliary selection gate line driver in the first programming mode;

[0024] Figure 5C and Figure 5D A schematic diagram of the bias voltage of the driving element in the first phase PH1 of the first programming mode;

[0025] Figure 5E and Fig. 5F A schematic diagram of the bias voltage of the driving element in the second phase PH2 of the first programming mode;

[0026] Fig. 6A A bias table for the array structure in the second programming mode (PGM mode2);

[0027] Figure 6B A schematic diagram of related signals of the auxiliary selection gate line driver in the second programming mode;

[0028] Figure 6C and Fig.6D A schematic diagram of the bias voltage of the driving element in the first phase PH1 of the second programming mode;

[0029] Fig. 6Eand Fig. 6F A schematic diagram of the bias voltage of the driving element in the second phase PH2 of the second programming mode;

[0030] Fig. 7A A bias table of the array structure in the first read mode (READ mode 1);

[0031] Figure 7B A schematic diagram of related signals of the auxiliary selection gate line driver in the first reading mode;

[0032] Figure 7C and Fig.7D is a schematic diagram of the bias voltage of the driving element during the reading action of the first reading mode;

[0033] Fig. 8A A bias table of the array structure in the second read mode (READ mode2);

[0034] Figure 8B A schematic diagram of related signals of the auxiliary selection gate line driver in the second reading mode;

[0035] Figure 8C and Fig.8D is a schematic diagram of the bias voltage of the driving element during the reading action of the second reading mode;

[0036] Fig.9A The bias table of the array structure in the first erasing mode (ERS mode 1);

[0037] Fig. 9B A schematic diagram of related signals of the auxiliary selection gate line driver in the first erasing mode;

[0038] Fig. 9C and Fig.9D is a schematic diagram of bias voltage of a driving element during an erasing action in a first erasing mode;

[0039] Fig. 10A The bias table of the array structure in the second erasing mode (ERS mode2);

[0040] Fig. 10B A schematic diagram of related signals of the auxiliary selection gate line driver in the second erasing mode;

[0041] Fig. 10C and Fig. 10D is a schematic diagram of the bias voltage of the driving element during the erasing action in the second erasing mode;

[0042] Fig.11A The bias table of the array structure in the third erasing mode (ERS mode3);

[0043] Fig. 11BA schematic diagram of related signals of the auxiliary selection gate line driver in the third erasing mode; and

[0044] Fig. 11C and Fig.11D FIG. 4 is a schematic diagram of the bias voltage of the driving element during the erasing action in the third erasing mode.

[0045]

Explanation of symbols

[0046] 10,36: floating gate

[0047] 100: array structure

[0048] 200: Non-volatile memory

[0049] 210: word line decoder

[0050] 220: word line driver

[0051] 230: Auxiliary selection gate line driver

[0052] 250: bit line selector

[0053] 260: Sensing circuit

[0054] 412: Pull-up controller

[0055] 414: Pull-down controller

[0056] 421~42M: driving element DETAILED DESCRIPTION

[0057] The present invention provides a 2T2C memory cell, and a plurality of 2T2C memory cells are used to form an array structure. The memory cells in the array structure are further connected to corresponding auxiliary select gate lines. Furthermore, the non-volatile memory of the present invention also includes an auxiliary select gate line driver, which can output a specific driving voltage to the auxiliary select gate line to improve the programming efficiency, erasing efficiency and reading efficiency of the non-volatile memory.

[0058] Please refer to Figure 2 , which shows the array structure of the non-volatile memory 200 of the present invention. The array structure 100 consists of M×N memory cells c 11 ~c MN where M and N are positive integers. Furthermore, each memory cell c 11 ~c MN The structure is the same as that of the present invention, and the memory cell of the present invention is an MTP memory cell.

[0059] First, the memory cell c in the array structure 100 11 Take the example to introduce the structure and connection relationship of the memory cell of the present invention. Figure 2 As shown, the memory cell c 11 Including: selection transistor M S , floating gate transistor M F , the first capacitor C1 and the second capacitor C2. That is, the memory cell c 11 A memory cell with two transistors and two capacitors (2T2C memory cell).

[0060] Select transistor M S With floating gate transistor M F It is a p-type transistor formed in the N-type well region NW. The selection transistor M S The source terminal of the transistor M is connected to the source line SL. S The gate terminal of the floating gate transistor M is connected to the word line WL1. F The source terminal is connected to the selection transistor M S The drain terminal of the floating gate transistor M F The drain terminal of the first capacitor C1 is connected to the bit line BL1. The first capacitor C1 is composed of an n-type transistor, which is formed in the P-type well region PW. The gate terminal of the n-type transistor forms the first end of the first capacitor C1, and the drain terminal and the source terminal of the n-type transistor are connected to each other to form the second end of the first capacitor C1. The first end of the first capacitor C1 is connected to the floating gate transistor M F The floating gate 36 of the first capacitor C1 is connected to the erase line EL. In addition, the second capacitor C2 can be a plate capacitor, and the first end of the second capacitor C2 is connected to the floating gate transistor M. F The second end of the second capacitor C2 is connected to the auxiliary selection gate line ASG1. Of course, the second capacitor C2 may not be a plate capacitor, but may be formed by a transistor similar to the first capacitor C1. Alternatively, the second capacitor C2 may be formed by connecting multiple different types of capacitors in parallel.

[0061] Basically, the memory cells c in the array structure 100 11 ~c MN When performing a programmed action, the electrons move in a path similar to Figure 1A and Figure 1B The memory cells c in the array structure 100 11 ~c MN When erasing, the electrons move in a path similar to Figure 1E The memory cell c in the array structure 100 11 ~c MNWhen performing a reading action, the judgment method is similar to Figure 1C The memory cells of the 1Dth are not described in detail here.

[0062] The technical feature of the present invention is that the memory cells c in the array structure 100 11 ~c MN Further connected to the corresponding auxiliary selection gate lines ASG1-ASG M When performing programming, erasing and reading operations, a specific driving voltage can be provided to the auxiliary selection gate lines ASG1 to ASG M , so as to improve the programming efficiency, erasing efficiency and reading efficiency of the non-volatile memory 200.

[0063] like Figure 2 As shown, the N memory cells c in the first row of the array structure 100 11 ~c 1N Connected to the same word line WL1 and auxiliary selection gate line ASG1, the N memory cells in the first row c 11 ~c 1N Connected to the corresponding bit lines BL1~BL N Similarly, the N memory cells c in the second row of the array structure 100 21 ~c 2N Connected to the same word line WL2 and auxiliary selection gate line ASG2, the N memory cells in the second row c 21 ~c 2N Connected to the corresponding bit lines BL1~BL N Similarly, the N memory cells c in the Mth row of the array structure 100 M1 ~c MN Connected to the same word line WL M and auxiliary selection gate line ASG M , N memory cells c in row M M1 ~c MN Connected to the corresponding bit lines BL1~BL N In addition, all memory cells c 11 ~c MN Connected to the same source line SL, all memory cells c 11 ~c MN Connected to the same erase line EL.

[0064] Please refer to Figure 3, which is a non-volatile memory of the present invention. The non-volatile memory 200 includes: a word line decoder 210, a word line driver 220, an auxiliary selection gate line driver 230, an array structure 100, a bit line selector 250, and a sensing circuit 260. Basically, the array structure 100 is the same as Figure 2 The array structure 100, its structure and connection relationship are not described in detail here.

[0065] The word line decoder 210 is connected to the word line driver 220 and the auxiliary selection gate line driver 230. The word line driver 220 is connected to the word lines WL1-WL2. M The auxiliary selection gate line driver 230 is connected to the auxiliary selection gate lines ASG1-ASG M The bit line selector 250 is connected to the bit lines BL1 to BL N Furthermore, the sensing circuit 260 is connected to the bit line selector 250, and the sensing circuit 260 can generate output data D OUT .

[0066] Basically, the memory cells c in the array structure 100 11 ~c MN For MTP memory cells, the nonvolatile memory 200 can be used for memory cells c 11 ~c MN Perform a program action, an erase action, or a read action.

[0067] According to an embodiment of the present invention, the word line driver 210 outputs a decoded signal (S D ) to the word line driver 220, so that the word line driver 220 activates M word lines WL1-WL M The bit line selector 250 may activate the bit lines to determine the selected memory cell in the selected row.

[0068] For example, the word line driver 220 activates the word line WL1, so the first row in the array structure 100 is the selected row. When the bit line selector 250 activates only the bit line BL1, only the memory cell c 11 When the bit line selector 250 activates the bit lines BL1 to BL8, the memory cell c11 ~Memory Cell c 18 For the selected memory cell.

[0069] During programming, the word line driver 220 provides a turn-on voltage V ON To M word lines WL1~WL M One of them makes M word lines WL1~WL M Furthermore, the auxiliary selection gate line driver 230 provides various driving voltages to the M auxiliary selection gate lines ASG1-ASG M According to the activated word line, a selected row in the array structure 100 can be determined. Furthermore, the bit line selector 250 activates at least one bit line. According to the activated word line and bit line, at least one selected memory cell in the selected row can be determined, and a programming operation is performed on the selected memory cell, so that the selected memory cell is programmed into a program state.

[0070] Similarly, during the read operation, the M word lines WL1 to WL M One of them is active to determine a selected row in the array structure 100. Furthermore, the auxiliary selection gate line driver 230 provides various driving voltages to the M auxiliary selection gate lines ASG1-ASG M Furthermore, the bit line selector 250 activates at least one bit line. According to the activated word line and bit line, at least one selected memory cell in the selected row can be determined. The bit line selector 250 transmits the memory cell current generated by the selected memory cell to the sensing circuit 260, so that the sensing circuit 260 performs a reading operation to determine the storage state of the selected memory cell and generate output data D OUT .

[0071] According to the embodiment of the present invention, since the memory cells c11-cMN in the array structure 100 are connected to the same erase line EL, in general, if during the erase operation, the auxiliary selection gate line driver 230 provides the same driving voltage to the M auxiliary selection gate lines ASG1-ASG M When all memory cells c in the array structure 100 11 ~c MN The erase operation will be performed simultaneously, so that all memory cells c 11 ~c MN Becomes erased.

[0072] According to an embodiment of the present invention, if the auxiliary selection gate line driver 230 provides different driving voltages to the M auxiliary selection gate lines ASG1-ASG M , the auxiliary selection gate line driver 230 can determine that a portion of the memory cells in the array structure 100 perform an erase operation, while another portion of the memory cells do not perform an erase operation.

[0073] Since the memory cells c in the array structure 100 11 ~c MN is an MTP storage cell. That is, the storage cell c 11 ~c MN Multiple programming and erasing operations can be performed. When the non-volatile memory 200 is just manufactured, the memory cell c 11 ~c MN The characteristics are better and it is less likely to have a program fail or an erase fail. 11 ~c MN After multiple programming and erasing operations, the memory cell c 11 ~c MN The characteristics of the memory cell will deteriorate, and programming failure or erase failure may occur. 11 ~c MN If the erase count does not exceed a certain number (e.g., 1000 times), the memory cell may be considered to have better characteristics. 11 ~c MN If the number of erase times exceeds a certain number, the memory cell can be considered to have poor characteristics. Of course, in addition to using the number of erase times as a reference, the characteristics of the memory cell can also be judged by the number of programming failures or erase failures.

[0074] For example, when the memory cell has good characteristics and is in an erase state, the floating gate transistor M F The threshold voltage (Vt) is -1V. When the memory cell characteristics deteriorate, over-erasure may occur after the memory cell is erased. When the memory cell characteristics deteriorate and are over-erased, the floating gate transistor M F The threshold voltage Vt may shift to -1.2V. Therefore, when the over-erased memory cell is programmed again, it will be difficult to turn on the floating gate transistor M. F, resulting in a programming failure due to a program current being too small. In this case, the memory cell needs to be programmed multiple times before it can be successful.

[0075] In order to cope with the above-mentioned memory cells with different characteristics, the present invention designs an auxiliary selection gate line driver 230, which can operate in programming, erasing and reading operations in different modes. In addition, during the programming cycle of the programming operation, the auxiliary selection gate line driver 230 provides different driving voltages in different phases to improve the programming efficiency. Similarly, during the erasing cycle of the erasing operation, the auxiliary selection gate line driver 230 can provide various driving voltages in different modes to improve the erasing efficiency. During the reading cycle of the reading operation, the auxiliary selection gate line driver 230 can provide various driving voltages in different modes to improve the reading efficiency.

[0076] Please refer to Figure 4 , which is a circuit diagram of the auxiliary selection gate line driver of the present invention. The auxiliary selection gate line driver 230 includes: a pull-up controller 412, a pull-down controller 414 and M driving elements 421~42M. Each driving element 421~42M has the same structure. For example, the driving element 421 includes a P-type transistor P1 and an N-type transistor N1. The source terminal of the P-type transistor P1 receives a first supply voltage (V ASGP ), the gate terminal of the P-type transistor P1 receives the control signal GP1, the drain terminal of the P-type transistor P1 is connected to the drain terminal of the N-type transistor N1, the gate terminal of the N-type transistor N1 receives the control signal GN1, and the source terminal of the N-type transistor N1 receives the second supply voltage V ASGN Furthermore, the drain terminal of the P-type transistor P1 is connected to the auxiliary selection gate line ASG1, and the driving element 421 can output a driving voltage to the auxiliary selection gate line ASG1.

[0077] like Figure 4 As shown, the pull-up controller 412 and the pull-down controller 414 are connected to the word line decoder 210 to receive the decoding signal S D The pull-up controller 412 and the pull-down controller 414 further receive a mode signal S M Furthermore, the two controllers 412 and 414 are connected to M driving elements 421-42M, and the M driving elements 421-42M are connected to corresponding M auxiliary selection gate lines ASG1-ASG M According to the decoded signal S D and the mode signal S M, the pull-up controller 412 generates control signals GP1-GP M , the pull-down controller 414 generates control signals GN1-GN M The M driving elements 421-42M receive corresponding control signals GP1-GP M GN1~GN M , so that the M driving elements 421-42M output various driving voltages to the auxiliary selection gate lines ASG1-ASG M Furthermore, each of the driving elements 421-42M includes two transistors. During normal operation, one of the transistors is turned on and the other is turned off.

[0078] According to an embodiment of the present invention, according to the mode signal S M The pull-up controller 412 and the pull-down controller 414 control the M driving elements 421-42M to output different driving voltages to the auxiliary selection gate lines ASG1-ASG M That is, in different modes, the first supply voltage V ASGP and the second supply voltage V ASGN The voltage level of the control signal GP1~GP M GN1~GN M For example, the pull-up controller 412 provides a first supply voltage V with different voltage levels in different modes. ASGP And control signals GP1~GP M , to control the P-type transistors P1-P in the driving elements 421-42M. M The pull-down controller 414 provides a second supply voltage V with different voltage levels in different modes. ASGN and control signals GN1 to GN2 of different voltage levels M , to control the N-type transistors N1-N in the driving elements 421-42M. M on and off.

[0079] The following describes in detail the operation of the auxiliary selection gate line driver 230 in different modes. In the following description, the first memory cell c in the first row of the array structure 100 is used as an example. 11 is the selected memory cell, and the other memory cells are non-selected memory cells. That is, the first row is the selected row, and the other rows are non-selected rows. D The auxiliary selection gate line driver 230 provides corresponding driving voltages to the auxiliary selection gate line ASG1 of the selected row and the auxiliary gate lines ASG2 to ASG3 of the non-selected row. MFurthermore, since the auxiliary gate lines ASG2 to ASG M The driving voltages of the auxiliary selection gate lines ASG1-ASG2 are the same, and the following only takes the driving element 42M as an example. M The driving voltage of other word lines WL1~WL M The bias voltage of the source line SL and the erase line EL is similar to Figures 1A to 1E , I will not go into details here.

[0080] According to the mode signal S M The nonvolatile memory 200 can operate in a first programming mode (PGM mode1), a second programming mode (PGM mode2), a first read mode (READ mode1), a second read mode (READ mode2), a first erase mode (ERS mode1), a second erase mode (ERS mode2), or a third erase mode (ERS mode3).

[0081] Please refer to Figure 5A , which shows a bias table of the array structure in the first programming mode (PGM mode1). Figure 5B A schematic diagram of related signals of the auxiliary selection gate line driver. Figure 5C and Figure 5D is a schematic diagram of the related bias voltages of the driving element in the first phase PH1. Figure 5E and Fig. 5F is a schematic diagram of the related bias voltages of the driving element in the second phase PH2.

[0082] The non-volatile memory 200 receives a first system operation voltage (V DD ) and the second system operating voltage V SS For example, V DD is 3.3V, V SS is the ground voltage (0V). PP1 Greater than the second programming voltage V PP2 The first programming voltage V PP1 The second programming voltage V PP2 It can be, for example, 7V. The first driving voltage V DV1 is a positive voltage, and the first driving voltage V DV1 Greater than or equal to the second programming voltage V PP2 The first driving voltage V DV1 It can be 9V, for example.

[0083] In addition, the programming cycle of the programming operation includes a first phase PH1 and a second phase PH2. The first phase PH1 is about 5 μs, and the second phase PH2 is about 45 μs. Of course, the present invention does not limit the duration of the two phases PH1 and PH2, as long as the duration of the second phase PH2 is greater than the duration of the first phase PH1.

[0084] In the first phase PH1, the first supply voltage V ASGP V PP1 , the second supply voltage V ASGN V SS Furthermore, the control signals GP1, GN1, and GP M With the control signal GN M Both are the first programming voltage V PP1 In the driving element 421, the P-type transistor P1 is turned off and the N-type transistor N1 is turned on. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 of the selected row is V SS (0V). In the driving element 42M, the P-type transistor P M The N-type transistor N M Turn on, drive element 42M provides auxiliary selection gate line ASG to the non-selected row M The driving voltage level is V SS (0V).

[0085] In the second phase PH2, the first supply voltage V ASGP V DV1 , the second supply voltage V ASGN V SS Furthermore, the control signal GP1 is V SS , the control signal GN1 is V SS , control signal GP M V DV1 And the control signal GN M V DV1 In the driving element 421, the P-type transistor P1 is turned on and the N-type transistor N1 is turned off. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 of the selected row is V DV1 In the driving element 42M, the P-type transistor P M The N-type transistor N M Turn on, drive element 42M provides auxiliary selection gate line ASG to the non-selected row M The driving voltage level is V SS (0V).

[0086] Please refer to Fig. 6A, which shows a bias table of the array structure in the second programming mode (PGM mode2). Figure 6B A schematic diagram of related signals of the auxiliary selection gate line driver. Figure 6C and Fig.6D is a schematic diagram of the related bias voltages of the driving element in the first phase PH1. Fig. 6E and Fig. 6F is a schematic diagram of the related bias voltage of the driving element in the second phase PH2. DV2 is a negative voltage, which may be -2V, for example.

[0087] In the first phase PH1, the first supply voltage V ASGP V DD / 2, the second supply voltage V ASGN is the second driving voltage V DV2 Furthermore, the control signal GP1 is V DD / 2, the control signal GN1 is V SS , control signal GP M V DD / 2 and the control signal GN M V SS In the driving element 421, the P-type transistor P1 is turned off and the N-type transistor N1 is turned on. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 of the selected row is V DV2 (-2V). In the driving element 42M, the P-type transistor P M The N-type transistor N M Turn on, drive element 42M provides auxiliary selection gate line ASG to the non-selected row M The driving voltage level is V DV2 (-2V).

[0088] In the second phase PH2, the first supply voltage V ASGP is the first driving voltage V DV1 , the second supply voltage V ASGN V SS Furthermore, the control signal GP1 is V SS , the control signal GN1 is V SS , control signal GP M V DV1 And the control signal GN M V DV1 In the driving element 421, the P-type transistor P1 is turned on and the N-type transistor N1 is turned off. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 of the selected row is V DV1 In the driving element 42M, the P-type transistor P M The N-type transistor NM Turn on, drive element 42M provides auxiliary selection gate line ASG to the non-selected row M The driving voltage level is V SS (0V).

[0089] According to an embodiment of the present invention, in the first phase PH1 of the second programming mode (PGM mode2), the first supply voltage V ASGP Not limited to V DD / 2, the first supply voltage V ASGP It can be a control voltage, and the control voltage is less than V DD And it can be greater than or equal to 0V. In addition, since in the first phase, the first supply voltage V ASGP In order to make the transistors P1 and P2 in the driving elements 421 and 42M M 、N1、N M To operate in a safe operating area (SOA), at the beginning of the first phase PH1, the first supply voltage V ASGP To V DD / 2, and then reduce the second supply voltage V ASGN To the second driving voltage V DV2 At the end of the first phase PH1, the second supply voltage V ASGN To V SS , and then increase the first supply voltage V ASGP To V DV1 .

[0090] According to an embodiment of the present invention, the first programming mode (PGM mode 1) may be applied to memory cells with better characteristics, and the second programming mode (PGM mode 2) may be applied to memory cells with worse characteristics.

[0091] exist Figure 5A and Fig. 6A In the programming operation of , in the first phase PH1, the voltage level on the auxiliary selection gate line is different. Fig. 6A In the first phase of the second programming mode (PGM mode2), a negative second driving voltage V is provided. DV2 To auxiliary selection gate line ASG 1， The floating gate transistor of the selected memory cell can be turned on more easily, allowing more electrons to be injected into the floating gate. Therefore, the selected memory cell with poor characteristics can be quickly converted from the over-erased state to the programmed state. Figure 5AIn the embodiment, since the selected memory cell has better characteristics, during the first phase PH1, even if no negative voltage is provided to the auxiliary selection gate line ASG1, electrons can be efficiently injected into the floating gate of the floating gate transistor.

[0092] In addition, Figure 5A and Fig. 6A In the second programming mode, in the second phase PH1, the auxiliary selection gate line ASG1 of the selected memory cell receives the first driving voltage V DV1 , can improve the programming efficiency of the selected memory cell. In addition, due to the auxiliary selection gate line ASG of the non-selected memory cell M The select transistor is not driven and is off, so electrons are not injected into the floating gates of the unselected memory cells.

[0093] The above two programming modes are described by taking programming a single selected memory cell as an example. However, the present invention is not limited thereto, and the above two programming modes can also be applied to programming operations of multiple memory cells in the array structure 100. For example, a byte program operation is to program 8 memory cells.

[0094] Taking the second programming mode as an example, the byte programming operation is performed on the first row of memory cells in the array structure 100. When performing the byte programming operation, the word line WL1 is activated to determine the first row in the array structure as the selected row, and then the eight bit lines BL1-BL8 are activated in sequence, so that the eight selected memory cells c 11 ~c 18 The operation of the first phase PH1 of the second programming mode is performed sequentially. After the above operation is completed, the eight bit lines BL1-BL8 are operated simultaneously so that the eight selected memory cells c 11 ~c 18 At the same time, the operation of the second phase PH2 of the second programming mode is performed. Therefore, the programming time consumed for performing the byte program operation is 85 μs (5×8+45).

[0095] Please refer to Fig. 7A , which shows a bias table of the array structure in the first read mode (READ mode1). Figure 7B A schematic diagram of related signals of the auxiliary selection gate line driver. Figure 7C and Fig.7D Schematic diagram of the related bias voltage of the driving element during the reading action. READ It can be, for example, 2V.

[0096] During the read cycle, the first supply voltage V ASGP V DD , the second supply voltage V ASGN VSS Furthermore, the control signals GP1, GN1, and GP M With the control signal GN M All V DD In the driving element 421, the P-type transistor P1 is turned off and the N-type transistor N1 is turned on. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 of the selected row is V SS (0V). In the driving element 42M, the P-type transistor P M The N-type transistor N M Turn on, drive element 42M provides auxiliary selection gate line ASG to the non-selected row M The driving voltage level is V SS That is, in the first read mode (READ mode 1), all auxiliary selection gate lines ASG1-ASG M The driving voltage is V SS (0V), representing all auxiliary selection gate lines ASG1~ASG M None were driven.

[0097] Please refer to Fig. 8A , which shows a bias table of the array structure in the second read mode (READ mode2). Figure 8B A schematic diagram of related signals of the auxiliary selection gate line driver. Figure 8C and Fig.8D Schematic diagram of the related bias voltage of the driving element during the reading operation. DV3 Less than the first system operating voltage V DD , greater than or equal to the second system operating voltage V SS For example, the third driving voltage V DV3 is 1V.

[0098] During the read cycle, the first supply voltage V ASGP V DV3 , the second supply voltage V ASGN V SS Furthermore, the control signals GP1, GN1, and GP M With the control signal GN M All V SS In the driving element 421, the P-type transistor P1 is turned on and the N-type transistor N1 is turned off. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 of the selected row is V DV3 (1V). In addition, in the driving element 42M, the P-type transistor P M The N-type transistor N MThe drive element 42M is turned off and provides the auxiliary selection gate line ASG of the non-selected row. M The driving voltage level is V DV3 That is, in the second read mode (READ mode 2), all auxiliary selection gate lines ASG1-ASG M The driving voltages are all the third driving voltage V DV3 (1V).

[0099] According to an embodiment of the present invention, the first read mode (READ mode 1) can be applied to memory cells with better characteristics, and the second read mode (READ mode 2) can be applied to memory cells with poorer characteristics. Fig. 8A In the reading operation, due to the poor characteristics of the memory cell, the driving voltage level provided to the auxiliary selection gate line ASG1 is V DV3 (1V), the memory cell will generate a larger read current, making it easier for the sensing circuit 260 to determine the storage state of the memory cell. Fig. 7A In the embodiment, since the memory cell has better characteristics, 0V is provided, that is, the auxiliary selection gate line ASG1 is not driven, and the memory cell can generate enough read current to allow the sensing circuit 260 to determine the storage state of the memory cell.

[0100] Please refer to Fig.9A , which shows the bias table of the array structure in the first erasing mode (ERS mode1). Fig. 9B A schematic diagram of related signals of the auxiliary selection gate line driver. Fig. 9C and Fig.9D Schematic diagram of the related bias voltage of the driving element during the erase operation.

[0101] During the erase cycle, the first supply voltage V ASGP V DD , the second supply voltage V ASGN V SS Furthermore, the control signals GP1, GN1, and GP M With the control signal GN M All V DD In the driving element 421, the P-type transistor P1 is turned off and the N-type transistor N1 is turned on. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 is V SS (0V). In the driving element 42M, the P-type transistor P M The N-type transistor N M Turn on, drive element 42M provides to auxiliary selection gate line ASG M The driving voltage level is V SSThat is, in the first erasing mode (ERS mode 1), all auxiliary selection gate lines ASG1-ASG M The driving voltage is V SS (0V), representing all auxiliary selection gate lines ASG1~ASG M None were driven.

[0102] Please refer to Fig. 10A , which shows the bias table of the array structure in the second erasing mode (ERS mode2). Fig. 10B A schematic diagram of related signals of the auxiliary selection gate line driver. Fig. 10C and Fig. 10D is a schematic diagram of the related bias voltage of the driving element during the erasing operation. DV4 It is a negative value, such as -2.5V.

[0103] During the erase cycle, the first supply voltage V ASGP V DD / 2, the second supply voltage V ASGN is the fourth driving voltage V DV4 Furthermore, the control signal GP1 is V DD / 2, the control signal GN1 is V SS , control signal GP M V DD / 2 and the control signal GN M V SS In the driving element 421, the P-type transistor P1 is turned off and the N-type transistor N1 is turned on. The driving voltage level provided by the driving element 421 to the auxiliary selection gate line ASG1 is V DV4 (-2.5V). In the driving element 42M, the P-type transistor P M The N-type transistor N M Turn on, drive element 42M provides auxiliary selection gate line ASG M The driving voltage level is V DV4 (-2.5V). That is, in the second erasing mode (ERS mode2), all auxiliary selection gate lines ASG1-ASG M The driving voltage is V DV4 (-2.5V).

[0104] According to an embodiment of the present invention, in the second erase mode (ERS mode 2), the first supply voltage V ASGP Not limited to V DD / 2, the first supply voltage V ASGP It can be a control voltage, and the control voltage is less than V DDAnd it can be greater than or equal to 0V. In addition, during the erase cycle, the second supply voltage V ASGN In order to make the transistors P1 and P2 in the driving elements 421 and 42M M 、N1、N M Operating in the safe operating range (SOA), at the beginning of the erase cycle, the first supply voltage V ASGP To V DD / 2, and then reduce the second supply voltage V ASGN To the fourth driving voltage V DV4 At the end of the erase cycle, the second supply voltage V ASGN To V SS , and then increase the first supply voltage V ASGP To V DD .

[0105] According to an embodiment of the present invention, the first erasing mode (ERS mode 1) can be applied to memory cells with better characteristics, and the second erasing mode (ERS mode 2) can be applied to memory cells with poorer characteristics. Fig. 10A In the erasing cycle of the second erasing mode (ERS mode2), a fourth driving voltage V of a negative voltage is provided. DV4 To auxiliary selection gate lines ASG1~ASG M , which can make all memory cells c 11 ~c MN The voltage difference between the internal floating gate and the erase gate line EL, that is, (V EE -V DV4 ), and the electrons stored in the floating gate are ejected to the erase line EL. After the erase operation, all memory cells c 11 ~c MN It will become erased.

[0106] In addition, Fig.9A In the memory cell c 11 ~c MN The characteristics are better, only providing V SS (0V), that is, the auxiliary selection gate lines ASG1-ASG are not driven. M That is, during the erase cycle of the first erase mode (ERS mode1), V SS (0V) to auxiliary selection gate lines ASG1~ASG M , the electrons stored in the floating gate can be ejected to the erase line EL. After the erase operation, all memory cells c 11 ~cMN It will become erased.

[0107] In the above two erasing modes, after the erasing operation is performed, all memory cells c in the array structure 100 are 11 ~c MN The present invention further proposes a third erasing mode (ERS mode 3). During the erasing operation, the auxiliary selection gate line driver 230 can output different driving voltages to M auxiliary selection gate lines ASG1-ASG M Under the control of the auxiliary selection gate line driver 230, a portion of the memory cells in the array structure 100 can be erased, while another portion of the memory cells will not be erased.

[0108] Please refer to Fig.11A , which shows the bias table of the array structure in the third erasing mode (ERS mode3). Fig. 11B A schematic diagram of related signals of the auxiliary selection gate line driver. Fig. 11C and Fig.11D is a schematic diagram of the related bias voltage of the driving element during the erasing operation. DV5 is a negative value, such as -2V. The sixth driving voltage V DV6 is a positive value, the sixth driving voltage V DV6 Greater than V DD , which may be, for example, 5 V. In addition, the pull-up controller 412 and the pull-down controller 414 may provide more supply voltages to the driving elements 421 ˜ 42M.

[0109] During the erase cycle, the driving element 421 receives the first supply voltage V ASGP V DD / 2, the second supply voltage V ASGN is the fifth driving voltage V DV5 The third supply voltage V received by the driving element 42M ASGP ' is the sixth driving voltage V DV6 , the fourth supply voltage V ASGN ' is V SS Furthermore, the control signal GP1 is V DD / 2, the control signal GN1 is V SS , control signal GP M V SS And the control signal GN M V SS In the driving element 421, the P-type transistor P1 is turned off and the N-type transistor N1 is turned on. The driving voltage level provided by the driving element 421 to the selected auxiliary selection gate line ASG1 is V DV5(-2V). In the driving element 42M, the P-type transistor P M The N-type transistor N M The driver element 42M is turned off to provide power to the unselected auxiliary select gate line ASG. M The driving voltage level is V DV6 That is, in the third erasing mode (ERS mode 3), the auxiliary selection gate line driver can provide different driving voltages to the auxiliary selection gate lines ASG1-ASG M .

[0110] For example, when the erasing operation is performed in the third erasing mode (ERS mode 3), only the driving voltage of the auxiliary selection gate line ASG1 is the fifth driving voltage (-2V), and the other auxiliary selection gate lines ASG2 to ASG M The driving voltage of the first row of N memory cells c is the sixth driving voltage (5V). 11 ~c 1N The voltage difference between the internal floating gate and the erase gate line EL, that is, (V EE -V DV5 ) is large enough to allow the electrons stored in the floating gate to be ejected to the erase line EL. After the erase operation, the N memory cells in the first row are 11 ~c 1N It will become erased.

[0111] In addition, the memory cells c in other rows 21 ~c MN The voltage difference between the internal floating gate and the erase gate line EL, that is, (V EE -V DV6 ) is not large enough to allow the electrons stored in the floating gate to be ejected to the erase line EL. Therefore, after the erase operation, the memory cells in other rows are 21 ~c MN The storage status of the data remains unchanged and will not be erased.

[0112] In summary, the present invention provides a non-volatile memory with an auxiliary select gate line driver, wherein the array structure of the non-volatile memory is composed of 2T2C memory cells. Furthermore, the memory cells in the array structure are further connected to corresponding auxiliary select gate lines. In addition, the non-volatile memory of the present invention is further designed with an auxiliary select gate line driver, which can output a specific driving voltage to the auxiliary select gate line to improve the programming efficiency, erasing efficiency and reading efficiency of the non-volatile memory.

[0113] As can be seen from the above description, the auxiliary selection gate line driver 230 in the non-volatile memory of the present invention is configured to generate a gate line according to the mode signal S M , operating in one of the seven modes. That is, the first programming mode (PGM mode1), the second programming mode (PGM mode2), the first read mode (READ mode1), the second read mode (READ mode2), the first erase mode (ERS mode1), the second erase mode (ERS mode2) and the third programming mode (ERS mode3). Of course, the auxiliary selection gate line driver 230 can also selectively operate in fewer modes. For example, the auxiliary selection gate line driver 230 can operate in the first programming mode (PGM mode1) or the second programming mode (PGM mode1) during the programming action. And during the read action and the erase action, it only operates in the second read mode and the second erase mode.

[0114] In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A non-volatile memory, comprising: An array structure, the array structure is connected to a first word line, a second word line, a source line, an erase line, a first auxiliary selection gate line, a second auxiliary selection gate line and a bit line; wherein the array structure includes a first memory cell and a second memory cell; the first memory cell is connected to the first word line, the first auxiliary selection gate line, the erase line, the source line and the first bit line; the second memory cell is connected to the second word line, the second auxiliary selection gate line, the erase line, the source line and the first bit line; A word line decoder, generating a decoding signal; A word line driver receives the decoding signal and is connected to the first word line and the second word line, wherein the word line driver operates one of the first word line and the second word line according to the decoding signal; an auxiliary selection gate line driver, receiving a mode signal and the decoding signal, and the auxiliary selection gate line driver is connected to the first auxiliary selection gate line and the second auxiliary selection gate line; A bit line selector connected to the first bit line; and a sensing circuit connected to the bit line selector; wherein, during a programming operation, the first memory cell is determined to be a selected memory cell and the second memory cell is determined to be a non-selected memory cell; wherein, according to the mode signal, in a first phase of the first programming mode, the auxiliary selection gate line driver does not drive the first auxiliary selection gate line and the second auxiliary selection gate line; in a second phase of the first programming mode, the auxiliary selection gate line driver provides a first driving voltage to the first auxiliary selection gate line, and the auxiliary selection gate line driver does not drive the second auxiliary selection gate line; and the first driving voltage is a positive voltage; Wherein, according to the mode signal, in a first phase of a second programming mode, the auxiliary selection gate line driver provides a second driving voltage to the first auxiliary selection gate line and the second auxiliary selection gate line; in a second phase of the second programming mode, the auxiliary selection gate line driver provides the first driving voltage to the first auxiliary selection gate line, and the auxiliary selection gate line driver does not drive the second auxiliary selection gate line; and the second driving voltage is a negative voltage.

2. The nonvolatile memory of claim 1 , wherein the first memory cell comprises: a first selection transistor, wherein a source terminal of the first selection transistor is connected to the source line, and a gate terminal of the first selection transistor is connected to the first word line; a first floating gate transistor, a source terminal of the first floating gate transistor being connected to a drain terminal of the first selection transistor, and a drain terminal of the first floating gate selection transistor being connected to the first bit line; a first capacitor, a first terminal of the first capacitor being connected to the floating gate of the first floating gate transistor, and a second terminal of the first capacitor being connected to the erase line; as well as A second capacitor has a first terminal connected to the floating gate of the first floating gate transistor and a second terminal connected to the first auxiliary selection gate line.

3. The nonvolatile memory as claimed in claim 2, wherein the second memory cell comprises: a second selection transistor, wherein a source terminal of the second selection transistor is connected to the source line, and a gate terminal of the second selection transistor is connected to the second word line; a second floating gate transistor, a source terminal of the second floating gate transistor being connected to a drain terminal of the second selection transistor, and a drain terminal of the second floating gate selection transistor being connected to the first bit line; a third capacitor, a first terminal of the third capacitor being connected to the floating gate of the second floating gate transistor, and a second terminal of the third capacitor being connected to the erase line; as well as A fourth capacitor has a first terminal connected to the floating gate of the second floating gate transistor and a second terminal connected to the second auxiliary selection gate line.

4. The nonvolatile memory according to claim 1, wherein: According to the mode signal, in the first reading mode, the auxiliary selection gate line driver does not drive the first auxiliary selection gate line and the second auxiliary selection gate line; And, according to the mode signal, in the second reading mode, the auxiliary selection gate line driver provides a third driving voltage to the first auxiliary selection gate line and the second auxiliary selection gate line, and the third driving voltage is a positive voltage.

5. The nonvolatile memory according to claim 4, wherein: According to the mode signal, in the first erasing mode, the auxiliary selection gate line driver does not drive the first auxiliary selection gate line and the second auxiliary selection gate line; And, according to the mode signal, in the second erasing mode, the auxiliary selection gate line driver provides a fourth driving voltage to the first auxiliary selection gate line and the second auxiliary selection gate line, and the fourth driving voltage is a negative voltage.

6. The nonvolatile memory according to claim 5, wherein: According to the mode signal, in the third erase mode, the auxiliary selection gate line driver provides a fifth driving voltage to the first auxiliary selection gate line, and the auxiliary selection gate line driver provides a sixth driving voltage to the second auxiliary selection gate line; the storage state of the first memory cell becomes an erased state, and the storage state of the second memory cell does not change; the fifth driving voltage is a negative voltage; and the sixth driving voltage is a positive voltage.

7. The nonvolatile memory device of claim 6, wherein the auxiliary selection gate line driver comprises: A pull-up controller receives the decoded signal and the mode signal, and the pull-up driver generates a first control signal and a second control signal; A pull-down controller receives the decoded signal and the mode signal, and the pull-down driver generates a third control signal and a fourth control signal; A first driving element, comprising a first P-type transistor and a first N-type transistor; The source terminal of the first P-type transistor receives the first supply voltage, the gate terminal of the first P-type transistor receives the first control signal, and the drain terminal of the first P-type transistor is connected to the first auxiliary selection gate line; and the drain terminal of the first N-type transistor is connected to the drain terminal of the first P-type transistor, the gate terminal of the first N-type transistor receives the third control signal, and the source terminal of the first N-type transistor receives the second supply voltage; as well as A second driving element, comprising a second P-type transistor and a second N-type transistor; The source terminal of the second P-type transistor receives a third supply voltage, the gate terminal of the second P-type transistor receives the second control signal, and the drain terminal of the second P-type transistor is connected to the second auxiliary selection gate line; and the drain terminal of the second N-type transistor is connected to the drain terminal of the second P-type transistor, the gate terminal of the second N-type transistor receives the fourth control signal, and the source terminal of the second N-type transistor receives a fourth supply voltage.

8. The nonvolatile memory as claimed in claim 7, wherein in the third erase mode, the first supply voltage is a control voltage, the second supply voltage is a fifth driving voltage, the third supply voltage is a sixth driving voltage, the fourth supply voltage is a ground voltage, the first control signal is the control voltage, the second control signal, the third control signal and the fourth control signal are the ground voltage, the first auxiliary selection gate line outputs the fifth driving voltage, and the second auxiliary selection gate line outputs the sixth driving voltage.

9. The nonvolatile memory device as claimed in claim 5, wherein the auxiliary selection gate line driver comprises: A pull-up controller receives the decoded signal and the mode signal, and the pull-up driver generates a first control signal and a second control signal; A pull-down controller receives the decoded signal and the mode signal, and the pull-down driver generates a third control signal and a fourth control signal; A first driving element, comprising a first P-type transistor and a first N-type transistor; The source terminal of the first P-type transistor receives the first supply voltage, the gate terminal of the first P-type transistor receives the first control signal, and the drain terminal of the first P-type transistor is connected to the first auxiliary selection gate line; and the drain terminal of the first N-type transistor is connected to the drain terminal of the first P-type transistor, the gate terminal of the first N-type transistor receives the third control signal, and the source terminal of the first N-type transistor receives the second supply voltage; as well as A second driving element, comprising a second P-type transistor and a second N-type transistor; The source terminal of the second P-type transistor receives the first supply voltage, the gate terminal of the second P-type transistor receives the second control signal, and the drain terminal of the second P-type transistor is connected to the second auxiliary selection gate line; and the drain terminal of the second N-type transistor is connected to the drain terminal of the second P-type transistor, the gate terminal of the second N-type transistor receives the fourth control signal, and the source terminal of the second N-type transistor receives the second supply voltage.

10. The nonvolatile memory as claimed in claim 9, wherein in the first phase of the first programming mode, the first supply voltage is a first programming voltage, the second supply voltage is a ground voltage, the first control signal, the second control signal, the third control signal and the fourth control signal are the first programming voltage, and the first auxiliary selection gate line and the second auxiliary selection gate line output the ground voltage.

11. The nonvolatile memory of claim 10, wherein in the second phase of the first programming mode, the first supply voltage is the first driving voltage, the second supply voltage is the ground voltage, the first control signal and the third control signal are the ground voltage, the second control signal and the fourth control signal are the first driving voltage, the first auxiliary selection gate line outputs the first driving voltage, and the second auxiliary selection gate line outputs the ground voltage.

12. The nonvolatile memory as claimed in claim 9, wherein in the first phase of the second programming mode, the first supply voltage is the control voltage, the second supply voltage is the second driving voltage, the first control signal and the second control signal are the control voltages, the third control signal and the fourth control signal are ground voltages, and the first auxiliary selection gate line and the second auxiliary selection gate line output the second driving voltage.

13. The nonvolatile memory as claimed in claim 12, wherein in the second phase of the second programming mode, the first supply voltage is the first driving voltage, the second supply voltage is the ground voltage, the first control signal and the third control signal are the ground voltage, the second control signal and the fourth control signal are the first driving voltage, the first auxiliary selection gate line outputs the first driving voltage, and the second auxiliary selection gate line outputs the ground voltage.

14. The nonvolatile memory as claimed in claim 9, wherein in the first read mode, the first supply voltage is a system operating voltage, the second supply voltage is a ground voltage, the first control signal, the second control signal, the third control signal and the fourth control signal are the system operating voltage, and the first auxiliary selection gate line and the second auxiliary selection gate line output the ground voltage.

15. The nonvolatile memory as claimed in claim 9, wherein in the second read mode, the first supply voltage is the third driving voltage, the second supply voltage is a ground voltage, the first control signal, the second control signal, the third control signal and the fourth control signal are the ground voltage, and the first auxiliary selection gate line and the second auxiliary selection gate line output the third driving voltage.

16. The nonvolatile memory as claimed in claim 9, wherein in the first erase mode, the first supply voltage is a system operating voltage, the second supply voltage is a ground voltage, the first control signal, the second control signal, the third control signal and the fourth control signal are the system operating voltages, and the first auxiliary selection gate line and the second auxiliary selection gate line output the ground voltage.

17. The nonvolatile memory as claimed in claim 9, wherein in the second erase mode, the first supply voltage is the control voltage, the second supply voltage is the fourth driving voltage, the first control signal and the second control signal are the control voltages, the third control signal and the fourth control signal are ground voltages, and the first auxiliary selection gate line and the second auxiliary selection gate line output the fourth driving voltage.

Images