Method of fabricating a semiconductor structure

Abstract

The application relates to a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate; forming a first mask pattern, the first mask pattern extending along a first direction and being arranged at intervals along a second direction; forming a second mask pattern, the second mask pattern being arranged at intervals above the first mask pattern along the first direction; etching the first mask pattern according to the second mask pattern, so as to divide the first mask pattern into first target patterns arranged at intervals along the first direction; forming a third mask pattern, the third mask pattern extending along the first direction and being arranged at intervals along the second direction; forming a fourth mask pattern, the fourth mask pattern being arranged at intervals above the third mask pattern along the first direction; and etching the third mask pattern according to the fourth mask pattern, so as to divide the third mask pattern into second target patterns arranged at intervals along the first direction. The application reduces the pattern density of the first target patterns and the second target patterns, and improves the pattern quality of the first target patterns and the second target patterns.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] With the continuous advancement of integrated circuit (IC) development, the critical dimension (CD) of electronic components in ICs is constantly decreasing, and the integration density is continuously increasing to achieve higher integration levels. The fabrication of electronic components in ICs requires photolithography to transfer patterns from a photomask to a silicon wafer. The photolithography process includes exposure, development, and etching. The increased density of electronic components in ICs also increases the difficulty of the photolithography process. Currently, the resolution of photolithography technology is insufficient to meet the manufacturing requirements of ICs, posing a significant challenge to IC fabrication processes. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for fabricating semiconductor structures to address the problem that the resolution of existing photolithography technology is insufficient to meet the manufacturing requirements of integrated circuits.

[0004] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0005] Provide a base;

[0006] A first mask pattern is formed on the substrate, the first mask pattern extends along a first direction, and the first mask patterns are spaced apart along a second direction perpendicular to the first direction;

[0007] A second mask pattern is formed, wherein the second mask patterns are arranged at intervals above the first mask pattern along the first direction;

[0008] The first mask pattern is etched according to the second mask pattern, and the first mask pattern is divided into first target patterns arranged at intervals along the first direction;

[0009] A third mask pattern is formed above the first target pattern. The third mask pattern extends along the first direction and is spaced apart along the second direction. The projections of the first mask pattern onto the substrate and the projections of the third mask pattern onto the substrate have no overlapping areas.

[0010] A fourth mask pattern is formed, wherein the fourth mask pattern is arranged at intervals above the third mask pattern along the first direction;

[0011] The third mask pattern is etched according to the fourth mask pattern, and the third mask pattern is divided into second target patterns arranged at intervals along the first direction.

[0012] In one embodiment, along the second direction, the projections of the first mask pattern onto the substrate and the projections of the third mask pattern onto the substrate are alternately arranged.

[0013] In one embodiment, the projections of the second mask pattern onto the substrate and the projections of the fourth mask pattern onto the substrate have no overlapping areas.

[0014] In one embodiment, forming the first mask pattern includes:

[0015] A first sub-mask pattern is formed, which extends along the first direction and is spaced apart along the second direction;

[0016] A first mask material layer is formed, which covers the sidewalls, top surface, and area between the first sub-mask patterns. The first mask material layer includes a first material.

[0017] The first mask material layer located on the top surface of the first sub-mask pattern and the first mask material layer located between the first sub-mask patterns are removed, and the first mask material layer covering the sidewall of the first sub-mask pattern is used to form the first mask pattern.

[0018] In one embodiment, the first material comprises a semiconductor material, and the first material is doped with a group IIIA element.

[0019] In one embodiment, forming the second mask pattern includes:

[0020] A first photoresist layer is formed on top of the first mask pattern;

[0021] The first photoresist layer is exposed and developed to form a first patterned hole in the first photoresist layer.

[0022] In one embodiment, forming the second mask pattern further includes:

[0023] A second mask material layer is formed, which covers the sidewalls and bottom wall of the first patterned hole and the top surface of the first photoresist layer;

[0024] The second mask material layer covering the bottom wall of the first patterned hole is etched away, and the etched second mask material layer forms the second mask pattern in the first patterned hole.

[0025] In one embodiment, forming the second mask pattern includes:

[0026] A second sub-mask pattern is formed, the second sub-mask pattern extends along the second direction, and the second sub-mask patterns are arranged at intervals along the first direction;

[0027] The second mask pattern is formed on the sidewall of the second sub-mask pattern.

[0028] In one embodiment, the first mask pattern has a first size in the second direction, and adjacent first mask patterns have a second size;

[0029] The third mask pattern has a third dimension in the second direction, and there is a fourth dimension between adjacent third mask patterns;

[0030] The size of the second mask pattern in the second direction is greater than or equal to the first size, and the size of the fourth mask pattern in the second direction is greater than or equal to the third size;

[0031] The first dimension is smaller than the fourth dimension, and the third dimension is smaller than the second dimension.

[0032] In one embodiment, there is a first spacing between adjacent second mask patterns in the first direction;

[0033] There is a second spacing between adjacent fourth mask patterns in the first direction, and the first spacing and the second spacing are equal.

[0034] The method for fabricating the semiconductor structure of the present invention has the following beneficial effects:

[0035] The semiconductor structure fabrication method of the present invention splits the target pattern to be formed into a first target pattern and a second target pattern, and uses two processes to form the first target pattern and the second target pattern respectively, thereby reducing the pattern density of the first target pattern and the second target pattern, increasing the process window for forming the first target pattern and the second target pattern, and improving the pattern quality of the formed first target pattern and the second target pattern. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1This is a schematic diagram of a sub-mask pattern formed on a first mask material layer, provided as an exemplary comparative example.

[0038] Figure 2 This is a schematic diagram of the first mask pattern provided as an exemplary comparative example.

[0039] Figure 3 This is a schematic diagram showing the formation of the second and third mask patterns as an exemplary comparative example.

[0040] Figure 4 The second and third mask patterns provided as an exemplary comparative example are projections of the patterns formed on a substrate.

[0041] Figure 5 This is a schematic diagram of a first mask pattern formed as an example comparison.

[0042] Figure 6 This is a schematic diagram of an active region formed as an example comparison.

[0043] Figure 7 A flowchart illustrating a method for fabricating a semiconductor structure as provided in an exemplary embodiment.

[0044] Figure 8 A projection of a first submask pattern formed for an exemplary embodiment onto a substrate.

[0045] Figure 9 for Figure 8 A cross-sectional view of section AA.

[0046] Figure 10 A cross-sectional view of section AA after the formation of the first mask material layer, as an exemplary embodiment.

[0047] Figure 11 A cross-sectional view of section AA after forming the first mask pattern, as an exemplary embodiment.

[0048] Figure 12 A projection of a first mask pattern formed for an exemplary embodiment onto a substrate.

[0049] Figure 13 A projection of a second mask pattern formed for an exemplary embodiment onto a substrate.

[0050] Figure 14 A cross-sectional view of the BB section after the formation of the first photoresist layer, as an exemplary embodiment.

[0051] Figure 15 A cross-sectional view of the CC section after the formation of the first photoresist layer, as an exemplary embodiment.

[0052] Figure 16A cross-sectional view of the BB section after the second mask material layer has been formed, as an exemplary embodiment.

[0053] Figure 17 A cross-sectional view of the CC section after the second mask material layer has been formed, as an exemplary embodiment.

[0054] Figure 18 A cross-sectional view of the BB section after forming the second mask pattern, as an exemplary embodiment.

[0055] Figure 19 A cross-sectional view of the CC section after forming the second mask pattern, as shown in an exemplary embodiment.

[0056] Figure 20 A projection of a second mask pattern formed for an exemplary embodiment onto a substrate.

[0057] Figure 21 A cross-sectional view of the DD section after forming the second sub-mask pattern, as an exemplary embodiment.

[0058] Figure 22 A cross-sectional view of the DD section after the second mask material layer has been formed, as an exemplary embodiment.

[0059] Figure 23 A cross-sectional view of the DD section after the formation of the third sub-mask material layer, as an exemplary embodiment.

[0060] Figure 24 A cross-sectional view of the DD section after forming the second mask pattern, as an exemplary embodiment.

[0061] Figure 25 A cross-sectional view of the EE section after forming the second mask pattern, as shown in an exemplary embodiment.

[0062] Figure 26 A cross-sectional view of the DD section after forming the first target pattern, as an exemplary embodiment.

[0063] Figure 27 A cross-sectional view of the EE section after forming the first target pattern, as an exemplary embodiment.

[0064] Figure 28 A projection of a first target pattern formed in an exemplary embodiment onto a substrate.

[0065] Figure 29 A projection of a fourth submask pattern formed for an exemplary embodiment onto a substrate.

[0066] Figure 30 for Figure 29 A cross-sectional view of the FF section.

[0067] Figure 31A cross-sectional view of the FF section after the formation of the third mask material layer, as an exemplary embodiment.

[0068] Figure 32 A cross-sectional view of the FF section after forming the third mask pattern, as shown in an exemplary embodiment.

[0069] Figure 33 A projection of a third mask pattern formed for an exemplary embodiment onto a substrate.

[0070] Figure 34 A projection of a fourth mask pattern formed for an exemplary embodiment onto a substrate.

[0071] Figure 35 A projection of a fourth mask pattern formed for an exemplary embodiment onto a substrate.

[0072] Figure 36 A projection of a second target pattern formed on a substrate, as an exemplary embodiment.

[0073] Figure 37 for Figure 36 A cross-sectional view of the GG section.

[0074] Figure 38 for Figure 36 A cross-sectional view of the HH section.

[0075] Figure 39 A top view of the substrate after the active region has been formed, as an exemplary embodiment.

[0076] Explanation of reference numerals in the attached figures:

[0077] 10. Substrate; 101. Shallow trench; 102. Active region; 11. First target pattern; 12. Second target pattern; 120. First hard mask layer; 130. First sub-mask pattern; 140. First mask pattern; 141. First mask material layer; 150. First dielectric layer; 160. First photoresist layer; 161. First patterned hole; 220. Second hard mask layer; 230. Second sub-mask pattern; 240. Second mask pattern; 241. Second mask material layer; 250. Second dielectric layer; 331. Third sub-mask material layer; 340. Third mask pattern; 341. Third mask material layer; 430. Fourth sub-mask pattern; 440. Fourth mask pattern;

[0078] D1, First Direction; D2, Second Direction;

[0079] D1, first dimension; d2, second dimension; d3, third dimension; d4, fourth dimension; L1, first spacing; L2, second spacing;

[0080] 1' Substrate; 2' Hard mask layer; 3' First mask pattern; 31' First mask material layer; 4' Second mask pattern; 5' Third mask pattern; 7' Sub-mask pattern. Detailed Implementation

[0081] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0082] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0083] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0084] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0085] In current semiconductor manufacturing processes, self-aligned quadruple patterning (SAQP) is commonly used to form high-density, small-size devices. As semiconductor technology advances, the critical dimensions of semiconductor devices are required to become smaller and the integration density to become higher. However, SAQP uses a large number of masks, and the overlay accuracy between the masks is difficult to control. This results in pattern defects in the formed mask patterns, such as pattern breakdown, poor critical dimension uniformity (CDU), poor line edge roughness (LER), poor line width roughness (LWR), or poor pitch uniformity.

[0086] Taking the formation of an active region (AA) as an example, the following implementation method is used in the related art to form an active region:

[0087] First, refer to Figure 1 As shown, a substrate 1' is provided, and a hard mask layer 2' is formed on the top surface of the substrate 1'. A first mask material layer 31' is formed on the hard mask layer 2', covering the hard mask layer 2'. Sub-mask patterns 7' are formed on the first mask material layer 31', extending along a first direction D1 and spaced apart along a second direction D2 perpendicular to the first direction D1. (Refer to...) Figure 2 As shown, the first mask pattern 3' is formed by etching the first mask material layer 31' according to the sub-mask pattern 7'.

[0088] Next, refer to Figure 3 , Figure 4As shown, a self-aligned quadruple patterning technique is used to form a second mask pattern 4' and a third mask pattern 5' above a first mask pattern 3'. The second mask pattern 4' and the third mask pattern 5' intersect above the first mask pattern 3' to form a cross aperture. The first mask pattern 3' is etched according to the second mask pattern 4' and the third mask pattern 5', and the cross aperture is transferred to the first mask pattern 3', thereby dividing the first mask pattern 3' into target patterns.

[0089] In related technologies, a self-aligned quadruple patterning technique is used to form the second mask pattern 4' and the third mask pattern 5'. However, the linewidth uniformity, edge roughness, linewidth roughness, or pitch uniformity of the intersecting apertures formed by the second mask pattern 4' and the third mask pattern 5' are poor. The high pattern density and small size of the sub-mask pattern 7' may lead to "dog-tooth" defects at the top of the sub-mask pattern 7'. The first mask pattern 3' is usually formed from polysilicon, which has poor etching resistance. (Refer to...) Figure 2 or Figure 5 As shown in region A, the first mask pattern 3' may be tilted or adjacent first mask patterns 3' may be connected together. This may result in under-etching at the bottom of the tilted or connected positions of the first mask patterns 3' when etching the substrate 1' according to the target pattern. As shown in region B in 6, this affects the pattern quality of the formed active region, and the under-etching problem is difficult to alleviate by increasing the etching amount.

[0090] In view of this, this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a first mask pattern on the substrate, the first mask pattern extending along a first direction and the first mask patterns being spaced apart along a second direction perpendicular to the first direction; forming a second mask pattern, the second mask patterns being spaced apart above the first mask pattern along the first direction; etching the first mask pattern according to the second mask pattern to divide the first mask pattern into first target patterns spaced apart along the first direction; forming a third mask pattern above the first target patterns, the third mask pattern extending along the first direction and the third mask pattern being spaced apart along the second direction, wherein the projections of the first mask pattern and the third mask pattern formed on the substrate have no overlapping areas; forming a fourth mask pattern, the fourth mask pattern being spaced apart above the third mask pattern along the first direction; etching the third mask pattern according to the fourth mask pattern to divide the third mask pattern into second target patterns spaced apart along the first direction. This application splits the target pattern to be formed into a first target pattern and a second target pattern, and forms the first target pattern and the second target pattern in two different mask layers respectively, thereby reducing the pattern density of the first target pattern and the second target pattern and improving the pattern quality of the formed first target pattern and the second target pattern. For example, the first target pattern and the second target pattern have better line width uniformity, line edge roughness and line width roughness.

[0091] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 7 As shown, Figure 7 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 8-39 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 8-39 And refer to Figure 7 The method for fabricating the semiconductor structure in this embodiment will be introduced. This embodiment does not limit the semiconductor structure. The following will take the active region of the semiconductor structure as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.

[0092] like Figure 7 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0093] Step S110: Provide a substrate.

[0094] Step S120: A first mask pattern is formed on the substrate. The first mask pattern extends along a first direction and is spaced apart along a second direction perpendicular to the first direction.

[0095] Step S130: Form a second mask pattern, the second mask patterns being arranged at intervals above the first mask pattern along the first direction.

[0096] Step S140: Etch the first mask pattern according to the second mask pattern, and divide the first mask pattern into first target patterns arranged at intervals along the first direction.

[0097] Step S150: A third mask pattern is formed above the first target pattern. The third mask pattern extends along the first direction and is arranged at intervals along the second direction. The projections of the first mask pattern onto the substrate and the projections of the third mask pattern onto the substrate have no overlapping areas.

[0098] Step S160: Form a fourth mask pattern, which is arranged at intervals above the third mask pattern along the first direction.

[0099] Step S170: Etch the third mask pattern according to the fourth mask pattern, and divide the third mask pattern into second target patterns arranged at intervals along the first direction.

[0100] In step S110, refer to Figure 9 As shown, the substrate 10 can be a semiconductor substrate, which is made of semiconductor material. The semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials with semiconductor properties, such as gallium arsenide and other group III-V compounds.

[0101] Alternatively, substrate 10 can be other material layers used to form semiconductor devices, such as dielectric layers or metal layers. For example, substrate 10 can be an amorphous carbon layer, oxide layer, nitride layer, copper layer, tungsten layer, aluminum layer, etc., but is not limited to these.

[0102] Prior to step S120, the following steps were also performed: (Refer to...) Figure 8 , Figure 9 As shown, a first hard mask layer 120 is formed on the substrate 10. The first hard mask layer 120 can be formed by depositing a hard mask material using chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first hard mask layer 120 covers the top surface of the substrate 10. The material of the first hard mask layer 120 may include nitrides, oxides of nitride, or oxides; for example, the material of the first hard mask layer 120 may include silicon nitride. It is understood that the first hard mask layer 120 may include a single-layer or multi-layer structure.

[0103] In step S120, the first mask pattern is formed on the substrate, which can be implemented in the following ways:

[0104] Step S121: Form a first sub-mask pattern, which extends along a first direction and is spaced apart along a second direction.

[0105] First, a first sub-mask material layer (not shown in the figure) can be deposited using chemical vapor deposition or physical vapor deposition. The first sub-mask material layer covers the first hard mask layer 120 (see reference). Figure 9 The top surface of the first submask material layer may be made of at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0106] Then, a photoresist material layer (not shown in the figure) is formed on the top surface of the first sub-mask material layer. The photoresist material layer is then blocked by a light-shielding mask. The photoresist material layer is exposed and developed to transfer the mask pattern of the light-shielding mask into the photoresist material layer to form a photoresist mask. Then, the undeveloped photoresist material layer is removed.

[0107] Reference Figure 8 , Figure 9 As shown, the first sub-mask material layer is then etched according to the photoresist mask to form a plurality of first sub-mask patterns 130. The first sub-mask patterns 130 extend along the first direction D1 and are arranged at intervals along the second direction D2.

[0108] Step S122: Form a first mask material layer. The first mask material layer covers the sidewalls, top surface, and area between the first sub-mask patterns of the first sub-mask pattern. The first mask material layer includes a first material.

[0109] like Figure 10 As shown, refer to Figure 9 Atomic Layer Deposition (ALD) can be used to deposit a first material, which covers the exposed top surface of the first sub-mask pattern 130 and the first hard mask layer 120, forming a first mask material layer 141. Using ALD to form the first mask material layer 141 allows for more precise control over its thickness, resulting in a thinner layer that facilitates the formation of denser patterns.

[0110] The first material includes a semiconductor material, which is doped with a Group IIIA element. For example, the first material may include monocrystalline silicon or polycrystalline silicon, and may be doped with at least one of boron or aluminum. In this embodiment, the first material includes boron- or aluminum-doped polycrystalline silicon, which has better etching resistance.

[0111] Step S123: Remove the first mask material layer located on the top surface of the first sub-mask pattern and the first mask material layer located between the first sub-mask patterns, and cover the sidewalls of the first sub-mask pattern with the first mask material layer to form the first mask pattern.

[0112] like Figure 11 , Figure 12 As shown, refer to Figure 8 , Figure 10 The first mask material layer 141 is etched using an anisotropic etching process. The etching rate in the vertical direction is greater than the etching rate in the horizontal direction. This removes the first mask material layer 141 covering the top surface of the first sub-mask pattern 130 and the top surface of the first hard mask layer 120, thus forming the first mask pattern 140 by covering the sidewalls of the first sub-mask pattern 130. The first mask pattern 140 has a first dimension d1 in the second direction D2, and adjacent first mask patterns 140 have a second dimension d2.

[0113] In this embodiment, the first mask material layer 141 includes a first material, which is boron- or aluminum-doped polycrystalline silicon. The first material has good etching resistance. Thus, the upper and lower linewidths of the first mask pattern 140 formed after anisotropic etching are equal, and the pattern accuracy of the first mask pattern 140 is high with few pattern defects.

[0114] Next, the first sub-mask pattern 130 is etched away to expose the top surface of the first hard mask layer 120 between the first mask patterns 140.

[0115] In step S130, as Figure 13 Or such as Figure 20 As shown, a second mask pattern 240 is formed, and the second mask patterns 240 are spaced apart above the first mask pattern 140 along a first direction D1, with a first spacing L1 between adjacent second mask patterns 240 in the first direction D1. In some examples, such as Figure 13 As shown, the second mask pattern 240 can be patterned holes spaced apart along the second direction D2, or, in some examples, such as Figure 20 As shown, the second mask pattern 240 can be a linear pattern extending along the second direction D2.

[0116] In some embodiments, the second mask pattern 240 may be formed using the following implementation:

[0117] Step S131a: Form a first photoresist layer on top of the first mask pattern.

[0118] Figure 14 The image shows the BB after the formation of the first photoresist layer 160 (reference). Figure 13 ) Cross-sectional view of the section, Figure 15 The CC (reference) is shown after the formation of the first photoresist layer 160. Figure 13 (Cross-sectional view of the section)

[0119] like Figure 14 , Figure 15 As shown, firstly, a dielectric material is deposited to cover the first mask pattern 140 and fill the gaps between the first mask patterns 140, forming a first dielectric layer 150. A second hard mask layer 220 is then deposited, covering the top surface of the first dielectric layer 150. The material of the first dielectric layer 150 may include silicon oxide, and the material of the second hard mask layer 220 may include silicon nitride and / or silicon oxynitride. Next, a photoresist is coated onto the top surface of the second hard mask layer 220 to form a first photoresist layer 160.

[0120] Step S132a: Expose and develop the first photoresist layer to form a first patterned hole in the first photoresist layer.

[0121] like Figure 14 , Figure 15 As shown, the first photoresist layer 160 is exposed and developed to form a first patterned hole 161 in the first photoresist layer 160. Then, the undeveloped first photoresist layer 160 is removed.

[0122] In some embodiments, forming the second mask pattern further includes the following steps:

[0123] Step S133a: Form a second mask material layer, which covers the sidewalls and bottom wall of the first patterned hole and the top surface of the first photoresist layer.

[0124] like Figure 16 , Figure 17 As shown, refer to Figure 14 , Figure 15 The second mask material layer 241 can be deposited using an atomic layer deposition process. The second mask material layer 241 covers the sidewall of the first patterned hole 161, the top surface of the first photoresist layer 160, and the top surface of the second hard mask layer 220 exposed by the first patterned hole 161. The material of the second mask material layer 241 may include silicon oxide or silicon nitride.

[0125] Step S134a: Etch away the second mask material layer covering the bottom wall of the first patterned hole, and etch away the remaining second mask material layer to form a second mask pattern in the first patterned hole.

[0126] like Figure 18 , Figure 19 As shown, refer to Figure 16 , Figure 17The second mask material layer 241 is etched by an anisotropic etching process. The etching rate in the vertical direction is greater than that in the horizontal direction. The etching removes the second mask material layer 241 covering the top surface of the first photoresist layer 160 and the second mask material layer 241 covering the second hard mask layer 220. The second mask material layer 241 covering the sidewall of the first patterned hole 161 is etched and retained to form the second mask pattern 240.

[0127] Reference Figure 13 As shown, the second mask pattern 240 formed in this embodiment is a pattern hole. The second mask pattern 240 is arranged at intervals along the first direction D1 and the second direction D2. The size of the second mask pattern 240 in the second direction D2 is larger than the first size d1 of the first mask pattern 140 in the second direction D2, so that the first mask pattern 140 can be divided into first target patterns 11 that are independently and spaced along the first direction D1 (which will be described in detail in subsequent steps).

[0128] In other embodiments, the second mask pattern 240 can be formed in the following ways:

[0129] Step S131b: Form a second sub-mask pattern, the second sub-mask pattern extends along a second direction, and the second sub-mask patterns are arranged at intervals along a first direction.

[0130] Figure 21 The diagram shows the DD after the formation of the second sub-mask pattern 230 (reference). Figure 20 A cross-sectional view of the section, such as Figure 21 As shown, similarly, in this embodiment, a deposition medium material covers the first mask pattern 140 and fills the gaps between the first mask patterns 140 to form a first medium layer 150. Then, a second hard mask layer 220 is deposited to form, which covers the top surface of the first medium layer 150.

[0131] Then, a second sub-mask material layer (not shown in the figure) is formed on the second hard mask layer 220, and the second sub-mask material layer is etched to form the second sub-mask pattern 230 (e.g., ...). Figure 21 As shown), the second sub-mask pattern 230 extends along the second direction D2, and the second sub-mask patterns 230 are arranged at intervals along the first direction D1.

[0132] Step S132b: Form a second mask pattern on the sidewall of the second sub-mask pattern.

[0133] like Figure 22 As shown, refer to Figure 21First, a second mask material layer 241 is formed, which covers the top surface and sidewalls of the second sub-mask pattern 230 and the top surface of the second hard mask layer 220 located between the second sub-mask patterns 230.

[0134] like Figure 23 As shown, refer to Figure 22 Then, a third sub-mask material layer 331 is deposited to form a third sub-mask material layer 331, which covers the second mask material layer 241 and fills the unfilled areas between the second sub-mask patterns 230.

[0135] Figure 24 The DD (reference) after forming the second mask pattern 240 is shown. Figure 20 ) Cross-sectional view of the section, Figure 25 The EE after forming the second mask pattern 240 is shown (reference). Figure 20 A cross-sectional view of the section, such as Figure 24 , Figure 25 As shown, refer to Figure 23 Next, the third sub-mask material layer 331 is ground until the top surface of the second mask material layer 241 is exposed. The second mask material layer 241 covering the sidewalls of the second sub-mask pattern 230 is etched away, and the second mask pattern 240 is formed in the area where the second mask material layer 241 is removed.

[0136] Reference Figure 20 As shown, the second mask pattern 240 formed in this embodiment is a linear pattern extending along the second direction D2, which can ensure that when the first mask pattern 140 is etched according to the second mask pattern 240, the second mask pattern 240 is transferred into the first mask pattern 140, and the first mask pattern 140 can be divided into first target patterns 11 that are independently and spaced along the first direction D1 (which will be described in detail in subsequent steps).

[0137] In step S140, as Figure 26 , Figure 27 , Figure 28 As shown, refer to 13. Figure 20 Using the second mask pattern 240 as a mask, the second hard mask layer 220, the first dielectric layer 150, and the first mask pattern 140 are etched layer by layer to remove the second hard mask layer 220, the first dielectric layer 150, and the first mask pattern 140 exposed by the second mask pattern 240 until the surface of the first hard mask layer 120 is exposed. The second mask pattern 240 is then transferred into the first mask pattern 140, and the first mask pattern 140 is divided into first target patterns 11 spaced along the first direction D1.

[0138] In step S150, the implementation of forming the third mask pattern 340 in this embodiment is the same as the implementation of forming the first mask pattern 140 in step S120.

[0139] First, refer to Figure 30 As shown, a second dielectric layer 250 is formed, which fills the gaps between the first target patterns 11 and covers the first target patterns 11. (Refer to...) Figure 29 , Figure 30 As shown, a fourth sub-mask pattern 430 is then formed on the second dielectric layer 250. The fourth sub-mask pattern 430 extends along the first direction D1 and is spaced apart along the second direction D2. Next, referring to... Figure 31 As shown, a third mask material layer 341 is formed, which covers the sidewalls and top surface of the fourth sub-mask pattern 430 and the top surface of the second dielectric layer 250. Then, the third mask material layer 341 covering the top surface of the fourth sub-mask pattern 430 and the third mask material layer 341 covering the top surface of the second dielectric layer 250 are etched away. (Refer to...) Figure 32 , Figure 33 As shown, the third mask material layer 341 on the sidewall of the fourth sub-mask pattern 430 forms the third mask pattern 340.

[0140] The material of the third mask pattern 340 includes a first material, which includes a semiconductor material and is doped with a Group IIIA element. For example, the first material may include monocrystalline silicon or polycrystalline silicon, and may be doped with at least one of boron or aluminum. In this embodiment, the first material includes boron- or aluminum-doped polycrystalline silicon, which has better etching resistance. The third mask pattern 340 formed in this embodiment has equal upper and lower linewidths, and the pattern accuracy and defects of the third mask pattern 340 are high.

[0141] In this embodiment, refer to Figure 12 , Figure 33 As shown, the projections of the first mask pattern 140 onto the substrate 10 and the third mask pattern 340 onto the substrate 10 have no overlapping areas. For example, the projections of the first mask pattern 140 onto the substrate 10 and the third mask pattern 340 onto the substrate 10 can be arranged at intervals according to a preset rule, or the projection of the first mask pattern 140 onto the substrate 10 may fall on one region of the substrate 10, and the projection of the third mask pattern 340 onto the substrate 10 may fall on another region of the substrate 10.

[0142] In this embodiment, along the second direction D2, the projections of the first mask pattern 140 onto the substrate 10 and the projections of the third mask pattern 340 onto the substrate 10 are arranged alternately. The third mask pattern 340 has a third dimension d3 in the second direction D2, and adjacent third mask patterns 340 have a fourth dimension d4. The first dimension d1 is smaller than the fourth dimension d4, and the third dimension d3 is smaller than the second dimension d2. This ensures that the projection of the first mask pattern 140 onto the substrate 10 is located between the projections of two adjacent third mask patterns 340 onto the substrate 10, and the projection of the third mask pattern 340 onto the substrate 10 is located between the projections of two adjacent first mask patterns 140 onto the substrate 10, forming a dense pattern array.

[0143] In step S160, the implementation of forming the fourth mask pattern 440 in this embodiment is the same as the implementation of forming the second mask pattern 240 in step S130. (Refer to...) Figure 34 or Figure 35 As shown, the fourth mask pattern 440 is spaced above the third mask pattern 340 along the first direction D1. Adjacent fourth mask patterns 440 along the first direction D1 have a second spacing L2, and the first spacing L1 and the second spacing L2 are equal. The dimension of the fourth mask pattern 440 in the second direction D2 is larger than the third dimension d3 of the third mask pattern 340 in the second direction D2. The fourth mask pattern 440 can be a pattern of holes spaced apart along the second direction D2, or it can be a linear pattern extending along the second direction D2.

[0144] In step S170, refer to Figure 36 , Figure 37 , Figure 38 As shown, the third mask pattern 340 is etched using the fourth mask pattern 440 as a mask, and the fourth mask pattern 440 is transferred into the third mask pattern 340, thereby dividing the third mask pattern 340 into second target patterns 12 arranged at intervals along the first direction D1.

[0145] In some embodiments, the projections of the second mask pattern 240 onto the substrate 10 and the projections of the fourth mask pattern 440 onto the substrate 10 have no overlapping areas. Thus, the first target pattern 11 and the second target pattern 12 formed in this embodiment are spaced apart and staggered.

[0146] The semiconductor structure fabrication method of this embodiment splits the target pattern to be formed into a first target pattern and a second target pattern, and uses two similar processes to form the first target pattern and the second target pattern respectively. This reduces the pattern density of the first target pattern and the second target pattern, increases the process window for forming the first target pattern and the second target pattern, and improves the pattern quality of the formed first target pattern and the second target pattern. For example, the linewidth uniformity, line edge roughness, and linewidth roughness of the first target pattern and the second target pattern are better. At the same time, the use of two similar processes to form the first target pattern and the second target pattern in this embodiment reduces the fabrication difficulty and reduces the number of mask layers used in the fabrication process to less than 20 layers, thus saving process costs.

[0147] The semiconductor structure fabrication method of this embodiment uses a first material to form a first mask pattern. The first material has good etching resistance, ensuring that the formed first mask pattern has equal width at the top and bottom, without structural defects. This avoids the problem of the first mask pattern being tilted or adjacent first mask patterns being connected together, thus preventing the problem of under-etching at the bottom due to tilting or adhesion of the first mask pattern. Similarly, this embodiment uses the first material to fabricate a third mask pattern, avoiding the problem of the third mask pattern being tilted or adjacent first mask patterns being connected together, thus preventing the problem of under-etching at the bottom due to tilting or adhesion of the third mask pattern. As a result, the first target pattern and the second target pattern formed in this embodiment have higher pattern accuracy, which can reduce the pattern defects formed by subsequent etching of the substrate based on the first target pattern and the second target pattern, and improve the accuracy and clarity of the pattern formed in the substrate.

[0148] The semiconductor structure fabrication method of this embodiment employs Self-Aligned Double Pattern (SADP) to form a first mask pattern, and then uses SADP to form a second mask pattern on top of the first mask pattern. The second mask pattern is then transferred into the first mask pattern to form a first target pattern. SADP can achieve excellent linewidth and pitch control. Thus, the first target pattern formed in this embodiment has better linewidth uniformity, line edge roughness, linewidth roughness, and pitch uniformity. Similarly, the second target pattern formed in this embodiment has better linewidth uniformity, line edge roughness, linewidth roughness, and pitch uniformity. The first and second target patterns can form a pattern array with higher quality and greater density.

[0149] According to an exemplary embodiment, this embodiment is a description of the above embodiments. This embodiment includes all the steps of the above embodiments. The difference between this embodiment and the above embodiments is that, after step S170, this embodiment further performs the following steps:

[0150] Step S180: Etch the substrate according to the first target pattern and the second target pattern.

[0151] In this embodiment, refer to Figure 26 , Figure 36 , Figure 39 As shown, a first hard mask layer 120 is patterned according to a first target pattern 11 and a second target pattern 12 to transfer the first target pattern 11 and the second target pattern 12 into the first hard mask layer 120. Then, the substrate 10 is etched according to the patterned first hard mask layer 120 to remove a portion of the substrate 10 and form shallow trenches 101 in the substrate 10. The shallow trenches 101 divide the substrate 10 into active regions 102 arrayed along the first direction D1.

[0152] The semiconductor structure fabrication method of this embodiment reduces the problems of adhesion of the first mask pattern and the third mask pattern, and avoids the problem of under-etching at the bottom of the adhesion position of the first mask pattern or the adhesion position of the third mask pattern during the etching process of the substrate according to the first target pattern and the second target pattern. This improves the morphology of the formed active region, and the linewidth uniformity, line edge roughness, linewidth roughness and pitch uniformity of the active region are better.

[0153] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The method comprises the following steps: providing a substrate; forming a first mask pattern on the substrate, the first mask pattern extending along a first direction, the first mask pattern being spaced apart along a second direction perpendicular to the first direction; forming a second mask pattern, the second mask pattern being spaced apart above the first mask pattern along the first direction; etching the first mask pattern according to the second mask pattern, the first mask pattern being divided into first target patterns spaced apart along the first direction; forming a third mask pattern above the first target patterns, the third mask pattern extending along the first direction, the third mask pattern being spaced apart along the second direction, the first mask pattern and the third mask pattern having no overlapping area on the substrate; forming a fourth mask pattern, the fourth mask pattern being spaced apart above the third mask pattern along the first direction; etching the third mask pattern according to the fourth mask pattern, the third mask pattern being divided into second target patterns spaced apart along the first direction; the first mask pattern has a first size in the second direction, and a second size between adjacent first mask patterns; the third mask pattern has a third size in the second direction, and a fourth size between adjacent third mask patterns; a size of the second mask pattern in the second direction is greater than or equal to the first size, and a size of the fourth mask pattern in the second direction is greater than or equal to the third size; the first size is smaller than the fourth size, and the third size is smaller than the second size.

2. The method of fabricating a semiconductor structure of claim 1, wherein, In the second direction, the first mask pattern and the third mask pattern are alternately arranged on the substrate.

3. The method of fabricating a semiconductor structure of claim 2, wherein, The second mask pattern and the fourth mask pattern have no overlapping area on the substrate.

4. The method of fabricating a semiconductor structure of claim 1, wherein, The method comprises the following steps: forming a first mask pattern, comprising: forming a first sub-mask pattern, the first sub-mask pattern extending along the first direction and being spaced apart along the second direction; forming a first mask material layer covering a side wall, a top surface of the first sub-mask pattern and a region between the first sub-mask patterns, the first mask material layer comprising a first material; 5. The method of fabricating a semiconductor structure of claim 4, wherein, removing the first mask material layer on the top surface of the first sub-mask pattern and the first mask material layer between the first sub-mask patterns, the first mask material layer covering the side wall of the first sub-mask pattern forming the first mask pattern.

6. The method of fabricating a semiconductor structure of claim 1, wherein, The first material comprises a semiconductor material, and the first material is doped with a group IIIA element. The method comprises the following steps: forming a second mask pattern, comprising:

7. The method of fabricating a semiconductor structure of claim 6, wherein, forming a first photoresist layer above the first mask pattern; exposing and developing the first photoresist layer to form a first pattern hole in the first photoresist layer. The method for forming a second mask pattern further comprises: forming a second mask material layer covering the sidewall and the bottom wall of the first pattern hole and the top surface of the first photoresist layer; etching to remove the second mask material layer covering the bottom wall of the first pattern hole, and the remaining second mask material layer is reserved to form the second mask pattern in the first pattern hole.

8. The method of fabricating a semiconductor structure of claim 1, wherein, forming a second mask pattern, comprising: forming a second sub-mask pattern, the second sub-mask pattern extending along the second direction, and the second sub-mask pattern being arranged at intervals along the first direction; forming the second mask pattern on the sidewall of the second sub-mask pattern.

9. The method of fabricating a semiconductor structure of claim 1, wherein, the first interval between the second mask patterns adjacent in the first direction; the second interval between the fourth mask patterns adjacent in the first direction, and the first interval and the second interval being equal.

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