Wafer overlay marking, overlay measurement system and related methods

Abstract

The invention relates to wafer overlay marking and overlay measurement systems and related methods. A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of overlay marks with a direction in which an illumination source emits light at the wafer and to align other portions of the lines of the pattern in a direction perpendicular to the direction in which the illumination source emits light at the wafer and extension. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining a contrast of a region of the overlay mark and determining a location of the overlay mark. The overlay mark includes a pattern defining a column array. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of the column and in a second, different direction within a second region of the column.

Description

[0001] Divisional application

[0002] This application is a divisional application of the invention patent application with application date of December 18, 2020, application number 202011508435.9, and invention name “Wafer overlay mark, overlay measurement system and related methods”.

[0003] Cross Reference

[0004] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 719,366, filed on December 18, 2019, for “Wafer Overlay Marks, Overlay Measurement Systems, and Related Methods.” Technical Field

[0005] The present disclosure generally relates to wafer overlay marks and overlay measurement systems. In addition, the present disclosure relates to overlay marks that include continuous patterns with minimal to no interruptions. Background Art

[0006] A lithographic apparatus is a machine that applies a desired pattern to a substrate, typically to a target portion of a bulk semiconductor substrate (e.g., a semiconductor wafer). For example, a lithographic apparatus may be used in the manufacture of semiconductor devices. In the example, a patterning device, referred to in the art as a mask or reticle, may be used to generate a circuit pattern to be formed on a die location from individual material levels on the active surface of the wafer. This pattern may be transferred to a target portion (e.g., a portion including one or several die locations) on a wafer (e.g., a silicon wafer). Pattern transfer is typically achieved by imaging onto a layer of radiation-sensitive material (i.e., photoresist) disposed on the wafer. In general, the wafer will contain a grid of adjacent target portions corresponding to successively patterned die locations. In the lithographic process, it is often desirable to frequently measure the features (i.e., structures) produced and their locations on the wafer, such as for process control and verification. Various tools are known for making such measurements, including scanning electron microscopes (which are typically used to measure critical dimensions (CDs)) and tools for measuring overlay (measuring the accuracy of alignment of two layers in a semiconductor device). Overlay can be described in terms of the degree of misalignment between two layers, for example, a measured overlay with reference to 1 nm can describe a scenario where the two layers are laterally misaligned by up to 1 nm. Conventional optical methods of measuring overlay typically include using an optical microscope and measuring spectra and / or diffraction patterns. Additional conventional optical methods of measuring overlay typically include measuring overlay with captured images from an optical microscope. Conventional overlay marks typically incorporate pattern interruptions (areas that do not contain a pattern) to create optical contrast. However, pattern interruptions are typically destroyed during processing, which adversely affects overlay measurements. Summary of the invention

[0007] One or more embodiments of the present disclosure include a method of determining an overlay measurement (e.g., positional offset) between a level of interest of a wafer and a reference level of the wafer. The method may include orienting a wafer within an overlay metrology measurement system (e.g., rotating the wafer on a wafer chuck) to align a portion of a line of a pattern of overlay marks with a direction in which an illumination source of the overlay metrology measurement system emits light (e.g., radiation) at the wafer. Further, orienting the wafer may include aligning other portions of the line of the pattern of overlay marks to extend in a direction perpendicular to the direction in which the illumination source of the overlay metrology measurement system emits light at the wafer. The method further includes emitting light at the wafer via the illumination source, and capturing at least one image of the wafer via an imager sensor of the overlay metrology measurement system. The method also includes determining a contrast of an area of ​​the overlay mark based at least in part on the capturing of at least one image, and determining a position of the overlay mark based on the determined contrast. Further, the method may include determining a position of the overlay mark of the reference level of the wafer and a position of the overlay mark of the level of interest of the wafer via the method described above. Furthermore, based on the determined position of the overlay mark, the overlay metrology measurement system may determine a position offset between the reference level and the level of interest of a wafer.

[0008] Some embodiments of the present disclosure include an overlay mark for determining a positional offset between the reference level and the level of interest of a wafer. The overlay mark may include a pattern defining an array of columns, each column including a set of parallel bar marks, wherein each bar mark is separated from an adjacent bar mark by a spacing mark. In addition, the pattern within each column of the array of columns may include a set of lines oriented parallel to each other and extending in a first direction within each bar mark of the corresponding column and in a second different direction within each spacing mark of the corresponding column. Each line of the set of lines may be continuous and may extend from an uppermost region of the corresponding column to a lowermost region of the corresponding column. In addition, the first direction may be perpendicular to the second direction.

[0009] One or more embodiments of the present disclosure include an overlay metrology measurement system. The overlay metrology measurement system may include: a substrate support for supporting a wafer; an illumination source for emitting light at the wafer in a first direction; an imager sensor configured to at least identify a location of a visible element on the wafer; and a controller operably coupled to the substrate support, the imager sensor, and the illumination source. The controller may include at least one processor and at least one non-transitory computer-readable storage medium storing instructions thereon, the instructions causing the controller, when executed by the at least one processor, to: cause the supporting substrate to rotate the wafer relative to a default position to: align a line of a first region of a pattern of overlay marks on a reference level of the wafer with the first direction; and cause a line of a second region of the pattern of overlay marks adjacent to the first region to extend in a second direction perpendicular to the first direction; cause the illumination source to emit light at the wafer in the first direction; cause the imager sensor to capture at least one image of the wafer; and based at least in part on the capturing of at least one image, distinguish between the first region and the second region of the pattern of overlay marks based on a detected contrast of the first region and the second region of the overlay marks.

[0010] Further embodiments of the present disclosure include methods of forming a pattern of overlay marks on a wafer. The method may include forming bar marks of a column of overlay marks and forming space marks of a column of overlay marks. Forming the bar marks of the column may include forming parallel lines extending from a first lateral end of a respective column to a second opposite lateral end of the respective column. Forming the space marks of the column may include forming parallel segmentation lines extending from the first lateral end of the respective column to the second opposite lateral end of the respective column between adjacent bar marks. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a detailed understanding of the present disclosure, reference should be made to the following detailed description in conjunction with the accompanying drawings, in which the same reference numerals are generally used to indicate the same elements, and in which:

[0012] Figure 1 A schematic diagram illustrating an overlay metrology measurement system according to one or more embodiments of the present disclosure;

[0013] Figure 2A is a simplified top view of a wafer according to one or more embodiments of the present disclosure;

[0014] Figure 2B is a simplified top view of a portion of a wafer having an overlay mark formed thereon according to one or more embodiments of the present disclosure;

[0015] Figure 2Cis a simplified illustration of an overlay mark as detected by an imager sensor according to one or more embodiments of the present disclosure;

[0016] Figure 3A is a schematic diagram of a pattern of a portion (e.g., a column) of an overlay mark according to one or more embodiments of the present disclosure;

[0017] Figure 3B is a schematic representation of a contrast curve as determined by an overlay metric measurement system;

[0018] Figure 4A is a schematic diagram of a pattern of a portion (e.g., a column) of an overlay mark according to one or more embodiments of the present disclosure;

[0019] Figure 4B is a schematic representation of a contrast curve as determined by an overlay metric measurement system;

[0020] Figure 5A is a schematic diagram of a pattern of a portion (e.g., a column) of an overlay mark according to one or more embodiments of the present disclosure;

[0021] Figure 5B is a schematic representation of a contrast curve as determined by an overlay metric measurement system;

[0022] Figure 5C yes Figure 5A An enlarged partial view of the pattern of the overlay markings.

[0023] Figure 5D yes Figure 5C an enlarged partial view of a pattern;

[0024] Figure 5E yes Figure 5A a design view of a portion of a pattern;

[0025] Fig. 6A is a schematic diagram of a pattern of a portion (e.g., a column) of an overlay mark according to one or more embodiments of the present disclosure;

[0026] Figure 6B is a schematic representation of a contrast curve as determined by an overlay metric measurement system;

[0027] Figure 7 is a flow chart of a method for determining an overlay measurement between a reference level and a level of interest of a wafer according to one or more embodiments of the present disclosure;

[0028] Figure 8 is a flow chart of a method for forming an overlay mark according to one or more embodiments of the present disclosure;

[0029] Fig. 9is a flow chart of a method for forming an overlay mark according to one or more embodiments of the present disclosure; and

[0030] Fig.10 is a flow chart of a method for forming an overlay mark according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] The illustrations presented herein are not actual views of any overlay measurement system, overlay markers, or any of their components, but are merely idealized representations, which are used to describe embodiments of the present invention.

[0032] As used herein, the singular forms following “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0033] As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that it is expected to be used in implementing an embodiment of the present disclosure, and this term is used in preference to the more restrictive term "is" to avoid implying that other compatible materials, structural features, or methods that may be used in conjunction therewith should or must be excluded.

[0034] As used herein, any relational terms (e.g., "first," "second," "above," "upper," etc.) are used for clarity and convenience in understanding the present disclosure and the accompanying drawings, and do not imply or rely on any particular preference or order, unless the context clearly indicates otherwise. For example, these terms may refer to the orientation of an overlay measurement system, an overlay mark, a wafer, and / or an element of a wafer clamp in a conventional orientation. In addition, these terms may refer to the orientation of an overlay measurement system, an overlay mark, a wafer, and / or an element of a wafer clamp as illustrated in the accompanying drawings.

[0035] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes to the extent that one of ordinary skill in the art would understand that the given parameter, property, or condition is satisfied with a small degree of variation (e.g., within acceptable manufacturing tolerances). For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 95.0% satisfied, at least 99.0% satisfied, or even at least 99.9% satisfied.

[0036] As used herein, the term "about" used in reference to a given parameter is inclusive of the stated value and has the meaning dictated by the context (eg, it includes the degree of error associated with measurement of the given parameter, as well as variations caused by manufacturing tolerances, etc.).

[0037] As used herein, the term "wafer" means and includes materials on and in which structures including micrometer- and nanometer-scale feature sizes are partially or completely fabricated. Such materials include conventional semiconductor (e.g., silicon) wafers, as well as other semiconductor materials and bulk substrates of other materials. For convenience, such materials will be referred to as "wafers" hereinafter. Example structures formed on such materials may include, for example, integrated circuits (active and passive), MEMS devices, and combinations thereof.

[0038] Many details of specific embodiments are described below with reference to semiconductor devices. The term "semiconductor device" is used throughout to include various manufactured articles, including, for example, individual integrated circuit dies, imager dies, sensor dies, and / or dies with other semiconductor features. Embodiments of the apparatus and processes described below can be used to measure the overlay between layers of materials of components including integrated circuits on a wafer and individual dies or dies singulated from the wafer accordingly. The wafer (e.g., in the form of a semiconductor device) can be unsingulated silicon including die locations or a carrier wafer refilled with previously singulated dies. The refilled carrier wafer can include a viscous molding compound (e.g., a flexible adhesive) surrounded by a generally rigid frame having a peripheral shape equivalent to the peripheral shape of the device wafer, and the laterally separated singulated elements (e.g., dies) are surrounded by the molding compound.

[0039] Some embodiments of the present disclosure include an overlay metrology measurement system configured for determining an overlay measurement (e.g., measuring overlay) between a level of interest of a wafer and a reference level of a semiconductor device substrate (e.g., a wafer or other bulk substrate including semiconductor material). The overlay metrology measurement system may utilize an optical microscope imaging or scatterometry system to determine the location of an overlay mark (e.g., an optically detectable overlay mark) on a level of interest (referred to herein as a "level of interest") of a semiconductor device (e.g., a top material level of a semiconductor device that overlays one or more other levels). For example, a registration system may utilize an optical microscope imaging or scatterometry system to optically determine the location of an overlay mark or other element (e.g., a conductive via end) on an exposed surface of a wafer or through a transparent or translucent material. Furthermore, while a particular optical microscope imaging or scatterometry system is described herein, the present disclosure is not limited thereto, and the overlay metrology measurement system may include any conventional optical scanner for locating visible overlay marks and performing overlay measurements. Additionally, the overlay metrology measurement system may utilize optical microscope imaging or a scatterometry system to determine the position of an overlay mark placed within a lower level (e.g., referred to herein as a “reference level”) of the wafer. Furthermore, based on the determined positions of the overlay marks of the reference level and the overlay marks of the level of interest, the overlay metrology measurement system may determine to calculate a position offset (e.g., and an overlay measurement) between the level of interest and the reference level of the wafer.

[0040] One or more embodiments of the present disclosure include a method of determining an overlay measurement (e.g., positional offset) between a level of interest of a wafer and a reference level of the wafer. The method may include orienting a wafer within an overlay metrology measurement system (e.g., rotating the wafer on a wafer chuck) to align a portion of a line of a pattern of overlay marks with a direction in which an illumination source of the overlay metrology measurement system emits light (e.g., radiation) at the wafer. Further, orienting the wafer may include aligning other portions of the line of the pattern of overlay marks to extend in a direction perpendicular to the direction in which the illumination source of the overlay metrology measurement system emits light at the wafer. The method further includes emitting light at the wafer via the illumination source, and capturing at least one image of the wafer via an imager sensor of the overlay metrology measurement system. The method also includes determining a contrast of an area of ​​the overlay mark based at least in part on the capturing of at least one image, and determining a position of the overlay mark based on the determined contrast. Further, the method may include determining a position of the overlay mark of the reference level of the wafer and a position of the overlay mark of the level of interest of the wafer via the method described above. Furthermore, based on the determined position of the overlay mark, the overlay metrology measurement system may determine a position offset between the reference level and the level of interest of a wafer.

[0041] Some embodiments of the present disclosure include an overlay mark for determining a positional offset between the reference level and the level of interest of a wafer. The overlay mark may include a pattern defining an array of columns, each column including a set of parallel bar marks, wherein each bar mark is separated from an adjacent bar mark by a spacing mark. In addition, the pattern within each column of the array of columns may include a set of lines oriented parallel to each other and extending in a first direction within each bar mark of the corresponding column and in a second different direction within each spacing mark of the corresponding column. Each line of the set of lines may be continuous and may extend from an uppermost region of the corresponding column to a lowermost region of the corresponding column. In addition, the first direction may be perpendicular to the second direction.

[0042] The overlay marks and patterns for forming overlay marks described herein are superior to conventional overlay marks and patterns. For example, conventional overlay marks typically include interruptions in the pattern (e.g., missing patterns) to assist in distinguishing portions of the pattern (e.g., bar marks) when optically detected. However, these interruptions (or the edges of the pattern defining the interruptions) are typically destroyed during conventional processing. The destroyed interruptions adversely affect subsequent overlay measurements. However, the overlay marks and patterns for forming overlay marks of the present disclosure do not include the interruptions described above and are at least substantially continuous. In addition, due to the shapes and designs described herein, the patterns maintain detectability and distinguishability (e.g., optical contrast) of portions of the pattern when scanned by an imager system. Therefore, because the overlay marks and patterns for forming overlay marks of the present disclosure do not require interruptions for detecting portions of the overlay marks, the overlay marks and patterns for forming overlay marks of the present disclosure can provide more robust and reliable overlay marks that can withstand subsequent processing better than conventional overlay marks. Therefore, the overlay mark and pattern for forming the overlay mark of the present disclosure may result in more accurate overlay measurement, which leads to better processing and higher quality semiconductor devices.

[0043] Figure 1 is a schematic diagram of an overlay metrology measurement system 100 according to one or more embodiments of the present disclosure. As shown, the overlay metrology measurement system 100 may be configured as a lithography system with additional components, as described herein, but the present disclosure is not limited thereto. The overlay metrology measurement system 100 may be used to align semiconductor devices, determine overlay measurements of a wafer and perform registration (e.g., alignment) operations on a semiconductor wafer in process relative to a processing tool, and if configured for additional functions (e.g., exposing materials through photolithography of a mask), then perform processes for semiconductor manufacturing on the wafer. Thus, it will be appreciated that the present technology is not limited to the overlay metrology measurement system itself, but is also applicable to semiconductor processing tools that require accurate overlay measurements of wafers. As a non-limiting example, the present technology may also be used in processes and systems for proper alignment in laser cutting and drilling tools, saws, 3-D printing tools, and other processes that require overlay marking and overlay measurements between various materials (e.g., layers) of a wafer in process. To illustrate, the overlay metrology measurement system 100 includes an optical microscope imaging or scatterometry system that includes an image sensor 102, an illumination source 103, a condenser lens 104, a polarizer 110, and a substrate support 112 arranged in series. As described above, some of the above-described components enable the overlay metrology measurement system 100 to perform processing actions.

[0044] As in Figure 1, the controller 118 is operably coupled to the image sensor 102, the illumination source 103, the condenser 104, the polarizer 110, and the substrate (eg, wafer) support 112 of the overlay metrology measurement system 100 for monitoring or controlling the operation of these components. Figure 1 1 , but the overlay metrology measurement system 100 may also include a substrate transfer station, structural supports (e.g., polarizer supports, etc.), position sensors (e.g., scatterometers), immersion hoods, support actuators (e.g., motors), and / or other suitable mechanical and / or electrical components. In general, the controller 118 may be configured to control the movement of the wafer and / or components of the overlay metrology measurement system 100 before, during, and / or after a semiconductor manufacturing process. For example, the wafer 114 may undergo photoresist deposition, patterning via a light source and a mask, development, baking, cleaning, and / or other suitable processing, and the overlay metrology measurement system 100 may be used to measure overlay and / or align the wafer 114 and / or tools or other components associated with the overlay metrology measurement system 100 before, during, and / or after these processes.

[0045] The controller 118 may include a processor 120 coupled to a memory 122 and an input / output component 124. The processor 120 may include a microprocessor, a field programmable gate array, and / or other suitable logic devices. The memory 122 may include volatile and / or non-volatile media (e.g., ROM, RAM, magnetic disk storage media, optical storage media, flash memory devices, and / or other suitable storage media) and / or other types of computer-readable storage media configured to store data. The memory 122 may store algorithms for alignment, edge detection, filters, shape recognition, determining optical contrast detected by the image sensor 102 for execution by the processor 120. In some embodiments, the processor 120 may be configured to send data to a computing device (e.g., a server or a personal computer) operably coupled (e.g., via the Internet) to the controller 118. The input / output component 124 may include a display, a touch screen, a keyboard, a mouse, and / or other suitable types of input / output devices configured to accept input from an operator and provide output to the operator.

[0046] In some embodiments, the overlay metrology measurement system 100 may utilize an image sensor 102 to capture light reflected from a wafer and send the captured image data to a controller 118 where the image data is stored in a memory 122, processed by a processor 120, and / or sent to an input / output component 124. In some embodiments, the image sensor 102 may be configured to capture radiation that is not in the visible spectrum, such as UV light or infrared radiation. Alternatively, the image sensor 102 may be configured to capture imaging data of the wafer in both the visible and non-visible radiation spectrums and send such imaging data to the controller 118. Although Figure 1 , but image sensor 102 may include a lens, an aperture, an image sensing element, a digital signal processor, and an analog or digital output. Figure 1 Image sensor 102 is shown above illumination source 103 in , but in some embodiments, image sensor 102 may be laterally spaced from substrate support 112 and a mirror may be positioned to reflect light representative of the wafer surface topography into image sensor 102 .

[0047] Additionally, illumination source 103 may include an ultraviolet light source (e.g., a fluorescent lamp), a laser source (e.g., an argon fluoride excimer laser), and / or other suitable electromagnetic radiation emitting sources. In certain embodiments, illumination source 103 may be configured to produce substantially coherent illumination at a single frequency. In other embodiments, illumination source 103 may also be at least partially incoherent. In further embodiments, illumination source 103 may also be configured to produce illumination at multiple frequencies.

[0048] The condenser mirror 104 and the polarizer 110 may be used to project radiation (e.g., a radiation pattern) onto the wafer 114. In some embodiments, the polarizer 110 may be configured to polarize radiation (e.g., light) from the illumination source 103 before the radiation reaches the wafer 114. For example, the overlay metrology measurement system 100 may include at least a portion of the optical scanner described in U.S. Pat. No. 9,748,128 to Zhao et al., issued on August 29, 2017.

[0049] As described in more detail below, the overlay metrology measurement system 100 may utilize an optical microscope imaging or scatterometry system (e.g., image sensor 102) to determine the location of an overlay mark (e.g., an optically detectable overlay mark) on a level of interest (referred to herein as a "level of interest") of a semiconductor device (e.g., a top material level of a semiconductor device that overlays one or more other levels). For example, the overlay metrology measurement system 100 may utilize an optical microscope imaging or scatterometry system (e.g., image sensor 102) to determine the location of an overlay mark or other element (e.g., a conductive via end) on an exposed surface of a wafer or through a transparent or translucent material via conventional optical methods. Furthermore, while a particular optical microscope imaging or scatterometry system (e.g., image sensor 102) is described herein, the present disclosure is not limited thereto, and the overlay metrology measurement system 100 may include any conventional optical scanner for locating visible overlay marks and performing overlay measurements.

[0050] Furthermore, the overlay metrology measurement system 100 may utilize the determined positions of the overlay marks within the reference level of the wafer 114 and the determined positions of the overlay marks in the level of interest (obtained via optical microscope imaging or a scatterometry system) to calculate a positional offset between the level of interest and the reference level (i.e., an overlay measurement).

[0051] The substrate support 112 may be configured to carry and / or move the wafer 114. The substrate support 112 (which may also be characterized as a platform or stage) may include a vacuum chuck, a mechanical chuck, and / or other suitable support devices. Figure 1 , but the overlay metrology measurement system 100 may include at least one actuator configured to move the substrate support 112 laterally (as indicated by the X-axis), laterally (as indicated by the Y-axis), and / or vertically (as indicated by the Z-axis) relative to the response sensor 132 and / or other components of the optical overlay metrology measurement system 100. As used herein, Figure 1 The X-axis, Y-axis, and Z-axis depicted in FIG. 1 define a Cartesian space. In certain embodiments, the substrate support 112 may also include a position monitor (not shown) such as a linear encoder configured to monitor the position of the substrate support 112 along the X-axis, Y-axis, and / or Z-axis. Additionally, a rotary encoder may be used to monitor the rotational position of the wafer about the Z-axis. Even in Figure 11 , but in certain embodiments, the overlay metrology measurement system 100 may include two, three, or any desired number of substrate supports having structures and / or functions substantially similar to or different from the substrate support 112, such that multiple wafers may be quickly moved into and out of alignment with the rest of the metrology measurement system 100. In operation, according to aspects of the present invention, a controller 118 may be used to position the substrate support 112 to properly align the wafer 114 with a tool or other component associated with the overlay metrology measurement system 100.

[0052] Figure 2A is a schematic top view of a wafer 114 according to one or more embodiments of the present disclosure. Figure 2B is an enlarged schematic diagram of a portion of the wafer 114 (eg, a semiconductor device, a singulated portion of the wafer 114 , etc.) having one or more overlay marks 204 formed thereon in accordance with one or more embodiments of the present disclosure. Figure 2C is an enlarged schematic diagram of the overlay mark 204 as detected via an optical imager system (eg, imager sensor 102 ) according to one or more embodiments of the present disclosure.

[0053] Reference together Figures 2A to 2C In some embodiments, the overlay marks 204 may be formed on a reference level and / or a level of interest of the wafer 114. For example, the reference level of the wafer 114 may include a first set of overlay marks 204 placed within the reference level of the wafer 114 and the level of interest may include a second set of overlay marks 204 formed in or on the level of interest of the wafer 114. In some embodiments, one or more additional levels may be placed between the level of interest and the reference level. Furthermore, as is known in the art, overlay measurements may be performed by determining a centroid of the overlay marks 204 on the reference level and a centroid of the associated overlay marks 204 on the level of interest and determining an offset between the centroids.

[0054] In one or more embodiments, each overlay mark 204 may include a pattern of material and / or absence of material defining an array 206 of columns 208, the columns 208 including a set of parallel bar marks 210 extending in a direction perpendicular to the height of the respective columns 208 and having spacer marks 211 defined between adjacent bar marks 210. In other words, each column 208 may include a stack of bar marks 210 and spacer marks 211. In some embodiments, the upper region 212 of the overlay mark 204 may include a plurality of parallel bar marks 210 extending in a direction perpendicular to the height of the respective columns 208. Figure 2C One or more rows 208 (e.g., two adjacent rows) extending in the second direction 216 (in the orientation depicted in FIG. Figure 2CIn addition, the lower area 218 of the overlay mark 204 may also include one or more columns (e.g., two adjacent columns) extending in the first direction 214 (in the horizontal direction). Figure 2C One or more rows 208 (e.g., two adjacent rows) extending in the second direction 216 (in the orientation depicted in FIG. Figure 2C The overlay mark 204, the row 208, the bar mark 210 and the space mark 211 are described below with respect to Figures 3A to 5D Describe in more detail.

[0055] In one or more embodiments, the overlay mark 204 may include (e.g., may be formed of) conventional materials for an overlay mark 204 that is detectable and visible via a conventional optical scanner. Furthermore, the overlay mark 204 may be formed via conventional systems. For example, the overlay mark 204 may include one or more of a fill material, a recess, a plating, or any other type of structure commonly used to form an overlay mark 204. However, as described with respect to Figures 3A to 5D Discussed in further detail, the structures and patterns used to form the overlay mark 204 of the present disclosure can minimize discontinuities in the pattern while maintaining contrast (ie, optical contrast) variability within the overlay mark 204, which improves durability of the overlay mark while maintaining detectability of the overlay mark.

[0056] Figure 3A An example pattern 302 (eg, a light spatial pattern) of bar marks 310 defining columns 308 of overlay marks is shown. Figure 3B The display can be viewed via an imaging system (e.g., Figure 1 image sensor 102) and through image capture and image analysis from Figure 3A306a, 306b, 306c, 306d, etc. along the length of the height of the column 208. In some embodiments, the set of lines 304 may extend longitudinally at a first angle relative to the longitudinal axis of the column 308 in the first region 306a, and the set of lines 304 may extend longitudinally at a second angle relative to the longitudinal axis of the column 308 in the adjacent region 306b. In some embodiments, the first angle may be 45° and the second angle may be 135°. In view of the foregoing, the set of lines 304 may extend in a first direction in the first region 306a, and extend in a second, different direction in the second, adjacent region 306b, wherein the first direction is perpendicular to the second, different direction. Additionally, the angle at which the lines 304 extend may alternate between the regions 306. In view of the foregoing, each line of the set of lines 304 may have a periodic shape.

[0057] Still refer to Figure 3AAs described in further detail below, the overlay metrology measurement system 100 may utilize polarization (and / or polarization effects) to detect and distinguish portions of the pattern 302. Specifically, in operation, the overlay metrology measurement system 100 (e.g., the illumination source 103 of the overlay metrology measurement system 100) may emit light at the wafer 114 in a direction parallel to the direction in which the set of lines 304 extend within the second, adjacent region 306b (or the first region 306a) of the pattern 302. Thus, the set of lines 304 within the first region 306a (or the second, adjacent region 306b) may extend in a direction perpendicular to the direction in which the light was emitted at the wafer 114. Furthermore, extending portions of the set of lines 304 in a direction parallel to the direction in which the light was emitted at the wafer 114 and extending other portions of the set of lines 304 in a direction perpendicular to the direction in which the light was emitted at the wafer 114 may produce a polarization effect in the light detection imager sensor of the overlay metrology measurement system 100. For example, the pattern 302 of the overlay mark may act as a polarizing filter and / or have a polarizing effect on reflected light. In such embodiments, light emitted at the wafer 114 in a direction parallel to the set of lines 304 is reflected back and / or diffracted normally, while light emitted at the wafer 114 in a direction perpendicular to the set of lines 304 is at least partially absorbed and / or reflected back and / or diffracted differently, thereby producing a detected contrast difference between portions of the set of lines 304. In view of the foregoing, via polarization, the overlay metrology measurement system 100 changes the detectable contrast of the second, adjacent region 306b (or the first region 306a) to below or nearly below a detectable level, and changes the detectable contrast of the first region 306a (or the second, adjacent region 306b) to an increased level.

[0058] In one or more embodiments, the overlay metrology measurement system 100 may emit linearly polarized light at the wafer 114. In additional embodiments, the overlay metrology measurement system 100 may include a polarizing filter that polarizes reflected light detected by the imager sensor 102. In further embodiments, a portion of the light reflected by the wafer 114 may be polarized (e.g., due to reflected polarization).

[0059] In view of the foregoing, a first level of contrast may be identified (e.g., detected) in an area where the set of lines 304 (e.g., a collection of bar marks) extends in a direction perpendicular to the direction in which light is emitted at the wafer 114, and a second level of contrast may be identified (e.g., detected) in an area where the set of lines 304 (e.g., a collection of bar marks) extends in a direction parallel to the direction in which light is emitted at the wafer 114. Thus, as described in more detail herein, when detected via the imager sensor 102, an area where the lines 304 of the pattern 302 defining a collection of bar marks (e.g., columns 308) extend in a first direction may be distinguished from an area where the lines 304 of the pattern 302 defining the collection of bar marks extend in a second direction. For example, in Figure 3B The scanning process can be performed by the scanner Figure 3A 308 of overlay marks detected by the overlay metrology measurement system 100. Furthermore, as described in more detail below, using the contrast curve for each column 308 of overlay marks, the overlay metrology measurement system 100 can determine the location of the centroid of the overlay marks, and can use the location of the centroid to perform overlay measurements between levels of the wafer 114.

[0060] In view of the foregoing, in operation, the illumination source 103 may emit light at the wafer 114, and the image sensor 102 (e.g., an optical microscope) may detect (e.g., capture) an image of the overlay mark (e.g., light returning to the image sensor 102). In addition, the overlay metrology measurement system 100 may measure / determine the contrast level across the scan distance by analyzing the image of the overlay mark to determine a contrast curve via conventional methods. In one or more embodiments, a region 306a having a line 304 extending at a first angle may be detected as a first region having a first contrast, wherein the first region has a shape that is the same as the shape of the region 306a, and a region 306b having a line 304 extending at a second angle may be detected as a second region having a second, different contrast, wherein the second region has a shape that is the same as the shape of the region 306b. Due to the different contrasts, the shape and position of the region 306 may be detected and determined, and as discussed in more detail below, the overlay mark (e.g., Figure 2C Moreover, in some examples, when the lines defining the outer fill portion 307 (e.g., the area surrounding and spaced apart from the column 308) extend in a direction parallel to the direction in which light is emitted at the wafer 114, the outer fill portion 307 can become undetectable or nearly undetectable via contrast detection.

[0061] Still refer to Figure 3A In some embodiments, one or more regions 306 of the pattern of overlay marks 302 may be detected by the overlay metrology measurement system 100 as bar marks 310 (eg, Figure 2C For example, in some embodiments, regions 306 having lines 304 extending at a first angle may be detected as bar marks 310 (e.g., similar in shape to bar marks 310), and regions 306 having lines 304 extending at a second angle may be detected as spaces between bar marks 310.

[0062] In one or more embodiments, the regions 306 may have at least substantially equal widths in a direction along the height of the columns 308. In addition, at least some of the lines 304 may be at least substantially continuous from an uppermost region to a lowermost region of the regions 306. For example, at least some of the lines 304 may extend from one longitudinal end of the columns 308 to another longitudinal end of the columns 308. Thus, the pattern 302 may be at least substantially continuous from an uppermost region to a lowermost region of the columns 308. In one or more embodiments, the regions 306 (e.g., a pattern of overlay marks) may be separated from the remainder of the pattern of the wafer 114 by an interruption of the pattern (e.g., the absence of any pattern).

[0063] Figure 4A An example pattern 402 (eg, a light spatial pattern) of bar marks 410 defining columns 408 of overlay marks is shown. Figure 4B The display can be viewed via an imager system (e.g., Figure 1 The imager sensor 102) from Figure 4A Example contrast curve of overlay mark detection. Similar to the above Figure 3A and 3B 302, pattern 402 may be formed on wafer 114 (e.g., transferred to wafer 114) via any conventional method, and pattern 402 may include a set of lines 404 oriented parallel to each other. The set of lines 404 may define adjacent regions 406a, 406b, 406c, 406d, etc. along the length of the height of column 408. In some embodiments, the set of lines 404 may extend longitudinally at a first angle relative to the longitudinal axis of the column in the first region 406a, and the set of lines 404 may extend longitudinally at a second angle relative to the longitudinal axis of the column in the adjacent region 406b. In some embodiments, the first angle may be 45° and the second angle may be 135°. In view of the foregoing, the set of lines 404 may extend in a first direction in the first region 406a, and extend in a second, different direction in the adjacent region 406b, wherein the first direction is perpendicular to the second, different direction. In addition, the angle at which the lines 404 extend may alternate between regions 406. In view of the foregoing, each line of the set of lines 404 may have a periodic shape.

[0064] Same as above about Figure 3A and 3BIn the manner described, the overlay metrology measurement system 100 can utilize polarized light (and / or polarized light effects) to detect the pattern 402. For example, the overlay metrology measurement system 100 can utilize polarized light to detect contrast levels of regions 406a, 406b, 406c, 406d, etc. of the set of lines 404, and can determine a contrast curve representing the row 408.

[0065] In some embodiments, one or more of the regions 406 of the pattern 402 may be detected by the overlay metrology measurement system 100 as bar marks 410. For example, in some embodiments, regions 406 having lines 404 extending at a first angle may be detected as bar marks 410, and regions 406 having lines 404 extending at a second angle may be detected as spaces between the bar marks 410.

[0066] In one or more embodiments, the regions 406 representing the bar marks 410 may have at least substantially equal widths along the direction of the height of the columns 408. In addition, the width of the regions 406 between the regions 406 representing the bar marks 410 (i.e., the spacing regions) may be less than the width of the regions 406 representing the bar marks 410. In addition, at least some of the lines 404 may be at least substantially continuous from the uppermost region to the lowermost region of the regions 406. For example, at least some of the lines 404 may extend from one longitudinal end of the columns 408 to the other longitudinal end of the columns 408. Thus, the pattern 402 may be at least substantially continuous from the uppermost region to the lowermost region of the columns 408. In one or more embodiments, the regions 406 (e.g., the pattern 402 of the overlay marks) may be separated from the remainder of the pattern of the wafer 114 by an interruption of the pattern 402 (e.g., the absence of any pattern).

[0067] Figure 5A An example pattern 502 (eg, a light spatial pattern) of bar marks 510 defining columns 508 of overlay marks is shown in accordance with one or more embodiments of the present disclosure. Figure 5B The display can be viewed via an imager system (e.g., Figure 1 The imager sensor 102) from Figure 5A Example contrast curves for overlay mark detection. Figure 5C An enlarged view of a portion of bar marks 510 and a portion of space marks 511 of pattern 502 is shown. Figure 5D exhibit Figure 5C A further enlarged view of a portion of the bar mark 510 and the spacer mark 511. Figure 5E A schematic diagram depicting a design of a portion of pattern 502 .

[0068] Reference together Figures 5A to 5EIn some embodiments, the pattern 502 may include bar marks 510 separated by spacing marks 511. Each bar mark 510 may include parallel lines 514 (e.g., a plurality of parallel lines) extending from a first lateral side of the column 508 to an opposite, second lateral side of the column 508. In one or more embodiments, the parallel lines 504 may extend in a direction perpendicular to the height of the column 508. In some embodiments, the spacing between the parallel lines 504 may be less than the width of the parallel lines 504 themselves, such that the pattern 502 within the bar mark 510 is substantially continuous along the width of the bar mark 510.

[0069] In addition, each spacing mark 511 may include parallel segment lines 506. Each segment line 516 may include a segment 518. In addition, the segment 518 of each segment line 516 may be aligned with the associated segment 518 of other segment lines 516 of the corresponding spacing mark 511. Therefore, the set of associated segments between the parallel segment lines 516 may form a corresponding column 508. In one or more embodiments, the longitudinal length of each segment 518 of each segment line 516 may be significantly longer than the spacing between adjacent segments 518. For example, each segment 518 may have a longitudinal length in the range of about 0.20 μm and about 0.25 μm. For example, each segment 518 may have a longitudinal length in the range of about 0.217 μm and about 0.240 μm. In some embodiments, the length of the segment 518 may vary. For example, the length of the outer segment (i.e., the segment near the parallel line 514) may be shorter, and the length of the inner segment (i.e., the segment away from the parallel line 514) may be longer. In addition, the distance between adjacent segments 518 may be in the range of about 0.08 μm and about 0.10 μm. For example, the distance between adjacent segments 518 may be about 0.0945 μm. In addition, the distance between the last parallel line 504 of the bar mark 510 and the first segment line 516 of the spacing mark 511 may be a distance greater than the distance between adjacent parallel lines 504 of the bar mark 510 and the distance between adjacent segment lines 516 of the spacing mark 511. In some embodiments, the distance between adjacent parallel lines 504 of the bar mark 510 may vary. However, there is no interruption of the pattern 502 between the bar mark 510 and the spacing mark 511 within the pattern 502.

[0070] The pattern 502 may be formed on the wafer 114 (e.g., transferred to the wafer 114) via any conventional method. In addition, the pattern 502 may include conventional materials for overlay marks that are detectable and visible via conventional optical scanners and formed by conventional methods. For example, the pattern 502 may include fill materials, grooves, plating, or any other type of structure commonly used to form overlay marks 204.

[0071] In one or more embodiments, when scanned via conventional methods and when identifying / determining the contrast curve of the pattern 502 of the column 508 of overlay marks, the difference in the pattern 502 of the bar marks 510 and the pattern 502 of the space marks 511 can produce a distinguishable level of contrast between the bar marks 510 and the space marks 511, as shown in FIG. Figure 5B However, because the spacing between adjacent parallel lines 504, the spacing between adjacent segment lines 506, and the spacing between parallel lines and segment lines are constant, the pattern is at least generally continuous and does not include any interruptions in the pattern that could be easily damaged during processing.

[0072] Fig. 6A An example pattern 602 (eg, a light spatial pattern) of conventional bar marks 610 defining columns 608 of overlay marks is shown in accordance with one or more embodiments of the present disclosure. Figure 6B The display can be viewed via an imager system (e.g., Figure 1 The imager sensor 102) from Fig. 6A 602 may include conventional bar marks 610, but may have an extended fill pattern 612 that contacts and at least substantially fills the spaces between the conventional bar marks 610. The conventional bar marks 610 may include parallel lines. The pattern 602 may be described above with respect to Figures 3A to 5E The pattern 602 may be formed by any of the methods and means described herein, and may include any of the materials and pattern structures described herein. In addition, the pattern 602 may be scanned and detected by any of the methods described herein.

[0073] Figure 7 A flow chart is shown of an example method 700 for detecting the location of overlay marks and for determining an overlay measurement in accordance with one or more embodiments of the present disclosure.

[0074] In some embodiments, the method 700 may include causing the overlay metrology measurement system 100 ( Figure 1 ) of the wafer chuck, such as in Figure 7 In one or more embodiments, the wafer may have an overlay mark formed on a reference level of the wafer and a level of interest of the wafer. For example, the overlay mark may include the Figures 3A to 4B In particular, the overlay mark may include a light spatial pattern of bar marks defining a column. Furthermore, the pattern may include a set of lines defining adjacent regions, wherein the lines extend at a first angle relative to the longitudinal axis of the column within the region representing the bar marks, and wherein the lines extend longitudinally at a second angle relative to the longitudinal axis of the column region representing the spaces between the marks. The first and second angles may include those described above with respect to Figures 3A to 4B Any angle of description.

[0075] In some embodiments, rotating the wafer may include rotating the wafer about the central axis by an angle relative to a default position (e.g., a default position of a wafer chuck). For example, rotating the wafer may include rotating the wafer by an angle equal to the angle described above with respect to Figure 3A and 4A For example, rotating the wafer may include rotating the wafer 45°. In other embodiments, rotating the wafer may include rotating the wafer 15°, 30°, 60°, 75°, 90°, or any other angle. In one or more embodiments, the wafer may be rotated to a position such that light emitted by the overlay metrology measurement system 100 (described below) will be emitted in a direction perpendicular to the portion of the line of the pattern extending at the first angle and in a direction parallel to the portion of the line of the pattern extending at the second angle. Alternatively, instead of or in addition to rotating the wafer, the method 700 may also include rotating the overlay metrology measurement system 100 ( Figure 1 ) is rotated so that polarized light emitted by the overlay metrology measurement system 100 (described below) will be emitted in a direction perpendicular to a portion of the line of the pattern extending at a first angle and in a direction parallel to a portion of the line of the pattern extending at a second angle.

[0076] Method 700 may further include emitting light at the wafer, such as at Figure 7 . For example, as mentioned above, the overlay metrology measurement system 100 may emit light at the wafer in a direction perpendicular to the portion of the line of the pattern of overlay marks extending at a first angle and in a direction parallel to the portion of the line of the pattern of overlay marks extending at a second angle. The light may include any type of light and / or radiation described above.

[0077] After emitting light at the wafer, method 700 may include capturing image data (eg, at least one image) of the wafer, such as in Figure 7 For example, the overlay metrology measurement system 100 may capture at least one image of the wafer via an imager sensor (eg, imager sensor 102) via any conventional means.

[0078] Based at least in part on the at least one captured image of the wafer, method 700 may include determining a contrast curve of an overlay mark of the wafer, such as in Figure 7 For example, the overlay metrology measurement system 100 may determine the contrast curve of the overlay mark on the reference level of the wafer and the contrast curve of the related overlay mark on the level of interest of the wafer through conventional methods.

[0079] After determining a contrast curve for the overlay mark of the wafer, method 700 may include determining a location of a centroid of the overlay mark based at least in part on the contrast curve, such as in Figure 7, which is shown in action 710 of . For example, the overlay metrology measurement system 100 may determine the location of the centroid of the first overlay mark on the reference level of the wafer and the location of the centroid of the second overlay mark on the level of interest of the wafer via conventional methods. In other embodiments, the overlay metrology measurement system 100 may identify the side, edge, point, or any other feature of the overlay mark. Furthermore, based on the determined location of the centroid and / or feature of the overlay mark, the location and orientation of the overlay mark may be calculated and determined.

[0080] In response to determining the location of the centroid of the overlay mark (or any other feature), the method may include calculating a position offset (e.g., an overlay measurement) between a level of interest and a reference level of the wafer, such as in Figure 7 7, 2008. The method 700 is shown in action 712 of . For example, based on the location of the centroids (or any other features) of the first overlay mark of the reference level and the second overlay mark of the level of interest, the overlay metrology measurement system 100 may calculate or may be used to calculate a position offset via conventional methods. As non-limiting examples, the method 700 may include calculating a position offset based on the two overlay marks via any of the methods described in U.S. Pat. No. 6,779,171 to Baggenstoss, issued Aug. 17, 2004, U.S. Pat. No. 6,778,275 to Bowes, issued Aug. 17, 2004, and / or U.S. Pat. No. 7,463,367 to Bowes, issued Dec. 9, 2008. In addition to calculating the offset, various mathematical models may be applied to interpolate and extrapolate the obtained data to generate a geometric model of the overlay.

[0081] In some embodiments, Figure 7 Any of actions 702 to 712 may be repeated multiple times to calculate the position offset between the level of interest and the reference level of the wafer. In some embodiments, further overlay marks may be applied to higher levels of interest, and may be repeated. Figure 7 Actions 702 to 712 are performed to recalibrate wafer alignment and perform further overlay measurements. Empirical data when processing a given batch of wafers can be used to determine the most useful frequency and level for performing overlay measurements according to the present disclosure.

[0082] Additionally, the method 700 may include adjusting future semiconductor manufacturing processes on the wafer based on the calculated positional offset (i.e., overlay measurement). For example, the overlay metrology measurement system 100 may be used to adjust relative wafer and tool positions in future processes, such as forming capping material levels, patterning, etching, etc., based on the calculated positional offset via conventional methods.

[0083] Figure 8A flow chart showing an exemplary method 800 for forming an overlay mark on a wafer according to one or more embodiments of the present disclosure. In some embodiments, the method 800 may include forming at least one line of a pattern on a wafer to extend in a first direction within a first area of ​​the pattern, such as in Figure 8 802 of . For example, the lithography system may form at least one line of a pattern of overlay marks on the surface of the wafer. In one or more embodiments, the first direction may extend at an angle relative to a longitudinal axis of a column of the pattern. The first angle may be in a range of 0° to 90°. For example, the first angle may be approximately 45°.

[0084] In some embodiments, forming a pattern on a wafer may include depositing a material on a wafer by conventional methods, forming a groove in a wafer by conventional methods, electroplating the wafer by conventional methods, a dry etching process, a thin film deposition process, a chemical mechanical polishing process, etc. For example, in some embodiments, the pattern on the wafer may include a fill material or any other conventional material. In some embodiments, forming a pattern on a wafer may include multiple steps separated by one or more other processes. For example, a portion of a pattern may be formed downstream of a first step of forming a pattern.

[0085] The method 800 may further include forming at least one line of the pattern on the wafer to extend in a second direction in a second area adjacent to the first area of ​​the pattern, such as in Figure 8 804 of . For example, the lithography system may form at least one line of the pattern of the overlay mark on the surface of the wafer. In addition, the second direction may be perpendicular to the first direction. Therefore, a portion of the at least one line of the pattern within the first area may form a 90° angle with a portion of the at least one line of the pattern within the second area. In addition, the second direction may extend at an angle relative to the longitudinal axis of the column of the pattern. The second angle may be in the range of 90° to 180°. For example, the first angle may be approximately 135°.

[0086] In one or more embodiments, the second region may be immediately adjacent to the first region in the direction of the longitudinal axis of the row design of the pattern. Furthermore, in some embodiments, the first and second regions may have substantially the same width along the longitudinal axis of the row design of the pattern. In other embodiments, the first and second regions may have different (e.g., variable) widths along the longitudinal axis of the row design of the pattern.

[0087] Additionally, method 800 may include repeating actions 802 and 804 to form a set of adjacent regions defining a row of patterns, such as in Figure 8806 of . For example, the lithography system may repeat actions 802 and 804 to form a set of adjacent regions to define a row of patterns. In addition, the direction of at least one line of the pattern may alternate across the regions. For example, at least one line may extend in a first direction within a first region, extend in a second direction within a second region, extend in a first direction within a third region, extend in a second direction within a fourth region, and so on. Furthermore, repeating actions 802 and 804 may include forming at least one line to continuously extend across the regions of the row of patterns. Likewise, repeating actions 802 and 804 may include forming at least one line to have a periodic shape.

[0088] Referring to actions 802 to 806 together, in some embodiments, method 800 may include forming a set of parallel lines according to actions 802 to 806 to define Figures 3A to 4B Describes the bar and space markings.

[0089] Fig. 9 A flow chart showing an exemplary method 900 for forming an overlay mark on a wafer according to one or more embodiments of the present disclosure. In some embodiments, the method 900 may include forming a plurality of parallel lines of a pattern in a first region of the pattern on the wafer, such as in Fig. 9 902 of . For example, the lithography system may form a plurality of parallel lines of a pattern of overlay marks on the surface of the wafer. In some embodiments, the plurality of parallel lines may extend from a first lateral side of a column design of the pattern to an opposite, second lateral side of the column design of the pattern. In one or more embodiments, forming the parallel lines may include forming parallel lines extending in a direction perpendicular to the height of the column design. In some embodiments, forming the parallel lines may include forming parallel lines with spaces therebetween that are less than a width of the parallel lines themselves, such that the pattern formed by the parallel lines is substantially continuous throughout the first region.

[0090] In one or more embodiments, method 900 may include forming a plurality of parallel segment lines of the pattern in a second region of the pattern on a wafer, such as in Fig. 9 904 of . For example, the lithography system may form a plurality of parallel segment lines of a pattern of overlay marks on the surface of the wafer. In some embodiments, the plurality of segmented parallel lines may extend from a first lateral side of a row design of the pattern to an opposite, second lateral side of the row design of the pattern. In one or more embodiments, forming the parallel segment lines may include forming the parallel segment lines such that a segment of each segment line is aligned with an associated segment of other segment lines within the second region. Additionally, forming the parallel segment lines may include forming the parallel segment lines such that a longitudinal length of each segment of each segment line is significantly longer than a spacing between adjacent segments of the segment lines.

[0091] Additionally, action 904 may include forming parallel segment lines on the surface of the wafer such that the segment lines in the second region are parallel to the parallel lines of the first region. Furthermore, action 904 may include forming the parallel segment lines such that the distance between adjacent parallel lines of the first region and the segment lines of the second region may be the same distance as the distance between adjacent parallel lines of the first region and the distance between adjacent segment lines of the second region. Thus, there is no interruption of the pattern between the first region (e.g., bar marks) and the second region (e.g., spaced marks).

[0092] In one or more embodiments, the second region may be immediately adjacent to the first region in the direction of the longitudinal axis of the row design of the pattern. Furthermore, in some embodiments, the first and second regions may have substantially the same width along the longitudinal axis of the row design of the pattern. In other embodiments, the first and second regions may have different (e.g., variable) widths along the longitudinal axis of the row design of the pattern.

[0093] In some embodiments, method 900 may include repeating actions 902 and 904 to form a set of adjacent regions defining a row of patterns, such as in Fig. 9 906 of . For example, the lithography system may repeat acts 902 and 904 to form a set of adjacent regions to define a column of the pattern. In some embodiments, the lithography system may form a plurality of parallel lines in a first region, a plurality of parallel segmented lines in a second region, a plurality of parallel lines in a third region, a plurality of parallel segmented lines in a fourth region, and so on. Furthermore, repeating acts 902 and 904 may include forming a pattern that is at least substantially continuous across regions of the column without interruptions in the pattern between regions.

[0094] Referring to actions 902 through 906 together, in some embodiments, method 900 may include forming a pattern to define a Figures 5A to 5E Describes the bar and space markings.

[0095] Fig.10 1 is a flow chart showing an exemplary method 1000 for forming an overlay mark on a wafer according to one or more embodiments of the present disclosure. In some embodiments, the method 1000 may include forming at least two parallel bar marks on a wafer, such as Fig.10 1002 is shown in FIG. For example, the photolithography system may form at least two parallel strip marks on the wafer. In one or more embodiments, the photolithography system may form at least two parallel strip marks according to conventional methods.

[0096] The method 1000 may further include forming an extended fill pattern between at least two parallel bar marks, such as Fig.101004. For example, the lithography system may form an extended fill pattern between at least two parallel bar marks. In one or more embodiments, act 1004 may include forming an extended fill pattern that contacts each of the at least two parallel bar marks and at least substantially fills a space between adjacent bar marks of the at least two parallel bar marks.

[0097] Additionally, method 1000 may include repeating actions 1002 and 1004 to form a set of adjacent bar markers defining a column, such as in Fig. 9 For example, the lithography system may repeat actions 1002 and 1004 to form the Fig. 6A and 6B Describes the bar markings and extended fill pattern.

[0098] Reference together Figures 1 to 10 , the overlay marks and patterns for forming overlay marks described herein are superior to conventional overlay marks and patterns. For example, conventional overlay marks typically include interruptions in the pattern (e.g., the absence of the pattern) to assist in distinguishing portions of the pattern (e.g., bar marks). However, these interruptions (or the edges of the pattern defining the interruptions) are typically destroyed during conventional processing. The destroyed interruptions adversely affect overlay measurements. However, the overlay marks and patterns for forming overlay marks of the present disclosure do not include the interruptions described above and are at least substantially continuous. In addition, due to the shapes and designs described herein, the patterns maintain detectability and distinguishability (e.g., optical contrast) of portions of the pattern when scanned by an imager system. Therefore, because the overlay marks and patterns for forming overlay marks do not require interruptions for detecting portions of the overlay marks, the overlay marks and patterns for forming overlay marks of the present disclosure can provide more robust and reliable overlay marks that can withstand processing better than conventional overlay marks. Therefore, the overlay mark and pattern for forming the overlay mark of the present disclosure may result in more accurate overlay measurement, which leads to better processing and higher quality semiconductor devices.

[0099] One or more embodiments of the present disclosure include a method of determining an overlay measurement (e.g., positional offset) between a level of interest of a wafer and a reference level of the wafer. The method may include orienting a wafer within an overlay metrology measurement system (e.g., rotating the wafer on a wafer chuck) to align a portion of a line of a pattern of overlay marks with a direction in which an illumination source of the overlay metrology measurement system emits light (e.g., radiation) at the wafer. Further, orienting the wafer may include aligning other portions of the line of the pattern of overlay marks to extend in a direction perpendicular to the direction in which the illumination source of the overlay metrology measurement system emits light at the wafer. The method further includes emitting light at the wafer via the illumination source, and capturing at least one image of the wafer via an imager sensor of the overlay metrology measurement system. The method also includes determining a contrast of an area of ​​the overlay mark based at least in part on the capturing of at least one image, and determining a position of the overlay mark based on the determined contrast. Further, the method may include determining a position of the overlay mark of the reference level of the wafer and a position of the overlay mark of the level of interest of the wafer via the method described above. Furthermore, based on the determined position of the overlay mark, the overlay metrology measurement system may determine a position offset between the reference level and the level of interest of a wafer.

[0100] Some embodiments of the present disclosure include an overlay mark for determining a positional offset between the reference level and the level of interest of a wafer. The overlay mark may include a pattern defining an array of columns, each column including a set of parallel bar marks, wherein each bar mark is separated from an adjacent bar mark by a spacing mark. In addition, the pattern within each column of the array of columns may include a set of lines oriented parallel to each other and extending in a first direction within each bar mark of the corresponding column and in a second different direction within each spacing mark of the corresponding column. Each line of the set of lines may be continuous and may extend from an uppermost region of the corresponding column to a lowermost region of the corresponding column. In addition, the first direction may be perpendicular to the second direction.

[0101] One or more embodiments of the present disclosure include an overlay metrology measurement system. The overlay metrology measurement system may include: a substrate support for supporting a wafer; an illumination source for emitting light at the wafer in a first direction; an imager sensor configured to at least identify a location of a visible element on the wafer; and a controller operably coupled to the substrate support, the imager sensor, and the illumination source. The controller may include at least one processor and at least one non-transitory computer-readable storage medium storing instructions thereon, the instructions, when executed by the at least one processor, causing the controller to: cause the supporting substrate to rotate the wafer relative to a default position to: align a line of a first region of a pattern of overlay marks on a reference level of the wafer with the first direction; and cause a line of a second region of the pattern of overlay marks adjacent to the first region to extend in a second direction perpendicular to the first direction; cause the illumination source to emit light at the wafer in the first direction; cause the imager sensor to capture at least one image of the wafer; and based at least in part on the capturing of at least one image, distinguish the first region from the second region of the overlay mark based on a detected contrast of the first region and the second region of the overlay mark.

[0102] Further embodiments of the present disclosure include methods of forming a pattern of overlay marks on a wafer. The method may include forming bar marks of a column of overlay marks and forming space marks of a column of overlay marks. Forming the bar marks of the column may include forming parallel lines extending from a first lateral end of a respective column to a second opposite lateral end of the respective column. Forming the space marks of the column may include forming parallel segmentation lines extending from the first lateral end of the respective column to the second opposite lateral end of the respective column between adjacent bar marks.

[0103] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0104] Embodiment 1. A method comprising: orienting a wafer to align lines of a first area of ​​a pattern of an overlay mark with a direction in which an illumination source emits light at the wafer; emitting light at the wafer via the illumination source; capturing at least one image of the wafer via an imager sensor; and determining, based at least in part on the at least one captured image, a contrast of a second area of ​​the pattern of the overlay mark in which lines of the pattern are not aligned with the direction in which the illumination source emits light at the wafer, and determining a contrast of the first area of ​​the pattern of the overlay mark.

[0105] Embodiment 2. The method of embodiment 1, wherein orienting the wafer comprises rotating the wafer by approximately 45° relative to a default position of the wafer so as to align the line of the first region of the pattern of the overlay mark with the direction in which the illumination source emits light at the wafer.

[0106] Embodiment 3. The method of any one of embodiments 1 and 2, wherein orienting the wafer comprises rotating the wafer by about 45° relative to a default position of the wafer so that the lines of the second region of the pattern of the overlay mark extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer.

[0107] Embodiment 4. The method of any one of embodiments 1 to 3, further comprising determining a location of a centroid of the overlay mark based at least in part on the determined contrast of the first and second regions.

[0108] Embodiment 5. The method of embodiment 4, further comprising determining a position offset of the overlay mark relative to another registered overlay mark formed on another level of the wafer based at least in part on the determined position of the centroid of the overlay mark.

[0109] Embodiment 6. The method of any one of embodiments 1 to 5, wherein determining the contrast of the first and second regions of the pattern of the overlay mark comprises determining a contrast level between the second region and a surrounding region of the wafer that is higher than a contrast level between the first region and the surrounding region of the wafer.

[0110] Embodiment 7. The method of any one of embodiments 1 to 6, wherein the wafer is oriented so that the lines of the first region of the pattern of overlay marks are aligned with the direction in which the illumination source emits light at the wafer and a polarizing filter is implemented when imaging through the imager sensor of at least one of the first region or the second region via the illumination source emitting light at the wafer.

[0111] Embodiment 8. The method of any one of embodiments 1 to 7, further comprising determining a position and shape of at least one bar mark of the overlay mark based at least in part on the determined contrast of the first and second regions.

[0112] Embodiment 9. The method of any one of embodiments 1 to 8, further comprising determining a position and shape of at least one column of bar marks of the overlay mark based at least in part on the determined contrast of the first and second regions.

[0113] Embodiment 10. An overlay mark for a wafer, comprising: a pattern defining an array of columns, each column comprising a set of parallel bar marks, wherein each bar mark is spaced apart from an adjacent bar mark by a spacing mark, and wherein the pattern within each column of the array of columns comprises a set of lines oriented parallel to each other and extending in a first direction within each bar mark of the corresponding column and in a second, different direction within each spacing mark of the corresponding column, wherein each line of the set of lines is continuous and extends from an uppermost region of the corresponding column to a lowermost region of the corresponding column.

[0114] Embodiment 11. The wafer overlay mark according to embodiment 10, wherein the first direction is perpendicular to the second, different direction.

[0115] Embodiment 12. The overlay mark of a wafer according to any one of embodiments 10 and 11, wherein the first direction extends at an angle of 45° relative to the longitudinal axis of the corresponding row, and wherein the second, different direction extends at an angle of 135° relative to the longitudinal axis of the corresponding row.

[0116] Embodiment 13. The wafer overlay mark according to any one of embodiments 10 to 12, wherein each line of the set of lines of the pattern comprises a periodic shape.

[0117] Embodiment 14. The wafer overlay mark according to any one of embodiments 10 to 13, wherein the width of each bar mark of the corresponding column in the direction of the longitudinal axis of the corresponding column is at least substantially equal to the width of each space mark of the corresponding column in the direction of the longitudinal axis of the corresponding column.

[0118] Embodiment 15. The wafer overlay mark according to any one of embodiments 10 to 14, wherein the width of each bar mark of the corresponding column in the direction of the longitudinal axis of the corresponding column is greater than the width of each space mark of the corresponding column in the direction of the longitudinal axis of the corresponding column.

[0119] Embodiment 16. The overlay mark of a wafer according to any one of embodiments 10 to 15, wherein the pattern comprises one or more of a filling material, a groove, or a plating.

[0120] Embodiment 17. An overlay metrology measurement system comprising: a substrate support for supporting a wafer; an illumination source for emitting light at the wafer in a first direction; an imager sensor configured to at least identify a location of a visible element on the wafer; and a controller operably coupled to the substrate support, the imager sensor, and the illumination source, the controller comprising: at least one processor; and at least one non-transitory computer-readable storage medium storing instructions thereon, the instructions, when executed by the at least one processor, causing the controller to: cause the supporting substrate to rotate the wafer relative to a default position to: align lines of a first region of a pattern of overlay marks on a reference level of the wafer with the first direction; and cause lines of a second region of the pattern of overlay marks adjacent to the first region to extend in a second direction perpendicular to the first direction; cause the illumination source to emit light at the wafer in the first direction; cause the imager sensor to capture at least one image of the wafer; and based at least in part on the capturing of the at least one image, distinguish between the first region and the second region of the pattern of overlay marks based on detected contrast of the first region and the second region of the pattern of overlay marks.

[0121] Embodiment 18. The overlay metrology measurement system of Embodiment 17, wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to determine a location of a centroid of the overlay mark on the reference level of the wafer based at least in part on the detected contrast of the first and second regions.

[0122] Embodiment 19. The overlay metrology measurement system of embodiment 18, wherein the controller further comprises instructions that, when executed by the at least one processor, cause the controller to: determine a position of another centroid of another overlay mark on a level of interest of the wafer; and determine a position offset between the level of interest and the reference level of the wafer based on the determined position of the overlay mark on the reference level and the determined position of the overlay mark on the level of interest.

[0123] Embodiment 20. The overlay metrology measurement system of any one of Embodiments 17 to 19, wherein aligning the lines of the first region of the pattern of overlay marks on the reference level of the wafer with the first direction comprises rotating the wafer by 45° relative to a default position of the wafer.

[0124] Embodiment 21. The overlay metrology measurement system of any one of embodiments 17 to 20, wherein aligning the lines of the first region of the pattern of the overlay mark on the reference level of the wafer with the first direction causes a polarizing effect on light emitted by the illumination source, thereby causing the lines within the second region of the overlay mark to be more detectable via the imager sensor than the lines within the first region of the overlay mark.

[0125] Embodiment 22. A method of forming a pattern of overlay marks on a wafer, the method comprising: forming bar marks of columns of overlay marks, including forming parallel lines extending from a first lateral end of a corresponding column to a second opposite lateral end of the corresponding column; and forming spacer marks of columns of overlay marks, including forming parallel segmented lines extending from the first lateral end of the corresponding column to the second opposite lateral end of the corresponding column between adjacent bar marks.

[0126] Embodiment 23. The method according to embodiment 22, further comprising forming spaces between adjacent parallel lines and parallel segment lines to have the same width as the spaces between adjacent parallel lines.

[0127] Embodiment 24. The method of any one of Embodiments 22 and 23, wherein forming the parallel segment lines comprises forming a segment of each segment line to have a longitudinal length that is greater than a distance between adjacent segments of the segment lines.

[0128] Embodiment 25. The method of any one of embodiments 22 to 24, further comprising at least six bar marks and at least five spaced marks per column.

[0129] Embodiment 26. The method of any one of embodiments 22 to 25, wherein forming bar marks and forming space marks include depositing a fill material on the surface of the wafer.

[0130] The embodiments of the present disclosure described above and illustrated in the accompanying drawings do not limit the scope of the present disclosure, which is covered by the scope of the attached claims and their legal equivalents. Any equivalent embodiments are within the scope of the present disclosure. In fact, those skilled in the art will understand from the description various modifications of the present disclosure other than those shown and described herein, such as alternative useful combinations of the described elements. Such modifications and embodiments also fall within the scope of the attached claims and their equivalents.

Claims

1. A wafer overlay mark, comprising: A pattern defining an array of columns, each column comprising a set of parallel bar marks, wherein each bar mark is spaced apart from an adjacent bar mark by a spacing mark, and wherein each bar mark comprises parallel lines formed extending from a first lateral end of a corresponding column to a second opposite lateral end of the corresponding column, and wherein the spacing marks comprise parallel segmented lines formed between adjacent bar marks extending from the first lateral end of the corresponding column to the second opposite lateral end of the corresponding column. 2 . The wafer overlay mark according to claim 1 , further comprising a space between adjacent parallel lines and parallel segment lines, wherein the space has the same width as a space between adjacent parallel lines. 3 . The wafer overlay mark according to claim 1 , wherein each segment line has a longitudinal length greater than a distance between adjacent segments of the segment line.

4. The wafer overlay mark according to claim 1, further comprising at least six bar marks and at least five space marks in each row.

5. The wafer overlay mark according to any one of claims 1 to 4, wherein forming the bar mark and forming the space mark comprises depositing a filling material on the surface of the wafer.

6. A method for forming a pattern of overlay marks on a wafer, the method comprising: forming bar markings of columns of overlay markings, including forming parallel lines extending from a first lateral end of a respective column to a second opposite lateral end of the respective column; and Forming the spacing marks of the columns of the overlay marks includes forming parallel segment lines between adjacent bar marks extending from the first lateral end of the corresponding column to the second opposite lateral end of the corresponding column. 7 . The method of claim 6 , further comprising forming spaces between adjacent parallel lines and the parallel segment lines, the spaces having the same width as spaces between adjacent parallel lines. 8 . The method of claim 6 , wherein forming the parallel segment lines comprises forming a segment of each segment line to have a longitudinal length that is greater than a distance between adjacent segments of the segment lines.

9. The method of claim 6, further comprising at least six bar marks and at least five space marks per column.

10. The method of any one of claims 6 to 9, wherein forming bar marks and forming space marks include depositing a fill material on a surface of the wafer.

11. A wafer overlay mark, comprising: A pattern defining a column array, the columns of the column array comprising lines oriented parallel to each other and extending continuously from one end of the column in a first direction to another end of the column in the first direction individually in a non-linear path, the lines comprising: regions, each region extending linearly in a second direction at an acute angle relative to the first direction and defining bar marks of the column, the bar marks respectively having substantially the same width in the first direction and being oriented parallel to each other in a third direction perpendicular to the first direction; and Additional regions alternate with the regions in the first direction, and each additional region extends linearly in a fourth direction at an obtuse angle relative to the first direction, the additional regions defining spacing marks of the columns, the spacing marks respectively having approximately the same additional width in the first direction and being oriented parallel to each other in the third direction.

12. The wafer overlay mark according to claim 11, wherein: The second direction extends at an angle of 45° relative to the first direction; and The fourth direction extends at an angle of 135° relative to the first direction. 13 . The wafer overlay mark of claim 11 , wherein the width of corresponding ones of the bar marks is substantially equal to the additional width of corresponding ones of the space marks. 14 . The wafer overlay mark of claim 11 , wherein the width of a corresponding one of the bar marks is greater than the additional width of a corresponding one of the space marks. 15 . The wafer overlay mark according to claim 11 , wherein the pattern comprises one or more of a filling material, a groove or a plating layer. 16 . The wafer overlay mark of claim 11 , wherein the number of the regions of the line is different from the number of the additional regions of the line. 17 . The wafer overlay mark of claim 16 , wherein the number of the areas of the line is greater than the number of the additional areas of the line.

18. The wafer overlay mark of claim 11, wherein the columns further include additional lines parallel to each other and oriented parallel to the lines, the additional lines individually extending only partially through the columns in the first direction in additional non-linear paths. 19 . The wafer overlay mark according to claim 18 , wherein the additional lines are respectively positioned at one ends of the columns in the third direction.

20. The wafer overlay mark according to claim 11, wherein the additional lines respectively include: a first region extending linearly in the second direction and defining a portion of one of the bar markings of the column; and A second region adjacent to the first region in the first direction and extending linearly in the fourth direction, the second region defining a portion of one of the spacing marks of the column.

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