Semiconductor device and method of forming interconnect structure for semiconductor device

Abstract

Semiconductor devices and methods of forming interconnect structures for semiconductor devices are disclosed. The semiconductor device includes: a front surface structure including at least one of a front end of line (FEOL) structure, an intermediate process (MOL) structure, and a back end of line (BEOL) structure; a first metal line on the front surface structure; and a second metal line on the front surface structure, in which the first metal line has a greater width than the second metal line in the same direction, and the first metal line and the second metal line have the same height.

Description

Technical Field

[0001] Apparatuses and methods consistent with example embodiments of the present disclosure relate to an interconnect structure including a metal line and a top via formed thereon, and more particularly, to a semiconductor device including the metal line and the top via formed by different processes. Background Art

[0002] The performance of a semiconductor device may be affected by how interconnect structures are formed in the semiconductor device. The interconnect structures may include back-end-of-line (BEOL) structures, such as metal lines and vias, that connect front-end-of-line (FEOL) structures to voltage sources or other circuit elements through middle-of-line (MOL) structures. The FEOL structures may include source / drain regions and gate structures of transistors, and the MOL structures may include contact plugs or vias formed on the source / drain regions or gate structures.

[0003] As semiconductor devices are developed to have high device density and performance, the design and formation of interconnect structures have become more difficult and complicated, while the semiconductor devices require improved resistance and capacitance (RC) characteristics.

[0004] The information disclosed in this background technology section was known to the inventors before implementing the embodiments of the present application, or was technical information acquired during the implementation of the embodiments described herein. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0005] The present disclosure provides example embodiments of an interconnect structure for a semiconductor device or an integrated circuit and a method of manufacturing the interconnect structure.

[0006] According to an embodiment, a semiconductor device is provided, which may include: a frontside structure, including at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a first metal line on the frontside structure; and a second metal line on the frontside structure, wherein, in the same direction, the first metal line has a larger width than the second metal line, and the first metal line and the second metal line have equal heights.

[0007] The first metal line may have a first top via formed on the first metal line without an intervening layer such as a barrier metal line therebetween. The first top via and the first metal line may be a single contiguous structure formed of the same material such as ruthenium (Ru).

[0008] According to an embodiment, a semiconductor device is provided, which may include: a front side structure, including at least one of a front end of line (FEOL) structure, a middle of line (MOL) structure, and a back end of line (BEOL) structure; a first metal line; and a first top via, on the first metal line without an intervening layer therebetween, wherein the first metal line and the first top via have the same material composition, and the first metal line and the first top via have different material structures.

[0009] The first metal line may have a columnar material structure, and the first top via may have an amorphous or polycrystalline structure.

[0010] According to an embodiment, a method for forming an interconnect structure for a semiconductor device is provided. The method may include: (a) forming a first initial metal structure by a first deposition process; (b) forming a second initial metal structure on the first initial metal structure by a second deposition process; (c) forming a plurality of hard mask patterns at selected positions on the second initial metal structure; (d) patterning the second initial metal structure and the first initial metal structure thereunder based on the hard mask pattern to form at least one narrow structure and at least one wide structure, each of the at least one narrow structure and the at least one wide structure including a metal structure and a via structure thereon; (e) patterning the hard mask pattern to form a reduced hard mask pattern; and (f) simultaneously patterning the via structure in each of the narrow structure and the wide structure based on the reduced hard mask pattern until the portion of the via structure not covered by the reduced hard mask pattern is completely removed, thereby forming a wide metal line and a narrow metal line having a corresponding top via thereon.

[0011] The first deposition process may be one of physical vapor deposition (PVD) and chemical vapor deposition (CVD), and the second deposition process may be the other of PVD and CVD. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figures 1A-1E A semiconductor device including an interconnect structure formed of a plurality of metal lines and a top via according to an embodiment is shown;

[0014] Figure 2-11 An intermediate semiconductor device including an intermediate interconnect structure according to an embodiment is shown, the intermediate interconnect structure being obtained from respective steps of forming an interconnect structure including wide metal lines and narrow metal lines having respective top vias thereon and having different heights;

[0015] Figures 12A-12DA semiconductor device including an interconnect structure formed of a plurality of metal lines and a top via according to an embodiment is shown;

[0016] Figure 13-23 An intermediate semiconductor device including an intermediate interconnect structure according to an embodiment is shown, the intermediate interconnect structure being obtained from respective steps of forming an interconnect structure including wide metal lines and narrow metal lines having respective top vias thereon and having the same height;

[0017] Fig.24 A flow chart showing a method of forming an interconnect structure in which wide metal lines and narrow metal lines have corresponding top vias thereon and have the same height according to an embodiment; and

[0018] Fig.25 is a diagram showing a method according to an example embodiment including Figures 12A-12D A schematic block diagram of an electronic device of an interconnect structure 200A is shown. DETAILED DESCRIPTION

[0019] The embodiments of the present disclosure described here are example embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms. It is not excluded that each embodiment provided in the following description is associated with one or more features of another example or another embodiment that is also provided here or not provided here but consistent with the present disclosure. For example, even if the matters described in a specific example or embodiment are not described in an example or embodiment different from it, these matters can also be understood as being related to or combined with the different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural equivalents and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described here can take different types or forms, as long as the present disclosure can be applied thereto.

[0020] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on" another element of the semiconductor device, "above" another element of the semiconductor device, "on" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "under" another element of the semiconductor device, "connected to" another element of the semiconductor device, or "coupled to" another element of the semiconductor device, it can be directly on, directly on, directly below, directly below, directly below, directly connected to, or directly coupled to the other element, or there may be intervening elements. In contrast, when an element of a semiconductor device is referred to as being “directly on” another element of the semiconductor device, “directly over” another element of the semiconductor device, “directly on” another element of the semiconductor device, “directly below” another element of the semiconductor device, “directly under” another element of the semiconductor device, “directly connected to” another element of the semiconductor device, or “directly coupled to” another element of the semiconductor device, there are no intervening elements. Like reference numerals refer to like elements throughout this disclosure.

[0021] For ease of description, spatial relationship terms such as "above", "above", "on", "below", "below", "below", "under", "under", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used here to describe the relationship of an element to another element as shown in the figure. It will be understood that in addition to the orientations depicted in the figure, the spatial relationship terms are also intended to cover different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is turned over, the element described as "below" or "below" another element will be oriented to be "above" the other element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used here are interpreted accordingly. As another example, when a device or structure including elements referred to as "left" elements and "right" elements are oriented differently, these elements can be "right" elements and "left" elements. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, and the necessary description is performed to distinguish the two elements.

[0022] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below could be referred to as the second element without departing from the teachings of the present disclosure.

[0023] As used herein, expressions such as "at least one of," when following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term "same" or "equal" is used to compare the size of two or more elements, the term may encompass "substantially the same" or "substantially equal" sizes.

[0024] It will also be understood that even if a step or operation of manufacturing a device or structure is described earlier than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0025] Many embodiments are described herein with reference to cross-sectional views that are schematic diagrams of embodiments (and intermediate structures). As such, variations relative to the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments should not be construed as limited to the specific shapes of the regions shown herein, but will include shape deviations, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0026] For the sake of brevity, conventional elements of semiconductor devices may or may not be described in detail or shown in the drawings. For example, when a MOL or FEOL structure is not relevant to the concept of the present disclosure, the structure may not be described or shown in detail.

[0027] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0028] Top vias have been introduced to reduce contact resistance and capacitance that may occur between a metal line and a via formed thereon, thereby at least adversely affecting the connection performance of a semiconductor device including the metal line and the via.

[0029] Figures 1A-1E A semiconductor device including an interconnect structure formed of a plurality of metal lines and a top via according to an embodiment is shown.

[0030] Figure 1A is a plan view of a semiconductor device including an interconnect structure, Figure 1B It is along Figure 1A A side cross-sectional view taken along line II' is shown. Figure 1C and Figure 1D Along the Figure 1A Side cross-sectional views taken along line II-II' and line III-III' are shown. Figure 1E It is along Figure 1A An alternative side cross-sectional view taken along line II' is shown.

[0031] Reference Figures 1A-1D, the semiconductor device 10 may include an interconnect structure 100A formed on the front structure 100 with a first adhesive layer 101 therebetween. The interconnect structure 100A may include first to fifth metal lines 110-150 arranged in the D1 direction and extending in the D2 direction intersecting the D1 direction. Here, the front structure 100 may be or include at least one of a FEOL structure, a MOL structure, and a BEOL structure. Therefore, the semiconductor device 10 may be a single integrated circuit (IC) device or an IC chip, such as a memory chip or a system on chip (SoC).

[0032] The metal lines 110-150 may each be formed of a metal such as ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co), or a compound thereof, but are not limited thereto. The first adhesion layer 101 between the front structure 100 and each of the first to fifth metal lines 110-150 may be formed of a material that can conductively connect the metal lines 110-150 to the front structure 100, such as titanium nitride (TiN), tantalum nitride (TaN), or an equivalent material.

[0033] A first top via 115, a second top via 135, and a third top via 136 in the form of a protrusion in the D3 direction from the top surface of the first metal line 110 and the third metal line 130 may be formed on the first metal line 110 and the third metal line 130, respectively. In addition, a fourth top via 145 may be formed on the fourth metal line 140 in the form of a protrusion in the D3 direction from the top surface of the fourth metal line 140. The D3 direction intersects the D1 direction and the D2 direction. The top vias 115, 135, 136, and 145 may be formed of the same material forming the metal lines 110-150, because each top via and the corresponding metal line form a single continuous structure as described below.

[0034] The metal lines 110-150 and the top vias 115, 135, 136, and 145 may be surrounded by the isolation structure 103 with the second adhesive layer 102 therebetween. The isolation structure 103 may isolate or insulate the metal lines and the top vias from each other or from other circuit elements, and the second adhesive layer 102 may promote adhesion of the metal lines and the top vias to the isolation structure 103 and protect the metal lines and the top vias from other processes including an annealing process performed when the isolation structure 103 is formed thereon. The one or more materials forming the isolation structure 103 may include a low-k dielectric material such as silicon oxide (e.g., SiO 2 , SiCOH, etc.), but not limited thereto. One or more materials forming the second adhesive layer 102 may also include a low-k material, such as silicon nitride (eg, SiN, Si 3 N 4 wait).

[0035] Here we need to understand that Figure 1A The isolation structure 103 is not shown. Figure 1B-1D The portions formed on the top surface of the metal line and the side surfaces of the top via are shown as they will Figure 1A Cover the metal wire below.

[0036] Here, the top via refers to a via connection structure formed on a metal line without an intervening layer (such as a barrier metal line) that may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. In addition, there may be no boundary, interface, seam or connection surface (collectively referred to as "connection surface") between the metal line and the top via. Conventionally, the metal line and via of a semiconductor device are formed by a damascene process in which an isolation structure formed on a MOL or FEOL structure or another BEOL structure is patterned, and metal and vias are formed in the patterned isolation layer at vertically adjacent layers of the isolation structure, respectively. In contrast, the top via can be formed by patterning the metal structure itself, and therefore, no intervening layer or connection surface may be formed between the top via and the patterned underlying metal structure (which forms the metal line of the semiconductor device). Therefore, the first metal line 110 and the first top via 115 thereon can form a single continuum metal structure without a connection surface or intervening layer therebetween. Likewise, the third metal line 130 and each of the second top via 135 and the third top via 136 thereon may form another single continuous metal structure without connecting surfaces or intervening layers therebetween. Thus, the material forming the top vias 115, 135, 136, and 145 may also be formed of the same metal forming the corresponding metal lines 110, 130, and 140. It is to be understood here that Figure 1B-1D The dashed lines shown between each of the top vias 115, 135, 136, and 145 and the corresponding one of the metal lines 110, 130, and 140 do not indicate the presence of the aforementioned connecting surface or intervening layer, as there is no such connecting surface therebetween. These dashed lines are shown in the drawings only for the purpose of clearly indicating the top vias and the corresponding metal lines.

[0037] Reference Figure 1A and Figure 1B, each of the first to third metal lines 110-130 may be a narrow metal line having a first width W1 and arranged at a first pitch P1 in the D1 direction. Each of the fourth metal line 140 and the fifth metal line 150 may be a wide metal line having a second width W2 and arranged at a second pitch P2 in the same D1 direction. The first width W1 may be smaller than the second width W2, and the first pitch P1 may be smaller than the second pitch P2. In the semiconductor device 10, the fourth metal line 140 and the fifth metal line 150 may each be used as a power rail for connecting the front structure 100 to a voltage source, and because they have a relatively large width, the first to third metal lines 110-130 may each be used as a signal line for internal wiring.

[0038] at the same time, Figure 1B-1D It is shown that the height H2 of each of the fourth metal line 140 and the fifth metal line 150 is smaller than the height H1 of each of the first to third metal lines 110-130 by a depth D1. Therefore, the height of the fourth top via 145 is greater than the height of each of the first to third top vias 115, 135, and 136 by a depth D1. This is because the fourth metal line 140 and the fifth metal line 150 are wide metal lines, while the first to third metal lines 110-130 are narrow metal lines. As will be referred to later Figure 2-11 As described, the first to fourth top vias 115, 135, 136, and 145 can be formed by patterning the corresponding metal structures based on the same initial metal structure through the same patterning process (e.g., dry etching), and therefore, the wide metal structure can be patterned faster than the narrow metal structure. Therefore, the fourth metal line 140 and the fifth metal line 150 formed by patterning the wide metal structure can have a smaller height than the first to third metal lines 110-130 formed by patterning the narrow metal structure.

[0039] However, the present disclosure is not limited to Figure 1B According to an embodiment, the semiconductor device 10 may have an interconnect structure 100A. Figure 1B The interconnect structure 100A shown is different from the interconnect structure 100B. Figure 1E As shown, the interconnect structure 100B may include a fourth metal line 140 and a fifth metal line 150, which may be formed to have a height H3 greater than the height H1 of the first to third metal lines 110-130 by a depth D2 due to patterning process variations. However, still due to the different widths between the wide metal structure and the narrow metal structure, the wide metal line and the narrow metal line respectively formed by patterning the wide metal structure and the narrow metal structure through the same patterning process may have different heights.

[0040] Figure 2-11An intermediate semiconductor device including an intermediate interconnect structure according to an embodiment is shown, the intermediate interconnect structure being obtained from the corresponding steps of forming an interconnect structure including wide metal lines and narrow metal lines having different heights. Here, the interconnect structure completed from the intermediate interconnect structure through the corresponding steps described below can be combined with Figures 1A-1D The interconnect structure 100A of the semiconductor device 10 shown is the same or corresponds. Therefore, repeated description may be omitted, and the same reference numerals and characters used in the description of the interconnect structure 100A of the semiconductor device 10 may be used below.

[0041] Reference Figure 2 , an initial metal structure 105 may be formed on the front structure 100 of the intermediate semiconductor device 10'. The initial metal structure 105 may extend along the D1 direction and the D2 direction on the front structure 100, and the front structure 100 may be or include at least one of a FEOL structure, a MOL structure, and a BEOL structure.

[0042] Before forming the initial metal structure 105 on the front structure 100, the first adhesion layer 101 may be stacked on the top surface of the front structure 100 by, for example, atomic layer deposition (ALD) (but not limited thereto). Then, the initial metal structure 105 may be formed on the first adhesion layer 101 by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition, or any other deposition process, and the initial metal structure 105 may be planarized by, for example, chemical mechanical polishing (CMP).

[0043] Reference Figure 3 , can be formed on the top surface of the initial metal structure 105 and below it by, for example, photolithography and masking operations. Figures 1A-1D First to fifth hard mask patterns HM1 - HM5 are formed at the locations of the first to fifth metal lines 110 - 150 as shown.

[0044] Since the first to fifth metal lines 110-150 are to be formed based on the first to fifth hard mask patterns HM1-HM5, respectively, the first to fifth hard mask patterns HM1-HM5 may be aligned with the first to fifth metal lines 110-150 in the D1 direction. Figure 1AThe pitches P1 and P2 arranged in the D1 direction as shown are arranged at corresponding pitches P1' and P2'. The pitch P1' may be smaller than the pitch P2' because the pitch P1 is smaller than the pitch P2. In addition, the first to fifth hard mask patterns HM1-HM5 may have widths corresponding to the widths of the first to fifth metal lines 110-150, respectively. For example, the width W1' of each of the first to third hard mask patterns HM1-HM3 may be smaller than the width W2' of each of the fourth and fifth hard mask patterns HM4-HM5. This is because in a later step, each of the first to third hard mask patterns HM1-HM3 will be used to form a narrow metal line, and each of the fourth and fifth hard mask patterns HM4-HM5 will be used to form a wide metal line.

[0045] The material or material composition forming the first to fifth hard mask patterns HM1-HM5 may be silicon nitride (eg, Si 3 N 4 ) or silicon dioxide (e.g., SiO 2 ), but are not limited to them.

[0046] Reference Figure 4 , the preliminary metal structure 105 and the first adhesion layer 101 thereunder may be patterned based on the first to fifth hard mask patterns HM1 - HM5 to form first to fifth metal structures 110 ′- 150 ′.

[0047] The formation of the first to fifth metal structures 110'-150' may be performed by, for example, dry etching (eg, reactive ion etching, plasma etching, ion beam etching, or laser ablation), but is not limited thereto. Figure 3 With widths W1 ′ and W2 ′ shown, the first through third metal structures 110 ′- 130 ′ may each be formed as a narrow metal structure, while the fourth and fifth metal structures 140 ′- 150 ′ may each be formed as a wide metal structure.

[0048] It is to be understood here that due to the etching aspect ratio, the width of each of the recesses r1, r2, r3 and r4 formed between the first to fifth metal structures 110'-150' by the etching operation may vary gradually decreasingly along the depth direction of each recess. For example, the recess r2 between the second metal structure 120' and the third metal structure 130' may have a top width TW greater than the bottom width BW. Therefore, each of the first to fifth metal structures 110'-150' may have a top width less than its bottom width. However, still subject to the accuracy of the etching operation, the top width and bottom width of each of the recesses r1-r4 may be substantially equal to each other, and therefore, the top width and bottom width of each of the first to fifth metal structures 110'-150' may be substantially equal to each other.

[0049] The recesses r1 - r4 formed between the first to fifth metal structures 110 ′ - 150 ′ may expose a top surface of the front-end structure 100 .

[0050] Reference Figure 5A and Figure 5B , the second hard mask pattern HM2 and the fifth hard mask pattern HM5 among the first to fifth hard mask patterns HM1-HM5 can be removed from the second metal structure 120' and the fifth metal structure 150', respectively, while the first hard mask pattern HM1, the third hard mask pattern HM3 and the fourth hard mask pattern HM4 are respectively retained on the first metal structure 110', the third metal structure 130' and the fourth metal structure 140'.

[0051] The second hard mask pattern HM2 and the fifth hard mask pattern HM5 may be selectively removed in this step to expose the top surfaces of the second metal structure 120' and the fifth metal structure 150' so that these metal structures may be recessed from their top surfaces in a later step. The selective removal operation of the hard mask patterns HM2 and HM5 may be performed by, for example, ashing or stripping, but is not limited thereto.

[0052] After the hard mask patterns HM2 and HM5 are selectively removed, a side cross-sectional view of the first metal structure 110 ′ having the first hard mask pattern HM1 thereon in the D2 direction may be taken as follows: Figure 5B The shape shown, Figure 5B is the intermediate semiconductor device 10' along Figure 5A The third metal structure 130' having the third hard mask pattern HM3 thereon and the fourth metal structure 140' having the fourth hard mask pattern HM4 thereon may have the same side cross-sectional view as the first metal structure 110' having the first hard mask pattern HM1 thereon in the D2 direction.

[0053] Reference Figures 6A-6C The first, third, and fourth hard mask patterns HM1, HM3, and HM4 may be patterned to correspond to locations where the first, second and third top vias 135-136, and a fourth top via 145 will be formed thereunder in a later step. Figure 6B and Figure 6C The intermediate semiconductor device 10' is respectively Fig. 6A Cross-sectional view along lines V-V' and VI-VI'.

[0054] Patterning the first, third, and fourth hard mask patterns HM1, HM3, and HM4 may be performed by, for example, another photolithography and masking operation.

[0055] After the patterning operation in this step, a reduced first hard mask pattern HM11 may be formed on the first metal structure 110', and reduced third hard mask patterns HM31 and HM32 may be formed on the third metal structure 130'. In addition, a reduced fourth hard mask pattern HM41 may be formed on the fourth metal structure 140'.

[0056] Figure 6B A side cross-sectional view of the first metal structure 110 ′ having the reduced first hard mask pattern HM11 thereon in the D2 direction is shown, which may be the same as a side cross-sectional view of the fourth metal structure 140 ′ having the reduced fourth hard mask pattern HM41 thereon. Figure 6C A side cross-sectional view in the D2 direction of the third metal structure 130 ′ having the reduced third hard mask patterns HM31 and HM32 thereon is shown.

[0057] Reference Figures 7A-7D , the first to fifth metal structures 110 ′- 150 ′ may be patterned based on the reduced hard mask patterns HM11 , HM31 - HM32 , and HM41 obtained in the previous steps. Figures 7B-7D The intermediate semiconductor device 10' is respectively Fig. 7A Cross-sectional views along lines VII-VII', VIII-VIII' and IX-IX'.

[0058] Through this patterning operation, a first metal line 110 having a first top via 115 thereon, a second metal line 120 , a third metal line 130 having second and third top vias 135 - 136 thereon, a fourth metal line 140 having a fourth top via 145 thereon, and a fifth metal line 150 may be formed on the front structure 100 .

[0059] The patterned metal structure 110'-150' can be performed by, for example, dry etching (e.g., reactive ion etching, ion beam etching, or laser ablation). When dry etching is performed, the first to fifth metal structures 110'-150' having reduced hard mask patterns HM11, HM31, HM32, and HM41 thereon can be simultaneously exposed to the reaction gas in the vacuum chamber. At this time, due to their width differences, the fourth and fifth metal structures 140'-150' (wide metal structures) can be etched more or less than the first to third metal structures 110'-130' (narrow metal structures). Therefore, the first to fifth metal lines 110-150 obtained by the patterning operation in this step can have different heights. For example, the etching rate can be higher on the fourth and fifth metal structures 140'-150' providing a larger gas reaction surface than on the first to third metal structures 110'-130' providing a smaller gas reaction surface. Therefore, each of the fourth and fifth metal structures 140'-150' may be etched faster or more than each of the first to third metal structures 110'-130' in a unit time. Therefore, the fourth and fifth metal lines 140-150 may have a height H2 that is smaller than the height H1 of the first to third metal lines 110-130 by a depth D1, as shown in FIG. Figures 7A-7D shown.

[0060] Reference Figure 8 , the reduced first hard mask pattern HM11 , the reduced third hard mask patterns HM31 - HM32 , and the reduced fourth hard mask pattern HM41 may be removed from the intermediate semiconductor device 10 ′.

[0061] Removing the reduced hard mask patterns HM11 , HM31 , HM32 , and HM41 in this step may be performed by, for example, ashing or stripping, but is not limited thereto.

[0062] Reference Fig. 9 , a second adhesive layer 102 may be formed on the metal lines 110-150 and the top vias 115, 135, 136, and 145 to facilitate bonding this intermediate interconnect structure to the isolation structure to be formed in the next step. The second adhesive layer 102 may also protect the intermediate interconnect structure from at least an annealing process that may be performed to form the isolation structure.

[0063] Forming the second adhesive layer may be performed by, for example, at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.

[0064] Reference Fig.10An isolation structure 103 may be formed on metal lines 110 - 150 and top vias 115 , 135 , 136 , and 145 to isolate the metal lines and top vias from each other or from other circuit elements.

[0065] Forming the isolation structure 103 may be performed by, for example, at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD), but is not limited thereto.

[0066] Reference Fig.11 The isolation structure 103 surrounding the metal lines 110 - 150 and the top vias 115 , 135 , 136 , and 145 may be planarized to expose top surfaces of the top vias 115 , 135 , 136 , and 145 for external connection of the intermediate semiconductor device 10 ′.

[0067] The planarization in this step may be performed by, for example, chemical mechanical polishing (CMP) to obtain an interconnect structure 100A for an intermediate semiconductor device 10', which may be connected to the semiconductor device 10'. Figures 1A-1D The semiconductor devices 10 shown are identical or correspond.

[0068] Meanwhile, the interconnect structure 100A of the semiconductor device 10 is characterized not only by its top via scheme, but also by the above reference Figures 7A-7D The height difference between the wide metal lines 140-150 and the narrow metal lines 110-130 is described. However, when the heights of the metal lines 110-150 are different from each other, the RC characteristics of the metal lines may be different from each other, and therefore, it may be difficult to estimate the connection performance of the interconnect structure 100A of the semiconductor device 10. In addition, when the wide metal structures 140'-150' are over-patterned to form wide metal lines 140-150 with smaller height H2, the connection performance of the semiconductor device 10 may be deteriorated. Therefore, the top via scheme may not be sufficient to benefit the connection performance of the semiconductor device 10 including the wide metal line 140 with the top via 145 thereon.

[0069] The following embodiments are provided to address the above-mentioned height difference between wide metal lines and narrow metal lines of an interconnect structure including a top via. In the following embodiments, a method of manufacturing an interconnect structure of a semiconductor device in which wide metal lines and narrow metal lines have equal heights is provided.

[0070] Figures 12A-12D A semiconductor device including an interconnect structure formed of a plurality of metal lines and a top via according to an embodiment is shown. Fig. 12A is a plan view of a semiconductor device including an interconnect structure, Fig. 12B It is along Fig. 12A A side cross-sectional view taken along line II' is shown. Fig. 12C and Fig.12D Along the Fig. 12A Side cross-sectional views taken along line II-II' and line III-III' are shown.

[0071] References correspond to Figures 1A-1D of Figures 12A-12D , the semiconductor device 20 may include an interconnect structure 200A, which is similar to Figures 1A-1D The interconnect structure 100A of the semiconductor device 10 is shown.

[0072] The interconnect structure 200A of the semiconductor device 20 may include first to fifth metal lines 210, 220, 230, 240, and 250 arranged in the D1 direction and extending in the D2 direction. The metal lines 210-250 may be formed on the front structure 200 with a first adhesive layer 201 therebetween. First to fourth top vias 215, 235, 236, and 245 may be formed on the metal lines 210-250, respectively. The metal lines 210-250 and the top vias 215, 235, 236, and 245 may be surrounded by an isolation structure 203 with a second adhesive layer 202 therebetween.

[0073] The width and pitch of the metal lines 210-250 of the interconnect structure 200A may be equal to the width and pitch of the metal lines 110-150 of the interconnect structure 100A. For example, in the D1 direction, each of the fourth and fifth metal lines 240 and 250 may be wider than each of the first to third metal lines 210-230. Repeated descriptions may be omitted below.

[0074] The metal lines 210 - 250 and the top vias 215 , 235 , 236 , and 245 may each be formed of a metal such as ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co), or a compound thereof, but are not limited thereto.

[0075] The front structure 200 , the first adhesive layer 201 , the second adhesive layer 202 and the isolation structure 203 may be the same as the front structure 100 , the first adhesive layer 101 , the second adhesive layer 202 and the isolation structure 103 of the semiconductor device 10 , and therefore, repeated descriptions may be omitted below.

[0076] However, the interconnect structure 200A of the semiconductor device 20 may differ from the interconnect structure 100A of the semiconductor device 10 in various aspects as described below.

[0077] The top vias 215, 235, 236, and 245 of the interconnect structure 200A may include a metal or metal compound that is processed differently from the metal or metal compound of the top vias 115, 135, 136, and 145 of the interconnect structure 100A. For example, a first metal structure including ruthenium (Ru) (but not limited thereto) may be deposited by physical vapor deposition (PVD) to form metal lines 210-250, and a second metal structure including the same Ru may be deposited on the first metal structure by chemical vapor deposition (CVD) to form the top vias 215, 235, 236, and 245.

[0078] Thus, even though metal lines 210-250 and top vias 215, 235, 236, and 245 may be formed of the same metal, they may have different microstructures, crystallography, or surface morphologies. For example, metal lines formed by PVD may have a columnar material structure, while top vias formed by CVD may have an amorphous or polycrystalline structure. Thus, unlike in the interconnect structure 100A of the semiconductor device 10, a boundary may exist between the top via and the corresponding metal line in the interconnect structure 200A even if there is no intervening layer (such as a barrier metal line). The boundary may be visible by a scanning electron microscope (SEM), a transmission electron microscope (TEM), or a focused ion beam (FIB) microscope.

[0079] Since metal lines 210 - 250 and top vias 215 , 235 , 236 , and 245 may have different structural characteristics as described above due to different formation processes applied thereto, metal lines 210 - 250 may have equal heights H1 after patterning corresponding top vias 215 , 235 , 236 , and 245 thereon.

[0080] Therefore, the connection performance of the semiconductor device 20 can be fully benefited by the interconnection structure 200A having the top via scheme, regardless of the width difference between the wide metal line and the narrow metal line. In addition, the estimation of the connection performance of the interconnection structure 200A of the semiconductor device 20 can become easier than the interconnection structure 100A of the semiconductor device 10 of the previous embodiment.

[0081] Figure 13-23 An intermediate semiconductor device including an intermediate interconnect structure according to an embodiment is shown, the intermediate interconnect structure being obtained from the corresponding steps of forming an interconnect structure including wide metal lines and narrow metal lines having corresponding top vias thereon and having the same height. Here, the interconnect structure completed from the intermediate interconnect structure by the corresponding steps described below can be compared with Figures 12A-12DThe interconnect structure 200A of the semiconductor device 20 shown is the same or corresponds. Therefore, repeated description may be omitted, and the same reference numerals and characters used in the description of the interconnect structure 200A of the semiconductor device 20 may be used below.

[0082] Reference Fig.13 , a first initial metal structure 205A and a second initial metal structure 205B may be formed on the front side structure 200 of the intermediate semiconductor device 20'. Both the initial metal structures 205A and 205B may extend along the D1 direction and the D2 direction on the front side structure 200, and the front side structure 200 may be or include at least one of a FEOL structure, a MOL structure, and a BEOL structure.

[0083] Before forming the initial metal structures 205A and 205B on the front structure 200, the first adhesion layer 201 may be stacked on the top surface of the front structure 200 by, for example, atomic layer deposition (ALD) (but not limited thereto). Then, the first initial metal structure 205A may be formed on the first adhesion layer 201 by, for example, physical vapor deposition (PVD), and the first initial metal structure 205A may be planarized by, for example, chemical mechanical polishing (CMP) so that the first initial metal structure 205A may have a height H1, which is a target height of each of the first to fifth metal lines 210-250. Subsequently, the second initial metal structure 205B may be formed on the first initial metal structure 205A by, for example, chemical vapor deposition (CVD), and the second initial metal structure 205B may be planarized by, for example, CMP so that the second initial metal structure 205B may have a target height of the first to fourth top vias 215, 235, 236, and 245. Therefore, the first initial metal structure 205A and the second initial metal structure 205B may be formed by different deposition processes.

[0084] Reference Fig.14 First to fifth hard mask patterns HM1 - HM5 may be formed on the top surface of the second preliminary metal structure 205B at locations where first to fifth metal lines 210 - 250 are to be formed thereunder, respectively, by, for example, photolithography and masking operations.

[0085] The first to fifth hard mask patterns HM1-HM5 formed in this step may be Figure 3 The hard mask patterns shown are the same, and thus, repeated descriptions regarding their materials and sizes may be omitted below.

[0086] Reference Fig.15Initial metal structures 205A and 205B having first adhesion layer 201 thereunder may be patterned based on hard mask patterns HM1 - HM5 to form first to fifth metal structures 210 ′- 250 ′ having first to fifth via structures 215 ′- 255 ′ thereon, respectively.

[0087] The first preliminary metal structure 205A may be patterned to form first to fifth metal structures 210'-250', which will become first to fifth metal lines 210-250, respectively. The second preliminary metal structure 205B may be patterned to form first to fifth via structures 215'-255', which will be further patterned in a later step to form first to fourth top vias 215, 235, 236, and 245, respectively. The first to third metal structures 210', 220', and 230' and the first to third via structures 215'-235' may form corresponding narrow structures, while the fourth and fifth metal structures 240'-250' and the fourth and fifth via structures 245'-255' may form corresponding wide structures.

[0088] The formation of the metal structures 210'-250' having the via structures 215'-255' thereon, respectively, can be performed by applying Figure 4 Therefore, the same recesses r1-r4 can be formed between the metal structures 210'-250' having the via structures 215'-255' thereon respectively. Fig.15 The size of the depressions r1-r4 and Figure 4 The sizes of the recesses r1-r4 in the embodiment may be the same. The repeated description may be omitted below.

[0089] Reference Fig.16A and Fig. 16B , the second hard mask pattern HM2 and the fifth hard mask pattern HM5 among the first to fifth hard mask patterns HM1-HM5 can be removed from the second via structure 225' and the fifth via structure 255', respectively, while the first hard mask pattern HM1, the third hard mask pattern HM3 and the fourth hard mask pattern HM4 remain on the first via structure 215', the third via structure 235' and the fourth via structure 245', respectively.

[0090] The second hard mask pattern HM2 and the fifth hard mask pattern HM5 may be selectively removed in this step to expose the top surfaces of the second via structure 225' and the fifth via structure 255' so that these via structures may be recessed from their top surfaces in a later step. The selective removal operation of the hard mask patterns HM2 and HM5 may be performed by, for example, ashing or stripping, but is not limited thereto.

[0091] After the hard mask patterns HM2 and HM5 are selectively removed, a side cross-sectional view of the first metal structure 210' having the first via structure 215' and the first hard mask pattern HM1 thereon in the D2 direction may be taken as follows: Fig. 16B The shape shown, Fig. 16B is the middle semiconductor device 20' along Fig.16A The third metal structure 230' having the third via structure 235' and the third hard mask pattern HM3 thereon and the fourth metal structure 240' having the fourth via structure 245' and the fourth hard mask pattern HM4 thereon may have the same side cross-sectional view as the first metal structure 210' having the first via structure 215' and the first hard mask pattern HM1 thereon in the D2 direction.

[0092] Reference Figures 17A-17C The first hard mask pattern HM1, the third hard mask pattern HM3, and the fourth hard mask pattern HM4 may be patterned to correspond to positions where the first top via 215, the second and third top vias 235-236, and the fourth top via 245 will be formed in a later step. Fig. 17B and Fig. 17C The intermediate semiconductor device 20' is respectively Fig.17A Cross-sectional view along lines V-V' and VI-VI'.

[0093] Patterning the first, third, and fourth hard mask patterns HM1, HM3, and HM4 in this step may be performed by, for example, another photolithography and masking operation.

[0094] After the patterning operation in this step, a reduced first hard mask pattern HM11 may be formed on the first via structure 215', and reduced third hard mask patterns HM31 and HM32 may be formed on the third via structure 235'. In addition, a reduced fourth hard mask pattern HM41 may be formed on the fourth via structure 245'.

[0095] Fig. 17B A side cross-sectional view of the first via structure 215 ′ and the first metal structure 210 ′ having the reduced first hard mask pattern HM11 thereon in the D2 direction is shown, which may be the same as the side cross-sectional view of the fourth via structure 245 ′ and the fourth metal structure 240 ′ having the reduced fourth hard mask pattern HM41 thereon. Fig. 17C A side cross-sectional view of the third via structure 235 ′ and the third metal structure 230 ′ in the D2 direction having the reduced third hard mask patterns HM31 and HM32 thereon is shown.

[0096] Reference Figures 18A-18E, the first to fifth via structures 215 ′- 255 ′ may be patterned based on the reduced hard mask patterns HM11 , HM31 , HM32 , and HM41 obtained in the previous steps. Figures 18B-18E The intermediate semiconductor device 20' is respectively Fig.18A Cross-sectional views along lines VII-VII', VIII-VIII', IX-IX' and XX'.

[0097] Through this patterning operation, a fourth metal line 240 having a fourth top via 245 thereon and a fifth metal line 250 may be formed from the fourth metal structure 240', the fourth via structure 245', and the fifth metal structure 250' on the front structure 200. The fourth and fifth metal lines 240-250 formed in this step may have a target height H1. However, the first to third metal lines 110-130 and the first to third top vias 215, 235, and 236 have not yet been formed on the front structure 200.

[0098] Patterning the metal structures 210'-250' having the via structures 215'-255' thereon can be performed by, for example, dry etching (e.g., reactive ion etching, ion beam etching, or laser ablation). When dry etching is performed, the via structures 215'-255' and the first to fifth metal structures 210'-250' having the reduced hard mask patterns HM11, HM31, HM32, and HM41 thereon can be simultaneously exposed to the reaction gas in the vacuum chamber. At this time, due to the difference in their widths, the fourth and fifth via structures 245' and 255' (wide metal structures) can be etched faster than the first to third via structures 215'-235' (narrow metal structures). For example, when the portion of the fourth via structure 245' not covered by the reduced fourth hard mask pattern HM41 and the fifth via structure 255' are completely removed, the portions of the first and third via structures 215' and 235' not covered by the reduced hard mask patterns HM11, HM31, and HM32, respectively, and the second via structure 225' may not be completely removed. Therefore, the residues R1-R3 of the first to third via structures 215'-235' not covered by the reduced hard mask patterns HM11, HM31, and HM32 may still remain on the first to third metal structures 210'-230', respectively.

[0099] Reference Figures 19A-19E , residues R1 - R3 of the first to third via structures 215 ′- 235 ′ not covered by the reduced hard mask patterns HM11 , HM31 , and HM32 may be completely removed, thereby forming first to third metal lines 210 - 230 and first to third top vias 215 , 235 , and 236 .

[0100] The residues R1-R3 may be removed by, for example, dry etching continued from the previous step. For example, dry etching may be continued for the residues R1-R3 of the first to third via structures 215'-235' that are not covered by the reduced hard mask patterns HM11, HM31, and HM32, by which the fourth top via 245 having the fourth metal line 240 below has been formed and the fifth via structure 255' has been removed to form the fifth metal line 250 below.

[0101] However, while the continued dry etching in this step removes the residues R1-R3 to form the first to third metal lines 210-230 having the target height H1, the fourth and fifth metal lines 240-250 may remain without being additionally etched by the continued dry etching, or the etching amount may be controlled to be negligible. This is because the metal forming the fourth and fifth metal lines 240-250 may have been deposited by CVD, while the same metal forming the residues R1-R3 of the first to third via structures 215'-235' may have been deposited by PVD.

[0102] Due to the different deposition methods to form two different metal structures including the same metal, i.e., Fig.13 The first initial metal structure 205A and the second initial metal structure 205B in the earlier step shown, so the etching rate can also be different between the two metal structures (i.e., the residues R1-R3 and the fourth and fifth metal lines 240-250). In addition, the etching rate can also be controlled by selectively using an etchant (such as a chlorine-based etchant, a nitric acid-based etchant, and a sulfuric acid-based etchant, but not limited to this). Therefore, even after removing the residues R1-R3 to form the first to third metal lines 210-230 with a target height H1, the fourth and fifth metal lines 240-250 formed earlier can maintain the same target height H1. Therefore, the first to fifth metal lines can have the same target height H1 to improve the connection performance of the interconnect structure 200A of the semiconductor device 20.

[0103] Reference Fig. 20 , the reduced first hard mask pattern HM11 , the reduced third hard mask patterns HM31 - HM32 , and the reduced fourth hard mask pattern HM41 may be removed from the intermediate semiconductor device 20 ′.

[0104] Removing the reduced hard mask patterns HM11 , HM31 , HM32 , and HM41 in this step may be performed by, for example, ashing or stripping, but is not limited thereto.

[0105] Reference Fig.21A second adhesive layer 202 may be formed on the metal lines 210-250 and the top vias 215, 235, 236, and 245 to facilitate bonding this intermediate interconnect structure to an isolation structure to be formed in a subsequent step. The second adhesive layer 202 may also protect the intermediate interconnect structure from an annealing process that may be performed to form the isolation structure.

[0106] Forming the second adhesive layer 202 may be performed by, for example, at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.

[0107] Reference Fig. 22 An isolation structure 203 may be formed on metal lines 210 - 250 and top vias 215 , 235 , 236 , and 245 to isolate these metal lines and top vias from each other or from other circuit elements.

[0108] The formation of the isolation structure 203 may be performed by, for example, at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD), but is not limited thereto.

[0109] Reference Fig.23 The isolation structure 203 surrounding the metal lines 210 - 250 and the top vias 215 , 235 , 236 , and 245 may be planarized to expose top surfaces of the top vias 215 , 235 , 236 , and 245 for external connection of the intermediate semiconductor device 20 ′.

[0110] The planarization in this step may be performed by, for example, chemical mechanical polishing (CMP) to obtain an interconnect structure for the intermediate semiconductor device 20', which may be connected to the intermediate semiconductor device 20'. Figures 12A-12D The semiconductor devices 20 shown are identical or correspond.

[0111] In the above-described embodiment, ruthenium (Ru) is deposited by PVD and CVD to form metal lines 210-250 and top vias 215, 235, 236, and 245 thereon, respectively. However, the present disclosure is not limited thereto, and thus, different metals such as molybdenum (Mo), tungsten (W), cobalt (Co), etc. may also be deposited to form these metal lines and the top via. In addition, the metal forming the metal line may be deposited by CVD, while the metal forming the top via may be deposited by PVD, so as to achieve the same height for wide metal lines and narrow metal lines having corresponding top vias thereon by controlling patterning conditions such as etching method, etching rate, etchant, etching time, etc.

[0112] Fig.24 A flow chart of a method for forming an interconnect structure according to an embodiment is shown, in which a wide metal line and a narrow metal line have corresponding top vias thereon and have the same height. Figure 13-23 This method is described and therefore, the same reference numerals may be used.

[0113] In step S10 , a first preliminary metal structure and a second preliminary metal structure stacked thereon may be provided on the front side structure, wherein the first preliminary metal structure and the second preliminary metal structure are deposited by different processes.

[0114] For example, the first initial metal structure 205A and the second initial metal structure 205B may be deposited by different deposition processes (eg, PVD and CVD). Fig.13 .

[0115] The metal or metal compound forming the initial metal structures 205A and 205B may be the same, for example, ruthenium (Ru). The first initial metal structure 205A may be deposited to have a target height H1, which may be the height of a metal line to be completed in a later step. The front side structure 200 may be or include at least one of a FEOL structure, a MOL structure, and a BEOL structure.

[0116] In step S20 , a plurality of hard mask patterns may be formed on the second preliminary metal structure at locations where at least one narrow metal line and at least one wide metal line are to be formed thereunder.

[0117] For example, a first hard mask pattern HM1 and a fourth hard mask pattern HM4 may be formed on the second preliminary metal structure 205B. Fig.14 .

[0118] In step S30 , the second preliminary metal structure and the first preliminary metal structure thereunder may be patterned in this order to form at least one narrow structure and at least one wide structure, each of which includes a metal structure and a via structure thereon.

[0119] For example, the narrow structure may include a first metal structure 210' having a first via structure 215' thereon, and the wide structure may include a fourth metal structure 240' having a fourth via structure 245' thereon. Fig.15 .

[0120] In step S40 , the hard mask pattern may be patterned to form a reduced hard mask pattern, which may correspond to a location where a top via on a narrow metal line and a top via on a wide metal line are to be formed thereunder.

[0121] For example, the reduced hard mask patterns HM11 and HM41 may be formed on the first via structure 215' and the fourth via structure 245', respectively. Figures 17A-17C .

[0122] In step S50, the via structure in each of the narrow structure and the wide structure may be simultaneously patterned based on the reduced hard mask pattern until a portion of the via structure not covered by the reduced hard mask pattern is completely removed, thereby forming a wide metal line and a narrow metal line having a corresponding top via thereon.

[0123] At this time, the portion of the via structure in the wide structure that is not covered by the hard mask pattern can be etched away faster than the portion of the via structure in the narrow structure that is not covered by the hard mask pattern. Therefore, the top via and the wide metal line below it can be formed first from the wide structure, while the top via and the narrow metal line below it are yet to be formed. This is because the via structure in the wide structure can provide a wider etchant reaction surface than the via structure in the narrow structure.

[0124] For example, before completely removing the portion of the first via structure 215' not covered by the reduced first hard mask pattern HM11 to form the first top via 215 and the first metal line 210 thereunder, completely remove the portion of the fourth via structure 245' not covered by the reduced fourth hard mask pattern HM41 to form the top via 245 and the fourth metal line 240 thereunder.

[0125] However, the fourth metal line 240 formed earlier can tolerate the continued patterning operation (e.g., dry etching) without being further etched until the portion of the first via structure 215' not covered by the reduced first hard mask pattern HM11 is completely removed to form the first top via 215 and the first metal line 210 thereunder. This is because the first initial metal structure forming the fourth metal line 240 and the second initial metal structure forming the first via structure 215' have been deposited by different processes (e.g., PVD and CVD). See Figures 18A-18E To 19A-19E.

[0126] In step S60 , the reduced hard mask pattern may be removed, an adhesive layer may be stacked on outer surfaces of the top via and the metal line, and an isolation structure may be formed to surround the top via and the metal line.

[0127] For example, after removing the reduced hard mask patterns HM11 and HM41 , the second adhesive layer 202 and the isolation structure 203 may be formed to surround the first metal line 210 having the first top via thereon and the fourth metal line 240 having the fourth top via 245 thereon.

[0128] Fig.25is a diagram showing a method according to an example embodiment including Figures 12A-12D A schematic block diagram of an electronic device of an interconnect structure 200A is shown.

[0129] Reference Fig.25 , the electronic device 4000 may include at least one application processor 4100, a communication module 4200, a display / touch module 4300, a storage device 4400, and a buffer RAM 4500. According to an embodiment, the electronic device 4000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0130] The application processor 4100 may control the operation of the electronic device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. The storage device 4400 may perform a cache of user data and mapping data as described above.

[0131] The buffer RAM 4500 may temporarily store data used for processing operations of the electronic device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0132] At least one component in the electronic device 4000 may include Figures 12A-12D A semiconductor device of the interconnect structure 200A is shown.

[0133] The foregoing is a description of exemplary embodiments and is not to be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the above-described embodiments without materially departing from the present disclosure.

Claims

1. A semiconductor device, comprising: a front-end structure, comprising at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a first metal line on the front structure; as well as a second metal line on the front structure, wherein, in the same direction, the first metal line has a greater width than the second metal line, and The first metal line and the second metal line have the same height. 2 . The semiconductor device of claim 1 , further comprising a first top via, the first top via being on the first metal line without an intervening layer therebetween.

3. The semiconductor device according to claim 2, wherein: The first top via and the first metal line include a same material composition.

4. The semiconductor device according to claim 3, wherein: The first top via and the first metal line include ruthenium (Ru).

5. The semiconductor device according to claim 3, wherein: The material structure of the first top via is different from the material structure of the first metal line and the second metal line.

6. The semiconductor device according to claim 5, wherein: The first top via has an amorphous or polycrystalline structure, and the first metal line and the second metal line have a columnar material structure.

7. The semiconductor device according to claim 2, further comprising a second top via, the second top via being on the second metal line without an intervening layer therebetween, in, The first top via and the second top via have equal heights.

8. A semiconductor device comprising: a front-end structure, comprising at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a first metal wire; as well as a first top via on the first metal line with no intervening layers therebetween, wherein the first metal line and the first top via have the same material composition, and The first metal line and the first top via have different material structures.

9. The semiconductor device according to claim 8, wherein: The first metal line has a columnar material structure, and the first top via has an amorphous or polycrystalline structure.

10. The semiconductor device according to claim 8, further comprising: a second metal wire; as well as a second top via on the second metal line, wherein, in the same direction, the second metal line has a greater width than the first metal line, The first metal line and the second metal line have the same height.

11. The semiconductor device according to claim 10, wherein: The first top via and the second top via have equal heights.

12. The semiconductor device according to claim 10, wherein: The second metal line and the second top via have different material structures.

13. The semiconductor device according to claim 12, wherein: The first metal line and the second metal line have the same material structure, and Wherein, the first top via and the second top via have the same material structure.

14. The semiconductor device according to claim 13, wherein: The first metal line and the second metal line have a columnar material structure, and the first top via and the second top via have an amorphous or polycrystalline structure.

15. The semiconductor device according to claim 14, wherein: The first metal line, the second metal line, the first top via, and the second top via have the same material composition.

16. The semiconductor device according to claim 15, wherein: The first metal line, the second metal line, the first top via, and the second top via include ruthenium (Ru).

17. A method of forming an interconnect structure for a semiconductor device, the method comprising: forming a first initial metal structure by a first deposition process; forming a second initial metal structure on the first initial metal structure by a second deposition process; forming a plurality of hard mask patterns at selected locations on the second initial metal structure; patterning the second initial metal structure and the first initial metal structure thereunder based on the hard mask pattern to form at least one narrow structure and at least one wide structure, each of the at least one narrow structure and the at least one wide structure comprising a metal structure and a via structure thereon; patterning the hard mask pattern to form a reduced hard mask pattern; as well as The via structure in each of the narrow structure and the wide structure is simultaneously patterned based on the reduced hard mask pattern until a portion of the via structure not covered by the reduced hard mask pattern is completely removed, thereby forming a wide metal line and a narrow metal line having a corresponding top via thereon.

18. The method according to claim 17, wherein: The first deposition process is one of physical vapor deposition (PVD) and chemical vapor deposition (CVD), and the second deposition process is the other of the PVD and the CVD.

19. The method according to claim 18, wherein: The first initial metal structure and the second initial metal structure include the same material composition.

20. The method according to claim 17, wherein: The top via and the wide metal line thereunder are formed earlier than the top via and the narrow metal line thereunder.

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