Driver circuit, half-bridge driver circuit, control circuit for electronic converter, integrated circuit and method

Abstract

The power stage includes a parallel FET including a reference FET. The input end PWM signal has a switching period. A current sensor senses a current flowing through the power stage during turn-on. The first circuit generates a first PWM signal having a duty cycle indicative of a reference FET drive loss of a reference current. The second circuit generates a second PWM signal having a duty cycle indicative of a reference FET conduction loss of the reference current. The duty cycles of the first PWM signal and the second PWM signal are compared to generate a comparison signal. The reference current is changed until the logic state of the comparison signal changes. A respective enable signal is generated for each FET by comparing the reference current to the sensed current flowing through the power stage. The FET driver circuit generates a respective drive signal for each FET by combining a respective enable signal with the input PWM signal.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000014532, filed on July 12, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments of the present disclosure relate to solutions for power stage partitioning, wherein electronic power stages are implemented using multiple field effect transistors (FETs) connected in parallel and / or a single FET in which the width of the active channel can be selectively controlled to virtually implement multiple electronic switches connected in parallel. Background Art

[0004] Power supply circuits, such as AC / DC or DC / DC switch mode power supplies (SMPS), are well known in the art. There are many types of electronic converters, which are mainly divided into isolated and non-isolated converters. For example, non-isolated electronic converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. In contrast, isolated converters are, for example, "flyback", "forward", "half-bridge" and "full-bridge" type converters. These types of converters are well known to those skilled in the art, as indicated, for example, in the application note AN513 / 00393 "Topologies for Switched Mode Power Supplies", L. Wuidart, 1999, STMicroelectronics (incorporated herein by reference).

[0005] Figure 1 is a schematic diagram of a DC / DC electronic converter 20. In particular, the universal electronic converter 20 includes a circuit for receiving a DC voltage V in The two input terminals 200a and 200b are used to supply a DC voltage V out For example, the input voltage V in The output voltage V may be supplied by a DC voltage source 10 such as a battery, or may be obtained from an AC voltage with the aid of a rectifier circuit such as a bridge rectifier and possibly a filtering circuit. out It can be used to supply power to the load 30 .

[0006] As is well known, an electronic converter includes: one or more reactive components such as inductors and / or capacitors; and one or more electronic switches configured to control: the current from input terminals 200a and 200b to the one or more reactive components; and / or the current flowing from the one or more reactive components to output terminals 202a and 202b.

[0007] In order to reduce the power consumption of the converter, it has recently been proposed to use power stage partitioning or segmentation, in which one or more electronic switches in the electronic converter 20 are implemented using: multiple electronic switches (such as FETs) connected in parallel; and / or a single FET, in which the width of the active channel can be selectively controlled, thereby virtually implementing multiple electronic switches connected in parallel.

[0008] For example, such a solution is disclosed in U.S. Patent Application Publication No. 2022 / 0173657A1 or Michal Vratislav's article "Peak-Efficiency Detection and Peak-Efficiency Tracking Algorithm for Switched-Mode DC-DC Power Converters", IEEE Transactions on Power Electronics, 2014, doi: 10.1109 / TPEL.2014.2304491 (both of which are incorporated herein by reference).

[0009] For example, Figure 2 An example is shown in which the power stage Q is implemented using a plurality of field effect transistors (FETs) connected in parallel, such as four FETs S1, S2, S3, and S4. In this case, the drain terminals of the plurality of FETs S1-S4 are connected to a first node / terminal N1, and the source terminals of the plurality of FETs S1-S4 are connected to a second node / terminal N2. Conversely, each of the gate terminals of the plurality of FETs S1-S4 is connected to a corresponding terminal to receive a corresponding drive signal (e.g., drive signals D1, D2, D3, and D4). In general, any other number of electronic switches connected in parallel and corresponding drive signals may also be used, such as 2, 3, 5, 6, 7, 8, or more electronic switches.

[0010] Therefore, in this case, the control circuit of the electronic converter may be configured to generate drive signals D1 - D4 for the electronic switches S1 - S4 in order to select the number of electronic switches that should be closed simultaneously.

[0011] In fact, the main loss sources of a FET typically vary with different load currents. For example, at high currents, the dominant loss source is the conversion of power into heat across the FET resistance, i.e., ohmic losses. At low currents, the dominant source comes from the switching on and off of the FET, i.e., dynamic losses such as switching operations and driving. For example, the power required to switch the gate of a FET on and off is typically fairly constant at any load, but as the load draws more and more current, the power used to switch the gate becomes a less significant portion of the total power converted.

[0012] Therefore, when the power stage Q is divided into multiple (physical and / or virtual) parallel FETs, the effective size of the power switches can be controlled and the control circuit of the electronic converter can balance the following: the total on-resistance R ds，ON , which resistance decreases when the number of closed electronic switches increases; and switching losses, which switching losses decrease when the number of closed electronic switches decreases.

[0013] For example, the control circuit can be configured to close more electronic switches S1-S4 at high current, thereby reducing the on-resistance R ds，ON and when low current flows, closing fewer electronic switches S1-S4, thereby reducing the switching losses required to close the electronic switches S1-S4.

[0014] For example, in order to decide the number of electronic switches S1-S4 that should be closed, i.e., the division or segmentation of the power stage Q, the control circuit can determine an indication of an average current flowing through the power stage Q (i.e., the total current flowing through the electronic switches S1-S4) (and preferably, proportional to the average current). For example, in a typical solution, the control circuit is configured to monitor the average current flowing through the power stage Q and set the number of active FETs using a predefined current threshold calculated for a typical application case. However, during use, operating conditions may change, and the predefined current threshold may no longer represent optimized efficiency. For example, when the supply voltage, switching frequency, turn-on and turn-off duration and / or operating temperature of the FETs change, and / or due to process variations and / or aging, the operating conditions may change.

[0015] In view of the above, there is a need to provide a solution for controlling the partitioning of the power stage in a more efficient manner. Summary of the invention

[0016] In various embodiments, the solutions disclosed herein are able to dynamically adapt the current threshold to the current operating conditions of the power stage.

[0017] According to one or more embodiments, one or more of the above objects are achieved by means of a driver circuit for a power stage.In addition, embodiments relate to related half-bridge driver circuits, control circuits for electronic converters, integrated circuits and methods.

[0018] As previously described, various embodiments of the present disclosure relate to a driver circuit including a power stage including a plurality of FETs. The driver circuit includes a terminal configured to receive a PWM signal having a given switching period, wherein the PWM signal is asserted for a switch-on period to indicate that the power stage should be closed, and the PWM signal is de-asserted for a switch-off period to indicate that the power stage should be opened. In various embodiments, the current sensor is configured to provide a signal indicating a current flowing through the power stage during the switch-on period. For example, in various embodiments, the signal indicating the current flowing through the power stage between the switch-on periods indicates the root mean square value of the current flowing through the power stage during the switch-on period or the maximum / peak value of the current flowing through the power stage during the switch-on period.

[0019] In various embodiments, the driver circuit includes a reference capacitor, a reference resistor, a first circuit, a second circuit, a duty cycle comparison circuit, a control circuit, a comparison circuit, and a FET driver circuit.

[0020] Specifically, in various embodiments, one of the plurality of FETs represents a reference FET, wherein the reference FET is closed by applying a gate-source voltage between a gate terminal and a source terminal of the reference FET. In this case, the reference capacitor includes a first scaled FET corresponding to a scaled version of the reference FET, and the reference resistor includes a second scaled FET corresponding to a scaled version of the reference FET.

[0021] In various embodiments, the first circuit is configured to generate a ramp signal at a reference capacitor by connecting a gate terminal of the first scaling FET to ground after a plurality of switching cycles and then applying a first current to the gate terminal of the first scaling FET, wherein the first current is proportional to the reference current. The first circuit also asserts a first PWM signal in response to determining that a voltage at the capacitor is less than a reference voltage, and de-asserts the first PWM signal in response to determining that a voltage at the capacitor is greater than a first reference voltage, wherein the reference voltage is proportional to a gate-source voltage. For example, in various embodiments, the first circuit connects the gate terminal of the first scaling FET to ground at the beginning of each switching cycle.

[0022] In various embodiments, the second circuit is configured to apply a second current to the capacitor when the PWM signal is asserted, wherein the second current is proportional to a reference current. In addition, the second circuit generates a third current by applying a voltage proportional to the gate-source voltage to a reference resistor, and applies the third current to the capacitor when the second PWM signal is asserted, wherein the second current applied to the capacitor and the third current applied to the capacitor have opposite signs. Finally, the second circuit asserts a second PWM signal in response to determining that the voltage at the capacitor exceeds a first threshold, and de-asserts the second PWM signal in response to determining that the voltage at the capacitor exceeds a second threshold.

[0023] In various embodiments, the duty cycle comparison circuit is configured to set the comparison signal to a first logic level in response to determining that the duty cycle of the first PWM signal is greater than the duty cycle of the second PWM signal, and to set the comparison signal to a second logic level in response to determining that the duty cycle of the first PWM signal is less than the duty cycle of the second PWM signal. For example, in various embodiments, the duty cycle comparison circuit includes a differential current integrator, and is configured to periodically reset the differential current integrator, then apply a first reference current to a first terminal of the differential current integrator when the first PWM signal is asserted and apply a second reference current to a second terminal of the differential current integrator when the second PWM signal is asserted. Finally, the duty cycle comparison circuit can generate a comparison signal based on a differential voltage at the output of the differential current integrator.

[0024] In various embodiments, the control circuit is configured to set the reference current to an initial value and then increase or decrease the reference current until the logic level of the comparison signal (eg, sampled after a given time period (eg, a given number of clock cycles)) changes.

[0025] In various embodiments, the comparison circuit is configured to determine a corresponding enable signal for each of the plurality of FETs by comparing a value of a reference current when a logic level of the comparison signal changes with a signal indicating a current flowing through the power stage during an on-period. For example, in various embodiments, the comparison circuit is configured to determine a signal indicating a division value of the power stage by determining a corresponding upper threshold and a lower threshold for each of a plurality of division values ​​according to a value of the reference current when a logic level of the comparison signal changes, and to select one of the division values ​​by comparing the signal indicating the current flowing through the power stage during the on-period with the upper threshold and the lower threshold. For example, in various embodiments, each of the plurality of FETs has a corresponding division factor, and the comparison circuit is configured to determine an enable signal according to the division factor of the FET of the plurality of FETs and the signal indicating the selected division value.

[0026] For example, in various embodiments, the driver circuit includes a current digital-to-analog converter configured to generate a reference current based on a digital signal. In this case, the control circuit can be configured to set the digital signal to an initial value and then increase or decrease the digital signal until the logic level of the comparison signal changes. Next, the control circuit can store the digital signal in response to determining that the logic level of the comparison signal changes. Therefore, in this case, the comparison circuit can be configured to compare the stored digital signal with a signal indicating the current flowing through the power stage during the on period.

[0027] Finally, in various embodiments, the FET driver circuit is configured to generate a corresponding drive signal for each of the plurality of FETs by combining the corresponding enable signal with the PWM signal. For example, in various embodiments, the FET driver circuit is configured to generate a corresponding drive signal for each of the plurality of FETs by asserting the corresponding drive signal when the PWM signal is asserted and the corresponding enable signal indicates that the corresponding FET is enabled, and de-asserting the corresponding drive signal when the PWM signal is de-asserted or the corresponding enable signal indicates that the corresponding FET is disabled.

[0028] In various embodiments, the driver circuit may also be used to drive a low-side power stage and a high-side power stage implementing a half-bridge.

[0029] For example, in various embodiments, the power stage of the driver circuit can be a low-side power stage, which includes a plurality of low-side FETs connected between the switch node and the ground, wherein one of the low-side FETs represents a reference FET; wherein the terminal of the driver circuit is configured to receive a low-side PWM signal. In this case, the driver circuit therefore also includes a high-side power stage, which includes a plurality of high-side FETs connected between the power supply voltage and the switch node and is configured to receive a high-side PWM signal with a given switching cycle. The other terminal, wherein the high-side PWM signal is asserted for the on period to indicate that the high-side power stage should be closed, and the high-side PWM signal is de-asserted for the off period to indicate that the high-side power stage should be disconnected. In this case, the current sensor of the driver circuit can be configured to provide a signal indicating the current provided by the switch node.

[0030] The driver circuit can use a low-side mode and a high-side mode instead of using two independent driver circuits. Specifically, in this case, the second circuit of the driver circuit can be configured to: in the low-side mode, when the low-side PWM signal is asserted, the second current is applied to the capacitor, and in the high-side mode, when the high-side PWM signal is asserted, the second current is applied to the capacitor. In addition, the control circuit of the driver circuit can be configured to: in the low-side mode, the reference current is set to an initial value, and then the reference current is increased or decreased until the logic level of the comparison signal changes, and the low-side value indicating the reference current value is stored when the logic level of the comparison signal changes. Similarly, in the high-side mode, the control circuit can set the reference current to an initial value, and then increase or decrease the reference current until the logic level of the comparison signal changes, and store the high-side value indicating the reference current value when the logic level of the comparison signal changes.

[0031] Thus, in this case, the comparison circuit of the driver circuit can be configured to determine a corresponding low-side enable signal for each of the plurality of low-side FETs by comparing the low-side value with a signal indicating the current provided by the switch node. Conversely, the additional comparison circuit can be configured to determine a corresponding high-side enable signal for each of the plurality of high-side FETs by comparing the high-side value with a signal indicating the current provided by the switch node.

[0032] Thus, the FET driver circuit of the driver circuit may be configured to generate a corresponding drive signal for each of the plurality of low-side FETs by combining a corresponding low-side enable signal with a low-side PWM signal, and the further FET driver circuit may be configured to generate a corresponding drive signal for each of the plurality of high-side FETs by combining a corresponding high-side enable signal with a high-side PWM signal. In various embodiments, for each high-side enable signal, the further FET driver circuit may include a corresponding level shifter circuit configured to generate a level-shifted version of the corresponding enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, provided by way of non-limiting examples only, in which:

[0034] Figure 1 An example of an electronic converter is shown;

[0035] Figure 2 An example of an implementation of a power stage with multiple parallel FETs is shown;

[0036] Figure 3 An embodiment of a buck converter is shown;

[0037] Figure 4a-4e Shows Figure 3 Exemplary waveforms of the operation of the converter;

[0038] Figure 5A shows exemplary waveforms when the electronic converter is operated in CCM;

[0039] Figure 5B shows exemplary waveforms when the electronic converter is operated in DCM;

[0040] Figure 6 An embodiment of a buck converter including one or more current sensors is shown;

[0041] Figure 7 and Figure 8 An embodiment of a general electronic converter is shown;

[0042] Fig. 9 shows the power loss of the power stage with switch partitioning;

[0043] Fig.10 An embodiment for selecting a partition value for a power level is shown;

[0044] Fig.11 and Fig.12 An embodiment of a circuit configured to generate a signal indicative of a drive loss of a FET is shown;

[0045] Fig.13 An embodiment of a circuit configured to generate a signal indicative of a FET conduction loss is shown;

[0046] Fig.14 An embodiment of a circuit is shown, which comprises Fig.11 and 13 Circuit;

[0047] Fig.15 shows a configuration that will be Fig.13 The signal generated by the circuit is the same as that generated by Fig.14 Embodiments of the comparator circuit for comparing the signals generated by the circuit;

[0048] Fig.16 An embodiment of a circuit configured to determine a division value of a power level is shown;

[0049] Fig.17 Shows Fig.16 A current comparison circuit of the circuit;

[0050] Fig.18 An example of a driver circuit with a switch-partitioned power stage is shown;

[0051] Fig.19A half-bridge driver circuit for a half-bridge power stage with switch partitioning is shown;

[0052] Fig. 20 shows a configuration to determine Fig.19 Embodiments of a circuit for dividing values ​​of a high-side power stage and a low-side power stage in a circuit;

[0053] Fig.21 Shown for Fig.19 A first embodiment of a level shifter circuit; and

[0054] Fig. 22 and 23 Shown for Fig.19 A second embodiment of the level shifter circuit is provided. DETAILED DESCRIPTION

[0055] In the subsequent description, numerous specific details are given to provide a comprehensive understanding of the embodiments. The embodiments may be practiced without one or more of the specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0056] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in multiple places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0057] The headings provided herein are for convenience only and are not intended to interpret the scope or meaning of the embodiments.

[0058] In the subsequent Figures 3 to 23 In, reference has been made Figure 1 and Figure 2 Described parts, elements or components are identified by the same reference numerals used previously in these figures; the description of such previously described elements will not be repeated subsequently to avoid unduly complicating this detailed description.

[0059] As mentioned above, the present disclosure relates to a solution for controlling the partitioning / segmentation of a power stage. As mentioned above, this solution is particularly useful in the case of electronic converters. However, the solution disclosed herein can also be used in other applications where it is necessary to control the partitioning / segmentation of a power stage.

[0060] Figure 3FIG. 2 shows a circuit diagram of an embodiment of a buck converter 20 a. In particular, the buck converter 20 a includes a circuit for receiving a DC input voltage V in The two input terminals 200a and 200b are used to provide a regulated voltage V out The two output terminals 202a and 202b, where the output voltage is equal to or lower than the input voltage V in .

[0061] In the embodiment considered, the buck converter 20a comprises two electronic switches Q1 and Q2 (with their current paths) connected in series (e.g., directly) between input terminals 200a and 200b, wherein the intermediate node between the electronic switches Q1 and Q2 represents the switching node Lx. Specifically, the electronic switch Q1 is a high-side switch connected (e.g., directly) between the (positive) terminal 200a and the switching node Lx, and the electronic switch Q2 is a low-side switch connected (e.g., directly) between the switching node Lx and the (negative) terminal 200b, which typically represents the ground GND. Therefore, the (high-side) switch Q1 and the (low-side) switch Q2 represent a half-bridge configured to connect the switching node Lx to the terminal 200a (voltage Vin) or the terminal 200b (ground GND).

[0062] In various embodiments, switches Q1 and / or Q2 are transistors, such as field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs), for example n-channel FETs, such as NMOS. Typically, the second electronic switch Q2 is also implemented simply with a diode, with the anode connected to terminal 200b and the cathode connected to the switch node Lx.

[0063] In the considered embodiment, an inductance L (such as an inductor) is connected (eg directly) between the switching node Lx and the (positive) output terminal 202a. Conversely, the (negative) output terminal 202b is connected (eg directly) to the (negative) input terminal 200b.

[0064] In the embodiment considered, in order to stabilize the output voltage V out , the converter 20 typically includes a capacitor C connected (eg, directly) between the output terminals 202a and 202b. out .

[0065] In this context, FIG4 shows exemplary waveforms of signals of such an electronic converter, where: Figure 4a A signal DRV1 for switching the electronic switch Q1 is shown; Figure 4b shows a signal DRV2 for switching the second electronic switch Q2; Figure 4c shows the current I through the electronic switch Q1 Q1 ; Figure 4d shows the voltage V at the switch node Lx Lx (i.e., the voltage at the second switch Q2); Figure 4e shows the current I through the inductor L L .

[0066] Specifically, when the electronic switch Q1 is closed at time t1 (on state), and the current I in the inductor L L (Substantially) linear increase. At the same time, the electronic switch Q2 is turned off. On the contrary, when the electronic switch Q1 is in the interval T ON1 Then, when it is disconnected at time t2 (off state), the electronic switch Q2 is closed, and the current I L (essentially) linearly decreases. Finally, in the interval T OFF1 Afterwards, switch Q1 is closed again. In the example considered, when switch Q1 is open, switch Q2 is therefore closed, and vice versa. Therefore, the current I L can be used to charge capacitor Cout, which supplies voltage V at terminals 202a and 202b. out .

[0067] In the embodiment considered, the electronic converter 20a thus comprises a control circuit 22 configured to drive the switching of the switch Q1 and the switch Q2 for periodically repeating the interval T ON1 and T OFF1 For example, the buck converter 20 typically further includes a feedback circuit 24 such as a voltage divider, the feedback circuit 24 being configured to generate a voltage indicating the output voltage V out The control circuit 22 is configured to generate a feedback signal FB (and preferably proportional thereto) by comparing the feedback signal FB with a reference signal (such as a reference voltage V ref ) are compared to generate driving signals DRV1 and DRV2.

[0068] A large number of drive schemes for generating the drive signals DRV1 and DRV2 are known. These solutions have in common that the interval T ON1 and / or interval T OFF1 The duration of the regulation of the output voltage V out For example, in various embodiments, the control circuit 22 generates a pulse width modulation (PWM) signal DRV1, where the duty cycle D=T ON1 / (T ON1 +T OFF1 For example, a typical control scheme involves varying the duty cycle D via a regulator circuit having at least one integral component, such as a PI (proportional-integral) or PID (proportional-integral-derivative) regulator.

[0069] Typically, a buck converter can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or transition mode (TM). Typically, the control circuit can also be configured to selectively operate the switch stage in high power mode (HPM) or low power mode (LPM).

[0070] For example, in the high power mode, the control circuit 22 may be configured to drive the switch in CCM. Figure 5A As shown, when the control circuit 22 operates the converter in CCM, when the switching period T SW At the end, the current I flowing through the inductor L L has a value different from zero. In this case, the control circuit 22 uses two switching phases T1 and T2 (T SW =T1+T2), where: In stage T1 (T1=T ON1 =T OFF2 ), the switch Q1 is closed and the switch / diode Q2 is open; and in phase T2 (T2=T OFF1 =T ON2 ), switch Q1 is open and switch / diode Q2 is closed.

[0071] In various embodiments, CCM uses constant frequency PWM modulation. For example, in this case, time t1 can be periodically changed at a constant time T SW After that, it starts. On the contrary, it can be based on the feedback signal FB and the reference signal V ref The time t2 is determined, for example, by using a proportional-integral (PI) or proportional-integral-derivative (PID) regulator, which is configured to directly change the duty cycle D or the on-time T ON1 To adjust the feedback signal FB to the reference signal V ref ; or by the current I flowing through the inductor L L (or the value indicating the current) reaches the maximum threshold value and ends the on-time T ON1 , where the PI or PID regulator is configured to change the maximum threshold to adjust the feedback signal FB to the reference signal V ref .

[0072] Conversely, in the low power mode, the control circuit 22 may be configured to drive the switches in a burst mode. Specifically, in this case, the control circuit 22 is configured to alternately close the electronic switches Q1 and Q2 for one or more cycles, and then both electronic switches are opened. Thus, in this case, the control circuit 22 (at least for the last burst) actually uses three switching phases T1, T2, and T3 (where T SW =T1+T2+T3), where: in stage T1 (T1=T ON1), the switch Q1 is closed and the switch / diode Q2 is open; in phase T2 (T2 = T ON2 ), switch Q1 is open and switch / diode Q2 is closed; and in phase T3 (T OFF1 =T2+T3 and T OFF2 =T3+T1), the switch Q1 is turned off and the switch / diode Q2 is turned off.

[0073] For example, Figure 5B As shown, the control circuit 22 can be configured to: at time t2 after a constant on-time or after an on-time determined according to the feedback signal FB, open the switch Q1 and close the switch Q2; at time t3, preferably at a current I L When it reaches zero, the electronic switch Q2 is turned off, thereby reducing the switching loss; and a new switching cycle starts at the time t1 when the feedback signal FB reaches the lower threshold.

[0074] For example, the output voltage V out The reference signal V ref Determine the lower threshold.

[0075] In various embodiments, a (usually fixed) dead time may also be introduced between the switching of the drive signals, for example, between the falling edge of the signal DRV1 and the rising edge of the signal DRV2, and similarly (in CCM mode) between the falling edge of the signal DRV2 and the rising edge of the signal DRV1. ON and T OFF These intervals will not be considered specifically in the following because of their generally shorter range.

[0076] Therefore, in essence, the burst mode can correspond to a special case of DCM, in which when the current I L When zero is reached, the electronic switch Q2 turns off (and remains off during interval T3).

[0077] like Figure 6 As shown, to this end, the control circuit 22 may include or be connected to a zero current detection (ZCD) circuit 26, which is configured to generate a zero current signal ZC, which indicates (at least) when the current I L The zero current detection circuit 26 may include a current sensor 26a connected directly in series with the inductor L, wherein the current sensor 26a provides an indication of the current I flowing through the inductor L. L In various embodiments, current sensor 26a may be replaced by current sensor 26c, which is configured to provide a current I indicative of the current flowing through switch Q2.Q2 (and preferably proportional to) the signal CS3, the current I Q2 Corresponding to the current I flowing through the inductor L during the interval T2 L .

[0078] For example, the zero current signal ZC may be determined via a comparator (so-called zero current comparator) of the ZCD circuit 26, which is configured, for example, to determine whether the monitored signal CS1 or CS3 is below a given threshold value (which is usually close to zero). Figure 5B An example of a zero current signal ZC is shown in , which is set high when the measured current is less than a threshold value (close to zero).

[0079] Thus, in the embodiment considered, the electronic switches Q1 and Q2 are the power switches of the electronic converter 20a. Figure 2 As described, each of the electronic switches Q1 and Q2 can be replaced by a corresponding power stage Q, which includes multiple (physical) parallel electronic switches and / or one electronic switch, which can be divided into multiple partitions / segments. In this case, the control circuit 22 is therefore configured to generate a number K of drive signals D1-DK for the corresponding number K (physical or virtual) switches S1-SK of each of the power stages Q1 and Q2 to select the number N of electronic switches to be closed. For example, in various embodiments, the power stages Q1 and Q2 are implemented using the same number of parallel (physical or virtual) electronic switches S1-SK, that is, K1=K2=K.

[0080] For example, in order to close a given number N1 of electronic switches S1-SK implementing the power stage Q1, the control circuit 22 may set the N1 drive signals D1-DK of the power stage Q1 to the drive signals DRV1 as described above, and set the other K1-N1 drive signals D1-DK of the electronic switches Q1 to a logic level (e.g., low) that keeps the corresponding switches open. Similarly, in order to close a given number N2 of electronic switches S1-SK implementing the power stage Q2, the control circuit 22 may set the N2 drive signals D1-DK of the power stage Q2 to the drive signals DRV2 as described above, and set the other K2-N2 drive signals D1-DK of the electronic switches Q2 to a logic level (e.g., low) that keeps the corresponding switches open.

[0081] In various embodiments, the power stage includes K (physical and / or virtual) electronic switches S1-SK having different division factors. For example, electronic switch S1 may have a (normalized) division ratio of one, electronic switch S2 may have a division ratio of two, electronic switch S3 may have a division ratio of four, and electronic switch S4 may have a division ratio of eight, i.e., considering a general electronic switch Si, the division factor of the switch may be 2 (i-1) Therefore, in this case, similar to binary coding, the power level Q can be divided into 1 and (2 K -1), that is, 1≤N≤(2 K -1). For example, assuming that the power stage includes 4 electronic switches S1-S4, the power stage can have a division value N selected between 1 and 15. Therefore, in this case, the driver circuit of the power stage Q can determine the required division rate N and then drive the K electronic switches S1-SK to obtain the required division rate N.

[0082] For example, the driver circuit may drive: electronic switch S1 to obtain a division rate of N=1; electronic switches S1 and S2 to obtain a division rate of N=3; electronic switch S3 to obtain a division rate of N=4; and electronic switches S1, S2, S3 and S4 to obtain a division rate of N=15.

[0083] Therefore, in various embodiments, the driver circuit can convert the required division value N into its binary representation, where each bit of the binary value (having K bits) indicates whether the corresponding electronic switch S1-SK should be driven / enabled during the switching cycle. In general, different division rates can also be used for the electronic switches S1-SK.

[0084] Therefore, in general, the driver circuit can first determine the required division value N, which can be between the minimum value N min (corresponding to the partition factor of the switch with the smallest partition factor, e.g., a (normalized) partition value of one) and the maximum value N max (corresponding to the division value when all switches S1-SK are driven / enabled), and then driving K electronic switches according to the required division value N and the division rate of the electronic switches S1-SK to obtain the required division value N.

[0085] As will be described in more detail below, in various embodiments, the control circuit 22 can therefore determine the corresponding required division value N for each power stage Q1 and Q2 based on the (total) current flowing through the corresponding power stage. Q1The current I flowing through the power stage Q2 can be monitored via the current sensor 26a or the current sensor 26b connected in series with the power stage Q1. Similarly, the current I flowing through the power stage Q2 can be monitored via the current sensor 26a or the current sensor 26c. Q2 .

[0086] Similar problems exist in other electronic converters, or in general, where variable currents may flow through a power stage Q.

[0087] For example, Figure 7 A general electronic converter is shown. Specifically, in the embodiment considered, the electronic converter 20a comprises a switching stage / circuit 28 connected between input terminals 200a, 200b and output terminals 202a, 202b. Such a switching stage 28 comprises one or more reactive components (such as an inductor L and / or a capacitor C out ) and one or more electronic switches (such as Q1 and Q2) are configured to selectively transfer energy from the input terminals 200a and 200b to the one or more reactive components and / or from the one or more reactive components to the output terminals 202a and 202b.

[0088] Specifically, in this case, the electronic converter further comprises a control circuit 22a, which is configured to generate a corresponding drive signal, such as drive signals DRV1 and DRV2, for each of the electronic switches Q1 and Q2. For example, typically, the control circuit 22a is configured to generate the drive signal according to the feedback signal FB provided by the feedback circuit 24, wherein the feedback signal FB indicates the output voltage V out (in the case of a regulated voltage generator) or the output current I out( In the case of a regulated current generator, this is schematically illustrated, for example, via a PWM generator (PWM Gen.) circuit 220 configured to generate a PWM signal (PWM). For example, the circuit 220 may be an analog and / or digital PI or PID regulator configured to vary the on-duration of the signal DRV, or more generally, the duty cycle, to vary the reference signal V ref The difference between the feedback signal FB is adjusted to zero.

[0089] For example, when using CCM, the driver circuit 210 can be configured to detect rising and falling edges in the drive signal PWM and: in response to a rising edge in the drive signal PWM, set the signal DRV2 for the electronic switch Q2 to low (e.g., immediately) and set the signal DRV1 for the electronic switch Q1 to high (e.g., after a first dead time); and in response to a falling edge in the drive signal PWM, set the signal DRV1 to low (e.g., immediately) and set the signal DRV2 to high (e.g., after a second dead time).

[0090] Conversely, when DCM is used, the driver circuit 210 may also receive a zero current signal ZC from a zero current detector (ZCD) circuit 26 configured to monitor a signal CS indicating a current flowing through the inductor L. For example, in this case, the driver circuit 210 may be configured to detect rising and falling edges in the drive signal DRV, and: in response to a rising edge in the drive signal PWM, set a signal DRV1 for the electronic switch Q1 to high (e.g., immediately or after a first dead time); in response to a falling edge in the drive signal PWM, set the signal DRV1 to low (e.g., immediately) and set the signal DRV2 to high (e.g., after a second dead time); and in response to detecting that the current flowing through the inductor L reaches zero, set the signal DRV2 to low (e.g., immediately).

[0091] However, other different numbers of electronic switches Q1 and Q2 and / or different driving schemes may also be used. In fact, as will be described in more detail below, it is sufficient that each electronic switch Q1 and Q2 receives a corresponding drive signal for switching the corresponding electronic device on (when the corresponding drive signal has a first logic level / is asserted) and off (when the corresponding drive signal has a second logic level / is de-asserted).

[0092] For example, as described above, in various embodiments, each drive signal is a PWM signal. Figure 8 As shown, the PWM signal has a switching period T Sw (e.g., with a fixed, predetermined, or variable period), where for a first duration T ON , the signal PWM is asserted / set to a first logic level (eg, high) to close the corresponding electronic switch, and for a second duration T OFF , the signal PWM is de-asserted / set to a second logic level (eg, low) to turn off the corresponding electronic switch, wherein T Sw =T ON +T OFF Usually, various driving signals have the same period T Sw For example, regarding Figure 5A and 5B , on-time T ON Corresponding to T1 of the driving signal DRV1 and T2 of the driving signal DRV2, and both the driving signals DRV1 and DRV2 have the same switching period T Sw .

[0093] Thus, also in this case, at least one of the electronic switches Q1 and Q2 may be implemented with a power stage Q comprising a plurality K of (physical and / or virtual) electronic switches (particularly FETs) connected in parallel, wherein each of the K electronic switches receives a respective drive signal D1-DK. Thus, in the embodiment considered, the driver circuit of the power stage Q1 (e.g. the driver circuit 210) is configured to generate a drive signal D1 to DK for each of the power stages Q1 and Q2.

[0094] As mentioned above, various embodiments of the present disclosure relate to a solution for selecting a partition value N of a power stage Q comprising K (physical and / or virtual) electronic switches (especially FETs), and for selecting a partition value N of a power stage Q comprising K (physical and / or virtual) electronic switches (especially FETs) ... SW The corresponding electronic switches to be driven / enabled during this period.

[0095] As mentioned above, the losses of field effect transistors mainly come from ohmic losses and dynamic losses. For example, as also disclosed in the document George Lakkas, “MOSFET power losses and how they affect power-supplyefficiency”, 2016, Texas Instruments (incorporated herein by reference), the power loss P of a FET driven by a PWM signal is FET It can be approximated by the following equation including conduction loss and drive loss:

[0096]

[0097] Among them, Q g (V gs ) is the gate charge, which depends on the gate-source voltage V gs , f sw =1 / T Sw is the switching frequency, I rms is the root mean square (RMS) current flowing through the FET, and R ds，ON (V gs ) is the on-resistance of the FET, which depends on the gate-source voltage V gs .

[0098] Therefore, when driving a given number N of parallel FETs, the gate charge and hence the dynamic losses increase proportionally, and the on-resistance and hence the ohmic losses decrease proportionally, i.e., the total losses P of the power stage Q are lossCD for:

[0099]

[0100] The first term corresponds to the drive loss P lossD , the second term corresponds to the conduction loss P lossC .

[0101] Therefore, in order to determine the optimal value N of the split value N for a given power level Q opt , we can calculate the derivative of equation (2) and determine the conditions when the derivative is zero, namely:

[0102]

[0103] It can be rewritten as:

[0104]

[0105] In fact, the power loss P of the FET FET Not only the driving losses are included, but also the switching losses. However, it should be noted that the switching losses of the power stage are quite independent of the number of closed electronic switches of the power stage. Therefore, for a given operating condition, these losses are essentially constant in equation (1) and are removed when calculating the derivative.

[0106] For example, Fig. 9 The driving loss P according to the division value N of the power level Q is shown. lossD , conduction loss P lossC and total loss P lossCD The relationship between the optimal partition value N opt The loss P lossCD The minimum value of .

[0107] Specifically, considering equation (4), the minimum loss condition of a given FET is achieved when the driving loss of the given FET is equal to the conduction loss of the FET, and the minimum loss condition of the given FET is achieved when the driving loss of the given FET is equal to the conduction loss of the given FET. Sw The number of FETs turned on during the period is irrelevant, that is:

[0108]

[0109] Based on equation (5), the optimal value of the RMS load current can be determined (At this optimized value the given reference FET of the power stage Q operates with minimum losses):

[0110]

[0111] Therefore, in various embodiments, the driver circuit can be configured to control the power stage according to the (total) current I Q RMS value of I Q，rms , reference FET optimized value The partition value is determined by the partition factor of the reference FET. For example, in various embodiments, the reference FET corresponds to the FET with the minimum partition factor, which is associated with a normalized partition factor of one. Therefore, in this case, the optimized partition value can be calculated as:

[0112]

[0113] For example, in various embodiments, the driver circuit of the power stage Q is configured to divide the power stage Q by the value of To calculate the RMS value I Q，rms N corresponding thresholds.

[0114] For example, Fig.10 An embodiment is shown, in which the driver circuit of the power stage Q is configured such that when the RMS value of the current flowing through the power stage I Q，rms At 0 and When the RMS value of the current flowing through the power stage is I Q，rms exist and When the RMS value of the current flowing through the power stage is I Q，rms exist and When between, select FET with division value N=3; and so on.

[0115] In this regard, the document Graovac, Marco Pürschel, Andreas Kiep, "MOSFET Power Losses Calculation Using the Data Sheet Parameters", Application Note, V 1.1, July 2006, Infineon Technologies AG (incorporated herein by reference), or The webpage "Root mean square" (incorporated herein by reference) discloses how to calculate the RMS value of different waveforms. In addition, the above-mentioned Graovac's document explicitly deals with current flowing through FETs, also in the context of a typical electronic converter.

[0116] For example, as mentioned above, in various embodiments, the driving signal of the power stage Q is a signal having a given on-time period T ON and the off period T OFF In this case, the RMS value I rms It can be calculated according to the following equation:

[0117]

[0118] Among them I rms，ON During the on-time period T ON The root mean square (RMS) current flowing through the FET during rms，OFF During the off period T OFF The root mean square (RMS) current flowing through the FET during the off period. OFF During this period, the current flowing through the FET is approximately zero, so equation (8) can be simplified to:

[0119]

[0120] Where D = T ON / T Sw is the duty cycle.

[0121] Therefore, in various embodiments, the driver circuit of the power stage Q can determine the switching interval T according to equations (6) and (9). ON The optimized RMS value of the current flowing through the reference FET during

[0122]

[0123] Next, the driver circuit of the power stage Q obtains (eg, measures or calculates) the current during the on period T ON The current I flowing through the power stage Q during Q RMS value of I Q，rms，ON , and according to the RMS value To determine the split value, similar to equation (7). For example, assuming again that the reference FET corresponds to a FET with a split factor of one, then the optimal split value N opt Can be determined as:

[0124]

[0125] For example, in various embodiments, the driver circuit of the power stage Q is configured to be divided into two groups according to the value Determine the RMS value I Q，rms，ON The corresponding threshold value.

[0126] In this regard, it is assumed that during the on-time T ONThe current flowing through the power stage Q is constant during this period, that is, the current I Q Corresponding to I Q，max The square wave current that switches between zero and zero, the driver circuit can calculate the RMS value I according to the following equation Q，rms，ON :

[0127] I Q，rms，ON =I Q，max , that is, I Q，max =I Q，rms，ON (12)

[0128] In contrast, in an electronic converter, the current I Q Usually during the on time T ON The period increases or decreases substantially linearly. In this case, the driver circuit can calculate the RMS value I according to the following equation Q，rms :

[0129]

[0130] Among them I Q，max corresponds to the maximum / peak value of the (increasing or decreasing) ramp, and I Q，min Corresponds to the minimum value of the (increasing or decreasing) ramp. For example, for DCM or TM control, the minimum current I Q，min is usually zero, and equation (13) can be simplified as follows:

[0131] Right now,

[0132] Therefore, for example, according to equation (12) or (14), in various embodiments, the driver circuit can obtain (eg, measure or calculate) the current during the on period T ON The current I during Q The peak value I Q，max , and according to the optimized value Determine the peak value for I Q，max For example, again assuming that the reference FET corresponds to a square wave current I Q FET, the driver circuit can determine the optimal division value N according to equation (11) opt :

[0133]

[0134] For example, in various embodiments, with the current I Q Regardless of the specific current profile of I, the driver circuit uses equation (12) as a simplification (worst case scenario), i.e., I Q，rms，ON =I Q，maxFor example, similar to what was described previously, in the following cases, the driver circuit of the power stage Q can select a given division value N: when the peak value I of the (total) current flowing through the power stage Q Q，max is between and or alternatively between and , where N is at least 1. Generally, other solutions can also be used to determine the threshold according to the value . For example, when the peak value of the (total) current flowing through the power stage Q is between and , where 0 < m ≤ 1 and N is at least 1, the driver circuit of the power stage Q can activate a given number N of FETs.

[0135] In various embodiments, the driver circuit can determine (as an approximation) the division value N according to other values indicating the current I Q , such as according to the average value ON of the current I Q during the on-time period T instead of directly using the value I Q，rms，ON or a value proportional to the value I Q，rms，ON (such as I Q，max for a square-wave or sawtooth current profile).

[0136] Therefore, in various embodiments, as shown in equation (10), the driver circuit of the power stage Q is configured to determine the optimized (optimized) value of the reference FET of the power stage, where the RMS value depends on the current operating conditions of the reference FET. For example, as shown in equation (10), the value depends at least on the gate-source voltage V gs , the switching frequency f sw and the duty cycle D. In addition, although not shown in equations (6) and (10), the optimized value also depends on aging, process, and temperature variations, which may affect the charge Q g and the on-resistance R ds，ON .

[0137] Hereinafter, embodiments of a circuit configured to generate a first signal indicating the drive loss Q g (V gs )V gs f sw and / or a second signal indicating the conduction loss DRd s (V gs ) will now be described.

[0138] For example, Fig.11An embodiment of a circuit 42 configured to generate a signal indicative of a drive loss is shown. As previously described, each power stage Q includes a plurality of K (physical and / or virtual) parallel-connected FETs that have substantially the same product characteristics, for example, because the FETs are implemented using the same production process. However, the FETs may have different sizes to achieve different division factors, for example, the FETs may have different channel widths. In addition, the power stage receives a PWM signal that is selectively forwarded to a given number of enabled FETs to achieve a given selected division value N.

[0139] In this regard, the drive loss estimation circuit 42 is configured to generate an indicator Q(V gs )·f sw ·V gs signal. To this end, in the embodiment under consideration, the circuit 42 includes a capacitor 424. Specifically, in the embodiment under consideration, the capacitor 424 is used to simulate the capacitance associated with the gate node of the reference FET of the power stage Q. For example, in the embodiment under consideration, a FET XM (such as an n-channel MOSFET), which represents a scaled version of the reference FET, is used to implement the capacitor 424. For example, in the embodiment under consideration, the source and drain nodes of the FET XM are (for example, directly) connected to the ground. The drain terminal can also be connected to another reference voltage, but shorting the drain terminal and the source terminal of the FET XM ensures that no additional losses are generated by the current flowing between the source terminal and the drain terminal of the FET XM. Typically, instead of using a single FET XM, the capacitor 424 can also include multiple FETXMs, wherein the gate terminals are connected to a common node.

[0140] Therefore, in the embodiment considered, the capacitor 422 has a value corresponding to C XM =a·C copy where a is the scaling factor between the FET(s) XM and the reference FET, and C copy represents the value of the gate capacitance of a FET that is an exact replica (not scaled) of the reference FET. Therefore, capacitance C XM The values ​​corresponding to the scaled values ​​of the gate-source and gate-drain capacitances of the reference FET include. In this regard, by implementing FET XM as a scaled replica of the reference FET, FET XM will also be subject to the same process variations. Furthermore, by placing FET XM in the vicinity of the reference FET, such as in the vicinity within the same integrated circuit, FET XM will (approximately) be subject to the same temperature variations and / or aging as the reference FET.

[0141] In the embodiment considered, the circuit 42 further comprises a current digital-to-analog converter (DAC) 420 configured to generate a current I DAC , the current I DAC is provided to the gate node of FET XM (also shown as node A). For example, in the embodiment considered, DAC 420 generates a current I according to the digital signal trial_current_cfg. DAC , which will be described in more detail later.

[0142] In various embodiments, DAC 420 does not convert current I DAC directly to the gate node A of FET XM, but an additional current mirror 422 is used to convert the current I DAC / b is applied to the gate node A of FET XM, where the current I DAC / b and current I DAC For example, in the embodiment under consideration, the current mirror 422 is implemented using p-channel FETs (eg, MOSFETs) M1 and M2 powered by a voltage VDD, wherein the input transistor M1 of the current mirror 422 receives the current I DAC , and the output transistor M2 of the current mirror 422 provides a current I DAC / b, the current I DAC / b is fed to the gate node A. Therefore, the current I DAC / b is fed to node A and charges the capacitance associated with node A.

[0143] In the embodiment considered, the circuit 42 further comprises an electronic switch Mdis configured to selectively discharge the capacitor 424 according to the reset signal Res. For example, in the embodiment considered, the electronic switch Mdis is an n-channel FET, wherein the drain node is connected to the node A, the source node is connected to the source node of the FET XM, i.e. to the ground, and the gate node receives the signal Res. Thus, in various embodiments, when the signal Res is asserted (e.g., set to high), the node A is connected to the ground via the electronic switch Mdis, and the capacitor 422 is discharged. Conversely, when the signal Res is de-asserted (e.g., set to low), the electronic switch Mdis is turned off, and the current I DAC Or generally speaking, DAC / b charges the capacitor 422, thereby generating a ramp signal at the node A.

[0144] In the embodiment considered, the voltage V at the node A is A is fed to comparator 426, which is configured to convert the voltage V ASpecifically, in various embodiments, the threshold voltage is compared to the gate-source voltage V of the reference FET used to drive the power stage Q. gs Proportional, that is, V gs / c. For example, in the embodiment under consideration, the threshold voltage Vgs / c is obtained via a voltage divider including two resistors R1 and R2 connected in series between the voltage Vgs and ground, whereby an intermediate node between the resistors R1 and R2 provides a scaled voltage Vgs / c based on the resistances of the resistors R1 and R2. Specifically, in the embodiment under consideration, the comparator 426 is configured to determine the voltage V in response to the voltage V A Less than the threshold voltage V gs / c asserts (eg, is set high) the signal Od, and in response to determining the voltage V A (equal to or) greater than the threshold voltage Vgs / c to assert (eg, set low) the signal Od.

[0145] For example, this means that the signal Od is initially asserted, and once the voltage V A Reaching the threshold voltage V gs / c, the signal Od is de-asserted. This also means, for example, that when the current I DAC If it is too small, the voltage V A The threshold voltage V is never reached gs / c, so the signal will have a 100% duty cycle. Therefore, when increasing the current I DAC When the duty cycle D Od Reduce.

[0146] In various embodiments, such as Fig.12 As shown, the signal Res corresponds to a trigger signal, which is activated in each switching cycle T of the reference FET. SW For example, the signal Res may be generated via an edge detector (such as a monostable circuit) configured to monitor a PWM drive signal for driving the power stage Q, or the signal Res may be provided directly by a circuit that generates a PWM drive signal.

[0147] therefore, Fig.11 The circuit 42 shown is configured to generate a signal Od having a value according to the current I DAC , the gate capacitance C of the scaled FET XM XM and the gate-source voltage V gs Determine the duty cycle D Od .

[0148] Specifically, in the embodiment considered, when the voltage V at the node A is A Reaching the threshold voltage V gsWhen / c is used, the following relationships apply:

[0149]

[0150] On the contrary, the duty cycle D of the signal Od Od can be written as:

[0151]

[0152] Using D Od =T Od，ON / T Sw , where T Od，ON Corresponding to the on-time when the signal Od is asserted, it can be written as:

[0153] D Od =(Q(V gs )·f sw ·V gs ).1 / V gs ·(a·b) / c·1 / I DAC (18)

[0154] Where Q(V gs )=C copy ·V gs The gate charge of an unscaled replica of the reference FET corresponding to power stage Q.

[0155] Thus, the term (a·b) / c represents the (constant) scaling factor of the circuit 42 and for a given current I DAC , as specified via the signal trial_current_cfg, the circuit 42 generates a current having a duty cycle D Od The duty cycle is proportional to the drive losses of the reference FET of the power stage Q and to the applied current I DAC and the gate-source voltage V gs Inversely proportional.

[0156] Thus, in the embodiment considered, the circuit 42 is configured to provide a current I DAC / b charges the scaled capacitor 424, and in response determines the voltage V at the capacitor 424 A The signal Od is asserted when a threshold proportional to the gate-source voltage Vgs is reached. In addition, the circuit sw The charge of the reset capacitor 424 is reset once, and thus the signal Od has a switching period T sw In various embodiments, the circuit can also be operated in multiple switching cycles T sw Capacitor 424 is then reset, whereby an additional scaling factor is added to equation (18).

[0157] Fig.13 4 shows an embodiment of a circuit 44, which is configured to generate a signal indicative of conduction losses. Specifically, the conduction loss estimation circuit 44 is configured to generate an indicator DR ds，ON (V gs ). To this end, in the embodiment considered, the circuit 44 comprises a resistor 444. Specifically, in the embodiment considered, the resistor 444 is used to simulate the on-resistance R of the reference FET of the power stage Q. ds，ON For example, in the embodiment under consideration, the resistor 444 is implemented using a FET XN (such as an n-channel MOSFET), wherein the FET XN represents a scaled version of the reference FET, and wherein the gate terminal of the FET XN is driven via the gate-source voltage Vgs of the reference FET. In general, instead of using a single FET XN, the resistor 444 may also include a plurality of FETs XN connected in series. For example, in the embodiment under consideration, the drain node of the FET XN (or the first FET XN) is connected to the node E, and the source node of the FET XN (or the last FET XN) is connected to the ground.

[0158] Therefore, in the embodiment considered, the resistor 442 has a value corresponding to R XN =d·R copy where d is the scaling factor and R copy represents the value of the on-resistance of a FET that is an exact replica (not scaled) of the reference FET. Therefore, the resistor R XN The on-resistance R of the reference FET ds，ON In this regard, by implementing FET XN as a scaled replica of the reference FET, FET XN will also be subject to the same process variations. Furthermore, by placing FET XN in the vicinity of the reference FET, such as in the vicinity within the same integrated circuit, FET XN will (approximately) be subject to the same temperature variations and / or aging as the reference FET.

[0159] In the embodiment considered, the circuit 44 comprises a regulator 448 configured to apply to the node E a voltage proportional to the gate-source voltage Vgs applied to the reference FET, whereby the voltage V at the node E E is set to V gs For example, in the embodiment considered, the scaled gate-source voltage Vgs / e is obtained via a voltage divider comprising two resistors R3 and R4 connected in series between the voltage Vgs and ground.

[0160] For example, in the embodiment under consideration, the regulator 448 includes an operational amplifier OP1 that receives at a first input terminal (typically an inverting / negative input terminal) a voltage V at the node E.E , and receives the scaled voltage Vgs / e at a second input terminal (typically the non-inverting / positive input terminal). In addition, the output terminal is configured to drive a variable current generator M5 (e.g., implemented via an n-channel FET) that adjusts the current supplied to node E based on the signal provided at the output of the operational amplifier OP1. Thus, in essence, the regulator 448 is configured to change (i.e., increase or decrease) the current flowing through the current generator M5 (and resistor 444) until the voltage V at node E is E Corresponding to the scaled voltage Vgs / e. Therefore, regulator 448 ensures the following current I XN Flowing through resistor 444:

[0161] I XN =V gs / d·e·R ds，ON (V gs ) (19)

[0162] Specifically, in the embodiment considered, the circuit 44 also includes a DAC 440 configured to generate a current I DAC , the current I DAC is provided to the node F. For example, in various embodiments, the DAC 440 receives a digital signal trial_current_cfg, which will be described in more detail later. In addition, in various embodiments, the DAC 440 does not directly provide the current I to the gate node F. DAC , but an additional (and optional) current mirror 442 is used to convert the current I DAC / f is applied to node F, where the current I DAC / f is based on the given mirror factor f of the current mirror 422 and the current I DAC For example, in the embodiment under consideration, the current mirror 442 is implemented using p-channel FETs (such as MOSFETs) M4 and M3 powered by the voltage VDD, wherein the input transistor M4 of the current mirror 442 receives the current I DAC , and the output transistor M3 of the current mirror 442 provides a current I DAC / f, the current I DAC / f is fed to node F. For example, in various embodiments, the mirroring factor f is unity.

[0163] In the embodiment considered, the circuit 44 also comprises a capacitance C (such as a capacitor), which may be located internally or externally with respect to the integrated circuit comprising the circuit 44, wherein the capacitance C is connected between the node B and ground.

[0164] Specifically, the circuit 44 includes an electronic switch SW1, which is configured to selectively switch the current I DAC (or generally speaking I DAC / f) is applied to node B, that is, the switch SW1 is configured to be on during the on period T of the PWM signal for driving the power stage Q. ON The capacitor C is charged during this period. Optionally, the circuit 44 may include another electronic switch SW2, which is configured to selectively switch the current I DAC (or generally speaking I DAC / f) is applied to ground. Basically, the switch is used only to avoid that the node F remains floating. For example, in the embodiment considered, the switches SW1 and SW2 are implemented using p-channel FETs (such as PMOS), wherein the p-channel MOSFET is driven via an inverted version of the signal PWM, and the p-channel FET SW2 is driven via the signal PWM.

[0165] In various embodiments, the circuit 44 further includes an electronic switch SW3 configured to selectively switch the current I flowing through the resistor 444 to the current I flowing through the resistor 444 when the signal O is asserted. XN Applied to node B, i.e., switch SW3 is configured to discharge capacitor C when signal O is asserted. Optionally, circuit 44 may also include an additional electronic switch SW4, which is configured to selectively connect regulator circuit 448 to a reference voltage, such as VDD, when signal O is de-asserted. Basically, this switch is only used to provide bias for current source M5. For example, in the embodiment considered, switches SW3 and SW4 are implemented using n-channel FETs (such as NMOS).

[0166] In the embodiment considered, the voltage V at the capacitor C is B is provided to a comparator 446 with hysteresis, and the comparator 446 is configured to B Reaching the upper threshold V th1 The signal is asserted O, and when the voltage V B Reaching the lower threshold V th2 to assert signal O.

[0167] Therefore, considering any time interval T, for the period D·T, the switch SW1 is closed and the current I DAC (or generally speaking I DAC / f) is applied to (in particular, sourced to) node B, thereby applying a given charge to capacitor C, which results in a theoretical voltage increase ΔV1 during interval T.

[0168] ΔV1=IDAC / f·C·D·T (20)

[0169] However, once the voltage V B Reaching the upper threshold V th1 , comparator 446 asserts signal 0, whereby the capacitor flows through current I XN Discharge until the voltage V B Reaching the lower threshold V th2 Therefore, consider an arbitrary time interval T, and assume that for a given duty cycle D o When switch SW3 is closed, for period D o The T switch SW3 is closed and a current IXN is applied to the node B (in particular is drawn from the node B), thereby applying a given charge to the capacitor C, which results in a theoretical voltage drop of ΔV2 during the interval T.

[0170]

[0171] Therefore, in the steady state, the theoretical voltage increase ΔV1 during the interval T should correspond to the theoretical voltage decrease ΔV2 during the interval T, that is:

[0172] I DAC / (f·C)·D·T=V gs / (d·e·R ds，ON (V gs )·C)·D O ·T (22)

[0173] Therefore, the duty cycle D of signal O under steady-state conditions can be determined using equation (22): o ,Right now:

[0174] D o =I DAC / (f·C)·D·(d·e·R ds，ON (V gs )·C) / V gs (twenty three)

[0175] This can be written as

[0176] D O =(D·R ds，ON (V gs )·I DAC 2 )·1 / I DAC ·(d·e) / f· / V gs (twenty four)

[0177] Therefore, the term (d·e) / f represents a (constant) proportionality factor and for a given current I DAC, as specified via the signal trial_current_cfg, the circuit 44 generates a current having a duty cycle D o The duty cycle is proportional to the conduction losses of the reference FET of the power stage Q and to the applied current I DAC and the gate-source voltage V gs Inversely proportional.

[0178] For example, the operation of circuit 44 means that signal O is first de-asserted, and once voltage V B The upper threshold voltage of comparator 446 is reached and signal O is asserted. This also means, for example, that when current I DAC If it is too small, the voltage V B The upper threshold voltage is never reached, and the signal will have a 0% duty cycle. Therefore, when increasing the current I DAC When the duty cycle D O Increase.

[0179] Therefore, in the embodiment considered, the circuit 44 is configured to ON During this period, the current I DAC / f charges the capacitor C of the drive signal PWM of the power stage Q, and when the signal O is asserted, the current I XN Discharge the capacitor C, where the current IX N is generated by applying the voltage Vgs / e to the scaled resistor 444, and the signal is generated via a comparator with hysteresis that is configured to convert the voltage V at the capacitor B Comparison is made to upper and lower thresholds. As previously described, although the thresholds are chosen between zero and VDD, the values ​​of the thresholds are fairly unrelated, and the voltage varies between these thresholds, thereby generating the theoretical voltage variations ΔV1 and ΔV2.

[0180] Fig.14 A combined solution including the above-mentioned circuits 42 and 44 is shown. Specifically, Fig.14 A circuit is shown including a single current DAC 400 and a current mirror 402 that receives a current I generated by the DAC 400 at an input stage M1. DAC , and provides mirrored (and possibly scaled) currents to nodes A and F via two output stages M2 and M3, respectively. Therefore, current mirror 402 implements Fig.11 and Fig.13 As shown, the current mirrors 424 and 444 are shown. For the rest, the circuit 40 includes Fig.11 and 13 Other components described.

[0181] By comparing equations (18) and (24), it can be observed that when the duty cycle D of the signal Od is Od Corresponding to the duty cycle D of signal O o When the current reaches I DAC The optimization conditions are:

[0182]

[0183] Right now:

[0184]

[0185] More specifically, solving I DAC Equation (26) provides:

[0186]

[0187] Therefore, by comparing equations (10) and (27), it can be observed that the current I is reached when DAC Optimization conditions

[0188]

[0189] Where g corresponds to a fixed gain, which can be set, for example, via a capacitance scaling factor a, a mirror ratio b, a threshold scaling factor c, a resistance scaling factor d, a threshold scaling factor e, and a mirror factor f. For example, in various embodiments, various coefficients a to f are set so that the gain g is unity, where the optimized value Corresponding to the optimized value

[0190] Fig.15 A possible embodiment of the circuit 46 is shown, which is configured to determine the duty cycle D of the signal Od. Od Does it correspond to the duty cycle D of signal O? O Specifically, in the embodiment under consideration, the circuit 46 comprises a differential integrator, for example, comprising a differential operational amplifier 476, a first (integrating) capacitor C connected between a negative output terminal of the differential operational amplifier 476 and a non-inverting / positive input terminal of the differential operational amplifier 476. I , and a second (integrating) capacitor C connected between the positive output terminal of the differential operational amplifier 476 and the inverting / negative input terminal of the differential operational amplifier 476 I In addition, the differential integrator includes a capacitor C I A device for resetting / discharging, such as a first capacitor C I The electronic switch 472 connected in parallel with the second capacitor C IThe electronic switches 474 are connected in parallel, wherein the electronic switches 472 and 474 are closed according to the reset signal RST.

[0191] In addition, the capacitor C is energized by the currents provided by the current sources 460 and 466 according to the signals O and Od. I Charge.

[0192] For example, in various embodiments, the current source 460 provides a current i1 and is connected to a first input terminal of the differential integrator, such as a non-inverting / positive input terminal of the operational amplifier 476, via a first electronic switch 462, wherein the electronic switch 462 is closed based on the signal O, i.e., the electronic switch 462 is closed when the signal O is asserted, and is opened when the signal O is de-asserted, thereby generating a voltage across the corresponding capacitor C. I Injection with D O ·i1 is proportional to the charge.

[0193] Similarly, in various embodiments, the current source 466 provides a current i2 and is connected to a second input terminal of the differential integrator, such as an inverting / negative input terminal of an operational amplifier 476, via a second electronic switch 470, wherein the electronic switch 470 is closed based on the signal Od, i.e., the electronic switch 470 is closed when the signal Od is asserted, and is opened when the signal Od is de-asserted, thereby injecting a current i2 in the corresponding capacitor CI that is equal to D Od · a charge proportional to i2. In various embodiments, currents i1 and i2 have the same value. However, these values ​​may also be different, thereby introducing an additional factor in the gain g shown in equation (24).

[0194] Therefore, in various embodiments, the comparator 478 is configured to respond to determining the first capacitance C I The voltage at the second capacitor C I The signal CompS is asserted, and in response to determining the first capacitor C I The voltage at the second capacitor C I Therefore, by gradually increasing (or decreasing) the current IDAC, the moment when the signal CompS changes the logic level can be determined, which indicates that the current IDAC is close to the optimal value.

[0195] Therefore, in various embodiments, the driver circuit can set the current IDAC to a first value via the digital signal trial_current_cfg, whereby the signal CompS has a first logic value, for example, set to low. Next, the driver circuit can increase (or decrease) the current IDAC via the digital signal trial_current_cfg. DACSpecifically, as described above, in various embodiments, the circuits 42 and 44 are configured such that when the current I DAC Duty cycle D Od The duty cycle D o Therefore, at a given value of the signal trial_current_cfg, the signal CompS changes its logic level, for example, is set to high. Therefore, the current I before the signal CompS changes its logic level DAC The final value corresponds to the current I DAC，1 , which is for example (slightly) too small, and the current I after the signal CompS changes its logic level DAC，2 The first value corresponds to the current I DAC However, both values ​​are close to the current I DAC The optimized value of And the driver circuit can select the current I DAC，1 (ie, the corresponding value trial_current_cfg) or the current I DAC，2 (ie, the corresponding value trial_current_cfg).

[0196] Fig.15 Two other optional electronic switches 464 and 468 are also shown. Specifically, the current source 460 is connected to the second input terminal of the differential integrator, such as the inverting / negative input terminal of the operational amplifier 476, via the electronic switch 464, wherein the electronic switch 464 is closed based on the inverted version of the signal O, that is, when the signal O is de-asserted, the electronic switch 464 is closed, and when the signal O is asserted, the electronic switch 464 is open, thereby I Injection and (1-D O )·i1. Similarly, the current source 466 is connected to a first input terminal of the differential integrator, such as the non-inverting / positive input terminal of the operational amplifier 476, via an electronic switch 468, wherein the electronic switch 468 is closed based on the inverted version of the signal Od, that is, the electronic switch 468 is closed when the signal Od is de-asserted, and the electronic switch 468 is open when the signal Od is asserted, thereby generating an additional charge proportional to the corresponding capacitor C I Injection and (1-D Od )·i2. Therefore, in the embodiment considered, the optimum value is reached when the following conditions occur:

[0197] D O ·i1+(1-D Od )·i2=(1-D o )·i1+D Od ·i2 (29)

[0198] Specifically, when i1=i2, in D o =D Od When , equation (25) is satisfied.

[0199] Fig.16 shows a circuit configured to determine the current I DAC The optimized value of 1 is an embodiment of a circuit 50. Specifically, according to the above description, the circuit 50 includes the circuit 42, the circuit 44 (or directly the combination circuit 40) and the duty ratio comparison circuit 46. Specifically, the circuit 42 is configured to generate the PWM signal Od based on the signal trial_current_cfg, and the circuit 44 is configured to generate the PWM signal O based on the signal trial_current_cfg. In addition, the duty ratio comparison circuit 46 is configured to generate the PWM signal Od when the duty ratio D of the signal O is o Less than the duty cycle D of signal Od Od When the comparison signal CompS is set to the first logic level, and when the duty cycle D of the signal O O When the duty cycle DOd of the signal Od is greater than the duty cycle DOd of the signal Od, the comparison signal CompS is set to a second logic level.

[0200] Therefore, the control circuit 52 of the circuit 50, such as a finite state machine (FSM), for example, implemented using a sequential logic circuit and / or a microprocessor programmed via software, can sequentially increase (or decrease) the signal trial_current_cfg from an initial value and monitor the signal CompS. Specifically, in response to detecting a change in the logic level of the signal CompS, the control circuit 52 can store the current (or previous) value of the signal trial_current_cfg to a register 502, which is schematically shown as being external to the circuit 52, but can also be integrated in the circuit 52. For example, in the embodiment considered, in response to detecting a change in the logic level of the signal CompS, the control circuit 52 stops increasing the signal trial_current_cfg and asserts the signal W_CFG, wherein the register 502 is configured to store the signal trial_current_cfg when the signal W_CFG is asserted.

[0201] In various embodiments, control circuit 52 may also generate a reset signal RST when a differential integrator is used in circuit 46. For example, control circuit 52 may generate a pulse in reset signal RST when signal trial_current_cfg is increased, and control circuit 52 may monitor signal CompS after a given period of time, such as a given number of clock cycles of a clock signal of control circuit 52, such as 8, 16, 32 clock cycles.

[0202] Thus, in the embodiment considered, register 502 provides an optimized value CFG_OPT of signal trial_current_cfg for the current operating condition of the reference FET of power stage Q, wherein signal trial_current_cfg indicates the current In various embodiments, the control circuit 50 may periodically repeat the above operations to determine a new optimization value CFG_OPT.

[0203] Therefore, similar to equations (11) and (15) and the corresponding description, the optimized value Can be used to calculate the RMS value I Q，rms，ON , Peak I Q，max Or another indication of the on-time period T ON The value of the current flowing through the power stage Q during the period (such as the current I Q The average ) determines the partition value N. For example, as described above, the driver circuit may assume a worst-case scenario and determine an optimal value N opt for:

[0204]

[0205] For example, as described above, instead of using equation (30) directly, the driver circuit may also determine the RMS value for each value of the division value N The corresponding threshold value, peak value I Q，max or average In this regard, when using the value To determine the peak current I Q，max When the threshold is , and in the case of a ramp current signal, the gain g can also include the term of equation (14)

[0206] Therefore, in various embodiments, the circuit 54 is configured to generate a voltage at the on-time T by comparing the value CFG_OPT with the voltage at the on-time T ON The signal indicating the division value N is generated by comparing the value CFG_OPT with the value of the current flowing through the power stage Q during the period. Generally, the comparison can be performed digitally, for example, by comparing the value CFG_OPT with the value indicating the current flowing through the power stage Q I Q The comparison may be performed by comparing the signal CFG_OPT to a digital sample of the signal CFG_OPT, or by performing the comparison in an analog manner, for example by converting the signal CFG_OPT into a corresponding analog signal.

[0207] For example, in the embodiment considered, the signal CFG_OPT is provided to the further current DAC 504, which is configured to generate the current i according to the signal CFG_OPT. opt , so the current i opt Corresponds to the value (or at least with = proportional to the current i. opt With indicated current I Q Signal i Q The comparison is performed to generate a signal indicating the partition value N. For example, as described above, the signal i Q Can indicate the RMS value I Q，rms，ON , Peak I Q，max , another indication connection time period T ON The value of the current flowing through the power stage Q during the period (such as the current I Q The average ).

[0208] In various embodiments, the comparison circuit 54 may select the partition value N as follows:

[0209] According to equation (11), the optimal partition value N is calculated opt :

[0210] N opt =i Q / i opt (31)

[0211] And let the value N opt Alternatively, the comparison circuit 54 may discretize the current i for each value of the division value N. opt Determine signal i Q The corresponding upper threshold and the corresponding lower threshold of the current i opt (between the corresponding upper threshold and the corresponding lower threshold) and select the corresponding division value N.

[0212] As previously mentioned, in general, for a given number K of electronic switches with corresponding partitioning factors, the circuit 54 can be configured to be min With the maximum partition value N max Select the partition value N between min ≤N≤N max For example, when using K electronic switches with a partitioning factor of one, N min =1,N max = K. On the contrary, when the partition factor is 2 (i-1) When K electronic switches are min =1,N max =(2 K -1). However, other partitioning factors may also be used.

[0213] For example, Fig.17An embodiment of an analog current comparator 54 is shown. Specifically, in the embodiment considered, the analog current comparator operates essentially as a current analog-to-digital converter (ADC), which is configured to receive the current to be measured and a reference current, and to determine a signal corresponding to the ratio between the current to be measured and the reference current. Thus, in this case, the current i opt Can be used as a reference current, current i Q π may be used as the current to be measured, and the ADC 54 provides the divided value N at the output.

[0214] For example, as previously described, in various embodiments, circuit 54 is configured to min =1 and the maximum partition value N max Select the partition value N between, that is, 1≤N≤N max .in this regard, Fig.17 The current comparator shown is configured to generate (N max -1) Signal IC1 to IC (Nmx-1) , where when the current i Q Greater than j·i opt When the given signal IC j (where 1≤j≤(N max -1)) is set to a first logic level, such as low; and when the current i Q Less than j·i opt When the given signal IC j is set to a second logic level, such as high.

[0215] For example, assuming the maximum partition value N max =5, then the circuit 54 can generate four signals IC1, IC2, IC3 and IC4, and: when i Q opt When all signals IC1 to IC4 are set to the second logic level; when i Q >i opt When i Q >2i opt When i Q >3i opt When i Q >4i opt When the signal IC4 is set to the first logic level.

[0216] Therefore, the conversion (CONV.) circuit 544 of the circuit 54 can be used to determine the division value N based on the signal IC. For example, the conversion circuit 544 can determine the most significant bit IC of the signal IC. m ​is set to a first logic level (e.g., low), and the division value N is determined to be (m+1). For example, assuming again that four signals IC1, IC2, IC3, and IC4 are used, the circuit 54 can be configured to generate a first logic level (e.g., low) according to the current i Q The following signals IC1, IC2, IC3, and IC4 are generated, and the conversion circuit 544 can map the signals IC1, IC2, IC3, and IC4 to corresponding partition values ​​N:

[0217] <![CDATA[i Q ]]> <![CDATA[IC1]]> <![CDATA[IC2]]> <![CDATA[IC3]]> <![CDATA[IC4]]> N <![CDATA[i Q <i opt ]]> 1 1 1 1 1 <![CDATA[i opt <and Q <2i opt ]]> 0 1 1 1 2 <![CDATA[2i opt Q <3i opt ]]> ​ 0 0 1 1 3 <![CDATA[3i opt <i Q <4i opt ]]> 0 0 0 1 4 <![CDATA[4i opt <i Q ]]> 0 0 0 0 5

[0218] For example, to generate the signal IC1 to IC (Nmax-1) , the conversion circuit 54 includes a current mirror 540, and the current mirror 540 includes a plurality of (N max Specifically, the input stage of the current mirror 540 receives the current i opt , and each output stage of the current mirror 540 has a different mirror factor. Specifically, the first output stage has a mirror factor of 1:1 and provides a current i opt , the second output stage has a mirror factor of 1:2 and provides a current of 2·I opt , the third output stage has a mirror factor of 1:3 and provides a current of 3·I opt Specifically, in various embodiments, the j-th output stage of the current mirror 540 has a mirror factor of 1:j and provides a current j·i opt , where j is an integer and 1≤j≤(N max -1).

[0219] Similarly, in the embodiment considered, the current i Q (such as peak current I Q，max ), is provided to include multiple (N max -1) output stage of the current mirror 542. Specifically, the input stage of the current mirror 540 receives the current i Q , and each output stage of the current mirror 542 has a mirror factor of 1:1.

[0220] In the embodiment considered, each output stage of the current mirror 540 is connected in series with a corresponding output stage of the current mirror 542. For example, in the embodiment considered, the current mirror 540 is implemented using a p-channel FET whose source terminal is connected to the supply voltage VDD, the current mirror 542 is implemented using an n-channel FET whose source terminal is connected to ground, and the drain terminal of each FET of the current mirror 540 is connected to the drain terminal of the corresponding FET of the current mirror 542. Therefore, in case the current absorbed by a given output stage / FET of the current mirror 542 is greater than the current sourced by the corresponding output stage / FET of the current mirror 540, the drain terminal of the FET is pulled to ground, i.e., the voltage at the intermediate node of the j-th output stage is set low in the following case:

[0221] i Q >j·i opt (32)

[0222] Therefore, if Fig.16 As shown, the mapping circuit 56 can be configured to generate corresponding enable signals EN1-ENK for each electronic switch S1-SK according to the partition value N, wherein each enable signal EN indicates whether the corresponding switch should be driven / enabled (e.g., EN=1) or should be not driven / disabled (e.g., EN=0). For example, as described above, the mapping circuit 56 can be configured to select / enable a subset of the electronic switches S1-SK to obtain the required partition value N.

[0223] Typically, the operation of the conversion circuit 544 may also be included in the mapping circuit 56 (and the conversion circuit 544 may be omitted), ie, the mapping circuit 56 may be configured to (directly) generate the enable signals EN1 -ENK according to the signals provided by the conversion circuit 54 .

[0224] Fig.18 An embodiment of a complete driver circuit for a power stage Q is shown. In various embodiments, the driver circuit is integrated in the same integrated circuit with the power stage Q. In particular, in the embodiment considered, again the power stage Q comprises a given number K of (physical and / or virtual) FETs S1-SK, such as MOSFETs, e.g. n-channel FETs. The drain terminal of each FET S1-SK is connected to a first node N1, and the source terminal of each FET S1-SK is connected to a second node N2. Thus, the path between nodes N1 and N2 corresponds to the current path of each FET S1-SK, and thereby to the power stage Q. Furthermore, the gate terminal of each FET S1-SK receives a corresponding drive signal D1-DK.

[0225] As described above, the circuit 50 is configured to provide a voltage for each FET S1-SK of the power stage Q according to the (total) current I flowing through the power stage Q.Q Signal i Q and having an on period T ON and the off period T oFF The signal PWM is used to generate the corresponding enable signals EN1-ENK. Generally, any suitable PWM generator circuit can be used to generate the signal PWM.

[0226] In the embodiment considered, the signal i Q is provided by a current sensor 26 which is configured to monitor the current i Q For example, the sensor 26 may include a shunt resistor connected between the source terminal of the FET S1-SK and the node N2 or between the drain terminal of the FET S1-SK and the node N1. Typically, the current sensor 26 is configured to monitor the current flowing during the on period T of the signal PWM. ON The current I during Q is sufficient. For example, Figure 6 As shown, the current sensor 26 may also be placed at other locations. For example, the current sensor 26a may provide a signal i Q . In addition, other current sensors may be used instead of using a shunt resistor. For example, in this context, U.S. Patent Application Publication No. 2022 / 0173657A1 may be cited, the contents of which are hereby incorporated by reference. As previously described, the signal i Q Can indicate the RMS value I Q，rms，ON , peak current I Q，max and another value indicating the current flowing through the power stage Q during the on period TON (such as the current I Q The average ). Therefore, the current sensor 26 may already provide a corresponding value, or the current sensor 26 may provide the current I Q The instantaneous value of the signal i Q The corresponding value of .

[0227] In the considered embodiment, the enable signals EN1-ENK and the signal PWM are provided to the FET driver circuit 58. Specifically, the FET driver circuit 58 is configured to generate a respective drive signal D1-DK for each FETS1-SK by combining the signal PWM with the respective enable signal EN1-ENK. Specifically, the FET driver circuit 58 is configured to:

[0228] When the signal PWM is asserted (indicating that the current path of the power stage Q should be closed) and the corresponding enable signal EN1-ENK is asserted, setting the corresponding drive signal D1-DK to a first logic level indicating that the corresponding FET should be closed; and

[0229] When the signal PWM is de-asserted (indicating that the current path of the power stage Q should be disconnected) or the corresponding enable signal EN1-ENK is de-asserted, the corresponding drive signal D1-DK is set to a second logic level indicating that the corresponding FET should be disconnected.

[0230] For example, to this end, the FET driver circuit 58 may include a corresponding combinational logic circuit A1-AK for each FET, which is configured to implement the above-mentioned operation. For example, each combinational logic circuit A1-AK can be implemented with an AND gate, where the current path of the power stage Q should be closed when the signal PMW is set high and the given FET should be enabled when the corresponding enable signal EN1-ENK is set high.

[0231] In various embodiments, the FET driver circuit 58 may also implement other functions to generate the drive signals D1-DK, such as slew rate control and / or level shifting. In various embodiments, the circuits 50 and 58 may be implemented in the same integrated circuit along with the power stage Q and the optional current sensor 26.

[0232] therefore, Fig.18 The circuit shown in can be used for each power stage Q of a more complex circuit (such as an electronic converter). For example, as previously described (see, for example, Figures 3 to 6 ), the electronic converter generally comprises two electronic switches, which can be arranged as a half bridge. Generally, the circuit can also include multiple half bridges, for example, to form a full bridge and / or to realize multiple phases of the electronic converter or motor drive.

[0233] For example, Fig.19 An embodiment of a half-bridge driver circuit according to the present disclosure is shown. Specifically, in the embodiment considered, the half-bridge is implemented with a half-bridge power stage QHB, including a high-side power stage QHS and a low-side power stage QLS. For example, the high-side power stage QHS can replace Figure 6 The high-side switch Q1, while the low-side power stage QLS can replace Figure 6 The low-side switch Q2 of the high-side power stage QHS is connected to a first voltage (such as a power supply voltage V in), node N2 (source node of FET SH1-SHK1) of the high-side power stage QHS is connected to the switch node SW, the switch node SW is connected to the node N1 (drain node of FET SL1-SLK2) of the low-side power stage QLS, and the node N2 (source node of FET SL1-SLK2) of the low-side power stage QLS is connected to a second voltage (such as ground).

[0234] For example, the switch node SW may be connected to a load 62, which may include, for example, reactive components of an electronic converter, such as L and / or C out , and / or other loads 30 (see Figures 1 to 8 description of), one or more motor windings, etc.

[0235] In the embodiment considered, the gate terminal of each FET SH1-SHK1 implementing the high-side power stage QHS is therefore connected to a corresponding drive signal DH1-DHK1, such as the signals DH1, DH2 and DH3, while the gate terminal of each FET SL1-SLK2 implementing the low-side power stage QLS is connected to a corresponding drive signal DL1-DLK2, such as the signals DL1, DL2 and DL3.

[0236] As described above, in various embodiments, each power stage Q is driven based on a corresponding PWM signal, i.e., signal PWMH for the high-side power stage QHS and signal PWML for the low-side power stage QLS. For example, signals PWMH and PWML may be generated via circuit 60, such as control circuit 22 of the electronic converter (see also Figure 3-8 description).

[0237] Thus, in various embodiments, the half-bridge driver circuit may include respective circuits 50 and 58 for each power stage QHS and QLS. Fig.19 An embodiment is shown in which the half-bridge driver circuit includes a combined division circuit 50HB configured to generate a signal indicating a division value NHS for a high-side power stage QHS and a signal indicating a division value NLS for a low-side power stage QLS. For example, as described above, the signal may correspond to an enable signal ENH1-ENHK1 for each FET of the high-side power stage QHS and an enable signal ENL1-ENLK2 for each FET of the low-side power stage QLS. As described above, the enable signal may be generated based on the division factor of the FET of a given power stage Q.

[0238] Thus, in the embodiment considered, the half-bridge dividing circuit 50HB is configured to divide the half-bridge into two parts according to the signal PWMH and the (total) current I flowing through the high-side power stage QHS. QHSThe signal of the low-side power stage QLS is used to generate a signal indicating the divided value NHS, such as the signal ENH1-ENHK1, and the (total) current I flowing through the low-side power stage QLS according to the signal PWML QLS The signal of the division value NLS is generated by the signal, for example, ENL1-ENLK2. Fig.19 In the embodiment, the half-bridge dividing circuit 50HB receives a single signal i indicating the current provided via the switching node SW. Q , the signal i Q Indicates the current I when the signal PWMH is asserted QHS and the current I when the signal PWML is asserted QLS However, two separate current sensors may also be used. For example, when the current provided via the node SW has a triangular shape (as in many electronic converters), the use of a single current sensor is particularly useful, because in this case the current sensor 26 can provide a value indicative of the peak current value, which is the same for the high-side power stage QHS and the low-side power stage QLS, i.e. the peak value I QHS，max =I QLS，max =I Q，max .

[0239] Thus, in the embodiment considered, the half-bridge driver circuit comprises a FET driver circuit 58H for power stage QHS and a FET driver circuit 58L for power stage QLS.

[0240] Specifically, the driver circuit described above can be used to drive a low-side power stage QLS, wherein one of the low-side FETs SL1-SLK2 represents a reference FET, and the driver circuit receives a low-side PWM signal PWML. Thus, the FET driver circuit 58, now identified as the driver circuit of the driver circuit 58L, is configured to generate a corresponding drive signal DL1-DLK2 for each low-side FET SL1-SLK2 by combining the corresponding low-side enable signal ENL1-ENLK2 with the low-side PWM signal PWML. Similarly, the additional FET driver circuit 58H is configured to generate a corresponding drive signal DH1-DHK1 for each high-side FET SH1-SHK1 by combining the corresponding high-side enable signal ENH1-ENHK1 with the high-side PWM signal PWMH.

[0241] For example, in the considered embodiment, the high-side FET driver circuit 58H comprises, for each high-side FET SH1-SHK1, a respective high-side driver 584H configured to generate a respective drive signal DH1-DHK1 according to a respective signal PWMH1-PWMHK1. For example, the high-side driver 584H may be supplied with a higher supply voltage, or preferably via a floating voltage V BOOTPower supply, floating voltage V BOOT For example, it is obtained via a conventional bootstrap circuit. For example, in various embodiments, the power supply voltage V BOOT With respect to the voltage V at the node SW SW is floating, and the voltage difference (V BOOT -V SW ) has the same magnitude as the voltage Vin reference ground.

[0242] Thus, in the embodiment under consideration, the circuit 582H may be configured to generate the signals PWMH1-PWMHK1 according to the signal PWMH and the signal indicating the division value NHS (e.g., the enable signals ENH1-ENHK1). For example, when the enable signals ENH1-ENHK1 are used, the circuit 582H may include a corresponding combinational logic circuit (e.g., a logic gate, such as an AND gate) for each enable signal ENH1-ENHK1, the corresponding combinational logic circuit being configured to generate the corresponding signal PWMH1-PWMHK1 by combining the signal PWMH with the corresponding enable signal ENH1-ENHK1 (e.g., see Fig.18 Description of circuits A1-AK).

[0243] Therefore, the circuit 582H may include one or more level shifters (LS) for shifting the levels of the enable signals ENH1-ENHK1, or one or more level shifters for shifting the levels of the signals PWMH1-PWMHK1. Fig.19 A circuit 580H is schematically shown, which is configured to generate a signal PWMH′ by adjusting the voltage level of the signal PWMH to a level of the circuit 580H, for example, by implementing a level shift, wherein the circuit 580H uses the signal PWMH′.

[0244] Similarly, in the embodiment under consideration, the low-side FET driver circuit 58L includes a respective low-side driver 584L for each low-side FET SL1-SLK2, which is configured to generate a respective drive signal DL1-DLK2 according to the respective signal PWML1-PWMLK2. For example, the voltage V in Power supply for low side driver 584L.

[0245] Thus, in the embodiment under consideration, the circuit 582L may be configured to generate the signals PWML1-PWMLK2 according to the signal PWML and the signal indicating the division value NLS (e.g., the enable signals ENL1-ENLK2). For example, when the enable signals ENL1-ENLK2 are used, the circuit 582L may include a corresponding combo logic circuit (e.g., a logic gate, such as an AND gate) for each enable signal ENL1-ENLK2, the combo logic circuit being configured to generate the corresponding signals PWML1-PWMLK2 by combining the signal PWML with the corresponding enable signals ENL1-ENLK2 (e.g., see Fig.18 Description of circuits A1-AK).

[0246] Typically, circuit 582L does not include one or more level shifters for enabling level shifting of signals ENL1-ENLK2, or one or more level shifters for enabling level shifting of signals PWML1-PWMLK2. However, in various embodiments, circuit 582L may have an associated circuit 580L configured to generate signal PWML' by adjusting the voltage of signal PWML to a level of level circuit 580L, wherein circuit 580L uses signal PWML'.

[0247] Therefore, in various embodiments, the aforementioned dividing circuit 50 is modified to generate not only the enable signals ENL1 - ENLK2 but also the additional enable signals ENH1 - ENHK1 .

[0248] Fig. 20 FIG. 5 shows an embodiment of a half-bridge dividing circuit 50HB. Fig.16 In contrast, the half-bridge dividing circuit 50HB includes a single circuit 42 for estimating driving losses and a single circuit 44 (or a single combined circuit 40 ) for estimating conduction losses.

[0249] Specifically, when using FETs of the same technology, the high-side reference FET and the low-side reference FET have the same driving loss and on-resistance R when the power stages QHS and QLS use the same gate-source voltage. ds，on Therefore, in various embodiments, the circuit 60HB may include a multiplexer 508 configured to provide the gate-source voltage V of the high-side power stage QHS to the circuits 42 and 44 according to the selection signal SEL. gsHS or the gate-source voltage V of the low-side power stage QLS gsLS As the voltage V gs However, as mentioned earlier, when using a bootstrap architecture, the gate-source voltage V gsHS and V gsLSThe magnitudes may also be the same and may correspond to, for example, a voltage V in Therefore, the multiplexer 508 may also be omitted.

[0250] Furthermore, in order to determine the conduction loss, the circuit 44 should consider the actual duty cycle of the PWM signal (i.e., the signal PWMH for the power stage QHS and the signal PWML for the power stage QHL) used to drive the power stage Q. Therefore, in various embodiments, the signal PWM used by the circuit 44 is provided by the multiplexer 506, which is configured to provide the signal PWMH or the signal PWML according to the selection signal SEL.

[0251] Thus, in this manner, control circuit 52HB of circuit 50HB (substantially implementing the functionality of control circuit 52) ​​can set select signal SEL to select signal PWMH as signal PWM for circuit 44 during high-side mode (first mode), and optionally gate-source voltage V gsHS , the control circuit 52HB is such as a finite state machine, for example, implemented with a sequential logic circuit and / or a microprocessor programmed via software. Next, the circuit 52HB can sequentially increase (or decrease) the signal trial_current_cfg from the initial value and monitor the signal CompS. Specifically, in response to detecting a change in the logic level of the signal CompS, the control circuit 52HB can store the current (or previous) value of the signal trial_current_cfg to the register 502HS. For example, in the embodiment considered, in response to detecting a change in the logic level of the signal CompS, the control circuit 52HB stops increasing the signal trial_current_cfg and asserts the signal W_CFGHS, wherein the register 502HS is configured to store the signal trial_current_cfg when the signal W_CFGHS is asserted.

[0252] Therefore, in various embodiments, the control circuit can then set the selection signal SEL to select the signal PWML as the signal PWM for circuit 44 during the low-side mode (second mode), and optionally select the gate-source voltage V gsLS. Next, the circuit 52HB may sequentially increase (or decrease) the signal trial_current_cfg from the initial value and monitor the signal CompS. Specifically, in response to detecting a change in the logic level of the signal CompS, the control circuit 52HB may store the current (or previous) value of the signal trial_current_cfg to the register 502LS. For example, in the embodiment under consideration, in response to detecting a change in the logic level of the signal CompS, the control circuit 52HB stops increasing the signal trial_current_cfg and asserts the signal W_CFGLS, wherein the register 502LS is configured to store the signal trial_current_cfg when the signal W_CFGLS is asserted.

[0253] As described above, the control circuit 52HB can also generate the reset signal RST.

[0254] Thus, in the embodiment considered, the register 502HS provides the optimized value CFG_OPTHS of the signal trial_current_cfg for the current operating condition of the FET of the power stage QHS, and the register 502LS provides the optimized value CFG_OPTLS of the signal trial_current_cfg for the current operating condition of the FET of the power stage QLS. Thus, similar to the previous description, the circuit 54HS can be operated by converting the signal CFG_OPTHS (or the corresponding current i generated by the DAC 540HS) to optHS ) and current i QHS (such as current I Q，max ) to generate the division value NHS or directly generate the corresponding enable signal ENH1-ENHK1 (as schematically shown via the mapping circuit 56HS). Similarly, the circuit 54LS can generate the corresponding current i generated by the DAC 540LS by converting the signal CFG_OPTLS (or the corresponding current i generated by the DAC 540LS) to optLS ) and current i QLS (such as current I Q，max ) are compared to generate a division value NLS or directly generate corresponding enable signals ENL1-ENLK2 (as schematically shown via mapping circuit 56LS).

[0255] Therefore, in the embodiment under consideration, the circuit 50HS uses the same circuits 42 and 44 (or similarly a single circuit 40) to determine the optimized values ​​CFG_OPTHS and CFG_OPTLS during both operating modes. Specifically, for this purpose, the circuits 44 and 506 are configured to, in the low-side mode, scale the reference current I when the low-side PWM signal PWML is asserted. DACapplied to capacitor C, and in high-side mode, when the high-side PWM signal PWMH is asserted, the scaled reference current I DAC is applied to capacitor C. In addition, control circuit 52HB is configured to, in low-side mode, set reference current I DAC Set to the initial value, and then increase or decrease the reference current I DAC Until the logic level of the comparison signal CompS changes, and when the logic level of the comparison signal CompS changes, the storage indicates that the reference current I DAC The value of i opt Similarly, in high-side mode, control circuit 52HB sets reference current I DAC Set to the initial value, and then increase or decrease the reference current I DAC Until the logic level of the comparison signal CompS changes, and when the logic level of the comparison signal CompS changes, the storage indicates that the reference current I DAC The value of i opt In addition, the comparison circuits 54, 56, 504 can be used to compare the low-side value CFG_OPTLS with the signal i indicating the current provided by the switch node SW. Q The comparison circuits 54HS, 56HS, 504HS are used to generate the low-side enable signals ENL1-ENLK2, while the additional comparison circuits 54HS, 56HS, 504HS are used for the high-side enable signals. Specifically, the additional comparison circuits 54HS, 56HS, 504HS are configured to compare the high-side value CFG_OPTHS with the signal i indicating the current provided by the switch node SW. Q The comparison is performed to determine a corresponding high-side enable signal ENH1 - ENHK1 for each high-side FET SH1 - SHK1 .

[0256] Fig.21 A first embodiment of a circuit 582H is shown, which is configured to generate a common high-side signal (such as PWMH1) from a corresponding enable signal (such as ENH1) and a (level-shifted) signal PWMH'. In general, the same circuit can also be used within the power stage driver circuit 58 where a level shifter is required.

[0257] In the embodiment under consideration, circuit 582H includes a data storage element. Specifically, in the embodiment under consideration, the storage element is implemented using two inverters (logical NOT gates) INV1 and INV2 connected to form a ring. However, any multiple of two inverter stages may also be used. Therefore, the input of each inverter stage is connected to the output of the upstream / previous inverter stage, and the input of the first inverter stage is connected to the output of the last inverter stage. Specifically, in the embodiment under consideration, the storage element is connected via a floating voltage VBOOT Power supply, for example, the inverter stage is connected at voltage V BOOT and V SW between.

[0258] Specifically, when the input of the first (or odd) inverter stage is set to low, the output of the corresponding inverter stage is set to high, so that the output of the last inverter stage is set to low. Conversely, when the input of the second (or even) inverter stage is set to low, the output of the corresponding inverter stage is set to high, so that the output of the last inverter stage is set to high. In the embodiment considered, the circuit 580H therefore also includes a first subcircuit and a second subcircuit, the first subcircuit being configured to selectively set the input of the first (or odd) inverter stage to low, and the second subcircuit being configured to selectively set the input of the second (or even) inverter stage to low.

[0259] For example, in the embodiment under consideration, the first subcircuit represents a reset circuit for the signal ENH1′ and is configured to set the input of the first (or odd) inverter stage to low in response to determining that the enable signal ENH1 indicates that the FET associated with the signal PWMH is disabled (e.g., when the signal ENH1 is set to low). For example, in the embodiment under consideration, the input of the first (or odd) inverter stage is connected to ground via an electronic switch ST1 (such as an n-channel FET), wherein a control terminal (e.g., a gate terminal) of the electronic switch ST1 is driven via an inverted version of the enable signal ENH1, as schematically shown via the inverter INV3.

[0260] Conversely, the second subcircuit represents a setting circuit for the signal ENH1′ and is configured to set the input of the second (or even) inverter stage to low in response to determining that the enable signal ENH1 indicates that the FET associated with the signal PWMH is enabled (e.g. when the signal ENH1 is set high). For example, in the embodiment considered, the input of the second (or even) inverter stage is connected to ground via an electronic switch ST2 (such as an n-channel FET), wherein the control terminal (e.g. gate terminal) of the electronic switch ST2 is driven via the enable signal ENH1, as schematically shown via an optional further inverter INV4.

[0261] Therefore, in this case, the output of the last inverter stage (eg, inverter stage INV2) corresponds to a level-shifted version ENH1′ of the enable signal ENH1, ie, the signal ENH1′ is set to the voltage V BOOT (High) or V at the switch node SW SW(Low). Therefore, in the embodiment under consideration, by combining the level-shifted signal PWMH′ with the level-shifted signal ENH1′, a logic gate A such as an AND gate can be used to generate the signal PWMH. In addition, the combinational logic circuit A is composed of a floating voltage V BOOT powered by.

[0262] In various embodiments, to ensure that the signal ENH1′ is updated only when the signal PWMH′ is de-asserted (e.g., low), the first subcircuit may be configured to set the input of the first (or odd) inverter stage low in response to determining that the enable signal ENH1 indicates that the FET associated with the signal PWMH is disabled (e.g., when the signal ENH1 is set low and the (unlevel-shifted) signal PWMH is de-asserted (e.g., low). For example, in the embodiment under consideration, the input of the first (or odd) inverter stage is connected to ground via a series connection of two electronic switches ST1 and ST3 (such as n-channel FETs), wherein the control terminal (e.g., gate terminal) of the electronic switch ST1 is driven via an inverted version of the enable signal ENH1, and the control terminal (e.g., gate terminal) of the electronic switch ST3 is driven via an inverted version of the signal PWMH.

[0263] Conversely, the second subcircuit may be configured to set the input of the second (or even) inverter stage to low in response to determining that the enable signal ENH1 indicates that the FET associated with the signal PWMH is enabled (e.g., when the signal ENH1 is set high and the (unlevel-shifted) signal PWMH is de-asserted (e.g., low). For example, in the embodiment under consideration, the input of the second (or even) inverter stage is connected to ground via a series connection of two electronic switches ST2 and ST4 (such as n-channel FETs), wherein the control terminal (e.g., gate terminal) of the electronic switch ST2 is driven via the enable signal ENH1, while the control terminal (e.g., gate terminal) of the electronic switch ST4 is driven via an inverted version of the signal PWMH.

[0264] In various embodiments, circuit 582H may use signal PWML (which corresponds approximately to an inverted version of signal PWMH) instead of using an inverted version of signal PWMH.

[0265] Thus, in the embodiment considered, when the corresponding signal is set (approximately) to V in When the corresponding signals are set to ground (approximately), the signals ENH1 and PWMH / PWML are set to high. Conversely, when the corresponding signals are set to ground (approximately), the signals ENH1 and PWMH / PWML are set to low. BOOT , the signals PWMH', ENH1' and PWMH1 are set high, and when the corresponding signals are (approximately) set to VSW , the signals PWMH', ENH1' and PWMH1 are set low.

[0266] Fig. 22 A second embodiment of a circuit 582H is shown, which is configured to generate a common high-side signal (such as PWMH1) based on a corresponding enable signal (such as ENH1) and a (level-shifted) signal PWMH'. In addition, this circuit can also be used within the power stage driver circuit 58 in case a level shifter is required.

[0267] Furthermore, in the embodiment considered, the circuit 582H comprises a storage element. Specifically, in the embodiment considered, the storage element is again implemented using inverters INV1 and INV2 connected to form a ring. However, any multiple of two inverter stages may also be used.

[0268] Therefore, also in this case, the storage element (e.g. the output of the last inverter stage) should provide a level-shifted version ENH1' of the signal ENH1. In fact, in the embodiment considered, a logic gate A (such as an AND gate) is used again to generate the signal PWMH1 by combining the level-shifted signal PWMH' with the level-shifted signal ENH1'.

[0269] Specifically, in the embodiment under consideration, the circuit 582H again includes a first subcircuit that serves as a reset circuit for the signal ENH1'. For example, in the embodiment under consideration, the input of the first (or odd) inverter stage is connected to ground via the electronic switch ST1 and optionally via the electronic switch ST3. Specifically, the control terminal (e.g., gate terminal) of the electronic switch ST1 is driven via an inverted version of the enable signal ENH1, while the control terminal (e.g., gate terminal) of the electronic switch ST3 is driven via an inverted version of the high-side signal PWMH or via the low-side signal PWML. Therefore, the electronic switch ST1 and the optional electronic switch ST3 can be used to set the signal ENH1' to low when the signal ENH1 is low.

[0270] Therefore, an additional setting circuit for the signal ENH1' is required. Specifically, in the embodiment considered, the setting circuit is implemented via a p-channel FET configured to connect the input of the first (or odd) inverter stage to the supply voltage V when the gate node of the FET ST4 is connected to ground. BOOT Specifically, in the embodiment under consideration, the gate node of the p-channel FET ST4 is connected to the voltage V via a pull-up resistor RPU1. BOOT, and is connected to ground via an electronic switch ST5 (such as an n-channel FET). Therefore, when the electronic switch ST5 is closed, the gate node of FET ST4 is connected to ground, and FET ST4 connects the input of the first (or odd) inverter stage to the supply voltage V BOOT , so that the signal ENH1' is set high. Conversely, when the electronic switch ST5 is turned off, the gate node of the FET ST4 is connected to the power supply voltage V BOOT And FET ST4 is turned off, so that the signal ENH1' maintains its logic level.

[0271] For example, in various embodiments, the control terminal (e.g., gate terminal) of the electronic switch is driven via a signal SET corresponding to the signal ENH1 or a delayed version thereof, as shown again via two inverter stages INV3 and INV4. For example, in the simplest case, the signal SET can be directly applied to the control terminal of the electronic switch ST5, i.e., the electronic switch ST5 is closed when the signal SET is high, and the electronic switch ST5 is open when the signal SET is low.

[0272] Instead, in the embodiment considered, the control terminal of the electronic switch ST5 is driven via a logic AND gate AND1 receiving at its input the set signal SET and the feedback signal FEEDBACK. In particular, the feedback signal FEEDBACK contributes to improving the stability of the system. In the embodiment considered, the feedback signal FEEDBACK is used to generate only pulses for setting the storage element when the signal ENH1' is de-asserted / set to low.

[0273] Specifically, in the embodiment under consideration, the electronic switch ST6 and the electronic switch ST7 are connected between the pull-down resistor RPD and the voltage V BOOT between, where the pull-down resistor RPD is connected to ground. Specifically, the electronic switch ST6 (such as a p-channel FET) is configured to close when the signal ENH1' is set to low, and the electronic switch ST7 is configured to close when the signal SET is asserted. Therefore, when the signal ENH1' is de-asserted and the signal SET is asserted, the voltage at the pull-down resistor PDB is set to high, and when the signal ENH1' is asserted or the signal SET is de-asserted, the voltage at the pull-down resistor PDB is set to low. Therefore, the voltage at the pull-down resistor RPD can be used as the feedback signal FEEDBACK, or an additional level conversion circuit can be used to generate the feedback signal FEEDBACK based on the voltage at the pull-down resistor RPD. For example, in the embodiment considered, the level conversion circuit is implemented with a first inverter stage, which is implemented with a pull-up resistor RPU2 and an electronic switch ST8 such as an n-channel FET, and the pull-up resistor RPU2 and the electronic switch ST8 are connected in series at the voltage V inand ground, wherein the control terminal (e.g., gate terminal) of the electronic switch ST8 is connected to the voltage at the pull-down resistor RPD, and the intermediate node between the pull-up resistor RPU2 and the electronic switch ST8 provides an inverted logic level of the voltage at the pull-down resistor RPD. in power supply) can be used to generate a feedback signal FEEDBACK by inverting the logic level at the intermediate node between the pull-up resistor RPU2 and the electronic switch ST8.

[0274] Therefore, in this case as well, the signals ENH1 and PWMH / PWML are set to (approximately) V in , and when the corresponding signals are (approximately) set to ground, the signals ENH1 and PWMH / PWML are set to low. Conversely, when the corresponding signals are (approximately) set to V BOOT , the signals PWMH', ENH1' and PWMH1 are set high, and when the corresponding signals are (approximately) set to V SW , the signals PWMH', ENH1' and PWMH1 are set low.

[0275] in this regard, Fig.23 shows the floating voltage V BOOT , the voltage at the switch node V SW (That is, the voltage V BOOT floating ground), signal ENH1 (set to V in or ground), an enable signal ENH1, a set signal SET, a level-shifted signal ENH1′, a feedback signal FEEDBACK (due to propagation delay, when the signal SET is asserted and the signal ENH1′ is de-asserted, the feedback signal FEEDBACK is set high for a short pulse), a signal PWMH′, and a signal PWMH1 (generated by a combination of signals PWMH′ and ENH1′).

[0276] As mentioned earlier, Fig.21 and Fig. 22 The circuit can also be used for other enable signals ENH1-ENHK1. Fig.21 and Fig. 22 The voltage Vin shown in may also not correspond to the voltage applied to the half-bridge QHB, but may be a different supply voltage.

[0277] Therefore, the solution disclosed herein has the advantage that the driver circuit can determine (via the signal trial_current_cfg) the optimal value of the reference FET for the power stage Q Specifically, this value takes into account the current operating conditions of the power stage Q, such as switching frequency, duty cycle, gate capacitance, on-resistance, and gate-source voltage.

[0278] In addition, in the case of several power stages (such as half-bridge power stages QHS and QLS), a division value N can be determined for each power stage. For example, for the high-side power stage QHS and the low-side power stage QLS, different FETs S1-SK can be closed to optimize the power loss of each switching stage Q.

[0279] Of course, without prejudice to the principle of the invention, the details of construction and of the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the invention as defined in the following claims.

[0280] The claims form an integral part of the technical teaching of the disclosure provided herein.

Claims

1. A driver circuit, comprising: a power stage comprising a plurality of FETs connected in parallel, wherein one of the plurality of FETs comprises a reference FET that closes in response to application of a gate-source voltage; An input terminal configured to receive a pulse width modulation (PWM) signal having a given switching period, wherein the PWM signal is asserted for an on period to control the power stage to close, and the PWM signal is de-asserted for an off period to control the power stage to open; a current sensor configured to provide a signal indicative of a current flowing through the power stage during the on-period; a reference capacitor including a first scaled FET corresponding to a scaled version of the reference FET; a reference resistor including a second scaled FET corresponding to another scaled version of the reference FET; The first circuit is configured as: generating a ramp signal at the reference capacitor by connecting the gate terminal of the first scaling FET to ground after a plurality of the given switching cycles and then applying a first current to the gate terminal of the first scaling FET, wherein the first current is proportional to a reference current; and asserting a first PWM signal in response to determining that the voltage at the capacitor is less than a reference voltage, and de-asserting the first PWM signal in response to determining that the voltage at the capacitor is greater than the reference voltage, wherein the reference voltage is proportional to the gate-source voltage; The second circuit is configured as follows: applying a second current to the capacitor when the PWM signal is asserted, wherein the second current is proportional to the reference current; generating a third current by applying a voltage proportional to the gate-source voltage to the reference resistor; applying the third current to the capacitor when the second PWM signal is asserted, wherein the third current and the second current have opposite signs; asserting the second PWM signal in response to the voltage at the capacitor reaching an upper threshold, and de-asserting the second PWM signal in response to the voltage at the capacitor reaching a lower threshold; a duty cycle comparison circuit configured to set a comparison signal to a first logic level in response to determining that the duty cycle of the first PWM signal is greater than the duty cycle of the second PWM signal, and to set the comparison signal to a second logic level in response to determining that the duty cycle of the first PWM signal is less than the duty cycle of the second PWM signal; a control circuit configured to set the reference current to an initial value and then increase or decrease the reference current until a change between a first logic level and a second logic level of the comparison signal occurs; a comparison circuit configured to determine a respective enable signal for each of the plurality of FETs by comparing a value of the reference current in response to a change between a first logic level and a second logic level of the comparison signal with the signal indicative of a current flowing through the power stage during the on-period; and The FET driver circuit is configured to generate a corresponding drive signal for each FET of the plurality of FETs by combining a corresponding enable signal with the PWM signal. 2 . The driver circuit of claim 1 , wherein the signal indicative of the current flowing through the power stage during the on-period is indicative of a root mean square value of the current flowing through the power stage during the on-period. 3 . The driver circuit of claim 1 , wherein the signal indicative of the current flowing through the power stage during the on-period indicates a maximum value of the current flowing through the power stage during the on-period.

4. The driver circuit of claim 1 , wherein the comparison circuit is further configured to determine the signal indicative of the division value of the power level by: determining, in response to a change between a first logic level and a second logic level of the comparison signal, a respective upper threshold and a lower threshold for each of a plurality of division values ​​according to the value of the reference current; and One of the split values ​​is selected by comparing the signal indicative of current flowing through the power stage during the on-period to the upper and lower thresholds.

5. The driver circuit of claim 4 , wherein each of the plurality of FETs has a corresponding division factor, the comparison circuit being configured to: The enable signal is determined based on the division factor of the plurality of FETs and a signal indicative of a selected division value.

6. The driver circuit according to claim 1 , further comprising a current digital-to-analog converter configured to generate the reference current according to a digital signal, wherein the control circuit is configured to: Setting the digital signal to an initial value; and then increasing or decreasing the digital signal until the change between the first logic level and the second logic level of the comparison signal; and then storing the digital signal; Wherein the comparison circuit is configured to compare the stored digital signal with the signal indicative of current flowing through the power stage during the on-period. 7 . The driver circuit of claim 1 , wherein the first circuit is configured to connect the gate terminal of the first scaling FET to ground at the beginning of each switching cycle.

8. The driver circuit of claim 1 , wherein the duty cycle comparison circuit comprises a differential current integrator, the duty cycle comparison being configured to: periodically resetting the differential current integrator; applying a first reference current to a first terminal of the differential current integrator when the first PWM signal is asserted; applying a second reference current to a second terminal of the differential current integrator when the second PWM signal is asserted; and The comparison signal is generated based on a differential voltage at the output of the differential current integrator.

9. The driver circuit of claim 1 , wherein the FET driver circuit is configured to generate a corresponding drive signal for each FET of the plurality of FETs by: When the PWM signal is asserted and the corresponding enable signal indicates that the corresponding FET is enabled, asserting the corresponding drive signal; and When the PWM signal is de-asserted or the corresponding enable signal indicates that the corresponding FET is disabled, the corresponding drive signal is de-asserted.

10. A half-bridge driver circuit comprising: The driver circuit according to claim 1, wherein the power stage of the driver circuit is a low-side power stage, the low-side power stage comprising a plurality of low-side FETs connected between a switch node and ground, wherein one of the plurality of low-side FETs represents the reference FET; wherein the input terminal of the driver circuit is configured to receive a low-side PWM signal; a high-side power stage comprising a plurality of high-side FETs connected between a supply voltage and the switch node; a further input terminal configured to receive a high-side PWM signal having the given switching period, wherein for an on-period the high-side PWM signal is asserted to indicate that the high-side power stage should be closed, and for an off-period the high-side PWM signal is de-asserted to indicate that the high-side power stage should be opened; wherein the current sensor of the driver circuit is configured to provide a signal indicative of a current provided through the switch node; The second circuit of the driver circuit is configured as follows: in a low-side mode, applying the second current to the capacitor when the low-side PWM signal is asserted; and in a high-side mode, applying the second current to the capacitor when a high-side PWM signal is asserted; The control circuit of the driver circuit is configured as follows: In the low-side mode, the reference current is set to an initial value, and then the reference current is increased or decreased until the logic level of the comparison signal changes, and when the logic level of the comparison signal changes, a low-side value indicating the value of the reference current is stored, In the high-side mode, the reference current is set to an initial value, and then the reference current is increased or decreased until the logic level of the comparison signal changes, and when the logic level of the comparison signal changes, a high-side value indicating the value of the reference current is stored; wherein the comparison circuit of the driver circuit is configured to determine a corresponding low-side enable signal for each FET of the plurality of low-side FETs by comparing the low-side value with the signal indicative of the current provided through the switch node; wherein the half-bridge driver circuit comprises a further comparison circuit configured to determine a respective high-side enable signal for each FET of the plurality of high-side FETs by comparing a high-side value with the signal indicative of a current provided through the switch node; wherein a FET driver circuit of the driver circuit is configured to generate a corresponding drive signal for each FET of the plurality of low-side FETs by combining a corresponding low-side enable signal with the low-side PWM signal; and Wherein the half-bridge driver circuit comprises an additional FET driver circuit configured to generate a corresponding drive signal for each FET of the plurality of high-side FETs by combining a corresponding high-side enable signal with the high-side PWM signal.

11. The half-bridge driver circuit of claim 10, wherein the further FET driver circuit comprises, for each high-side enable signal, a respective level shifter circuit configured to generate a level-shifted version of the respective enable signal.

12. An integrated circuit comprising the half-bridge driver circuit according to claim 10.

13. A control circuit for an electronic converter, comprising: The half-bridge driver circuit according to claim 10; and The PWM signal generator is configured to generate the low-side PWM signal and the high-side PWM signal.

14. An integrated circuit comprising the control circuit according to claim 13.

15. A control circuit for an electronic converter, comprising: The driver circuit according to claim 1; and The PWM signal generator is configured to generate the PWM signal.

16. An integrated circuit comprising the control circuit according to claim 15.

17. An integrated circuit comprising the driver circuit according to claim 1.

18. A driver circuit comprising: a power stage comprising a plurality of FETs connected in parallel, wherein one of the plurality of FETs comprises a reference FET; a FET driver circuit configured to generate a corresponding drive signal for each FET of the plurality of FETs by combining a corresponding enable signal with a PWM signal; a current sensor configured to sense a current flowing through the power stage; Reference capacitor; Reference resistor; a first circuit configured to apply a first current to the reference capacitor to generate a ramp signal, and compare the ramp signal with a reference voltage to generate a first PWM signal; a second circuit configured to provide a second current to the capacitor in response to assertion of a PWM signal and to sink a third current from the capacitor in response to a second PWM signal, wherein the second PWM is asserted in response to a voltage at the capacitor reaching an upper threshold and is de-asserted in response to the voltage at the capacitor reaching a lower threshold; a duty ratio comparison circuit configured to compare the duty ratios of the first PWM signal and the second PWM signal to generate a comparison signal; a control circuit configured to apply a change in the value of the reference current until the comparison signal changes logic state; and A comparison circuit is configured to generate respective enable signals for the plurality of FETs in response to a comparison of a value of the reference current and a sensed current flowing through the power stage when a comparison signal changes logic state.

19. The driver circuit of claim 18, wherein the sensed current flowing through the power stage is one of a root mean square value of the current flowing through the power stage or a maximum value of the current flowing through the power stage.

20. The driver circuit according to claim 18, wherein Each FET of the plurality of FETs has a corresponding partition factor, and the comparison circuit is configured to determine the enable signal based on the partition factor and a signal indicating a selected partition value. 21 . The driver circuit of claim 18 , further comprising a current digital-to-analog converter configured to generate the reference current according to a digital signal.

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