Parallel-to-serial conversion circuit and method based on clock edge alignment

Abstract

The present invention provides a parallel-to-serial conversion circuit and method based on clock edge alignment, wherein the circuit includes: a clock jump delay circuit for phase delaying the input signal of an analog circuit, a frequency division module for frequency division processing the phase-delayed signal, and for directly frequency-dividing the input signal and sending it to a digital circuit; a clock synchronization detection circuit for synchronously detecting the phase-delayed and frequency-divided signal and the signal output by the digital circuit; a logic control module for sending a control signal to the clock jump delay circuit according to the result of the synchronization detection; the clock jump delay circuit adjusts the phase of the analog clock according to the control signal until the synchronization detection results are consistent, completing the clock edge alignment of the analog circuit and the digital circuit; and performing data parallel-to-serial conversion according to the analog circuit and the digital circuit after the clock edge alignment. The above invention can automatically achieve clock alignment.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a parallel-to-serial conversion circuit and method based on clock edge alignment. Background Art

[0002] In a mixed-analog circuit, the digital circuit outputs data to the analog circuit under the drive of the clock, and the analog circuit also samples and further processes the data under the drive of the clock. However, due to the delay of the clock tree and logic gates inside the digital circuit, its output data is not synchronized with the analog domain clock, that is, the phase relationship between the data and the sampling clock is uncertain. Therefore, the output data of the digital circuit cannot be guaranteed to be correctly sampled by the analog circuit. In order to solve this problem, the clock edge alignment technology is proposed, which adjusts the clock phase of the analog domain to synchronize it with the digital domain clock, thereby achieving correct data sampling.

[0003] At present, traditional clock alignment technologies mainly include multi-phase selection technology and asynchronous FIFO technology. Among them, the driving of digital circuits in multi-phase selection technology is usually selected from multiple clocks with different phases. Since the delay from clock to data in digital circuits has been determined, by selecting driving clocks with different phases, output data with different phases can be obtained. By selecting the phase that matches the analog domain clock, correct data sampling can be achieved.

[0004] However, this technology requires the generation of multiple phases of driving clocks. The accuracy of clock alignment is limited by the number of phases. Improving the accuracy means more hardware overhead and greater power consumption. In addition, this technology cannot achieve automatic clock alignment and requires the selection of preset values ​​according to the working environment, which limits the flexibility of use.

[0005] In addition, asynchronous FIFO technology mainly achieves correct data sampling through asynchronous logic. By introducing asynchronous FIFO, data is continuously written into FIFO for temporary storage under the drive of digital domain clock, and then the data in FIFO is output to analog circuit under the drive of analog domain clock, so as to achieve correct data sampling. However, since this technology introduces asynchronous FIFO circuit, for applications with very large data volumes, asynchronous FIFO will significantly increase hardware overhead and power consumption. In addition, the introduction of asynchronous logic will also increase the delay of data transmission, which cannot meet the application requirements of low latency. Summary of the invention

[0006] In view of the above problems, the present invention provides a parallel-to-serial conversion circuit and method based on clock edge alignment to solve the problems of high cost, high power consumption, limited flexibility, and inability to meet low-latency application requirements in existing parallel-to-serial conversion.

[0007] The parallel-to-serial conversion circuit based on clock edge alignment provided by the present invention comprises: an analog circuit and a digital circuit; wherein the analog circuit comprises a clock jump delay circuit based on clock edge jump, a frequency division module and a clock synchronization detection circuit based on three phases, and the digital circuit comprises a logic control module; the clock jump delay circuit is used to phase-delay the input signal of the analog circuit; the frequency division module is used to divide the signal after phase delay and send it to the clock synchronization detection circuit, and to directly divide the input signal and send it to the digital circuit; the clock synchronization detection circuit is used to synchronously detect the signal after phase delay and frequency division and the signal output by the digital circuit; the logic control module is used to send a control signal to the clock jump delay circuit according to the result of the synchronous detection; the clock jump delay circuit adjusts the phase of the analog clock according to the control signal until the synchronous detection result is consistent, thereby completing the clock edge alignment of the analog circuit and the digital circuit; and performs data parallel-to-serial conversion according to the analog circuit and the digital circuit after the clock edge alignment.

[0008] In addition, an optional technical solution is that the frequency division module includes: a first clock frequency division module, a second clock frequency division module, and the analog circuit also includes: a first logic circuit, a first selector, a second selector and a buffer; wherein, one path of the input signal is input into the clock jump delay circuit, and the signal output by the clock jump delay circuit is sent to the clock synchronization detection circuit after the frequency division processing of the first clock frequency division module; another path of the input signal is sent to the digital circuit after the frequency division processing of the second clock frequency division module; another path of the input signal is input into the first selector through the buffer, and the first selector assists in the parallel-to-serial conversion of the data to be converted.

[0009] In addition, an optional technical solution is that the divided signal output by the first clock dividing module is sent to the clock synchronization detection circuit in one way and to the second selector in another way; the second selector assists in parallel-to-serial conversion of the data to be converted.

[0010] In addition, an optional technical solution is that the signal output by the synchronization detection circuit is sent to the logic control module in one way and to the first logic circuit in another way; wherein the first logic circuit is connected to the second selector, and the second selector is connected to the first selector, and the data after parallel-to-serial conversion is output through the first selector.

[0011] In addition, an optional technical solution is that the digital circuit also includes a second logic circuit connected to the first logic circuit; wherein the data to be converted is input through the second logic circuit; the signal output by the digital circuit is sent to the second logic circuit in one way, to the logic control module in another way, and then to the clock synchronization detection circuit in another way.

[0012] In addition, an optional technical solution is that the clock jump delay circuit includes: a clock edge jump frequency division module, a clock edge jump trigger, an AND operation module, and an OR operation module; wherein the clock jump frequency division module divides the input signal by at least 4 to obtain a first clock signal; the first clock signal is delayed for one cycle by the clock jump trigger, and then inverted to obtain a second clock signal; the first clock signal, the second clock signal and the control signal are ANDed through the AND operation module to obtain a third clock signal; when the control signal is at a high level, the third clock signal and the input signal are ORed through the OR operation module to obtain the phase-delayed signal.

[0013] In addition, an optional technical solution is that the clock synchronization detection circuit includes: three consecutively arranged synchronization detection triggers, and a sampling trigger that samples the output signals of the three synchronization detection triggers respectively through the signals output by the digital circuit; wherein, the signal output by the clock synchronization detection circuit includes 6 state results, and according to the state results, it is determined whether the signal sent to the first logic circuit is aligned with the signal output by the digital circuit.

[0014] In addition, an optional technical solution is that when the signal sent to the first logic circuit is aligned with the signal output by the digital circuit, the error between the signal sent to the first logic circuit and the signal output by the digital circuit is one cycle of the input signal.

[0015] In addition, an optional technical solution is that the state result output by the clock synchronization detection circuit has a cyclic pattern of: 3'b000-3'b100-3'b110-3'b111-3'b011-3'b001-3'b000.

[0016] On the other hand, the present invention also provides a parallel-to-serial conversion method based on clock edge alignment, which performs parallel-to-serial conversion using the above-mentioned parallel-to-serial conversion circuit based on clock edge alignment.

[0017] Utilizing the above-mentioned parallel-to-serial conversion circuit and method based on clock edge alignment, the input signal of the analog circuit is phase delayed and frequency divided, and then sent to the clock synchronization detection circuit. The clock synchronization detection circuit performs synchronization detection on the signal after phase delay and frequency division and the signal output by the digital circuit in the digital circuit, and sends a control signal to the clock jump delay circuit based on the detection result, so that the clock jump delay circuit can adjust the phase of the analog clock according to the control signal until the clock edges of the analog circuit and the digital circuit are aligned. A control loop can be formed to realize automatic alignment of the clock, and the alignment accuracy can reach one cycle of the input signal. The circuit structure is simple, can effectively reduce costs and power consumption, and can be applied to data parallel-to-serial conversion in a variety of scenarios.

[0018] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0020] Figure 1 is a structural block diagram of a parallel-to-serial conversion circuit based on clock edge alignment according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a clock jump delay circuit based on clock edge jump according to an embodiment of the present invention;

[0022] Figure 3 A timing diagram of a clock jump delay circuit based on clock edge jump according to an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of a three-phase clock synchronization detection circuit according to an embodiment of the present invention;

[0024] Figure 5 FIG. 4 is a timing diagram of a three-phase clock synchronization detection circuit according to an embodiment of the present invention.

[0025] The reference numerals include: a first selector 1 , a second selector 2 , a first logic circuit 3 , a second logic circuit 4 , a first clock frequency division module 5 , and a second clock frequency division module 6 . DETAILED DESCRIPTION

[0026] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0027] In the description of the present invention, it is necessary to understand that the connection method of the various circuit devices / elements in the drawings is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0028] It will be understood by those skilled in the art that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that the term "and / or" used herein includes any unit and all combinations of one or more associated listed items.

[0029] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the field to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0030] In the following description, all logic circuits involved can be composed of various types of gate circuits and triggers, and are not limited to the specific structures shown in the drawings.

[0031] To describe in detail the parallel-to-serial conversion circuit and method based on clock edge alignment of the present invention, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 A schematic structural block diagram of a parallel-to-serial conversion circuit based on clock edge alignment according to an embodiment of the present invention is shown.

[0033] like Figure 1As shown, the parallel-to-serial conversion circuit based on clock edge alignment of an embodiment of the present invention includes an analog circuit and a digital circuit connected to each other; wherein, the analog circuit includes a clock jump delay circuit based on clock edge jump, a frequency division module and a clock synchronization detection circuit based on three phases, and the digital circuit includes a logic control module; the clock jump delay circuit is used to phase delay the input signal of the analog circuit; the frequency division module is used to divide the signal after phase delay and send it to the clock synchronization detection circuit, and is used to directly divide the input signal and send it to the digital circuit.

[0034] In addition, a clock synchronization detection circuit is used to perform synchronization detection on the signal after phase delay and frequency division processing and the signal output by the digital circuit, and output the result of the synchronization detection to the logic control module; the logic control module is used to send a control signal to the clock jump delay circuit according to the result of the synchronization detection, so that the clock jump delay circuit can adjust the phase of the analog clock according to the control signal until the synchronization detection result is consistent, and the clock edge alignment of the analog circuit and the digital circuit is completed. Finally, data parallel-to-serial conversion is performed based on the analog circuit and the digital circuit after the clock edge alignment, which can realize automatic alignment of the clock. The data to be converted is input from the digital circuit, sampled by the analog circuit aligned with the clock edge of the digital circuit, and then output from the analog circuit.

[0035] Specifically, the frequency division module includes a first clock frequency division module and a second clock frequency division module, and the analog circuit also includes: a first logic circuit, a first selector, a second selector and a buffer BUF; wherein, the input signal is input into the clock skip delay circuit Plus skip, and the signal output by the clock skip delay circuit is sent to the clock synchronization detection circuit Phase detector after the frequency division processing of the first clock frequency division module; the other input signal is processed by the second clock frequency division module to form clk_div_a2d, which is sent to the digital circuit. The digital circuit will have a delay delay during the signal transmission process, and the delay is unknown and uncontrollable. The signal output by the digital circuit is the delayed clk_div_d2a; the input signal is input into the first selector through the buffer BUF, and the first selector is used to assist in the parallel-to-serial conversion of the data to be converted. In addition, the frequency division signal output by the first clock frequency division module is sent to the clock synchronization detection circuit in one way and to the second selector in the other way; the second selector is used to assist in the parallel-to-serial conversion of the data to be converted.

[0036] In addition, the signal output by the synchronization detection circuit is sent to the logic control module Clock align logic in one way and to the first logic circuit in another way; wherein the first logic circuit is connected to the second selector, the second selector is connected to the first selector, and the data after parallel-to-serial conversion is output through the first selector.

[0037] In addition, the digital circuit also includes a second logic circuit connected to the first logic circuit; wherein the data to be converted is input through the second logic circuit, and the converted data is output after passing through the second logic circuit, the first logic circuit, the second selector and the first selector in sequence; the signal output by the digital circuit is sent to the second logic circuit in one way, to the logic control module in another way, and then to the clock synchronization detection circuit in another way.

[0038] As a specific example, the analog circuit includes: a clock jump delay circuit based on clock edge jump, a clock synchronization detection circuit based on three phases, and other clock division modules, D-type flip-flops DFF, selectors MUX, buffers BUF, etc. for realizing circuit functions. The digital circuit includes the control logic of the clock alignment technology, that is, the logic control module, as well as the clock delay formed based on the clock tree and logic gates, D-type flip-flops DFF, etc.

[0039] In the working process of the above circuit, first, the clock clk4t is input as an input signal to the analog circuit, one of which passes through the buffer BUF to drive the high-speed first selector MUX circuit to convert the data from parallel to serial, one of which is sent to the clock jump delay circuit based on the clock edge jump, and the clock phase is delayed to obtain the clock clk4t_phase_shift, and then one of which passes through the second clock frequency division module CLK DIV to generate the clock clk_div_a2d to drive the digital circuit. The clock clk4t_phase_shift passes through the first clock frequency division module, one of which drives the low-speed MUX circuit to convert the data from parallel to serial, and the other clk_div is sent to the clock synchronization detection circuit based on 3 phases, and compared with the clock clk_div_d2a output after delay in the digital circuit, the phase detection result clk_phd_out[2:0] is obtained and sent to the digital circuit, and the clock edge is judged according to the data circuit. Whether it is aligned, finally, the output data of the digital circuit is correctly sampled through the aligned clock clk_div_align.

[0040] In addition, in the digital circuit, after the clock clk_div_a2d is delayed by the clock tree and the logic gate, it drives the second logic circuit 4 to output data and drives the control logic at the same time. The delayed clock clk_div_d2a is output to the clock synchronization detection circuit in the analog circuit and compared with the analog domain clock to obtain a phase detection result. The control logic determines whether it is necessary to continue to change the phase of the analog domain clock according to the phase detection result, and outputs the phase_shift_en signal to control the clock jump delay circuit in the analog circuit to adjust the delay until the clocks of the analog circuit and the digital circuit are aligned.

[0041] Figure 2 and Figure 3 The principle and timing diagram of a clock jump delay circuit based on clock edge jump according to an embodiment of the present invention are shown from different angles respectively.

[0042] Combination Figures 1 to 3 As shown together, in the parallel-to-serial conversion circuit based on clock edge alignment of the present invention, the clock jump delay circuit includes: a clock edge jump frequency division module, a clock edge jump trigger, an AND operation module, and an OR operation module; wherein, the clock jump frequency division module divides the input signal by 8 to obtain a first clock signal A; the first clock signal A is delayed for one cycle by the clock jump trigger, and then inverted to obtain a second clock signal B; the first clock signal A, the second clock signal B and the control signal phase_shift_en are ANDed by the AND operation module to obtain a third clock signal C; when the control signal phase_shift_en is at a high level, the third clock signal C is ORed with the input signal clk4t by the OR operation module to obtain a phase-delayed signal.

[0043] As a specific example, clk4t is divided by at least 4 by the clock frequency division module. As a specific example, clk4t is divided by 8 as an example for detailed description below. After clk4t is divided by 8 by the clock frequency division module, clock A (first clock signal) is obtained. Clock A is delayed by a DFF for a clk4t cycle and then inverted to obtain clock B (second clock signal). The phase_shift_en signal from the control logic performs an "AND" operation with clock A and clock B. If the phase_shift_en signal is high, the clock (third clock signal) C obtained by the "AND" operation is a high-level pulse of a clk4t cycle. Clock C is then "OR" operated with clock clk4t to obtain clock clk4t_phase_shift. At this time, clk4t_phase_shift will remain high in the cycle when clock C is high, and will no longer flip, which is called "clock edge jump"; if the phase_shift_en signal is low, clock C is always low, and clock clk4t_phase_shift keeps flipping normally. It can be seen that the "clock edge jump" of the clock is equivalent to a one-cycle delay of the clock phase, and this delay will be reflected in the divided clock of clk4t_phase_shift.

[0044] Figure 4 and Figure 5 The principle and timing diagram of the three-phase clock synchronization detection circuit according to an embodiment of the present invention are shown from different angles.

[0045] Combination Figures 1 to 5As shown together, in the parallel-to-serial conversion circuit based on clock edge alignment of the present invention, the clock synchronization detection circuit includes: three consecutively arranged synchronization detection triggers, and sampling triggers that respectively sample the output signals of the three synchronization detection triggers through the signals output by the digital circuit; wherein, the signal output by the clock synchronization detection circuit includes 6 state results, and according to the state results, it is determined whether the signal sent to the first logic circuit is aligned with the signal output by the digital circuit, and the state results are sent to the logic control module in the digital circuit.

[0046] Among them, when the signal sent to the first logic circuit is aligned with the signal output by the digital circuit, the error between the signal sent to the first logic circuit and the signal output by the digital circuit is one cycle of the input signal, that is, the calibration accuracy of the clock edge alignment of the embodiment of the present invention can reach a maximum clock cycle, with high accuracy and greater flexibility, and can realize automatic alignment of the clock.

[0047] As a specific example, the clock clk4t_phase_shift samples the clock clk_div through three consecutive triggers DFF to obtain the clk_div_early signal, clk_div_align signal and clk_div_late signal, which are one cycle apart in phase; then, the three signals are sampled respectively through the clock clk_div_d2a from the digital circuit to obtain the three bits of clk_phd_out[2:0], which represent the phase difference information of the current clock. When clk_phd_out[2:0] is equal to 3'b001 or 3'b011, it indicates that the clk_div_d2a signal is between the clk_div_early signal and the clk_div_late signal. At this time, it can be considered that the clocks of the clk_div_align signal and the clk_div_d2a signal are aligned, and the error is one clk4t signal cycle.

[0048] In other words, the calibration accuracy of the clock edge alignment proposed in the embodiment of the present invention can reach a maximum clock cycle. Figure 5 It can also be seen from the timing diagram shown that after the clock has a "clock edge jump", the divided clocks clk_div_early, clk_div_align and clk_div_late all achieve phase delay, and each delay is one clk4t cycle. The clock phase detection result clk_phd_out[2:0] changes from 3'b111 to 3'b011, and then to 3'b001.

[0049] Among them, clk_phd_out[2:0] usually represents a multi-bit signal, where clk_phd_out is the name of a signal, and [2:0] indicates that the signal contains three bits, and the three bits represent different information or functions respectively.

[0050] It can be seen that the control logic of the parallel-to-serial conversion circuit based on clock edge alignment of the present invention includes: at the beginning, the signal phase_shift_en is a low level, waiting for 15 clock cycles to allow the analog circuit to work stably, and then detecting whether clk_phd_out[2:0] is 3'b001 or 3'b011. If so, the clock phase calibration is completed, otherwise phase_shift_en outputs a high level of one clock cycle, at which time the analog circuit will perform clock delay and phase detection, waiting for 15 clock cycles to allow the analog circuit to work stably, and then detecting whether clk_phd_out[2:0] is 3'b001 or 3'b011, and repeating this cycle until the phase calibration is completed. By analyzing the proposed clock alignment, it can be concluded that the signal clk_phd_out[2:0] will change cyclically according to the following rule: 3'b000 ->3'b100 ->3'b110 ->3'b111 ->3'b011 ->3'b001 ->3'b000 until the clocks are aligned and locked.

[0051] Corresponding to the above-mentioned parallel-to-serial conversion circuit based on clock edge alignment, the present invention also provides a parallel-to-serial conversion method based on clock edge alignment, which completes the parallel-to-serial conversion of data based on the above-mentioned parallel-to-serial conversion circuit based on clock edge alignment, wherein the clocks of the analog circuit and the digital circuit can be automatically adjusted to a synchronous state, ensuring that the output data of the digital circuit is correctly sampled by the analog circuit, thereby improving the accuracy of data conversion.

[0052] It should be noted that the embodiments of the above-mentioned parallel-to-serial conversion method based on clock edge alignment can refer to the description in the embodiment of the parallel-to-serial conversion circuit based on clock edge alignment, and will not be described in detail here.

[0053] According to the parallel-to-serial conversion circuit and method based on clock edge alignment of the present invention, after the input signal of the analog circuit is phase delayed and frequency divided, it is sent to the clock synchronization detection circuit, and the signal after the phase delay and frequency division processing and the signal output by the digital circuit are synchronously detected based on the clock synchronization detection circuit, and a control signal is sent to the clock jump delay circuit according to the detection result, so that the clock jump delay circuit can adjust the phase of the analog clock according to the control signal until the clock edges of the analog circuit and the digital circuit are aligned, thereby forming a control loop and realizing automatic alignment of the clocks of the analog circuit and the digital circuit, and the alignment accuracy can reach one cycle of the input signal, the circuit structure is simple, the power consumption and cost are low, and it can meet the data parallel-to-serial conversion needs in a variety of scenarios.

[0054] As described above with reference to the accompanying drawings, the parallel-to-serial conversion circuit and method based on clock edge alignment according to the present invention are described by way of example. However, it should be understood by those skilled in the art that various improvements can be made to the parallel-to-serial conversion circuit and method based on clock edge alignment proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A parallel-to-serial conversion circuit based on clock edge alignment, characterized in that: include: Analog circuits and digital circuits; among them, The analog circuit includes a clock jump delay circuit based on clock edge jump, a frequency division module and a clock synchronization detection circuit based on three phases, and the digital circuit includes a logic control module; The clock jump delay circuit is used to phase delay the input signal of the analog circuit; The frequency division module is used to perform frequency division processing on the phase-delayed signal and send it to the clock synchronization detection circuit, and is used to perform frequency division processing on the input signal and send it to the digital circuit directly; The clock synchronization detection circuit is used to perform synchronization detection on the signal after phase delay and frequency division processing and the signal ckl_div_d2a after the input signal is directly frequency-divided and outputted by the digital circuit delay; The logic control module is used to send a control signal to the clock jump delay circuit according to the result of the synchronization detection; The clock jump delay circuit adjusts the phase of the input signal according to the control signal until the synchronization detection results are consistent, thereby completing the clock edge alignment of the analog circuit and the digital circuit; The clock jump delay circuit includes: a clock edge jump frequency division module, a clock edge jump trigger, an AND operation module, or an OR operation module; wherein, The clock skipping frequency division module divides the input signal by at least 4 to obtain a first clock signal; The first clock signal is delayed by one cycle by the clock skip trigger, and then inverted to obtain a second clock signal; The first clock signal, the second clock signal and the control signal are ANDed by the AND operation module to obtain a third clock signal; When the control signal is at a high level, the third clock signal and the input signal are ORed by the OR operation module to obtain the phase-delayed signal; Data parallel-to-serial conversion is performed based on the analog circuit and digital circuit after clock edge alignment.

2. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 1, characterized in that: The frequency division module includes: a first clock frequency division module and a second clock frequency division module, and the analog circuit also includes: a first logic circuit, a first selector, a second selector and a buffer; wherein, The input signal is input into the clock jump delay circuit, and the signal output by the clock jump delay circuit is sent to the clock synchronization detection circuit after being processed by the first clock frequency division module; The other path of the input signal is sent to the digital circuit after being processed by the second clock frequency division module; Another path of the input signal is input into the first selector through the buffer, and the first selector assists in performing parallel-to-serial conversion on the data to be converted.

3. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 2, characterized in that: The frequency division signal output by the first clock frequency division module is sent to the clock synchronization detection circuit in one way and to the second selector in another way; the second selector assists in parallel-to-serial conversion of the data to be converted.

4. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 2, characterized in that: The signal output by the synchronization detection circuit is sent to the logic control module in one way and to the first logic circuit in another way; wherein, The first logic circuit is connected to the second selector, and the second selector is connected to the first selector, and the data after parallel-to-serial conversion is output through the first selector.

5. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 3, characterized in that: The digital circuit also includes a second logic circuit connected to the first logic circuit; wherein, The data to be converted is input through the second logic circuit; The signal ckl_div_d2a delayed output by the digital circuit is sent to the second logic circuit in one way, sent to the logic control module in another way, and sent to the clock synchronization detection circuit in another way.

6. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 4, characterized in that: The clock synchronization detection circuit comprises: three synchronization detection triggers arranged in series, and sampling triggers for sampling the output signals of the three synchronization detection triggers respectively through the signal ckl_div_d2a delayed output by the digital circuit; wherein, The signal output by the clock synchronization detection circuit includes 6 status results. According to the status results, it is determined whether the signal ckl_div_align sent to the first logic circuit is aligned with the signal ckl_div_d2a delayed output by the digital circuit.

7. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 6, characterized in that: When the signal ckl_div_align sent to the first logic circuit is aligned with the signal ckl_div_d2a delayed output by the digital circuit, the error between the signal ckl_div_align sent to the first logic circuit and the signal ckl_div_d2a delayed output by the digital circuit is one cycle of the input signal.

8. The parallel-to-serial conversion circuit based on clock edge alignment according to claim 1, characterized in that: The cycle rule of the state result output by the clock synchronization detection circuit is: 3'b000-3'b100-3'b110-3'b111-3'b011-3'b001-3'b000.

9. A parallel-to-serial conversion method based on clock edge alignment, characterized in that: Parallel-to-serial conversion is performed using the parallel-to-serial conversion circuit based on clock edge alignment as described in any one of claims 1 to 8.

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